dmtbinfo2.c revision 1.1.1.7
1 /****************************************************************************** 2 * 3 * Module Name: dmtbinfo2 - Table info for non-AML tables 4 * 5 *****************************************************************************/ 6 7 /* 8 * Copyright (C) 2000 - 2021, Intel Corp. 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions, and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * substantially similar to the "NO WARRANTY" disclaimer below 19 * ("Disclaimer") and any redistribution must be conditioned upon 20 * including a substantially similar Disclaimer requirement for further 21 * binary redistribution. 22 * 3. Neither the names of the above-listed copyright holders nor the names 23 * of any contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * Alternatively, this software may be distributed under the terms of the 27 * GNU General Public License ("GPL") version 2 as published by the Free 28 * Software Foundation. 29 * 30 * NO WARRANTY 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 32 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 33 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 34 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 35 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 39 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 40 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 41 * POSSIBILITY OF SUCH DAMAGES. 42 */ 43 44 #include "acpi.h" 45 #include "accommon.h" 46 #include "acdisasm.h" 47 #include "actbinfo.h" 48 49 /* This module used for application-level code only */ 50 51 #define _COMPONENT ACPI_CA_DISASSEMBLER 52 ACPI_MODULE_NAME ("dmtbinfo2") 53 54 /* 55 * How to add a new table: 56 * 57 * - Add the C table definition to the actbl1.h or actbl2.h header. 58 * - Add ACPI_xxxx_OFFSET macro(s) for the table (and subtables) to list below. 59 * - Define the table in this file (for the disassembler). If any 60 * new data types are required (ACPI_DMT_*), see below. 61 * - Add an external declaration for the new table definition (AcpiDmTableInfo*) 62 * in acdisam.h 63 * - Add new table definition to the dispatch table in dmtable.c (AcpiDmTableData) 64 * If a simple table (with no subtables), no disassembly code is needed. 65 * Otherwise, create the AcpiDmDump* function for to disassemble the table 66 * and add it to the dmtbdump.c file. 67 * - Add an external declaration for the new AcpiDmDump* function in acdisasm.h 68 * - Add the new AcpiDmDump* function to the dispatch table in dmtable.c 69 * - Create a template for the new table 70 * - Add data table compiler support 71 * 72 * How to add a new data type (ACPI_DMT_*): 73 * 74 * - Add new type at the end of the ACPI_DMT list in acdisasm.h 75 * - Add length and implementation cases in dmtable.c (disassembler) 76 * - Add type and length cases in dtutils.c (DT compiler) 77 */ 78 79 /* 80 * Remaining tables are not consumed directly by the ACPICA subsystem 81 */ 82 83 84 /******************************************************************************* 85 * 86 * IORT - IO Remapping Table 87 * 88 ******************************************************************************/ 89 90 ACPI_DMTABLE_INFO AcpiDmTableInfoIort[] = 91 { 92 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeCount), "Node Count", 0}, 93 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (NodeOffset), "Node Offset", 0}, 94 {ACPI_DMT_UINT32, ACPI_IORT_OFFSET (Reserved), "Reserved", 0}, 95 ACPI_DMT_TERMINATOR 96 }; 97 98 /* Optional padding field */ 99 100 ACPI_DMTABLE_INFO AcpiDmTableInfoIortPad[] = 101 { 102 {ACPI_DMT_RAW_BUFFER, 0, "Optional Padding", DT_OPTIONAL}, 103 ACPI_DMT_TERMINATOR 104 }; 105 106 /* Common Subtable header (one per Subtable) */ 107 108 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr[] = 109 { 110 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 111 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 112 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 113 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Reserved", 0}, 114 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 115 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 116 ACPI_DMT_TERMINATOR 117 }; 118 119 /* Common Subtable header (one per Subtable)- Revision 3 */ 120 121 ACPI_DMTABLE_INFO AcpiDmTableInfoIortHdr3[] = 122 { 123 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Type), "Type", 0}, 124 {ACPI_DMT_UINT16, ACPI_IORTH_OFFSET (Length), "Length", DT_LENGTH}, 125 {ACPI_DMT_UINT8, ACPI_IORTH_OFFSET (Revision), "Revision", 0}, 126 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (Identifier), "Identifier", 0}, 127 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingCount), "Mapping Count", 0}, 128 {ACPI_DMT_UINT32, ACPI_IORTH_OFFSET (MappingOffset), "Mapping Offset", 0}, 129 ACPI_DMT_TERMINATOR 130 }; 131 132 ACPI_DMTABLE_INFO AcpiDmTableInfoIortMap[] = 133 { 134 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (InputBase), "Input base", DT_OPTIONAL}, 135 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (IdCount), "ID Count", 0}, 136 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputBase), "Output Base", 0}, 137 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (OutputReference), "Output Reference", 0}, 138 {ACPI_DMT_UINT32, ACPI_IORTM_OFFSET (Flags), "Flags (decoded below)", 0}, 139 {ACPI_DMT_FLAG0, ACPI_IORTM_FLAG_OFFSET (Flags, 0), "Single Mapping", 0}, 140 ACPI_DMT_TERMINATOR 141 }; 142 143 ACPI_DMTABLE_INFO AcpiDmTableInfoIortAcc[] = 144 { 145 {ACPI_DMT_UINT32, ACPI_IORTA_OFFSET (CacheCoherency), "Cache Coherency", 0}, 146 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (Hints), "Hints (decoded below)", 0}, 147 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Transient", 0}, 148 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Write Allocate", 0}, 149 {ACPI_DMT_FLAG2, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Read Allocate", 0}, 150 {ACPI_DMT_FLAG3, ACPI_IORTA_FLAG_OFFSET (Hints, 0), "Override", 0}, 151 {ACPI_DMT_UINT16, ACPI_IORTA_OFFSET (Reserved), "Reserved", 0}, 152 {ACPI_DMT_UINT8, ACPI_IORTA_OFFSET (MemoryFlags), "Memory Flags (decoded below)", 0}, 153 {ACPI_DMT_FLAG0, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Coherency", 0}, 154 {ACPI_DMT_FLAG1, ACPI_IORTA_FLAG_OFFSET (MemoryFlags, 0), "Device Attribute", 0}, 155 ACPI_DMT_TERMINATOR 156 }; 157 158 /* IORT subtables */ 159 160 /* 0x00: ITS Group */ 161 162 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0[] = 163 { 164 {ACPI_DMT_UINT32, ACPI_IORT0_OFFSET (ItsCount), "ItsCount", 0}, 165 ACPI_DMT_TERMINATOR 166 }; 167 168 ACPI_DMTABLE_INFO AcpiDmTableInfoIort0a[] = 169 { 170 {ACPI_DMT_UINT32, 0, "Identifiers", DT_OPTIONAL}, 171 ACPI_DMT_TERMINATOR 172 }; 173 174 /* 0x01: Named Component */ 175 176 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1[] = 177 { 178 {ACPI_DMT_UINT32, ACPI_IORT1_OFFSET (NodeFlags), "Node Flags", 0}, 179 {ACPI_DMT_IORTMEM, ACPI_IORT1_OFFSET (MemoryProperties), "Memory Properties", 0}, 180 {ACPI_DMT_UINT8, ACPI_IORT1_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 181 {ACPI_DMT_STRING, ACPI_IORT1_OFFSET (DeviceName[0]), "Device Name", 0}, 182 ACPI_DMT_TERMINATOR 183 }; 184 185 ACPI_DMTABLE_INFO AcpiDmTableInfoIort1a[] = 186 { 187 {ACPI_DMT_RAW_BUFFER, 0, "Padding", DT_OPTIONAL}, 188 ACPI_DMT_TERMINATOR 189 }; 190 191 /* 0x02: PCI Root Complex */ 192 193 ACPI_DMTABLE_INFO AcpiDmTableInfoIort2[] = 194 { 195 {ACPI_DMT_IORTMEM, ACPI_IORT2_OFFSET (MemoryProperties), "Memory Properties", 0}, 196 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (AtsAttribute), "ATS Attribute", 0}, 197 {ACPI_DMT_UINT32, ACPI_IORT2_OFFSET (PciSegmentNumber), "PCI Segment Number", 0}, 198 {ACPI_DMT_UINT8, ACPI_IORT2_OFFSET (MemoryAddressLimit), "Memory Size Limit", 0}, 199 {ACPI_DMT_UINT24, ACPI_IORT2_OFFSET (Reserved[0]), "Reserved", 0}, 200 ACPI_DMT_TERMINATOR 201 }; 202 203 /* 0x03: SMMUv1/2 */ 204 205 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3[] = 206 { 207 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (BaseAddress), "Base Address", 0}, 208 {ACPI_DMT_UINT64, ACPI_IORT3_OFFSET (Span), "Span", 0}, 209 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Model), "Model", 0}, 210 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (Flags), "Flags (decoded below)", 0}, 211 {ACPI_DMT_FLAG0, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "DVM Supported", 0}, 212 {ACPI_DMT_FLAG1, ACPI_IORT3_FLAG_OFFSET (Flags, 0), "Coherent Walk", 0}, 213 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (GlobalInterruptOffset), "Global Interrupt Offset", 0}, 214 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptCount), "Context Interrupt Count", 0}, 215 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (ContextInterruptOffset), "Context Interrupt Offset", 0}, 216 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptCount), "PMU Interrupt Count", 0}, 217 {ACPI_DMT_UINT32, ACPI_IORT3_OFFSET (PmuInterruptOffset), "PMU Interrupt Offset", 0}, 218 ACPI_DMT_TERMINATOR 219 }; 220 221 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3a[] = 222 { 223 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrpt), "NSgIrpt", 0}, 224 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgIrptFlags), "NSgIrpt Flags (decoded below)", 0}, 225 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgIrptFlags, 0), "Edge Triggered", 0}, 226 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrpt), "NSgCfgIrpt", 0}, 227 {ACPI_DMT_UINT32, ACPI_IORT3A_OFFSET (NSgCfgIrptFlags), "NSgCfgIrpt Flags (decoded below)", 0}, 228 {ACPI_DMT_FLAG0, ACPI_IORT3a_FLAG_OFFSET (NSgCfgIrptFlags, 0), "Edge Triggered", 0}, 229 ACPI_DMT_TERMINATOR 230 }; 231 232 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3b[] = 233 { 234 {ACPI_DMT_UINT64, 0, "Context Interrupt", DT_OPTIONAL}, 235 ACPI_DMT_TERMINATOR 236 }; 237 238 ACPI_DMTABLE_INFO AcpiDmTableInfoIort3c[] = 239 { 240 {ACPI_DMT_UINT64, 0, "PMU Interrupt", DT_OPTIONAL}, 241 ACPI_DMT_TERMINATOR 242 }; 243 244 /* 0x04: SMMUv3 */ 245 246 ACPI_DMTABLE_INFO AcpiDmTableInfoIort4[] = 247 { 248 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (BaseAddress), "Base Address", 0}, 249 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Flags), "Flags (decoded below)", 0}, 250 {ACPI_DMT_FLAG0, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "COHACC Override", 0}, 251 {ACPI_DMT_FLAG1, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "HTTU Override", 0}, 252 {ACPI_DMT_FLAG3, ACPI_IORT4_FLAG_OFFSET (Flags, 0), "Proximity Domain Valid", 0}, 253 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Reserved), "Reserved", 0}, 254 {ACPI_DMT_UINT64, ACPI_IORT4_OFFSET (VatosAddress), "VATOS Address", 0}, 255 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Model), "Model", 0}, 256 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (EventGsiv), "Event GSIV", 0}, 257 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (PriGsiv), "PRI GSIV", 0}, 258 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (GerrGsiv), "GERR GSIV", 0}, 259 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (SyncGsiv), "Sync GSIV", 0}, 260 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (Pxm), "Proximity Domain", 0}, 261 {ACPI_DMT_UINT32, ACPI_IORT4_OFFSET (IdMappingIndex), "Device ID Mapping Index", 0}, 262 ACPI_DMT_TERMINATOR 263 }; 264 265 /* 0x05: PMCG */ 266 267 ACPI_DMTABLE_INFO AcpiDmTableInfoIort5[] = 268 { 269 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page0BaseAddress), "Page 0 Base Address", 0}, 270 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (OverflowGsiv), "Overflow Interrupt GSIV", 0}, 271 {ACPI_DMT_UINT32, ACPI_IORT5_OFFSET (NodeReference), "Node Reference", 0}, 272 {ACPI_DMT_UINT64, ACPI_IORT5_OFFSET (Page1BaseAddress), "Page 1 Base Address", 0}, 273 ACPI_DMT_TERMINATOR 274 }; 275 276 277 /* 0x06: RMR */ 278 279 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6[] = 280 { 281 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (Flags), "Flags (decoded below)", 0}, 282 {ACPI_DMT_FLAG0, ACPI_IORT6_FLAG_OFFSET (Flags, 0), "Remapping Permitted", 0}, 283 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrCount), "Number of RMR Descriptors", 0}, 284 {ACPI_DMT_UINT32, ACPI_IORT6_OFFSET (RmrOffset), "RMR Descriptor Offset", 0}, 285 ACPI_DMT_TERMINATOR 286 }; 287 288 ACPI_DMTABLE_INFO AcpiDmTableInfoIort6a[] = 289 { 290 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (BaseAddress), "Base Address of RMR", DT_OPTIONAL}, 291 {ACPI_DMT_UINT64, ACPI_IORT6A_OFFSET (Length), "Length of RMR", 0}, 292 {ACPI_DMT_UINT32, ACPI_IORT6A_OFFSET (Reserved), "Reserved", 0}, 293 ACPI_DMT_TERMINATOR 294 }; 295 296 /******************************************************************************* 297 * 298 * IVRS - I/O Virtualization Reporting Structure 299 * 300 ******************************************************************************/ 301 302 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs[] = 303 { 304 {ACPI_DMT_UINT32, ACPI_IVRS_OFFSET (Info), "Virtualization Info", 0}, 305 {ACPI_DMT_UINT64, ACPI_IVRS_OFFSET (Reserved), "Reserved", 0}, 306 ACPI_DMT_TERMINATOR 307 }; 308 309 /* IVRS subtables */ 310 311 /* 0x10: I/O Virtualization Hardware Definition (IVHD) Block */ 312 313 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware1[] = 314 { 315 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 316 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 317 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 318 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 319 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 320 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 321 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 322 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 323 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 324 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 325 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 326 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 327 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (CapabilityOffset), "Capability Offset", 0}, 328 {ACPI_DMT_UINT64, ACPI_IVRS0_OFFSET (BaseAddress), "Base Address", 0}, 329 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 330 {ACPI_DMT_UINT16, ACPI_IVRS0_OFFSET (Info), "Virtualization Info", 0}, 331 {ACPI_DMT_UINT32, ACPI_IVRS0_OFFSET (FeatureReporting), "Feature Reporting", 0}, 332 ACPI_DMT_TERMINATOR 333 }; 334 335 /* 0x11, 0x40: I/O Virtualization Hardware Definition (IVHD) Block */ 336 337 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHware23[] = 338 { 339 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 340 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 341 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "HtTunEn", 0}, 342 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PassPW", 0}, 343 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "ResPassPW", 0}, 344 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Isoc Control", 0}, 345 {ACPI_DMT_FLAG4, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Iotlb Support", 0}, 346 {ACPI_DMT_FLAG5, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Coherent", 0}, 347 {ACPI_DMT_FLAG6, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Prefetch Support", 0}, 348 {ACPI_DMT_FLAG7, ACPI_IVRS_FLAG_OFFSET (Flags,0), "PPR Support", 0}, 349 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.Length), "Length", DT_LENGTH}, 350 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Header.DeviceId), "DeviceId", 0}, 351 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (CapabilityOffset), "Capability Offset", 0}, 352 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (BaseAddress), "Base Address", 0}, 353 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (PciSegmentGroup), "PCI Segment Group", 0}, 354 {ACPI_DMT_UINT16, ACPI_IVRS01_OFFSET (Info), "Virtualization Info", 0}, 355 {ACPI_DMT_UINT32, ACPI_IVRS01_OFFSET (Attributes), "Attributes", 0}, 356 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (EfrRegisterImage), "EFR Image", 0}, 357 {ACPI_DMT_UINT64, ACPI_IVRS01_OFFSET (Reserved), "Reserved", 0}, 358 ACPI_DMT_TERMINATOR 359 }; 360 361 /* 0x20, 0x21, 0x22: I/O Virtualization Memory Definition (IVMD) Device Entry Block */ 362 363 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsMemory[] = 364 { 365 {ACPI_DMT_IVRS, ACPI_IVRSH_OFFSET (Type), "Subtable Type", 0}, 366 {ACPI_DMT_UINT8, ACPI_IVRSH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 367 {ACPI_DMT_FLAG0, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Unity", 0}, 368 {ACPI_DMT_FLAG1, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Readable", 0}, 369 {ACPI_DMT_FLAG2, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Writeable", 0}, 370 {ACPI_DMT_FLAG3, ACPI_IVRS_FLAG_OFFSET (Flags,0), "Exclusion Range", 0}, 371 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (Length), "Length", DT_LENGTH}, 372 {ACPI_DMT_UINT16, ACPI_IVRSH_OFFSET (DeviceId), "DeviceId", 0}, 373 {ACPI_DMT_UINT16, ACPI_IVRS1_OFFSET (AuxData), "Auxiliary Data", 0}, 374 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (Reserved), "Reserved", 0}, 375 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (StartAddress), "Start Address", 0}, 376 {ACPI_DMT_UINT64, ACPI_IVRS1_OFFSET (MemoryLength), "Memory Length", 0}, 377 ACPI_DMT_TERMINATOR 378 }; 379 380 /* Device entry header for IVHD block */ 381 382 #define ACPI_DMT_IVRS_DE_HEADER \ 383 {ACPI_DMT_IVRS_DE, ACPI_IVRSD_OFFSET (Type), "Subtable Type", 0}, \ 384 {ACPI_DMT_UINT16, ACPI_IVRSD_OFFSET (Id), "Device ID", 0}, \ 385 {ACPI_DMT_UINT8, ACPI_IVRSD_OFFSET (DataSetting), "Data Setting (decoded below)", 0}, \ 386 {ACPI_DMT_FLAG0, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "INITPass", 0}, \ 387 {ACPI_DMT_FLAG1, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "EIntPass", 0}, \ 388 {ACPI_DMT_FLAG2, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "NMIPass", 0}, \ 389 {ACPI_DMT_FLAG3, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "Reserved", 0}, \ 390 {ACPI_DMT_FLAGS4, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "System MGMT", 0}, \ 391 {ACPI_DMT_FLAG6, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT0 Pass", 0}, \ 392 {ACPI_DMT_FLAG7, ACPI_IVRSDE_FLAG_OFFSET (DataSetting, 0), "LINT1 Pass", 0} 393 394 /* 4-byte device entry (Types 1,2,3,4) */ 395 396 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs4[] = 397 { 398 ACPI_DMT_IVRS_DE_HEADER, 399 ACPI_DMT_TERMINATOR 400 }; 401 402 /* 8-byte device entry (Type Alias Select, Alias Start of Range) */ 403 404 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8a[] = 405 { 406 ACPI_DMT_IVRS_DE_HEADER, 407 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved1), "Reserved", 0}, 408 {ACPI_DMT_UINT16, ACPI_IVRS8A_OFFSET (UsedId), "Source Used Device ID", 0}, 409 {ACPI_DMT_UINT8, ACPI_IVRS8A_OFFSET (Reserved2), "Reserved", 0}, 410 ACPI_DMT_TERMINATOR 411 }; 412 413 /* 8-byte device entry (Type Extended Select, Extended Start of Range) */ 414 415 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8b[] = 416 { 417 ACPI_DMT_IVRS_DE_HEADER, 418 {ACPI_DMT_UINT32, ACPI_IVRS8B_OFFSET (ExtendedData), "Extended Data", 0}, 419 ACPI_DMT_TERMINATOR 420 }; 421 422 /* 8-byte device entry (Type Special Device) */ 423 424 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrs8c[] = 425 { 426 ACPI_DMT_IVRS_DE_HEADER, 427 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Handle), "Handle", 0}, 428 {ACPI_DMT_UINT16, ACPI_IVRS8C_OFFSET (UsedId), "Source Used Device ID", 0}, 429 {ACPI_DMT_UINT8, ACPI_IVRS8C_OFFSET (Variety), "Variety", 0}, 430 ACPI_DMT_TERMINATOR 431 }; 432 433 /* Variable-length Device Entry Type 0xF0 */ 434 435 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHid[] = 436 { 437 ACPI_DMT_IVRS_DE_HEADER, 438 ACPI_DMT_TERMINATOR 439 }; 440 441 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidString[] = 442 { 443 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 444 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 445 {ACPI_DMT_IVRS_UNTERMINATED_STRING, 2, "UID", DT_OPTIONAL}, 446 ACPI_DMT_TERMINATOR 447 }; 448 449 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsUidInteger[] = 450 { 451 {ACPI_DMT_UINT8, 0, "UID Format", DT_DESCRIBES_OPTIONAL}, 452 {ACPI_DMT_UINT8, 1, "UID Length", DT_DESCRIBES_OPTIONAL}, 453 {ACPI_DMT_UINT64, 2, "UID", DT_OPTIONAL}, 454 ACPI_DMT_TERMINATOR 455 }; 456 457 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidString[] = 458 { 459 {ACPI_DMT_NAME8, 0, "ACPI HID", 0}, 460 ACPI_DMT_TERMINATOR 461 }; 462 463 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsHidInteger[] = 464 { 465 {ACPI_DMT_UINT64, 0, "ACPI HID", 0}, 466 ACPI_DMT_TERMINATOR 467 }; 468 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidString[] = 469 { 470 {ACPI_DMT_NAME8, 0, "ACPI CID", 0}, 471 ACPI_DMT_TERMINATOR 472 }; 473 474 ACPI_DMTABLE_INFO AcpiDmTableInfoIvrsCidInteger[] = 475 { 476 {ACPI_DMT_UINT64, 0, "ACPI CID", 0}, 477 ACPI_DMT_TERMINATOR 478 }; 479 480 481 /******************************************************************************* 482 * 483 * LPIT - Low Power Idle Table 484 * 485 ******************************************************************************/ 486 487 /* Main table consists only of the standard ACPI table header */ 488 489 /* Common Subtable header (one per Subtable) */ 490 491 ACPI_DMTABLE_INFO AcpiDmTableInfoLpitHdr[] = 492 { 493 {ACPI_DMT_LPIT, ACPI_LPITH_OFFSET (Type), "Subtable Type", 0}, 494 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Length), "Length", DT_LENGTH}, 495 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (UniqueId), "Unique ID", 0}, 496 {ACPI_DMT_UINT16, ACPI_LPITH_OFFSET (Reserved), "Reserved", 0}, 497 {ACPI_DMT_UINT32, ACPI_LPITH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 498 {ACPI_DMT_FLAG0, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "State Disabled", 0}, 499 {ACPI_DMT_FLAG1, ACPI_LPITH_FLAG_OFFSET (Flags, 0), "No Counter", 0}, 500 ACPI_DMT_TERMINATOR 501 }; 502 503 /* LPIT Subtables */ 504 505 /* 0: Native C-state */ 506 507 ACPI_DMTABLE_INFO AcpiDmTableInfoLpit0[] = 508 { 509 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (EntryTrigger), "Entry Trigger", 0}, 510 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Residency), "Residency", 0}, 511 {ACPI_DMT_UINT32, ACPI_LPIT0_OFFSET (Latency), "Latency", 0}, 512 {ACPI_DMT_GAS, ACPI_LPIT0_OFFSET (ResidencyCounter), "Residency Counter", 0}, 513 {ACPI_DMT_UINT64, ACPI_LPIT0_OFFSET (CounterFrequency), "Counter Frequency", 0}, 514 ACPI_DMT_TERMINATOR 515 }; 516 517 518 /******************************************************************************* 519 * 520 * MADT - Multiple APIC Description Table and subtables 521 * 522 ******************************************************************************/ 523 524 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt[] = 525 { 526 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Address), "Local Apic Address", 0}, 527 {ACPI_DMT_UINT32, ACPI_MADT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 528 {ACPI_DMT_FLAG0, ACPI_MADT_FLAG_OFFSET (Flags,0), "PC-AT Compatibility", 0}, 529 ACPI_DMT_TERMINATOR 530 }; 531 532 /* Common Subtable header (one per Subtable) */ 533 534 ACPI_DMTABLE_INFO AcpiDmTableInfoMadtHdr[] = 535 { 536 {ACPI_DMT_MADT, ACPI_MADTH_OFFSET (Type), "Subtable Type", 0}, 537 {ACPI_DMT_UINT8, ACPI_MADTH_OFFSET (Length), "Length", DT_LENGTH}, 538 ACPI_DMT_TERMINATOR 539 }; 540 541 /* MADT Subtables */ 542 543 /* 0: processor APIC */ 544 545 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt0[] = 546 { 547 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (ProcessorId), "Processor ID", 0}, 548 {ACPI_DMT_UINT8, ACPI_MADT0_OFFSET (Id), "Local Apic ID", 0}, 549 {ACPI_DMT_UINT32, ACPI_MADT0_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 550 {ACPI_DMT_FLAG0, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 551 {ACPI_DMT_FLAG1, ACPI_MADT0_FLAG_OFFSET (LapicFlags,0), "Runtime Online Capable", 0}, 552 ACPI_DMT_TERMINATOR 553 }; 554 555 /* 1: IO APIC */ 556 557 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt1[] = 558 { 559 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Id), "I/O Apic ID", 0}, 560 {ACPI_DMT_UINT8, ACPI_MADT1_OFFSET (Reserved), "Reserved", 0}, 561 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (Address), "Address", 0}, 562 {ACPI_DMT_UINT32, ACPI_MADT1_OFFSET (GlobalIrqBase), "Interrupt", 0}, 563 ACPI_DMT_TERMINATOR 564 }; 565 566 /* 2: Interrupt Override */ 567 568 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt2[] = 569 { 570 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (Bus), "Bus", 0}, 571 {ACPI_DMT_UINT8, ACPI_MADT2_OFFSET (SourceIrq), "Source", 0}, 572 {ACPI_DMT_UINT32, ACPI_MADT2_OFFSET (GlobalIrq), "Interrupt", 0}, 573 {ACPI_DMT_UINT16, ACPI_MADT2_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 574 {ACPI_DMT_FLAGS0, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 575 {ACPI_DMT_FLAGS2, ACPI_MADT2_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 576 ACPI_DMT_TERMINATOR 577 }; 578 579 /* 3: NMI Sources */ 580 581 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt3[] = 582 { 583 {ACPI_DMT_UINT16, ACPI_MADT3_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 584 {ACPI_DMT_FLAGS0, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 585 {ACPI_DMT_FLAGS2, ACPI_MADT3_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 586 {ACPI_DMT_UINT32, ACPI_MADT3_OFFSET (GlobalIrq), "Interrupt", 0}, 587 ACPI_DMT_TERMINATOR 588 }; 589 590 /* 4: Local APIC NMI */ 591 592 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt4[] = 593 { 594 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (ProcessorId), "Processor ID", 0}, 595 {ACPI_DMT_UINT16, ACPI_MADT4_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 596 {ACPI_DMT_FLAGS0, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 597 {ACPI_DMT_FLAGS2, ACPI_MADT4_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 598 {ACPI_DMT_UINT8, ACPI_MADT4_OFFSET (Lint), "Interrupt Input LINT", 0}, 599 ACPI_DMT_TERMINATOR 600 }; 601 602 /* 5: Address Override */ 603 604 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt5[] = 605 { 606 {ACPI_DMT_UINT16, ACPI_MADT5_OFFSET (Reserved), "Reserved", 0}, 607 {ACPI_DMT_UINT64, ACPI_MADT5_OFFSET (Address), "APIC Address", 0}, 608 ACPI_DMT_TERMINATOR 609 }; 610 611 /* 6: I/O Sapic */ 612 613 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt6[] = 614 { 615 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Id), "I/O Sapic ID", 0}, 616 {ACPI_DMT_UINT8, ACPI_MADT6_OFFSET (Reserved), "Reserved", 0}, 617 {ACPI_DMT_UINT32, ACPI_MADT6_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 618 {ACPI_DMT_UINT64, ACPI_MADT6_OFFSET (Address), "Address", 0}, 619 ACPI_DMT_TERMINATOR 620 }; 621 622 /* 7: Local Sapic */ 623 624 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt7[] = 625 { 626 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (ProcessorId), "Processor ID", 0}, 627 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Id), "Local Sapic ID", 0}, 628 {ACPI_DMT_UINT8, ACPI_MADT7_OFFSET (Eid), "Local Sapic EID", 0}, 629 {ACPI_DMT_UINT24, ACPI_MADT7_OFFSET (Reserved[0]), "Reserved", 0}, 630 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 631 {ACPI_DMT_FLAG0, ACPI_MADT7_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 632 {ACPI_DMT_UINT32, ACPI_MADT7_OFFSET (Uid), "Processor UID", 0}, 633 {ACPI_DMT_STRING, ACPI_MADT7_OFFSET (UidString[0]), "Processor UID String", 0}, 634 ACPI_DMT_TERMINATOR 635 }; 636 637 /* 8: Platform Interrupt Source */ 638 639 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt8[] = 640 { 641 {ACPI_DMT_UINT16, ACPI_MADT8_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 642 {ACPI_DMT_FLAGS0, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 643 {ACPI_DMT_FLAGS2, ACPI_MADT8_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 644 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Type), "InterruptType", 0}, 645 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Id), "Processor ID", 0}, 646 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (Eid), "Processor EID", 0}, 647 {ACPI_DMT_UINT8, ACPI_MADT8_OFFSET (IoSapicVector), "I/O Sapic Vector", 0}, 648 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (GlobalIrq), "Interrupt", 0}, 649 {ACPI_DMT_UINT32, ACPI_MADT8_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 650 {ACPI_DMT_FLAG0, ACPI_MADT8_OFFSET (Flags), "CPEI Override", 0}, 651 ACPI_DMT_TERMINATOR 652 }; 653 654 /* 9: Processor Local X2_APIC (ACPI 4.0) */ 655 656 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt9[] = 657 { 658 {ACPI_DMT_UINT16, ACPI_MADT9_OFFSET (Reserved), "Reserved", 0}, 659 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LocalApicId), "Processor x2Apic ID", 0}, 660 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (LapicFlags), "Flags (decoded below)", DT_FLAG}, 661 {ACPI_DMT_FLAG0, ACPI_MADT9_FLAG_OFFSET (LapicFlags,0), "Processor Enabled", 0}, 662 {ACPI_DMT_UINT32, ACPI_MADT9_OFFSET (Uid), "Processor UID", 0}, 663 ACPI_DMT_TERMINATOR 664 }; 665 666 /* 10: Local X2_APIC NMI (ACPI 4.0) */ 667 668 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt10[] = 669 { 670 {ACPI_DMT_UINT16, ACPI_MADT10_OFFSET (IntiFlags), "Flags (decoded below)", DT_FLAG}, 671 {ACPI_DMT_FLAGS0, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Polarity", 0}, 672 {ACPI_DMT_FLAGS2, ACPI_MADT10_FLAG_OFFSET (IntiFlags,0), "Trigger Mode", 0}, 673 {ACPI_DMT_UINT32, ACPI_MADT10_OFFSET (Uid), "Processor UID", 0}, 674 {ACPI_DMT_UINT8, ACPI_MADT10_OFFSET (Lint), "Interrupt Input LINT", 0}, 675 {ACPI_DMT_UINT24, ACPI_MADT10_OFFSET (Reserved[0]), "Reserved", 0}, 676 ACPI_DMT_TERMINATOR 677 }; 678 679 /* 11: Generic Interrupt Controller (ACPI 5.0) */ 680 681 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt11[] = 682 { 683 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (Reserved), "Reserved", 0}, 684 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (CpuInterfaceNumber), "CPU Interface Number", 0}, 685 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Uid), "Processor UID", 0}, 686 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 687 {ACPI_DMT_FLAG0, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Processor Enabled", 0}, 688 {ACPI_DMT_FLAG1, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Performance Interrupt Trigger Mode", 0}, 689 {ACPI_DMT_FLAG2, ACPI_MADT11_FLAG_OFFSET (Flags,0), "Virtual GIC Interrupt Trigger Mode", 0}, 690 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (ParkingVersion), "Parking Protocol Version", 0}, 691 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (PerformanceInterrupt), "Performance Interrupt", 0}, 692 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ParkedAddress), "Parked Address", 0}, 693 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (BaseAddress), "Base Address", 0}, 694 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicvBaseAddress), "Virtual GIC Base Address", 0}, 695 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GichBaseAddress), "Hypervisor GIC Base Address", 0}, 696 {ACPI_DMT_UINT32, ACPI_MADT11_OFFSET (VgicInterrupt), "Virtual GIC Interrupt", 0}, 697 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (GicrBaseAddress), "Redistributor Base Address", 0}, 698 {ACPI_DMT_UINT64, ACPI_MADT11_OFFSET (ArmMpidr), "ARM MPIDR", 0}, 699 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (EfficiencyClass), "Efficiency Class", 0}, 700 {ACPI_DMT_UINT8, ACPI_MADT11_OFFSET (Reserved2[0]), "Reserved", 0}, 701 {ACPI_DMT_UINT16, ACPI_MADT11_OFFSET (SpeInterrupt), "SPE Overflow Interrupt", 0}, 702 ACPI_DMT_TERMINATOR 703 }; 704 705 /* 12: Generic Interrupt Distributor (ACPI 5.0) */ 706 707 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt12[] = 708 { 709 {ACPI_DMT_UINT16, ACPI_MADT12_OFFSET (Reserved), "Reserved", 0}, 710 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GicId), "Local GIC Hardware ID", 0}, 711 {ACPI_DMT_UINT64, ACPI_MADT12_OFFSET (BaseAddress), "Base Address", 0}, 712 {ACPI_DMT_UINT32, ACPI_MADT12_OFFSET (GlobalIrqBase), "Interrupt Base", 0}, 713 {ACPI_DMT_UINT8, ACPI_MADT12_OFFSET (Version), "Version", 0}, 714 {ACPI_DMT_UINT24, ACPI_MADT12_OFFSET (Reserved2[0]), "Reserved", 0}, 715 ACPI_DMT_TERMINATOR 716 }; 717 718 /* 13: Generic MSI Frame (ACPI 5.1) */ 719 720 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt13[] = 721 { 722 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (Reserved), "Reserved", 0}, 723 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (MsiFrameId), "MSI Frame ID", 0}, 724 {ACPI_DMT_UINT64, ACPI_MADT13_OFFSET (BaseAddress), "Base Address", 0}, 725 {ACPI_DMT_UINT32, ACPI_MADT13_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 726 {ACPI_DMT_FLAG0, ACPI_MADT13_FLAG_OFFSET (Flags,0), "Select SPI", 0}, 727 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiCount), "SPI Count", 0}, 728 {ACPI_DMT_UINT16, ACPI_MADT13_OFFSET (SpiBase), "SPI Base", 0}, 729 ACPI_DMT_TERMINATOR 730 }; 731 732 /* 14: Generic Redistributor (ACPI 5.1) */ 733 734 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt14[] = 735 { 736 {ACPI_DMT_UINT16, ACPI_MADT14_OFFSET (Reserved), "Reserved", 0}, 737 {ACPI_DMT_UINT64, ACPI_MADT14_OFFSET (BaseAddress), "Base Address", 0}, 738 {ACPI_DMT_UINT32, ACPI_MADT14_OFFSET (Length), "Length", 0}, 739 ACPI_DMT_TERMINATOR 740 }; 741 742 /* 15: Generic Translator (ACPI 6.0) */ 743 744 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt15[] = 745 { 746 {ACPI_DMT_UINT16, ACPI_MADT15_OFFSET (Reserved), "Reserved", 0}, 747 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (TranslationId), "Translation ID", 0}, 748 {ACPI_DMT_UINT64, ACPI_MADT15_OFFSET (BaseAddress), "Base Address", 0}, 749 {ACPI_DMT_UINT32, ACPI_MADT15_OFFSET (Reserved2), "Reserved", 0}, 750 ACPI_DMT_TERMINATOR 751 }; 752 753 /* 16: Multiprocessor wakeup structure (ACPI 6.4) */ 754 755 ACPI_DMTABLE_INFO AcpiDmTableInfoMadt16[] = 756 { 757 {ACPI_DMT_UINT16, ACPI_MADT16_OFFSET (MailboxVersion), "Mailbox Version", 0}, 758 {ACPI_DMT_UINT32, ACPI_MADT16_OFFSET (Reserved), "Reserved", 0}, 759 {ACPI_DMT_UINT64, ACPI_MADT16_OFFSET (BaseAddress), "Mailbox Address", 0}, 760 ACPI_DMT_TERMINATOR 761 }; 762 763 764 /******************************************************************************* 765 * 766 * MCFG - PCI Memory Mapped Configuration table and Subtable 767 * 768 ******************************************************************************/ 769 770 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg[] = 771 { 772 {ACPI_DMT_UINT64, ACPI_MCFG_OFFSET (Reserved[0]), "Reserved", 0}, 773 ACPI_DMT_TERMINATOR 774 }; 775 776 ACPI_DMTABLE_INFO AcpiDmTableInfoMcfg0[] = 777 { 778 {ACPI_DMT_UINT64, ACPI_MCFG0_OFFSET (Address), "Base Address", 0}, 779 {ACPI_DMT_UINT16, ACPI_MCFG0_OFFSET (PciSegment), "Segment Group Number", 0}, 780 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (StartBusNumber), "Start Bus Number", 0}, 781 {ACPI_DMT_UINT8, ACPI_MCFG0_OFFSET (EndBusNumber), "End Bus Number", 0}, 782 {ACPI_DMT_UINT32, ACPI_MCFG0_OFFSET (Reserved), "Reserved", 0}, 783 ACPI_DMT_TERMINATOR 784 }; 785 786 787 /******************************************************************************* 788 * 789 * MCHI - Management Controller Host Interface table 790 * 791 ******************************************************************************/ 792 793 ACPI_DMTABLE_INFO AcpiDmTableInfoMchi[] = 794 { 795 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterfaceType), "Interface Type", 0}, 796 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Protocol), "Protocol", 0}, 797 {ACPI_DMT_UINT64, ACPI_MCHI_OFFSET (ProtocolData), "Protocol Data", 0}, 798 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (InterruptType), "Interrupt Type", 0}, 799 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (Gpe), "Gpe", 0}, 800 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDeviceFlag), "Pci Device Flag", 0}, 801 {ACPI_DMT_UINT32, ACPI_MCHI_OFFSET (GlobalInterrupt), "Global Interrupt", 0}, 802 {ACPI_DMT_GAS, ACPI_MCHI_OFFSET (ControlRegister), "Control Register", 0}, 803 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciSegment), "Pci Segment", 0}, 804 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciBus), "Pci Bus", 0}, 805 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciDevice), "Pci Device", 0}, 806 {ACPI_DMT_UINT8, ACPI_MCHI_OFFSET (PciFunction), "Pci Function", 0}, 807 ACPI_DMT_TERMINATOR 808 }; 809 810 811 /******************************************************************************* 812 * 813 * MPST - Memory Power State Table 814 * 815 ******************************************************************************/ 816 817 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst[] = 818 { 819 {ACPI_DMT_UINT8, ACPI_MPST_OFFSET (ChannelId), "Channel ID", 0}, 820 {ACPI_DMT_UINT24, ACPI_MPST_OFFSET (Reserved1[0]), "Reserved", 0}, 821 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (PowerNodeCount), "Power Node Count", 0}, 822 {ACPI_DMT_UINT16, ACPI_MPST_OFFSET (Reserved2), "Reserved", 0}, 823 ACPI_DMT_TERMINATOR 824 }; 825 826 /* MPST subtables */ 827 828 /* 0: Memory Power Node Structure */ 829 830 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0[] = 831 { 832 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 833 {ACPI_DMT_FLAG0, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Node Enabled", 0}, 834 {ACPI_DMT_FLAG1, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Power Managed", 0}, 835 {ACPI_DMT_FLAG2, ACPI_MPST0_FLAG_OFFSET (Flags,0), "Hot Plug Capable", 0}, 836 837 {ACPI_DMT_UINT8, ACPI_MPST0_OFFSET (Reserved1), "Reserved", 0}, 838 {ACPI_DMT_UINT16, ACPI_MPST0_OFFSET (NodeId), "Node ID", 0}, 839 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (Length), "Length", 0}, 840 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeAddress), "Range Address", 0}, 841 {ACPI_DMT_UINT64, ACPI_MPST0_OFFSET (RangeLength), "Range Length", 0}, 842 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPowerStates), "Num Power States", 0}, 843 {ACPI_DMT_UINT32, ACPI_MPST0_OFFSET (NumPhysicalComponents), "Num Physical Components", 0}, 844 ACPI_DMT_TERMINATOR 845 }; 846 847 /* 0A: Sub-subtable - Memory Power State Structure (follows Memory Power Node above) */ 848 849 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0A[] = 850 { 851 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (PowerState), "Power State", 0}, 852 {ACPI_DMT_UINT8, ACPI_MPST0A_OFFSET (InfoIndex), "InfoIndex", 0}, 853 ACPI_DMT_TERMINATOR 854 }; 855 856 /* 0B: Sub-subtable - Physical Component ID Structure (follows Memory Power State(s) above) */ 857 858 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst0B[] = 859 { 860 {ACPI_DMT_UINT16, ACPI_MPST0B_OFFSET (ComponentId), "Component Id", 0}, 861 ACPI_DMT_TERMINATOR 862 }; 863 864 /* 01: Power Characteristics Count (follows all Power Node(s) above) */ 865 866 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst1[] = 867 { 868 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (CharacteristicsCount), "Characteristics Count", 0}, 869 {ACPI_DMT_UINT16, ACPI_MPST1_OFFSET (Reserved), "Reserved", 0}, 870 ACPI_DMT_TERMINATOR 871 }; 872 873 /* 02: Memory Power State Characteristics Structure */ 874 875 ACPI_DMTABLE_INFO AcpiDmTableInfoMpst2[] = 876 { 877 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (StructureId), "Structure ID", 0}, 878 {ACPI_DMT_UINT8, ACPI_MPST2_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 879 {ACPI_DMT_FLAG0, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Memory Preserved", 0}, 880 {ACPI_DMT_FLAG1, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Entry", 0}, 881 {ACPI_DMT_FLAG2, ACPI_MPST2_FLAG_OFFSET (Flags,0), "Auto Exit", 0}, 882 883 {ACPI_DMT_UINT16, ACPI_MPST2_OFFSET (Reserved1), "Reserved", 0}, 884 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (AveragePower), "Average Power", 0}, 885 {ACPI_DMT_UINT32, ACPI_MPST2_OFFSET (PowerSaving), "Power Saving", 0}, 886 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (ExitLatency), "Exit Latency", 0}, 887 {ACPI_DMT_UINT64, ACPI_MPST2_OFFSET (Reserved2), "Reserved", 0}, 888 ACPI_DMT_TERMINATOR 889 }; 890 891 892 /******************************************************************************* 893 * 894 * MSCT - Maximum System Characteristics Table (ACPI 4.0) 895 * 896 ******************************************************************************/ 897 898 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct[] = 899 { 900 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (ProximityOffset), "Proximity Offset", 0}, 901 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxProximityDomains), "Max Proximity Domains", 0}, 902 {ACPI_DMT_UINT32, ACPI_MSCT_OFFSET (MaxClockDomains), "Max Clock Domains", 0}, 903 {ACPI_DMT_UINT64, ACPI_MSCT_OFFSET (MaxAddress), "Max Physical Address", 0}, 904 ACPI_DMT_TERMINATOR 905 }; 906 907 /* Subtable - Maximum Proximity Domain Information. Version 1 */ 908 909 ACPI_DMTABLE_INFO AcpiDmTableInfoMsct0[] = 910 { 911 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Revision), "Revision", 0}, 912 {ACPI_DMT_UINT8, ACPI_MSCT0_OFFSET (Length), "Length", DT_LENGTH}, 913 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeStart), "Domain Range Start", 0}, 914 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (RangeEnd), "Domain Range End", 0}, 915 {ACPI_DMT_UINT32, ACPI_MSCT0_OFFSET (ProcessorCapacity), "Processor Capacity", 0}, 916 {ACPI_DMT_UINT64, ACPI_MSCT0_OFFSET (MemoryCapacity), "Memory Capacity", 0}, 917 ACPI_DMT_TERMINATOR 918 }; 919 920 921 /******************************************************************************* 922 * 923 * NFIT - NVDIMM Firmware Interface Table and Subtables - (ACPI 6.0) 924 * 925 ******************************************************************************/ 926 927 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit[] = 928 { 929 {ACPI_DMT_UINT32, ACPI_NFIT_OFFSET (Reserved), "Reserved", 0}, 930 ACPI_DMT_TERMINATOR 931 }; 932 933 /* Common Subtable header */ 934 935 ACPI_DMTABLE_INFO AcpiDmTableInfoNfitHdr[] = 936 { 937 {ACPI_DMT_NFIT, ACPI_NFITH_OFFSET (Type), "Subtable Type", 0}, 938 {ACPI_DMT_UINT16, ACPI_NFITH_OFFSET (Length), "Length", DT_LENGTH}, 939 ACPI_DMT_TERMINATOR 940 }; 941 942 /* 0: System Physical Address Range Structure */ 943 944 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit0[] = 945 { 946 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (RangeIndex), "Range Index", 0}, 947 {ACPI_DMT_UINT16, ACPI_NFIT0_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 948 {ACPI_DMT_FLAG0, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Add/Online Operation Only", 0}, 949 {ACPI_DMT_FLAG1, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Proximity Domain Valid", 0}, 950 {ACPI_DMT_FLAG2, ACPI_NFIT0_FLAG_OFFSET (Flags,0), "Location Cookie Valid", 0}, 951 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (Reserved), "Reserved", 0}, 952 {ACPI_DMT_UINT32, ACPI_NFIT0_OFFSET (ProximityDomain), "Proximity Domain", 0}, 953 {ACPI_DMT_UUID, ACPI_NFIT0_OFFSET (RangeGuid[0]), "Region Type GUID", 0}, 954 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Address), "Address Range Base", 0}, 955 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (Length), "Address Range Length", 0}, 956 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (MemoryMapping), "Memory Map Attribute", 0}, 957 {ACPI_DMT_UINT64, ACPI_NFIT0_OFFSET (LocationCookie), "Location Cookie", 0}, /* ACPI 6.4 */ 958 ACPI_DMT_TERMINATOR 959 }; 960 961 /* 1: Memory Device to System Address Range Map Structure */ 962 963 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit1[] = 964 { 965 {ACPI_DMT_UINT32, ACPI_NFIT1_OFFSET (DeviceHandle), "Device Handle", 0}, 966 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (PhysicalId), "Physical Id", 0}, 967 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionId), "Region Id", 0}, 968 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RangeIndex), "Range Index", 0}, 969 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (RegionIndex), "Control Region Index", 0}, 970 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionSize), "Region Size", 0}, 971 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (RegionOffset), "Region Offset", 0}, 972 {ACPI_DMT_UINT64, ACPI_NFIT1_OFFSET (Address), "Address Region Base", 0}, 973 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveIndex), "Interleave Index", 0}, 974 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (InterleaveWays), "Interleave Ways", 0}, 975 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Flags), "Flags", DT_FLAG}, 976 {ACPI_DMT_FLAG0, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Save to device failed", 0}, 977 {ACPI_DMT_FLAG1, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Restore from device failed", 0}, 978 {ACPI_DMT_FLAG2, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Platform flush failed", 0}, 979 {ACPI_DMT_FLAG3, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Device not armed", 0}, 980 {ACPI_DMT_FLAG4, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events observed", 0}, 981 {ACPI_DMT_FLAG5, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Health events enabled", 0}, 982 {ACPI_DMT_FLAG6, ACPI_NFIT1_FLAG_OFFSET (Flags,0), "Mapping failed", 0}, 983 {ACPI_DMT_UINT16, ACPI_NFIT1_OFFSET (Reserved), "Reserved", 0}, 984 ACPI_DMT_TERMINATOR 985 }; 986 987 /* 2: Interleave Structure */ 988 989 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2[] = 990 { 991 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (InterleaveIndex), "Interleave Index", 0}, 992 {ACPI_DMT_UINT16, ACPI_NFIT2_OFFSET (Reserved), "Reserved", 0}, 993 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineCount), "Line Count", 0}, 994 {ACPI_DMT_UINT32, ACPI_NFIT2_OFFSET (LineSize), "Line Size", 0}, 995 ACPI_DMT_TERMINATOR 996 }; 997 998 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit2a[] = 999 { 1000 {ACPI_DMT_UINT32, 0, "Line Offset", DT_OPTIONAL}, 1001 ACPI_DMT_TERMINATOR 1002 }; 1003 1004 /* 3: SMBIOS Management Information Structure */ 1005 1006 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3[] = 1007 { 1008 {ACPI_DMT_UINT32, ACPI_NFIT3_OFFSET (Reserved), "Reserved", 0}, 1009 ACPI_DMT_TERMINATOR 1010 }; 1011 1012 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit3a[] = 1013 { 1014 {ACPI_DMT_RAW_BUFFER, 0, "SMBIOS Table Entries", DT_OPTIONAL}, 1015 ACPI_DMT_TERMINATOR 1016 }; 1017 1018 /* 4: NVDIMM Control Region Structure */ 1019 1020 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit4[] = 1021 { 1022 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RegionIndex), "Region Index", 0}, 1023 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (VendorId), "Vendor Id", 0}, 1024 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (DeviceId), "Device Id", 0}, 1025 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (RevisionId), "Revision Id", 0}, 1026 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemVendorId), "Subsystem Vendor Id", 0}, 1027 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemDeviceId), "Subsystem Device Id", 0}, 1028 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (SubsystemRevisionId), "Subsystem Revision Id", 0}, 1029 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ValidFields), "Valid Fields", 0}, 1030 {ACPI_DMT_UINT8, ACPI_NFIT4_OFFSET (ManufacturingLocation), "Manufacturing Location", 0}, 1031 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (ManufacturingDate), "Manufacturing Date", 0}, 1032 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Reserved[0]), "Reserved", 0}, 1033 {ACPI_DMT_UINT32, ACPI_NFIT4_OFFSET (SerialNumber), "Serial Number", 0}, 1034 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Code), "Code", 0}, 1035 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Windows), "Window Count", 0}, 1036 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (WindowSize), "Window Size", 0}, 1037 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandOffset), "Command Offset", 0}, 1038 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (CommandSize), "Command Size", 0}, 1039 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusOffset), "Status Offset", 0}, 1040 {ACPI_DMT_UINT64, ACPI_NFIT4_OFFSET (StatusSize), "Status Size", 0}, 1041 {ACPI_DMT_UINT16, ACPI_NFIT4_OFFSET (Flags), "Flags", DT_FLAG}, 1042 {ACPI_DMT_FLAG0, ACPI_NFIT4_FLAG_OFFSET (Flags,0), "Windows buffered", 0}, 1043 {ACPI_DMT_UINT48, ACPI_NFIT4_OFFSET (Reserved1[0]), "Reserved1", 0}, 1044 ACPI_DMT_TERMINATOR 1045 }; 1046 1047 /* 5: NVDIMM Block Data Window Region Structure */ 1048 1049 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit5[] = 1050 { 1051 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (RegionIndex), "Region Index", 0}, 1052 {ACPI_DMT_UINT16, ACPI_NFIT5_OFFSET (Windows), "Window Count", 0}, 1053 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Offset), "Offset", 0}, 1054 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Size), "Size", 0}, 1055 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (Capacity), "Capacity", 0}, 1056 {ACPI_DMT_UINT64, ACPI_NFIT5_OFFSET (StartAddress), "Start Address", 0}, 1057 ACPI_DMT_TERMINATOR 1058 }; 1059 1060 /* 6: Flush Hint Address Structure */ 1061 1062 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6[] = 1063 { 1064 {ACPI_DMT_UINT32, ACPI_NFIT6_OFFSET (DeviceHandle), "Device Handle", 0}, 1065 {ACPI_DMT_UINT16, ACPI_NFIT6_OFFSET (HintCount), "Hint Count", 0}, 1066 {ACPI_DMT_UINT48, ACPI_NFIT6_OFFSET (Reserved[0]), "Reserved", 0}, 1067 ACPI_DMT_TERMINATOR 1068 }; 1069 1070 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit6a[] = 1071 { 1072 {ACPI_DMT_UINT64, 0, "Hint Address", DT_OPTIONAL}, 1073 ACPI_DMT_TERMINATOR 1074 }; 1075 1076 ACPI_DMTABLE_INFO AcpiDmTableInfoNfit7[] = 1077 { 1078 {ACPI_DMT_UINT8, ACPI_NFIT7_OFFSET (HighestCapability), "Highest Capability", 0}, 1079 {ACPI_DMT_UINT24, ACPI_NFIT7_OFFSET (Reserved[0]), "Reserved", 0}, 1080 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Capabilities), "Capabilities (decoded below)", DT_FLAG}, 1081 {ACPI_DMT_FLAG0, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Cache Flush to NVDIMM", 0}, 1082 {ACPI_DMT_FLAG1, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Flush to NVDIMM", 0}, 1083 {ACPI_DMT_FLAG2, ACPI_NFIT7_FLAG_OFFSET (Capabilities,0), "Memory Mirroring", 0}, 1084 {ACPI_DMT_UINT32, ACPI_NFIT7_OFFSET (Reserved2), "Reserved", 0}, 1085 ACPI_DMT_TERMINATOR 1086 }; 1087 1088 1089 /******************************************************************************* 1090 * 1091 * PCCT - Platform Communications Channel Table (ACPI 5.0) 1092 * 1093 ******************************************************************************/ 1094 1095 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct[] = 1096 { 1097 {ACPI_DMT_UINT32, ACPI_PCCT_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, 1098 {ACPI_DMT_FLAG0, ACPI_PCCT_FLAG_OFFSET (Flags,0), "Platform", 0}, 1099 {ACPI_DMT_UINT64, ACPI_PCCT_OFFSET (Reserved), "Reserved", 0}, 1100 ACPI_DMT_TERMINATOR 1101 }; 1102 1103 /* PCCT subtables */ 1104 1105 ACPI_DMTABLE_INFO AcpiDmTableInfoPcctHdr[] = 1106 { 1107 {ACPI_DMT_PCCT, ACPI_PCCT0_OFFSET (Header.Type), "Subtable Type", 0}, 1108 {ACPI_DMT_UINT8, ACPI_PCCT0_OFFSET (Header.Length), "Length", DT_LENGTH}, 1109 ACPI_DMT_TERMINATOR 1110 }; 1111 1112 /* 0: Generic Communications Subspace */ 1113 1114 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct0[] = 1115 { 1116 {ACPI_DMT_UINT48, ACPI_PCCT0_OFFSET (Reserved[0]), "Reserved", 0}, 1117 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (BaseAddress), "Base Address", 0}, 1118 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (Length), "Address Length", 0}, 1119 {ACPI_DMT_GAS, ACPI_PCCT0_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1120 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (PreserveMask), "Preserve Mask", 0}, 1121 {ACPI_DMT_UINT64, ACPI_PCCT0_OFFSET (WriteMask), "Write Mask", 0}, 1122 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (Latency), "Command Latency", 0}, 1123 {ACPI_DMT_UINT32, ACPI_PCCT0_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1124 {ACPI_DMT_UINT16, ACPI_PCCT0_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1125 ACPI_DMT_TERMINATOR 1126 }; 1127 1128 /* 1: HW-reduced Communications Subspace (ACPI 5.1) */ 1129 1130 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct1[] = 1131 { 1132 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1133 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1134 {ACPI_DMT_FLAG0, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1135 {ACPI_DMT_FLAG1, ACPI_PCCT1_FLAG_OFFSET (Flags,0), "Mode", 0}, 1136 {ACPI_DMT_UINT8, ACPI_PCCT1_OFFSET (Reserved), "Reserved", 0}, 1137 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (BaseAddress), "Base Address", 0}, 1138 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (Length), "Address Length", 0}, 1139 {ACPI_DMT_GAS, ACPI_PCCT1_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1140 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (PreserveMask), "Preserve Mask", 0}, 1141 {ACPI_DMT_UINT64, ACPI_PCCT1_OFFSET (WriteMask), "Write Mask", 0}, 1142 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (Latency), "Command Latency", 0}, 1143 {ACPI_DMT_UINT32, ACPI_PCCT1_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1144 {ACPI_DMT_UINT16, ACPI_PCCT1_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1145 ACPI_DMT_TERMINATOR 1146 }; 1147 1148 /* 2: HW-reduced Communications Subspace Type 2 (ACPI 6.1) */ 1149 1150 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct2[] = 1151 { 1152 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1153 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1154 {ACPI_DMT_FLAG0, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1155 {ACPI_DMT_FLAG1, ACPI_PCCT2_FLAG_OFFSET (Flags,0), "Mode", 0}, 1156 {ACPI_DMT_UINT8, ACPI_PCCT2_OFFSET (Reserved), "Reserved", 0}, 1157 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (BaseAddress), "Base Address", 0}, 1158 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (Length), "Address Length", 0}, 1159 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1160 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (PreserveMask), "Preserve Mask", 0}, 1161 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (WriteMask), "Write Mask", 0}, 1162 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (Latency), "Command Latency", 0}, 1163 {ACPI_DMT_UINT32, ACPI_PCCT2_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1164 {ACPI_DMT_UINT16, ACPI_PCCT2_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1165 {ACPI_DMT_GAS, ACPI_PCCT2_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1166 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1167 {ACPI_DMT_UINT64, ACPI_PCCT2_OFFSET (AckWriteMask), "ACK Write Mask", 0}, 1168 ACPI_DMT_TERMINATOR 1169 }; 1170 1171 /* 3: Extended PCC Master Subspace Type 3 (ACPI 6.2) */ 1172 1173 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct3[] = 1174 { 1175 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1176 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1177 {ACPI_DMT_FLAG0, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1178 {ACPI_DMT_FLAG1, ACPI_PCCT3_FLAG_OFFSET (Flags,0), "Mode", 0}, 1179 {ACPI_DMT_UINT8, ACPI_PCCT3_OFFSET (Reserved1), "Reserved", 0}, 1180 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (BaseAddress), "Base Address", 0}, 1181 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Length), "Address Length", 0}, 1182 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1183 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (PreserveMask), "Preserve Mask", 0}, 1184 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (WriteMask), "Write Mask", 0}, 1185 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (Latency), "Command Latency", 0}, 1186 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1187 {ACPI_DMT_UINT32, ACPI_PCCT3_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1188 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1189 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1190 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1191 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (Reserved2), "Reserved", 0}, 1192 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1193 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1194 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1195 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1196 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1197 {ACPI_DMT_GAS, ACPI_PCCT3_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1198 {ACPI_DMT_UINT64, ACPI_PCCT3_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1199 ACPI_DMT_TERMINATOR 1200 }; 1201 1202 /* 4: Extended PCC Slave Subspace Type 4 (ACPI 6.2) */ 1203 1204 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct4[] = 1205 { 1206 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (PlatformInterrupt), "Platform Interrupt", 0}, 1207 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1208 {ACPI_DMT_FLAG0, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Polarity", 0}, 1209 {ACPI_DMT_FLAG1, ACPI_PCCT4_FLAG_OFFSET (Flags,0), "Mode", 0}, 1210 {ACPI_DMT_UINT8, ACPI_PCCT4_OFFSET (Reserved1), "Reserved", 0}, 1211 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (BaseAddress), "Base Address", 0}, 1212 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Length), "Address Length", 0}, 1213 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1214 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (PreserveMask), "Preserve Mask", 0}, 1215 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (WriteMask), "Write Mask", 0}, 1216 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (Latency), "Command Latency", 0}, 1217 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MaxAccessRate), "Maximum Access Rate", 0}, 1218 {ACPI_DMT_UINT32, ACPI_PCCT4_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1219 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (PlatformAckRegister), "Platform ACK Register", 0}, 1220 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckPreserveMask), "ACK Preserve Mask", 0}, 1221 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (AckSetMask), "ACK Set Mask", 0}, 1222 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (Reserved2), "Reserved", 0}, 1223 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1224 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1225 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (CmdUpdateRegister), "Command Update Register", 0}, 1226 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdatePreserveMask), "Command Update Preserve Mask", 0}, 1227 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (CmdUpdateSetMask), "Command Update Set Mask", 0}, 1228 {ACPI_DMT_GAS, ACPI_PCCT4_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1229 {ACPI_DMT_UINT64, ACPI_PCCT4_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1230 ACPI_DMT_TERMINATOR 1231 }; 1232 1233 /* 5: HW Registers based Communications Subspace */ 1234 1235 ACPI_DMTABLE_INFO AcpiDmTableInfoPcct5[] = 1236 { 1237 {ACPI_DMT_UINT16, ACPI_PCCT5_OFFSET (Version), "Version", 0}, 1238 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (BaseAddress), "Base Address", 0}, 1239 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (Length), "Length", 0}, 1240 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (DoorbellRegister), "Doorbell Register", 0}, 1241 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellPreserve), "Preserve Mask", 0}, 1242 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (DoorbellWrite), "Write Mask", 0}, 1243 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (CmdCompleteRegister), "Command Complete Register", 0}, 1244 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (CmdCompleteMask), "Command Complete Check Mask", 0}, 1245 {ACPI_DMT_GAS, ACPI_PCCT5_OFFSET (ErrorStatusRegister), "Error Status Register", 0}, 1246 {ACPI_DMT_UINT64, ACPI_PCCT5_OFFSET (ErrorStatusMask), "Error Status Mask", 0}, 1247 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (NominalLatency), "Nominal Latency", 0}, 1248 {ACPI_DMT_UINT32, ACPI_PCCT5_OFFSET (MinTurnaroundTime), "Minimum Turnaround Time", 0}, 1249 ACPI_DMT_TERMINATOR 1250 }; 1251 1252 1253 /******************************************************************************* 1254 * 1255 * PDTT - Platform Debug Trigger Table (ACPI 6.2) 1256 * 1257 ******************************************************************************/ 1258 1259 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt[] = 1260 { 1261 {ACPI_DMT_UINT8, ACPI_PDTT_OFFSET (TriggerCount), "Trigger Count", 0}, 1262 {ACPI_DMT_UINT24, ACPI_PDTT_OFFSET (Reserved), "Reserved", 0}, 1263 {ACPI_DMT_UINT32, ACPI_PDTT_OFFSET (ArrayOffset), "Array Offset", 0}, 1264 ACPI_DMT_TERMINATOR 1265 }; 1266 1267 ACPI_DMTABLE_INFO AcpiDmTableInfoPdtt0[] = 1268 { 1269 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (SubchannelId), "Subchannel Id", 0}, 1270 {ACPI_DMT_UINT8, ACPI_PDTT0_OFFSET (Flags), "Flags (Decoded Below)", DT_FLAG}, 1271 {ACPI_DMT_FLAG0, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Runtime Trigger", 0}, 1272 {ACPI_DMT_FLAG1, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Wait for Completion", 0}, 1273 {ACPI_DMT_FLAG2, ACPI_PDTT0_FLAG_OFFSET (Flags,0), "Trigger Order", 0}, 1274 ACPI_DMT_TERMINATOR 1275 }; 1276 1277 1278 /******************************************************************************* 1279 * 1280 * PHAT - Platform Health Assessment Table (ACPI 6.4) 1281 * 1282 ******************************************************************************/ 1283 1284 ACPI_DMTABLE_INFO AcpiDmTableInfoPhatHdr[] = 1285 { 1286 {ACPI_DMT_PHAT, ACPI_PHATH_OFFSET (Type), "Subtable Type", 0}, 1287 {ACPI_DMT_UINT16, ACPI_PHATH_OFFSET (Length), "Length", 0}, 1288 {ACPI_DMT_UINT8, ACPI_PHATH_OFFSET (Revision), "Revision", 0}, 1289 ACPI_DMT_TERMINATOR 1290 }; 1291 1292 /* 0: Firmware version table */ 1293 1294 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0[] = 1295 { 1296 {ACPI_DMT_UINT24, ACPI_PHAT0_OFFSET (Reserved), "Reserved", 0}, 1297 {ACPI_DMT_UINT32, ACPI_PHAT0_OFFSET (ElementCount), "Element Count", 0}, 1298 ACPI_DMT_TERMINATOR 1299 }; 1300 1301 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat0a[] = 1302 { 1303 {ACPI_DMT_UUID, ACPI_PHAT0A_OFFSET (Guid), "GUID", 0}, 1304 {ACPI_DMT_UINT64, ACPI_PHAT0A_OFFSET (VersionValue), "Version Value", 0}, 1305 {ACPI_DMT_UINT32, ACPI_PHAT0A_OFFSET (ProducerId), "Producer ID", 0}, 1306 ACPI_DMT_TERMINATOR 1307 }; 1308 1309 /* 1: Firmware Health Data Record */ 1310 1311 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1[] = 1312 { 1313 {ACPI_DMT_UINT16, ACPI_PHAT1_OFFSET (Reserved), "Reserved", 0}, 1314 {ACPI_DMT_UINT8, ACPI_PHAT1_OFFSET (Health), "Health", 0}, 1315 {ACPI_DMT_UUID, ACPI_PHAT1_OFFSET (DeviceGuid), "Device GUID", 0}, 1316 {ACPI_DMT_UINT32, ACPI_PHAT1_OFFSET (DeviceSpecificOffset), "Device specific offset", 0}, 1317 ACPI_DMT_TERMINATOR 1318 }; 1319 1320 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1a[] = 1321 { 1322 {ACPI_DMT_STRING, 0, "Namepath", 0}, 1323 ACPI_DMT_TERMINATOR 1324 }; 1325 1326 ACPI_DMTABLE_INFO AcpiDmTableInfoPhat1b[] = 1327 { 1328 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, 1329 ACPI_DMT_TERMINATOR 1330 }; 1331 1332 1333 /******************************************************************************* 1334 * 1335 * PMTT - Platform Memory Topology Table 1336 * 1337 ******************************************************************************/ 1338 1339 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt[] = 1340 { 1341 {ACPI_DMT_UINT32, ACPI_PMTT_OFFSET (MemoryDeviceCount), "Memory Device Count", 0}, 1342 ACPI_DMT_TERMINATOR 1343 }; 1344 1345 /* Common Subtable header (one per Subtable) */ 1346 1347 #define ACPI_DM_PMTT_HEADER \ 1348 {ACPI_DMT_PMTT, ACPI_PMTTH_OFFSET (Type), "Subtable Type", 0}, \ 1349 {ACPI_DMT_UINT8, ACPI_PMTTH_OFFSET (Reserved1), "Reserved", 0}, \ 1350 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Length), "Length", DT_LENGTH}, \ 1351 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Flags), "Flags (decoded below)", DT_FLAG}, \ 1352 {ACPI_DMT_FLAG0, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Top-level Device", 0}, \ 1353 {ACPI_DMT_FLAG1, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Physical Element", 0}, \ 1354 {ACPI_DMT_FLAGS2, ACPI_PMTTH_FLAG_OFFSET (Flags,0), "Memory Type", 0}, \ 1355 {ACPI_DMT_UINT16, ACPI_PMTTH_OFFSET (Reserved2), "Reserved", 0}, \ 1356 {ACPI_DMT_UINT32, ACPI_PMTTH_OFFSET (MemoryDeviceCount), "Memory Device Count", 0} 1357 1358 /* PMTT Subtables */ 1359 1360 /* 0: Socket */ 1361 1362 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt0[] = 1363 { 1364 ACPI_DM_PMTT_HEADER, 1365 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (SocketId), "Socket ID", 0}, 1366 {ACPI_DMT_UINT16, ACPI_PMTT0_OFFSET (Reserved), "Reserved", 0}, 1367 ACPI_DMT_TERMINATOR 1368 }; 1369 1370 /* 1: Memory Controller */ 1371 1372 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt1[] = 1373 { 1374 ACPI_DM_PMTT_HEADER, 1375 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (ControllerId), "Controller ID", 0}, 1376 {ACPI_DMT_UINT16, ACPI_PMTT1_OFFSET (Reserved), "Reserved", 0}, 1377 ACPI_DMT_TERMINATOR 1378 }; 1379 1380 /* 2: Physical Component */ 1381 1382 ACPI_DMTABLE_INFO AcpiDmTableInfoPmtt2[] = 1383 { 1384 ACPI_DM_PMTT_HEADER, 1385 {ACPI_DMT_UINT32, ACPI_PMTT2_OFFSET (BiosHandle), "Bios Handle", 0}, 1386 ACPI_DMT_TERMINATOR 1387 }; 1388 1389 /* 0xFF: Vendor Specific */ 1390 1391 ACPI_DMTABLE_INFO AcpiDmTableInfoPmttVendor[] = 1392 { 1393 ACPI_DM_PMTT_HEADER, 1394 {ACPI_DMT_UUID, ACPI_PMTT_VENDOR_OFFSET (TypeUuid), "Type Uuid", 0}, 1395 {ACPI_DMT_PMTT_VENDOR, ACPI_PMTT_VENDOR_OFFSET (Specific), "Vendor Data", 0}, 1396 ACPI_DMT_TERMINATOR 1397 }; 1398 1399 1400 /******************************************************************************* 1401 * 1402 * PPTT - Processor Properties Topology Table (ACPI 6.2) 1403 * 1404 ******************************************************************************/ 1405 1406 /* Main table consists of only the standard ACPI header - subtables follow */ 1407 1408 /* Common Subtable header (one per Subtable) */ 1409 1410 ACPI_DMTABLE_INFO AcpiDmTableInfoPpttHdr[] = 1411 { 1412 {ACPI_DMT_PPTT, ACPI_PPTTH_OFFSET (Type), "Subtable Type", 0}, 1413 {ACPI_DMT_UINT8, ACPI_PPTTH_OFFSET (Length), "Length", 0}, 1414 ACPI_DMT_TERMINATOR 1415 }; 1416 1417 /* 0: Processor hierarchy node */ 1418 1419 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0[] = 1420 { 1421 {ACPI_DMT_UINT16, ACPI_PPTT0_OFFSET (Reserved), "Reserved", 0}, 1422 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Flags), "Flags (decoded below)", 0}, 1423 {ACPI_DMT_FLAG0, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Physical package", 0}, 1424 {ACPI_DMT_FLAG1, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "ACPI Processor ID valid", 0}, 1425 {ACPI_DMT_FLAG2, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Processor is a thread", 0}, 1426 {ACPI_DMT_FLAG3, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Node is a leaf", 0}, 1427 {ACPI_DMT_FLAG4, ACPI_PPTT0_FLAG_OFFSET (Flags,0), "Identical Implementation", 0}, 1428 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (Parent), "Parent", 0}, 1429 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (AcpiProcessorId), "ACPI Processor ID", 0}, 1430 {ACPI_DMT_UINT32, ACPI_PPTT0_OFFSET (NumberOfPrivResources), "Private Resource Number", 0}, 1431 ACPI_DMT_TERMINATOR 1432 }; 1433 1434 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt0a[] = 1435 { 1436 {ACPI_DMT_UINT32, 0, "Private Resource", DT_OPTIONAL}, 1437 ACPI_DMT_TERMINATOR 1438 }; 1439 1440 /* 1: Cache type */ 1441 1442 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1[] = 1443 { 1444 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (Reserved), "Reserved", 0}, 1445 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Flags), "Flags (decoded below)", 0}, 1446 {ACPI_DMT_FLAG0, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Size valid", 0}, 1447 {ACPI_DMT_FLAG1, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Number of Sets valid", 0}, 1448 {ACPI_DMT_FLAG2, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Associativity valid", 0}, 1449 {ACPI_DMT_FLAG3, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Allocation Type valid", 0}, 1450 {ACPI_DMT_FLAG4, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache Type valid", 0}, 1451 {ACPI_DMT_FLAG5, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Write Policy valid", 0}, 1452 {ACPI_DMT_FLAG6, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Line Size valid", 0}, 1453 {ACPI_DMT_FLAG7, ACPI_PPTT1_FLAG_OFFSET (Flags,0), "Cache ID valid", 0}, 1454 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NextLevelOfCache), "Next Level of Cache", 0}, 1455 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (Size), "Size", 0}, 1456 {ACPI_DMT_UINT32, ACPI_PPTT1_OFFSET (NumberOfSets), "Number of Sets", 0}, 1457 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Associativity), "Associativity", 0}, 1458 {ACPI_DMT_UINT8, ACPI_PPTT1_OFFSET (Attributes), "Attributes", 0}, 1459 {ACPI_DMT_FLAGS0, ACPI_PPTT1_OFFSET (Attributes), "Allocation Type", 0}, 1460 {ACPI_DMT_FLAGS2, ACPI_PPTT1_OFFSET (Attributes), "Cache Type", 0}, 1461 {ACPI_DMT_FLAG4, ACPI_PPTT1_OFFSET (Attributes), "Write Policy", 0}, 1462 {ACPI_DMT_UINT16, ACPI_PPTT1_OFFSET (LineSize), "Line Size", 0}, 1463 ACPI_DMT_TERMINATOR 1464 }; 1465 1466 /* 1: cache type v1 */ 1467 1468 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt1a[] = 1469 { 1470 {ACPI_DMT_UINT32, ACPI_PPTT1A_OFFSET (CacheId), "Cache ID", 0}, 1471 ACPI_DMT_TERMINATOR 1472 }; 1473 1474 /* 2: ID */ 1475 1476 ACPI_DMTABLE_INFO AcpiDmTableInfoPptt2[] = 1477 { 1478 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (Reserved), "Reserved", 0}, 1479 {ACPI_DMT_UINT32, ACPI_PPTT2_OFFSET (VendorId), "Vendor ID", 0}, 1480 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level1Id), "Level1 ID", 0}, 1481 {ACPI_DMT_UINT64, ACPI_PPTT2_OFFSET (Level2Id), "Level2 ID", 0}, 1482 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MajorRev), "Major revision", 0}, 1483 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (MinorRev), "Minor revision", 0}, 1484 {ACPI_DMT_UINT16, ACPI_PPTT2_OFFSET (SpinRev), "Spin revision", 0}, 1485 ACPI_DMT_TERMINATOR 1486 }; 1487 1488 1489 /******************************************************************************* 1490 * 1491 * PRMT - Platform Runtime Mechanism Table 1492 * Version 1 1493 * 1494 ******************************************************************************/ 1495 1496 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHdr[] = 1497 { 1498 {ACPI_DMT_UUID, ACPI_PRMTH_OFFSET (PlatformGuid[0]), "Platform GUID", 0}, 1499 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoOffset), "Module info offset", 0}, 1500 {ACPI_DMT_UINT32, ACPI_PRMTH_OFFSET (ModuleInfoCount), "Module info count", 0}, 1501 ACPI_DMT_NEW_LINE, 1502 ACPI_DMT_TERMINATOR 1503 1504 }; 1505 1506 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtModule[] = 1507 { 1508 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Revision), "Revision", 0}, 1509 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (Length), "Length", 0}, 1510 {ACPI_DMT_UUID, ACPI_PRMT0_OFFSET (ModuleGuid[0]), "Module GUID", 0}, 1511 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MajorRev), "Major Revision", 0}, 1512 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (MinorRev), "Minor Revision", 0}, 1513 {ACPI_DMT_UINT16, ACPI_PRMT0_OFFSET (HandlerInfoCount), "Handler Info Count", 0}, 1514 {ACPI_DMT_UINT32, ACPI_PRMT0_OFFSET (HandlerInfoOffset), "Handler Info Offset", 0}, 1515 {ACPI_DMT_UINT64, ACPI_PRMT0_OFFSET (MmioListPointer), "Mmio List pointer", 0}, 1516 ACPI_DMT_NEW_LINE, 1517 ACPI_DMT_TERMINATOR 1518 1519 }; 1520 1521 ACPI_DMTABLE_INFO AcpiDmTableInfoPrmtHandler[] = 1522 { 1523 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Revision), "Revision", 0}, 1524 {ACPI_DMT_UINT16, ACPI_PRMT1_OFFSET (Length), "Length", 0}, 1525 {ACPI_DMT_UUID, ACPI_PRMT1_OFFSET (HandlerGuid[0]), "Handler GUID", 0}, 1526 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (HandlerAddress), "Handler address", 0}, 1527 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (StaticDataBufferAddress),"Satic Data Address", 0}, 1528 {ACPI_DMT_UINT64, ACPI_PRMT1_OFFSET (AcpiParamBufferAddress), "ACPI Parameter Address", 0}, 1529 ACPI_DMT_NEW_LINE, 1530 ACPI_DMT_TERMINATOR 1531 1532 }; 1533 1534 1535 /******************************************************************************* 1536 * 1537 * RASF - RAS Feature table 1538 * 1539 ******************************************************************************/ 1540 1541 ACPI_DMTABLE_INFO AcpiDmTableInfoRasf[] = 1542 { 1543 {ACPI_DMT_BUF12, ACPI_RASF_OFFSET (ChannelId[0]), "Channel ID", 0}, 1544 ACPI_DMT_TERMINATOR 1545 }; 1546 1547 1548 /******************************************************************************* 1549 * 1550 * RGRT - Regulatory Graphics Resource Table 1551 * 1552 ******************************************************************************/ 1553 1554 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt[] = 1555 { 1556 {ACPI_DMT_UINT16, ACPI_RGRT_OFFSET (Version), "Version", 0}, 1557 {ACPI_DMT_RGRT, ACPI_RGRT_OFFSET (ImageType), "Image Type", 0}, 1558 {ACPI_DMT_UINT8, ACPI_RGRT_OFFSET (Reserved), "Reserved", 0}, 1559 ACPI_DMT_TERMINATOR 1560 }; 1561 1562 /* 1563 * We treat the binary image field as its own subtable (to make 1564 * ACPI_DMT_RAW_BUFFER work properly). 1565 */ 1566 ACPI_DMTABLE_INFO AcpiDmTableInfoRgrt0[] = 1567 { 1568 {ACPI_DMT_RAW_BUFFER, 0, "Image", 0}, 1569 ACPI_DMT_TERMINATOR 1570 }; 1571 1572 1573 /******************************************************************************* 1574 * 1575 * S3PT - S3 Performance Table 1576 * 1577 ******************************************************************************/ 1578 1579 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt[] = 1580 { 1581 {ACPI_DMT_SIG, ACPI_S3PT_OFFSET (Signature[0]), "Signature", 0}, 1582 {ACPI_DMT_UINT32, ACPI_S3PT_OFFSET (Length), "Length", DT_LENGTH}, 1583 ACPI_DMT_TERMINATOR 1584 }; 1585 1586 /* S3PT subtable header */ 1587 1588 ACPI_DMTABLE_INFO AcpiDmTableInfoS3ptHdr[] = 1589 { 1590 {ACPI_DMT_UINT16, ACPI_S3PTH_OFFSET (Type), "Type", 0}, 1591 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Length), "Length", DT_LENGTH}, 1592 {ACPI_DMT_UINT8, ACPI_S3PTH_OFFSET (Revision), "Revision", 0}, 1593 ACPI_DMT_TERMINATOR 1594 }; 1595 1596 /* 0: Basic S3 Resume Performance Record */ 1597 1598 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt0[] = 1599 { 1600 {ACPI_DMT_UINT32, ACPI_S3PT0_OFFSET (ResumeCount), "Resume Count", 0}, 1601 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (FullResume), "Full Resume", 0}, 1602 {ACPI_DMT_UINT64, ACPI_S3PT0_OFFSET (AverageResume), "Average Resume", 0}, 1603 ACPI_DMT_TERMINATOR 1604 }; 1605 1606 /* 1: Basic S3 Suspend Performance Record */ 1607 1608 ACPI_DMTABLE_INFO AcpiDmTableInfoS3pt1[] = 1609 { 1610 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendStart), "Suspend Start", 0}, 1611 {ACPI_DMT_UINT64, ACPI_S3PT1_OFFSET (SuspendEnd), "Suspend End", 0}, 1612 ACPI_DMT_TERMINATOR 1613 }; 1614 1615 1616 /******************************************************************************* 1617 * 1618 * SBST - Smart Battery Specification Table 1619 * 1620 ******************************************************************************/ 1621 1622 ACPI_DMTABLE_INFO AcpiDmTableInfoSbst[] = 1623 { 1624 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (WarningLevel), "Warning Level", 0}, 1625 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (LowLevel), "Low Level", 0}, 1626 {ACPI_DMT_UINT32, ACPI_SBST_OFFSET (CriticalLevel), "Critical Level", 0}, 1627 ACPI_DMT_TERMINATOR 1628 }; 1629 1630 1631 /******************************************************************************* 1632 * 1633 * SDEI - Software Delegated Exception Interface Descriptor Table 1634 * 1635 ******************************************************************************/ 1636 1637 ACPI_DMTABLE_INFO AcpiDmTableInfoSdei[] = 1638 { 1639 ACPI_DMT_TERMINATOR 1640 }; 1641 1642 1643 /******************************************************************************* 1644 * 1645 * SDEV - Secure Devices Table (ACPI 6.2) 1646 * 1647 ******************************************************************************/ 1648 1649 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev[] = 1650 { 1651 ACPI_DMT_TERMINATOR 1652 }; 1653 1654 /* Common Subtable header (one per Subtable) */ 1655 1656 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevHdr[] = 1657 { 1658 {ACPI_DMT_SDEV, ACPI_SDEVH_OFFSET (Type), "Subtable Type", 0}, 1659 {ACPI_DMT_UINT8, ACPI_SDEVH_OFFSET (Flags), "Flags (decoded below)", 0}, 1660 {ACPI_DMT_FLAG0, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Allow handoff to unsecure OS", 0}, 1661 {ACPI_DMT_FLAG1, ACPI_SDEVH_FLAG_OFFSET (Flags,0), "Secure access components present", 0}, 1662 {ACPI_DMT_UINT16, ACPI_SDEVH_OFFSET (Length), "Length", 0}, 1663 ACPI_DMT_TERMINATOR 1664 }; 1665 1666 /* SDEV Subtables */ 1667 1668 /* 0: Namespace Device Based Secure Device Structure */ 1669 1670 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0[] = 1671 { 1672 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdOffset), "Device ID Offset", 0}, 1673 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (DeviceIdLength), "Device ID Length", 0}, 1674 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 1675 {ACPI_DMT_UINT16, ACPI_SDEV0_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 1676 ACPI_DMT_TERMINATOR 1677 }; 1678 1679 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0a[] = 1680 { 1681 {ACPI_DMT_STRING, 0, "Namepath", 0}, 1682 ACPI_DMT_TERMINATOR 1683 }; 1684 1685 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev0b[] = 1686 { 1687 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentOffset), "Secure Access Components Offset", 0}, 1688 {ACPI_DMT_UINT16, ACPI_SDEV0B_OFFSET (SecureComponentLength), "Secure Access Components Length", 0}, 1689 ACPI_DMT_TERMINATOR 1690 }; 1691 1692 /* Secure access components */ 1693 1694 /* Common secure access components header secure access component */ 1695 1696 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompHdr[] = 1697 { 1698 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Type), "Secure Component Type", 0}, 1699 {ACPI_DMT_UINT8, ACPI_SDEVCH_OFFSET (Flags), "Flags (decoded below)", 0}, 1700 {ACPI_DMT_UINT16, ACPI_SDEVCH_OFFSET (Length), "Length", 0}, 1701 ACPI_DMT_TERMINATOR 1702 }; 1703 1704 /* 0: Identification Based Secure Access Component */ 1705 1706 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompId[] = 1707 { 1708 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdOffset), "Hardware ID Offset", 0}, 1709 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareIdLength), "Hardware ID Length", 0}, 1710 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdOffset), "Subsystem ID Offset", 0}, 1711 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (SubsystemIdLength), "Subsystem ID Length", 0}, 1712 {ACPI_DMT_UINT16, ACPI_SDEVC0_OFFSET (HardwareRevision), "Hardware Revision", 0}, 1713 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (HardwareRevPresent), "Hardware Rev Present", 0}, 1714 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (ClassCodePresent), "Class Code Present", 0}, 1715 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciBaseClass), "PCI Base Class", 0}, 1716 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciSubClass), "PCI SubClass", 0}, 1717 {ACPI_DMT_UINT8, ACPI_SDEVC0_OFFSET (PciProgrammingXface), "PCI Programming Xface", 0}, 1718 ACPI_DMT_TERMINATOR 1719 }; 1720 1721 /* 1: Memory Based Secure Access Component */ 1722 1723 ACPI_DMTABLE_INFO AcpiDmTableInfoSdevSecCompMem[] = 1724 { 1725 {ACPI_DMT_UINT32, ACPI_SDEVC1_OFFSET (Reserved), "Reserved", 0}, 1726 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryBaseAddress), "Memory Base Address", 0}, 1727 {ACPI_DMT_UINT64, ACPI_SDEVC1_OFFSET (MemoryLength), "Memory Length", 0}, 1728 ACPI_DMT_TERMINATOR 1729 }; 1730 1731 1732 /* 1: PCIe Endpoint Device Based Device Structure */ 1733 1734 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1[] = 1735 { 1736 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (Segment), "Segment", 0}, 1737 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (StartBus), "Start Bus", 0}, 1738 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathOffset), "Path Offset", 0}, 1739 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (PathLength), "Path Length", 0}, 1740 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataOffset), "Vendor Data Offset", 0}, 1741 {ACPI_DMT_UINT16, ACPI_SDEV1_OFFSET (VendorDataLength), "Vendor Data Length", 0}, 1742 ACPI_DMT_TERMINATOR 1743 }; 1744 1745 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1a[] = 1746 { 1747 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Device), "Device", 0}, 1748 {ACPI_DMT_UINT8, ACPI_SDEV1A_OFFSET (Function), "Function", 0}, 1749 ACPI_DMT_TERMINATOR 1750 }; 1751 1752 ACPI_DMTABLE_INFO AcpiDmTableInfoSdev1b[] = 1753 { 1754 {ACPI_DMT_RAW_BUFFER, 0, "Vendor Data", 0}, /*, DT_OPTIONAL}, */ 1755 ACPI_DMT_TERMINATOR 1756 }; 1757 1758 /*! [End] no source code translation !*/ 1759
Indexes created Mon Sep 29 21:09:56 GMT 2025