amdgpu_pci.c revision 1.5.2.2
1 1.5.2.2 pgoyette /* $NetBSD: amdgpu_pci.c,v 1.5.2.2 2018/09/06 06:56:09 pgoyette Exp $ */ 2 1.5.2.2 pgoyette 3 1.5.2.2 pgoyette /*- 4 1.5.2.2 pgoyette * Copyright (c) 2018 The NetBSD Foundation, Inc. 5 1.5.2.2 pgoyette * All rights reserved. 6 1.5.2.2 pgoyette * 7 1.5.2.2 pgoyette * This code is derived from software contributed to The NetBSD Foundation 8 1.5.2.2 pgoyette * by Taylor R. Campbell. 9 1.5.2.2 pgoyette * 10 1.5.2.2 pgoyette * Redistribution and use in source and binary forms, with or without 11 1.5.2.2 pgoyette * modification, are permitted provided that the following conditions 12 1.5.2.2 pgoyette * are met: 13 1.5.2.2 pgoyette * 1. Redistributions of source code must retain the above copyright 14 1.5.2.2 pgoyette * notice, this list of conditions and the following disclaimer. 15 1.5.2.2 pgoyette * 2. Redistributions in binary form must reproduce the above copyright 16 1.5.2.2 pgoyette * notice, this list of conditions and the following disclaimer in the 17 1.5.2.2 pgoyette * documentation and/or other materials provided with the distribution. 18 1.5.2.2 pgoyette * 19 1.5.2.2 pgoyette * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 1.5.2.2 pgoyette * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 1.5.2.2 pgoyette * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 1.5.2.2 pgoyette * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 1.5.2.2 pgoyette * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 1.5.2.2 pgoyette * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 1.5.2.2 pgoyette * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 1.5.2.2 pgoyette * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 1.5.2.2 pgoyette * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 1.5.2.2 pgoyette * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 1.5.2.2 pgoyette * POSSIBILITY OF SUCH DAMAGE. 30 1.5.2.2 pgoyette */ 31 1.5.2.2 pgoyette 32 1.5.2.2 pgoyette #include <sys/cdefs.h> 33 1.5.2.2 pgoyette __KERNEL_RCSID(0, "$NetBSD: amdgpu_pci.c,v 1.5.2.2 2018/09/06 06:56:09 pgoyette Exp $"); 34 1.5.2.2 pgoyette 35 1.5.2.2 pgoyette #include <sys/types.h> 36 1.5.2.2 pgoyette #include <sys/queue.h> 37 1.5.2.2 pgoyette #include <sys/systm.h> 38 1.5.2.2 pgoyette #include <sys/workqueue.h> 39 1.5.2.2 pgoyette 40 1.5.2.2 pgoyette #include <drm/drmP.h> 41 1.5.2.2 pgoyette 42 1.5.2.2 pgoyette #include <amdgpu.h> 43 1.5.2.2 pgoyette #include "amdgpu_drv.h" 44 1.5.2.2 pgoyette #include "amdgpu_task.h" 45 1.5.2.2 pgoyette 46 1.5.2.2 pgoyette SIMPLEQ_HEAD(amdgpu_task_head, amdgpu_task); 47 1.5.2.2 pgoyette 48 1.5.2.2 pgoyette struct amdgpu_softc { 49 1.5.2.2 pgoyette device_t sc_dev; 50 1.5.2.2 pgoyette struct pci_attach_args sc_pa; 51 1.5.2.2 pgoyette enum { 52 1.5.2.2 pgoyette AMDGPU_TASK_ATTACH, 53 1.5.2.2 pgoyette AMDGPU_TASK_WORKQUEUE, 54 1.5.2.2 pgoyette } sc_task_state; 55 1.5.2.2 pgoyette union { 56 1.5.2.2 pgoyette struct workqueue *workqueue; 57 1.5.2.2 pgoyette struct amdgpu_task_head attach; 58 1.5.2.2 pgoyette } sc_task_u; 59 1.5.2.2 pgoyette struct drm_device *sc_drm_dev; 60 1.5.2.2 pgoyette struct pci_dev sc_pci_dev; 61 1.5.2.2 pgoyette }; 62 1.5.2.2 pgoyette 63 1.5.2.2 pgoyette static bool amdgpu_pci_lookup(const struct pci_attach_args *, 64 1.5.2.2 pgoyette unsigned long *); 65 1.5.2.2 pgoyette 66 1.5.2.2 pgoyette static int amdgpu_match(device_t, cfdata_t, void *); 67 1.5.2.2 pgoyette static void amdgpu_attach(device_t, device_t, void *); 68 1.5.2.2 pgoyette static void amdgpu_attach_real(device_t); 69 1.5.2.2 pgoyette static int amdgpu_detach(device_t, int); 70 1.5.2.2 pgoyette static bool amdgpu_do_suspend(device_t, const pmf_qual_t *); 71 1.5.2.2 pgoyette static bool amdgpu_do_resume(device_t, const pmf_qual_t *); 72 1.5.2.2 pgoyette 73 1.5.2.2 pgoyette static void amdgpu_task_work(struct work *, void *); 74 1.5.2.2 pgoyette 75 1.5.2.2 pgoyette CFATTACH_DECL_NEW(amdgpu, sizeof(struct amdgpu_softc), 76 1.5.2.2 pgoyette amdgpu_match, amdgpu_attach, amdgpu_detach, NULL); 77 1.5.2.2 pgoyette 78 1.5.2.2 pgoyette /* XXX Kludge to get these from amdgpu_drv.c. */ 79 1.5.2.2 pgoyette extern struct drm_driver *const amdgpu_drm_driver; 80 1.5.2.2 pgoyette extern const struct pci_device_id *const amdgpu_device_ids; 81 1.5.2.2 pgoyette extern const size_t amdgpu_n_device_ids; 82 1.5.2.2 pgoyette 83 1.5.2.2 pgoyette static bool 84 1.5.2.2 pgoyette amdgpu_pci_lookup(const struct pci_attach_args *pa, unsigned long *flags) 85 1.5.2.2 pgoyette { 86 1.5.2.2 pgoyette size_t i; 87 1.5.2.2 pgoyette 88 1.5.2.2 pgoyette for (i = 0; i < amdgpu_n_device_ids; i++) { 89 1.5.2.2 pgoyette if ((PCI_VENDOR(pa->pa_id) == amdgpu_device_ids[i].vendor) && 90 1.5.2.2 pgoyette (PCI_PRODUCT(pa->pa_id) == amdgpu_device_ids[i].device)) 91 1.5.2.2 pgoyette break; 92 1.5.2.2 pgoyette } 93 1.5.2.2 pgoyette 94 1.5.2.2 pgoyette /* Did we find it? */ 95 1.5.2.2 pgoyette if (i == amdgpu_n_device_ids) 96 1.5.2.2 pgoyette return false; 97 1.5.2.2 pgoyette 98 1.5.2.2 pgoyette if (flags) 99 1.5.2.2 pgoyette *flags = amdgpu_device_ids[i].driver_data; 100 1.5.2.2 pgoyette return true; 101 1.5.2.2 pgoyette } 102 1.5.2.2 pgoyette 103 1.5.2.2 pgoyette static int 104 1.5.2.2 pgoyette amdgpu_match(device_t parent, cfdata_t match, void *aux) 105 1.5.2.2 pgoyette { 106 1.5.2.2 pgoyette extern int amdgpu_guarantee_initialized(void); 107 1.5.2.2 pgoyette const struct pci_attach_args *const pa = aux; 108 1.5.2.2 pgoyette int error; 109 1.5.2.2 pgoyette 110 1.5.2.2 pgoyette error = amdgpu_guarantee_initialized(); 111 1.5.2.2 pgoyette if (error) { 112 1.5.2.2 pgoyette aprint_error("amdgpu: failed to initialize: %d\n", error); 113 1.5.2.2 pgoyette return 0; 114 1.5.2.2 pgoyette } 115 1.5.2.2 pgoyette 116 1.5.2.2 pgoyette if (!amdgpu_pci_lookup(pa, NULL)) 117 1.5.2.2 pgoyette return 0; 118 1.5.2.2 pgoyette 119 1.5.2.2 pgoyette return 7; /* beat genfb_pci and radeon */ 120 1.5.2.2 pgoyette } 121 1.5.2.2 pgoyette 122 1.5.2.2 pgoyette static void 123 1.5.2.2 pgoyette amdgpu_attach(device_t parent, device_t self, void *aux) 124 1.5.2.2 pgoyette { 125 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 126 1.5.2.2 pgoyette const struct pci_attach_args *const pa = aux; 127 1.5.2.2 pgoyette 128 1.5.2.2 pgoyette pci_aprint_devinfo(pa, NULL); 129 1.5.2.2 pgoyette 130 1.5.2.2 pgoyette if (!pmf_device_register(self, &amdgpu_do_suspend, &amdgpu_do_resume)) 131 1.5.2.2 pgoyette aprint_error_dev(self, "unable to establish power handler\n"); 132 1.5.2.2 pgoyette 133 1.5.2.2 pgoyette /* 134 1.5.2.2 pgoyette * Trivial initialization first; the rest will come after we 135 1.5.2.2 pgoyette * have mounted the root file system and can load firmware 136 1.5.2.2 pgoyette * images. 137 1.5.2.2 pgoyette */ 138 1.5.2.2 pgoyette sc->sc_dev = NULL; 139 1.5.2.2 pgoyette sc->sc_pa = *pa; 140 1.5.2.2 pgoyette 141 1.5.2.2 pgoyette config_mountroot(self, &amdgpu_attach_real); 142 1.5.2.2 pgoyette } 143 1.5.2.2 pgoyette 144 1.5.2.2 pgoyette static void 145 1.5.2.2 pgoyette amdgpu_attach_real(device_t self) 146 1.5.2.2 pgoyette { 147 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 148 1.5.2.2 pgoyette const struct pci_attach_args *const pa = &sc->sc_pa; 149 1.5.2.2 pgoyette bool ok __diagused; 150 1.5.2.2 pgoyette unsigned long flags = 0; /* XXXGCC */ 151 1.5.2.2 pgoyette int error; 152 1.5.2.2 pgoyette 153 1.5.2.2 pgoyette ok = amdgpu_pci_lookup(pa, &flags); 154 1.5.2.2 pgoyette KASSERT(ok); 155 1.5.2.2 pgoyette 156 1.5.2.2 pgoyette sc->sc_task_state = AMDGPU_TASK_ATTACH; 157 1.5.2.2 pgoyette SIMPLEQ_INIT(&sc->sc_task_u.attach); 158 1.5.2.2 pgoyette 159 1.5.2.2 pgoyette /* Initialize the Linux PCI device descriptor. */ 160 1.5.2.2 pgoyette linux_pci_dev_init(&sc->sc_pci_dev, self, device_parent(self), pa, 0); 161 1.5.2.2 pgoyette 162 1.5.2.2 pgoyette /* XXX errno Linux->NetBSD */ 163 1.5.2.2 pgoyette error = -drm_pci_attach(self, pa, &sc->sc_pci_dev, amdgpu_drm_driver, 164 1.5.2.2 pgoyette flags, &sc->sc_drm_dev); 165 1.5.2.2 pgoyette if (error) { 166 1.5.2.2 pgoyette aprint_error_dev(self, "unable to attach drm: %d\n", error); 167 1.5.2.2 pgoyette goto out; 168 1.5.2.2 pgoyette } 169 1.5.2.2 pgoyette 170 1.5.2.2 pgoyette while (!SIMPLEQ_EMPTY(&sc->sc_task_u.attach)) { 171 1.5.2.2 pgoyette struct amdgpu_task *const task = 172 1.5.2.2 pgoyette SIMPLEQ_FIRST(&sc->sc_task_u.attach); 173 1.5.2.2 pgoyette 174 1.5.2.2 pgoyette SIMPLEQ_REMOVE_HEAD(&sc->sc_task_u.attach, rt_u.queue); 175 1.5.2.2 pgoyette (*task->rt_fn)(task); 176 1.5.2.2 pgoyette } 177 1.5.2.2 pgoyette 178 1.5.2.2 pgoyette sc->sc_task_state = AMDGPU_TASK_WORKQUEUE; 179 1.5.2.2 pgoyette error = workqueue_create(&sc->sc_task_u.workqueue, "amdgpufb", 180 1.5.2.2 pgoyette &amdgpu_task_work, NULL, PRI_NONE, IPL_NONE, WQ_MPSAFE); 181 1.5.2.2 pgoyette if (error) { 182 1.5.2.2 pgoyette aprint_error_dev(self, "unable to create workqueue: %d\n", 183 1.5.2.2 pgoyette error); 184 1.5.2.2 pgoyette sc->sc_task_u.workqueue = NULL; 185 1.5.2.2 pgoyette goto out; 186 1.5.2.2 pgoyette } 187 1.5.2.2 pgoyette 188 1.5.2.2 pgoyette out: sc->sc_dev = self; 189 1.5.2.2 pgoyette } 190 1.5.2.2 pgoyette 191 1.5.2.2 pgoyette static int 192 1.5.2.2 pgoyette amdgpu_detach(device_t self, int flags) 193 1.5.2.2 pgoyette { 194 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 195 1.5.2.2 pgoyette int error; 196 1.5.2.2 pgoyette 197 1.5.2.2 pgoyette if (sc->sc_dev == NULL) 198 1.5.2.2 pgoyette /* Not done attaching. */ 199 1.5.2.2 pgoyette return EBUSY; 200 1.5.2.2 pgoyette 201 1.5.2.2 pgoyette /* XXX Check for in-use before tearing it all down... */ 202 1.5.2.2 pgoyette error = config_detach_children(self, flags); 203 1.5.2.2 pgoyette if (error) 204 1.5.2.2 pgoyette return error; 205 1.5.2.2 pgoyette 206 1.5.2.2 pgoyette if (sc->sc_task_state == AMDGPU_TASK_ATTACH) 207 1.5.2.2 pgoyette goto out; 208 1.5.2.2 pgoyette if (sc->sc_task_u.workqueue != NULL) { 209 1.5.2.2 pgoyette workqueue_destroy(sc->sc_task_u.workqueue); 210 1.5.2.2 pgoyette sc->sc_task_u.workqueue = NULL; 211 1.5.2.2 pgoyette } 212 1.5.2.2 pgoyette 213 1.5.2.2 pgoyette if (sc->sc_drm_dev == NULL) 214 1.5.2.2 pgoyette goto out; 215 1.5.2.2 pgoyette /* XXX errno Linux->NetBSD */ 216 1.5.2.2 pgoyette error = -drm_pci_detach(sc->sc_drm_dev, flags); 217 1.5.2.2 pgoyette if (error) 218 1.5.2.2 pgoyette /* XXX Kinda too late to fail now... */ 219 1.5.2.2 pgoyette return error; 220 1.5.2.2 pgoyette sc->sc_drm_dev = NULL; 221 1.5.2.2 pgoyette 222 1.5.2.2 pgoyette out: linux_pci_dev_destroy(&sc->sc_pci_dev); 223 1.5.2.2 pgoyette pmf_device_deregister(self); 224 1.5.2.2 pgoyette 225 1.5.2.2 pgoyette return 0; 226 1.5.2.2 pgoyette } 227 1.5.2.2 pgoyette 228 1.5.2.2 pgoyette static bool 229 1.5.2.2 pgoyette amdgpu_do_suspend(device_t self, const pmf_qual_t *qual) 230 1.5.2.2 pgoyette { 231 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 232 1.5.2.2 pgoyette struct drm_device *const dev = sc->sc_drm_dev; 233 1.5.2.2 pgoyette int ret; 234 1.5.2.2 pgoyette bool is_console = true; /* XXX */ 235 1.5.2.2 pgoyette 236 1.5.2.2 pgoyette if (dev == NULL) 237 1.5.2.2 pgoyette return true; 238 1.5.2.2 pgoyette 239 1.5.2.2 pgoyette ret = amdgpu_suspend_kms(dev, true, is_console); 240 1.5.2.2 pgoyette if (ret) 241 1.5.2.2 pgoyette return false; 242 1.5.2.2 pgoyette 243 1.5.2.2 pgoyette return true; 244 1.5.2.2 pgoyette } 245 1.5.2.2 pgoyette 246 1.5.2.2 pgoyette static bool 247 1.5.2.2 pgoyette amdgpu_do_resume(device_t self, const pmf_qual_t *qual) 248 1.5.2.2 pgoyette { 249 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 250 1.5.2.2 pgoyette struct drm_device *const dev = sc->sc_drm_dev; 251 1.5.2.2 pgoyette int ret; 252 1.5.2.2 pgoyette bool is_console = true; /* XXX */ 253 1.5.2.2 pgoyette 254 1.5.2.2 pgoyette if (dev == NULL) 255 1.5.2.2 pgoyette return true; 256 1.5.2.2 pgoyette 257 1.5.2.2 pgoyette ret = amdgpu_resume_kms(dev, true, is_console); 258 1.5.2.2 pgoyette if (ret) 259 1.5.2.2 pgoyette return false; 260 1.5.2.2 pgoyette 261 1.5.2.2 pgoyette return true; 262 1.5.2.2 pgoyette } 263 1.5.2.2 pgoyette 264 1.5.2.2 pgoyette static void 265 1.5.2.2 pgoyette amdgpu_task_work(struct work *work, void *cookie __unused) 266 1.5.2.2 pgoyette { 267 1.5.2.2 pgoyette struct amdgpu_task *const task = container_of(work, struct amdgpu_task, 268 1.5.2.2 pgoyette rt_u.work); 269 1.5.2.2 pgoyette 270 1.5.2.2 pgoyette (*task->rt_fn)(task); 271 1.5.2.2 pgoyette } 272 1.5.2.2 pgoyette 273 1.5.2.2 pgoyette int 274 1.5.2.2 pgoyette amdgpu_task_schedule(device_t self, struct amdgpu_task *task) 275 1.5.2.2 pgoyette { 276 1.5.2.2 pgoyette struct amdgpu_softc *const sc = device_private(self); 277 1.5.2.2 pgoyette 278 1.5.2.2 pgoyette switch (sc->sc_task_state) { 279 1.5.2.2 pgoyette case AMDGPU_TASK_ATTACH: 280 1.5.2.2 pgoyette SIMPLEQ_INSERT_TAIL(&sc->sc_task_u.attach, task, rt_u.queue); 281 1.5.2.2 pgoyette return 0; 282 1.5.2.2 pgoyette case AMDGPU_TASK_WORKQUEUE: 283 1.5.2.2 pgoyette if (sc->sc_task_u.workqueue == NULL) { 284 1.5.2.2 pgoyette aprint_error_dev(self, "unable to schedule task\n"); 285 1.5.2.2 pgoyette return EIO; 286 1.5.2.2 pgoyette } 287 1.5.2.2 pgoyette workqueue_enqueue(sc->sc_task_u.workqueue, &task->rt_u.work, 288 1.5.2.2 pgoyette NULL); 289 1.5.2.2 pgoyette return 0; 290 1.5.2.2 pgoyette default: 291 1.5.2.2 pgoyette panic("amdgpu in invalid task state: %d\n", 292 1.5.2.2 pgoyette (int)sc->sc_task_state); 293 1.5.2.2 pgoyette } 294 1.5.2.2 pgoyette } 295
Indexes created Thu Sep 25 16:09:42 GMT 2025