amdgpu.h revision 1.1.1.1
1 /* $NetBSD: amdgpu.h,v 1.1.1.1 2018/08/27 01:34:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #include <linux/atomic.h> 34 #include <linux/wait.h> 35 #include <linux/list.h> 36 #include <linux/kref.h> 37 #include <linux/interval_tree.h> 38 #include <linux/hashtable.h> 39 #include <linux/fence.h> 40 41 #include <ttm/ttm_bo_api.h> 42 #include <ttm/ttm_bo_driver.h> 43 #include <ttm/ttm_placement.h> 44 #include <ttm/ttm_module.h> 45 #include <ttm/ttm_execbuf_util.h> 46 47 #include <drm/drmP.h> 48 #include <drm/drm_gem.h> 49 #include <drm/amdgpu_drm.h> 50 51 #include "amd_shared.h" 52 #include "amdgpu_mode.h" 53 #include "amdgpu_ih.h" 54 #include "amdgpu_irq.h" 55 #include "amdgpu_ucode.h" 56 #include "amdgpu_gds.h" 57 58 #include "gpu_scheduler.h" 59 60 /* 61 * Modules parameters. 62 */ 63 extern int amdgpu_modeset; 64 extern int amdgpu_vram_limit; 65 extern int amdgpu_gart_size; 66 extern int amdgpu_benchmarking; 67 extern int amdgpu_testing; 68 extern int amdgpu_audio; 69 extern int amdgpu_disp_priority; 70 extern int amdgpu_hw_i2c; 71 extern int amdgpu_pcie_gen2; 72 extern int amdgpu_msi; 73 extern int amdgpu_lockup_timeout; 74 extern int amdgpu_dpm; 75 extern int amdgpu_smc_load_fw; 76 extern int amdgpu_aspm; 77 extern int amdgpu_runtime_pm; 78 extern int amdgpu_hard_reset; 79 extern unsigned amdgpu_ip_block_mask; 80 extern int amdgpu_bapm; 81 extern int amdgpu_deep_color; 82 extern int amdgpu_vm_size; 83 extern int amdgpu_vm_block_size; 84 extern int amdgpu_vm_fault_stop; 85 extern int amdgpu_vm_debug; 86 extern int amdgpu_enable_scheduler; 87 extern int amdgpu_sched_jobs; 88 extern int amdgpu_sched_hw_submission; 89 extern int amdgpu_enable_semaphores; 90 91 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 92 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 93 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 94 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 95 #define AMDGPU_IB_POOL_SIZE 16 96 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 97 #define AMDGPUFB_CONN_LIMIT 4 98 #define AMDGPU_BIOS_NUM_SCRATCH 8 99 100 /* max number of rings */ 101 #define AMDGPU_MAX_RINGS 16 102 #define AMDGPU_MAX_GFX_RINGS 1 103 #define AMDGPU_MAX_COMPUTE_RINGS 8 104 #define AMDGPU_MAX_VCE_RINGS 2 105 106 /* max number of IP instances */ 107 #define AMDGPU_MAX_SDMA_INSTANCES 2 108 109 /* number of hw syncs before falling back on blocking */ 110 #define AMDGPU_NUM_SYNCS 4 111 112 /* hardcode that limit for now */ 113 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 114 115 /* hard reset data */ 116 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 117 118 /* reset flags */ 119 #define AMDGPU_RESET_GFX (1 << 0) 120 #define AMDGPU_RESET_COMPUTE (1 << 1) 121 #define AMDGPU_RESET_DMA (1 << 2) 122 #define AMDGPU_RESET_CP (1 << 3) 123 #define AMDGPU_RESET_GRBM (1 << 4) 124 #define AMDGPU_RESET_DMA1 (1 << 5) 125 #define AMDGPU_RESET_RLC (1 << 6) 126 #define AMDGPU_RESET_SEM (1 << 7) 127 #define AMDGPU_RESET_IH (1 << 8) 128 #define AMDGPU_RESET_VMC (1 << 9) 129 #define AMDGPU_RESET_MC (1 << 10) 130 #define AMDGPU_RESET_DISPLAY (1 << 11) 131 #define AMDGPU_RESET_UVD (1 << 12) 132 #define AMDGPU_RESET_VCE (1 << 13) 133 #define AMDGPU_RESET_VCE1 (1 << 14) 134 135 /* CG block flags */ 136 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 137 #define AMDGPU_CG_BLOCK_MC (1 << 1) 138 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 139 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 140 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 141 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 142 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 143 144 /* CG flags */ 145 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 146 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 147 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 148 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 149 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 150 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 151 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 152 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 153 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 154 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 155 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 156 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 157 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 158 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 159 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 160 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 161 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 162 163 /* PG flags */ 164 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 165 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 166 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 167 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 168 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 169 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 170 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 171 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 172 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 173 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 174 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 175 176 /* GFX current status */ 177 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 178 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 179 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 180 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 181 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 182 183 /* max cursor sizes (in pixels) */ 184 #define CIK_CURSOR_WIDTH 128 185 #define CIK_CURSOR_HEIGHT 128 186 187 struct amdgpu_device; 188 struct amdgpu_fence; 189 struct amdgpu_ib; 190 struct amdgpu_vm; 191 struct amdgpu_ring; 192 struct amdgpu_semaphore; 193 struct amdgpu_cs_parser; 194 struct amdgpu_job; 195 struct amdgpu_irq_src; 196 struct amdgpu_fpriv; 197 198 enum amdgpu_cp_irq { 199 AMDGPU_CP_IRQ_GFX_EOP = 0, 200 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 201 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 202 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 203 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 204 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 205 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 206 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 207 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 208 209 AMDGPU_CP_IRQ_LAST 210 }; 211 212 enum amdgpu_sdma_irq { 213 AMDGPU_SDMA_IRQ_TRAP0 = 0, 214 AMDGPU_SDMA_IRQ_TRAP1, 215 216 AMDGPU_SDMA_IRQ_LAST 217 }; 218 219 enum amdgpu_thermal_irq { 220 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 221 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 222 223 AMDGPU_THERMAL_IRQ_LAST 224 }; 225 226 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 227 enum amd_ip_block_type block_type, 228 enum amd_clockgating_state state); 229 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 230 enum amd_ip_block_type block_type, 231 enum amd_powergating_state state); 232 233 struct amdgpu_ip_block_version { 234 enum amd_ip_block_type type; 235 u32 major; 236 u32 minor; 237 u32 rev; 238 const struct amd_ip_funcs *funcs; 239 }; 240 241 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 242 enum amd_ip_block_type type, 243 u32 major, u32 minor); 244 245 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 246 struct amdgpu_device *adev, 247 enum amd_ip_block_type type); 248 249 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 250 struct amdgpu_buffer_funcs { 251 /* maximum bytes in a single operation */ 252 uint32_t copy_max_bytes; 253 254 /* number of dw to reserve per operation */ 255 unsigned copy_num_dw; 256 257 /* used for buffer migration */ 258 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 259 /* src addr in bytes */ 260 uint64_t src_offset, 261 /* dst addr in bytes */ 262 uint64_t dst_offset, 263 /* number of byte to transfer */ 264 uint32_t byte_count); 265 266 /* maximum bytes in a single operation */ 267 uint32_t fill_max_bytes; 268 269 /* number of dw to reserve per operation */ 270 unsigned fill_num_dw; 271 272 /* used for buffer clearing */ 273 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 274 /* value to write to memory */ 275 uint32_t src_data, 276 /* dst addr in bytes */ 277 uint64_t dst_offset, 278 /* number of byte to fill */ 279 uint32_t byte_count); 280 }; 281 282 /* provided by hw blocks that can write ptes, e.g., sdma */ 283 struct amdgpu_vm_pte_funcs { 284 /* copy pte entries from GART */ 285 void (*copy_pte)(struct amdgpu_ib *ib, 286 uint64_t pe, uint64_t src, 287 unsigned count); 288 /* write pte one entry at a time with addr mapping */ 289 void (*write_pte)(struct amdgpu_ib *ib, 290 uint64_t pe, 291 uint64_t addr, unsigned count, 292 uint32_t incr, uint32_t flags); 293 /* for linear pte/pde updates without addr mapping */ 294 void (*set_pte_pde)(struct amdgpu_ib *ib, 295 uint64_t pe, 296 uint64_t addr, unsigned count, 297 uint32_t incr, uint32_t flags); 298 /* pad the indirect buffer to the necessary number of dw */ 299 void (*pad_ib)(struct amdgpu_ib *ib); 300 }; 301 302 /* provided by the gmc block */ 303 struct amdgpu_gart_funcs { 304 /* flush the vm tlb via mmio */ 305 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 306 uint32_t vmid); 307 /* write pte/pde updates using the cpu */ 308 int (*set_pte_pde)(struct amdgpu_device *adev, 309 void *cpu_pt_addr, /* cpu addr of page table */ 310 uint32_t gpu_page_idx, /* pte/pde to update */ 311 uint64_t addr, /* addr to write into pte/pde */ 312 uint32_t flags); /* access flags */ 313 }; 314 315 /* provided by the ih block */ 316 struct amdgpu_ih_funcs { 317 /* ring read/write ptr handling, called from interrupt context */ 318 u32 (*get_wptr)(struct amdgpu_device *adev); 319 void (*decode_iv)(struct amdgpu_device *adev, 320 struct amdgpu_iv_entry *entry); 321 void (*set_rptr)(struct amdgpu_device *adev); 322 }; 323 324 /* provided by hw blocks that expose a ring buffer for commands */ 325 struct amdgpu_ring_funcs { 326 /* ring read/write ptr handling */ 327 u32 (*get_rptr)(struct amdgpu_ring *ring); 328 u32 (*get_wptr)(struct amdgpu_ring *ring); 329 void (*set_wptr)(struct amdgpu_ring *ring); 330 /* validating and patching of IBs */ 331 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 332 /* command emit functions */ 333 void (*emit_ib)(struct amdgpu_ring *ring, 334 struct amdgpu_ib *ib); 335 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 336 uint64_t seq, unsigned flags); 337 bool (*emit_semaphore)(struct amdgpu_ring *ring, 338 struct amdgpu_semaphore *semaphore, 339 bool emit_wait); 340 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 341 uint64_t pd_addr); 342 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 343 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 344 uint32_t gds_base, uint32_t gds_size, 345 uint32_t gws_base, uint32_t gws_size, 346 uint32_t oa_base, uint32_t oa_size); 347 /* testing functions */ 348 int (*test_ring)(struct amdgpu_ring *ring); 349 int (*test_ib)(struct amdgpu_ring *ring); 350 /* insert NOP packets */ 351 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 352 }; 353 354 /* 355 * BIOS. 356 */ 357 bool amdgpu_get_bios(struct amdgpu_device *adev); 358 bool amdgpu_read_bios(struct amdgpu_device *adev); 359 360 /* 361 * Dummy page 362 */ 363 struct amdgpu_dummy_page { 364 struct page *page; 365 dma_addr_t addr; 366 }; 367 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 368 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 369 370 371 /* 372 * Clocks 373 */ 374 375 #define AMDGPU_MAX_PPLL 3 376 377 struct amdgpu_clock { 378 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 379 struct amdgpu_pll spll; 380 struct amdgpu_pll mpll; 381 /* 10 Khz units */ 382 uint32_t default_mclk; 383 uint32_t default_sclk; 384 uint32_t default_dispclk; 385 uint32_t current_dispclk; 386 uint32_t dp_extclk; 387 uint32_t max_pixel_clock; 388 }; 389 390 /* 391 * Fences. 392 */ 393 struct amdgpu_fence_driver { 394 uint64_t gpu_addr; 395 volatile uint32_t *cpu_addr; 396 /* sync_seq is protected by ring emission lock */ 397 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 398 atomic64_t last_seq; 399 bool initialized; 400 struct amdgpu_irq_src *irq_src; 401 unsigned irq_type; 402 struct timer_list fallback_timer; 403 wait_queue_head_t fence_queue; 404 }; 405 406 /* some special values for the owner field */ 407 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 408 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 409 410 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 411 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 412 413 struct amdgpu_fence { 414 struct fence base; 415 416 /* RB, DMA, etc. */ 417 struct amdgpu_ring *ring; 418 uint64_t seq; 419 420 /* filp or special value for fence creator */ 421 void *owner; 422 423 wait_queue_t fence_wake; 424 }; 425 426 struct amdgpu_user_fence { 427 /* write-back bo */ 428 struct amdgpu_bo *bo; 429 /* write-back address offset to bo start */ 430 uint32_t offset; 431 }; 432 433 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 434 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 435 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 436 437 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 438 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 439 struct amdgpu_irq_src *irq_src, 440 unsigned irq_type); 441 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 442 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 443 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 444 struct amdgpu_fence **fence); 445 void amdgpu_fence_process(struct amdgpu_ring *ring); 446 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 447 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 448 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 449 450 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 451 struct amdgpu_ring *ring); 452 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 453 struct amdgpu_ring *ring); 454 455 /* 456 * TTM. 457 */ 458 struct amdgpu_mman { 459 struct ttm_bo_global_ref bo_global_ref; 460 struct drm_global_reference mem_global_ref; 461 struct ttm_bo_device bdev; 462 bool mem_global_referenced; 463 bool initialized; 464 465 #if defined(CONFIG_DEBUG_FS) 466 struct dentry *vram; 467 struct dentry *gtt; 468 #endif 469 470 /* buffer handling */ 471 const struct amdgpu_buffer_funcs *buffer_funcs; 472 struct amdgpu_ring *buffer_funcs_ring; 473 }; 474 475 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 476 uint64_t src_offset, 477 uint64_t dst_offset, 478 uint32_t byte_count, 479 struct reservation_object *resv, 480 struct fence **fence); 481 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 482 483 struct amdgpu_bo_list_entry { 484 struct amdgpu_bo *robj; 485 struct ttm_validate_buffer tv; 486 struct amdgpu_bo_va *bo_va; 487 unsigned prefered_domains; 488 unsigned allowed_domains; 489 uint32_t priority; 490 }; 491 492 struct amdgpu_bo_va_mapping { 493 struct list_head list; 494 struct interval_tree_node it; 495 uint64_t offset; 496 uint32_t flags; 497 }; 498 499 /* bo virtual addresses in a specific vm */ 500 struct amdgpu_bo_va { 501 struct mutex mutex; 502 /* protected by bo being reserved */ 503 struct list_head bo_list; 504 struct fence *last_pt_update; 505 unsigned ref_count; 506 507 /* protected by vm mutex and spinlock */ 508 struct list_head vm_status; 509 510 /* mappings for this bo_va */ 511 struct list_head invalids; 512 struct list_head valids; 513 514 /* constant after initialization */ 515 struct amdgpu_vm *vm; 516 struct amdgpu_bo *bo; 517 }; 518 519 #define AMDGPU_GEM_DOMAIN_MAX 0x3 520 521 struct amdgpu_bo { 522 /* Protected by gem.mutex */ 523 struct list_head list; 524 /* Protected by tbo.reserved */ 525 u32 initial_domain; 526 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 527 struct ttm_placement placement; 528 struct ttm_buffer_object tbo; 529 struct ttm_bo_kmap_obj kmap; 530 u64 flags; 531 unsigned pin_count; 532 void *kptr; 533 u64 tiling_flags; 534 u64 metadata_flags; 535 void *metadata; 536 u32 metadata_size; 537 unsigned prime_shared_count; 538 /* list of all virtual address to which this bo 539 * is associated to 540 */ 541 struct list_head va; 542 /* Constant after initialization */ 543 struct amdgpu_device *adev; 544 struct drm_gem_object gem_base; 545 struct amdgpu_bo *parent; 546 547 struct ttm_bo_kmap_obj dma_buf_vmap; 548 pid_t pid; 549 struct amdgpu_mn *mn; 550 struct list_head mn_list; 551 }; 552 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 553 554 void amdgpu_gem_object_free(struct drm_gem_object *obj); 555 int amdgpu_gem_object_open(struct drm_gem_object *obj, 556 struct drm_file *file_priv); 557 void amdgpu_gem_object_close(struct drm_gem_object *obj, 558 struct drm_file *file_priv); 559 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 560 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 561 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 562 struct dma_buf_attachment *attach, 563 struct sg_table *sg); 564 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 565 struct drm_gem_object *gobj, 566 int flags); 567 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 568 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 569 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 570 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 571 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 572 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 573 574 /* sub-allocation manager, it has to be protected by another lock. 575 * By conception this is an helper for other part of the driver 576 * like the indirect buffer or semaphore, which both have their 577 * locking. 578 * 579 * Principe is simple, we keep a list of sub allocation in offset 580 * order (first entry has offset == 0, last entry has the highest 581 * offset). 582 * 583 * When allocating new object we first check if there is room at 584 * the end total_size - (last_object_offset + last_object_size) >= 585 * alloc_size. If so we allocate new object there. 586 * 587 * When there is not enough room at the end, we start waiting for 588 * each sub object until we reach object_offset+object_size >= 589 * alloc_size, this object then become the sub object we return. 590 * 591 * Alignment can't be bigger than page size. 592 * 593 * Hole are not considered for allocation to keep things simple. 594 * Assumption is that there won't be hole (all object on same 595 * alignment). 596 */ 597 struct amdgpu_sa_manager { 598 wait_queue_head_t wq; 599 struct amdgpu_bo *bo; 600 struct list_head *hole; 601 struct list_head flist[AMDGPU_MAX_RINGS]; 602 struct list_head olist; 603 unsigned size; 604 uint64_t gpu_addr; 605 void *cpu_ptr; 606 uint32_t domain; 607 uint32_t align; 608 }; 609 610 /* sub-allocation buffer */ 611 struct amdgpu_sa_bo { 612 struct list_head olist; 613 struct list_head flist; 614 struct amdgpu_sa_manager *manager; 615 unsigned soffset; 616 unsigned eoffset; 617 struct fence *fence; 618 }; 619 620 /* 621 * GEM objects. 622 */ 623 struct amdgpu_gem { 624 struct mutex mutex; 625 struct list_head objects; 626 }; 627 628 int amdgpu_gem_init(struct amdgpu_device *adev); 629 void amdgpu_gem_fini(struct amdgpu_device *adev); 630 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 631 int alignment, u32 initial_domain, 632 u64 flags, bool kernel, 633 struct drm_gem_object **obj); 634 635 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 636 struct drm_device *dev, 637 struct drm_mode_create_dumb *args); 638 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 639 struct drm_device *dev, 640 uint32_t handle, uint64_t *offset_p); 641 642 /* 643 * Semaphores. 644 */ 645 struct amdgpu_semaphore { 646 struct amdgpu_sa_bo *sa_bo; 647 signed waiters; 648 uint64_t gpu_addr; 649 }; 650 651 int amdgpu_semaphore_create(struct amdgpu_device *adev, 652 struct amdgpu_semaphore **semaphore); 653 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 654 struct amdgpu_semaphore *semaphore); 655 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 656 struct amdgpu_semaphore *semaphore); 657 void amdgpu_semaphore_free(struct amdgpu_device *adev, 658 struct amdgpu_semaphore **semaphore, 659 struct fence *fence); 660 661 /* 662 * Synchronization 663 */ 664 struct amdgpu_sync { 665 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 666 struct fence *sync_to[AMDGPU_MAX_RINGS]; 667 DECLARE_HASHTABLE(fences, 4); 668 struct fence *last_vm_update; 669 }; 670 671 void amdgpu_sync_create(struct amdgpu_sync *sync); 672 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 673 struct fence *f); 674 int amdgpu_sync_resv(struct amdgpu_device *adev, 675 struct amdgpu_sync *sync, 676 struct reservation_object *resv, 677 void *owner); 678 int amdgpu_sync_rings(struct amdgpu_sync *sync, 679 struct amdgpu_ring *ring); 680 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 681 int amdgpu_sync_wait(struct amdgpu_sync *sync); 682 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 683 struct fence *fence); 684 685 /* 686 * GART structures, functions & helpers 687 */ 688 struct amdgpu_mc; 689 690 #define AMDGPU_GPU_PAGE_SIZE 4096 691 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 692 #define AMDGPU_GPU_PAGE_SHIFT 12 693 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 694 695 struct amdgpu_gart { 696 dma_addr_t table_addr; 697 struct amdgpu_bo *robj; 698 void *ptr; 699 unsigned num_gpu_pages; 700 unsigned num_cpu_pages; 701 unsigned table_size; 702 struct page **pages; 703 dma_addr_t *pages_addr; 704 bool ready; 705 const struct amdgpu_gart_funcs *gart_funcs; 706 }; 707 708 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 709 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 710 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 711 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 712 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 713 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 714 int amdgpu_gart_init(struct amdgpu_device *adev); 715 void amdgpu_gart_fini(struct amdgpu_device *adev); 716 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 717 int pages); 718 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 719 int pages, struct page **pagelist, 720 dma_addr_t *dma_addr, uint32_t flags); 721 722 /* 723 * GPU MC structures, functions & helpers 724 */ 725 struct amdgpu_mc { 726 resource_size_t aper_size; 727 resource_size_t aper_base; 728 resource_size_t agp_base; 729 /* for some chips with <= 32MB we need to lie 730 * about vram size near mc fb location */ 731 u64 mc_vram_size; 732 u64 visible_vram_size; 733 u64 gtt_size; 734 u64 gtt_start; 735 u64 gtt_end; 736 u64 vram_start; 737 u64 vram_end; 738 unsigned vram_width; 739 u64 real_vram_size; 740 int vram_mtrr; 741 u64 gtt_base_align; 742 u64 mc_mask; 743 const struct firmware *fw; /* MC firmware */ 744 uint32_t fw_version; 745 struct amdgpu_irq_src vm_fault; 746 uint32_t vram_type; 747 }; 748 749 /* 750 * GPU doorbell structures, functions & helpers 751 */ 752 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 753 { 754 AMDGPU_DOORBELL_KIQ = 0x000, 755 AMDGPU_DOORBELL_HIQ = 0x001, 756 AMDGPU_DOORBELL_DIQ = 0x002, 757 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 758 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 759 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 760 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 761 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 762 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 763 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 764 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 765 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 766 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 767 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 768 AMDGPU_DOORBELL_IH = 0x1E8, 769 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 770 AMDGPU_DOORBELL_INVALID = 0xFFFF 771 } AMDGPU_DOORBELL_ASSIGNMENT; 772 773 struct amdgpu_doorbell { 774 /* doorbell mmio */ 775 resource_size_t base; 776 resource_size_t size; 777 u32 __iomem *ptr; 778 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 779 }; 780 781 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 782 phys_addr_t *aperture_base, 783 size_t *aperture_size, 784 size_t *start_offset); 785 786 /* 787 * IRQS. 788 */ 789 790 struct amdgpu_flip_work { 791 struct work_struct flip_work; 792 struct work_struct unpin_work; 793 struct amdgpu_device *adev; 794 int crtc_id; 795 uint64_t base; 796 struct drm_pending_vblank_event *event; 797 struct amdgpu_bo *old_rbo; 798 struct fence *excl; 799 unsigned shared_count; 800 struct fence **shared; 801 }; 802 803 804 /* 805 * CP & rings. 806 */ 807 808 struct amdgpu_ib { 809 struct amdgpu_sa_bo *sa_bo; 810 uint32_t length_dw; 811 uint64_t gpu_addr; 812 uint32_t *ptr; 813 struct amdgpu_ring *ring; 814 struct amdgpu_fence *fence; 815 struct amdgpu_user_fence *user; 816 struct amdgpu_vm *vm; 817 struct amdgpu_ctx *ctx; 818 struct amdgpu_sync sync; 819 uint32_t gds_base, gds_size; 820 uint32_t gws_base, gws_size; 821 uint32_t oa_base, oa_size; 822 uint32_t flags; 823 /* resulting sequence number */ 824 uint64_t sequence; 825 }; 826 827 enum amdgpu_ring_type { 828 AMDGPU_RING_TYPE_GFX, 829 AMDGPU_RING_TYPE_COMPUTE, 830 AMDGPU_RING_TYPE_SDMA, 831 AMDGPU_RING_TYPE_UVD, 832 AMDGPU_RING_TYPE_VCE 833 }; 834 835 extern struct amd_sched_backend_ops amdgpu_sched_ops; 836 837 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 838 struct amdgpu_ring *ring, 839 struct amdgpu_ib *ibs, 840 unsigned num_ibs, 841 int (*free_job)(struct amdgpu_job *), 842 void *owner, 843 struct fence **fence); 844 845 struct amdgpu_ring { 846 struct amdgpu_device *adev; 847 const struct amdgpu_ring_funcs *funcs; 848 struct amdgpu_fence_driver fence_drv; 849 struct amd_gpu_scheduler sched; 850 851 spinlock_t fence_lock; 852 struct mutex *ring_lock; 853 struct amdgpu_bo *ring_obj; 854 volatile uint32_t *ring; 855 unsigned rptr_offs; 856 u64 next_rptr_gpu_addr; 857 volatile u32 *next_rptr_cpu_addr; 858 unsigned wptr; 859 unsigned wptr_old; 860 unsigned ring_size; 861 unsigned ring_free_dw; 862 int count_dw; 863 uint64_t gpu_addr; 864 uint32_t align_mask; 865 uint32_t ptr_mask; 866 bool ready; 867 u32 nop; 868 u32 idx; 869 u64 last_semaphore_signal_addr; 870 u64 last_semaphore_wait_addr; 871 u32 me; 872 u32 pipe; 873 u32 queue; 874 struct amdgpu_bo *mqd_obj; 875 u32 doorbell_index; 876 bool use_doorbell; 877 unsigned wptr_offs; 878 unsigned next_rptr_offs; 879 unsigned fence_offs; 880 struct amdgpu_ctx *current_ctx; 881 enum amdgpu_ring_type type; 882 char name[16]; 883 bool is_pte_ring; 884 }; 885 886 /* 887 * VM 888 */ 889 890 /* maximum number of VMIDs */ 891 #define AMDGPU_NUM_VM 16 892 893 /* number of entries in page table */ 894 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 895 896 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 897 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 898 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 899 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 900 901 #define AMDGPU_PTE_VALID (1 << 0) 902 #define AMDGPU_PTE_SYSTEM (1 << 1) 903 #define AMDGPU_PTE_SNOOPED (1 << 2) 904 905 /* VI only */ 906 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 907 908 #define AMDGPU_PTE_READABLE (1 << 5) 909 #define AMDGPU_PTE_WRITEABLE (1 << 6) 910 911 /* PTE (Page Table Entry) fragment field for different page sizes */ 912 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 913 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 914 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 915 916 /* How to programm VM fault handling */ 917 #define AMDGPU_VM_FAULT_STOP_NEVER 0 918 #define AMDGPU_VM_FAULT_STOP_FIRST 1 919 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 920 921 struct amdgpu_vm_pt { 922 struct amdgpu_bo *bo; 923 uint64_t addr; 924 }; 925 926 struct amdgpu_vm_id { 927 unsigned id; 928 uint64_t pd_gpu_addr; 929 /* last flushed PD/PT update */ 930 struct fence *flushed_updates; 931 }; 932 933 struct amdgpu_vm { 934 struct rb_root va; 935 936 /* protecting invalidated */ 937 spinlock_t status_lock; 938 939 /* BOs moved, but not yet updated in the PT */ 940 struct list_head invalidated; 941 942 /* BOs cleared in the PT because of a move */ 943 struct list_head cleared; 944 945 /* BO mappings freed, but not yet updated in the PT */ 946 struct list_head freed; 947 948 /* contains the page directory */ 949 struct amdgpu_bo *page_directory; 950 unsigned max_pde_used; 951 struct fence *page_directory_fence; 952 953 /* array of page tables, one for each page directory entry */ 954 struct amdgpu_vm_pt *page_tables; 955 956 /* for id and flush management per ring */ 957 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 958 /* for interval tree */ 959 spinlock_t it_lock; 960 /* protecting freed */ 961 spinlock_t freed_lock; 962 }; 963 964 struct amdgpu_vm_manager { 965 struct { 966 struct fence *active; 967 atomic_long_t owner; 968 } ids[AMDGPU_NUM_VM]; 969 970 uint32_t max_pfn; 971 /* number of VMIDs */ 972 unsigned nvm; 973 /* vram base address for page table entry */ 974 u64 vram_base_offset; 975 /* is vm enabled? */ 976 bool enabled; 977 /* vm pte handling */ 978 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 979 struct amdgpu_ring *vm_pte_funcs_ring; 980 }; 981 982 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 983 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 984 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 985 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 986 struct amdgpu_vm *vm, 987 struct list_head *head); 988 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 989 struct amdgpu_sync *sync); 990 void amdgpu_vm_flush(struct amdgpu_ring *ring, 991 struct amdgpu_vm *vm, 992 struct fence *updates); 993 void amdgpu_vm_fence(struct amdgpu_device *adev, 994 struct amdgpu_vm *vm, 995 struct fence *fence); 996 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 997 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 998 struct amdgpu_vm *vm); 999 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 1000 struct amdgpu_vm *vm); 1001 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1002 struct amdgpu_sync *sync); 1003 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 1004 struct amdgpu_bo_va *bo_va, 1005 struct ttm_mem_reg *mem); 1006 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 1007 struct amdgpu_bo *bo); 1008 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 1009 struct amdgpu_bo *bo); 1010 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 1011 struct amdgpu_vm *vm, 1012 struct amdgpu_bo *bo); 1013 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 1014 struct amdgpu_bo_va *bo_va, 1015 uint64_t addr, uint64_t offset, 1016 uint64_t size, uint32_t flags); 1017 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1018 struct amdgpu_bo_va *bo_va, 1019 uint64_t addr); 1020 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 1021 struct amdgpu_bo_va *bo_va); 1022 int amdgpu_vm_free_job(struct amdgpu_job *job); 1023 1024 /* 1025 * context related structures 1026 */ 1027 1028 #define AMDGPU_CTX_MAX_CS_PENDING 16 1029 1030 struct amdgpu_ctx_ring { 1031 uint64_t sequence; 1032 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1033 struct amd_sched_entity entity; 1034 }; 1035 1036 struct amdgpu_ctx { 1037 struct kref refcount; 1038 struct amdgpu_device *adev; 1039 unsigned reset_counter; 1040 spinlock_t ring_lock; 1041 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1042 }; 1043 1044 struct amdgpu_ctx_mgr { 1045 struct amdgpu_device *adev; 1046 struct mutex lock; 1047 /* protected by lock */ 1048 struct idr ctx_handles; 1049 }; 1050 1051 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1052 struct amdgpu_ctx *ctx); 1053 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1054 1055 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1056 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1057 1058 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1059 struct fence *fence); 1060 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1061 struct amdgpu_ring *ring, uint64_t seq); 1062 1063 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1064 struct drm_file *filp); 1065 1066 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1067 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1068 1069 /* 1070 * file private structure 1071 */ 1072 1073 struct amdgpu_fpriv { 1074 struct amdgpu_vm vm; 1075 struct mutex bo_list_lock; 1076 struct idr bo_list_handles; 1077 struct amdgpu_ctx_mgr ctx_mgr; 1078 }; 1079 1080 /* 1081 * residency list 1082 */ 1083 1084 struct amdgpu_bo_list { 1085 struct mutex lock; 1086 struct amdgpu_bo *gds_obj; 1087 struct amdgpu_bo *gws_obj; 1088 struct amdgpu_bo *oa_obj; 1089 bool has_userptr; 1090 unsigned num_entries; 1091 struct amdgpu_bo_list_entry *array; 1092 }; 1093 1094 struct amdgpu_bo_list * 1095 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1096 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1097 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1098 1099 /* 1100 * GFX stuff 1101 */ 1102 #include "clearstate_defs.h" 1103 1104 struct amdgpu_rlc { 1105 /* for power gating */ 1106 struct amdgpu_bo *save_restore_obj; 1107 uint64_t save_restore_gpu_addr; 1108 volatile uint32_t *sr_ptr; 1109 const u32 *reg_list; 1110 u32 reg_list_size; 1111 /* for clear state */ 1112 struct amdgpu_bo *clear_state_obj; 1113 uint64_t clear_state_gpu_addr; 1114 volatile uint32_t *cs_ptr; 1115 const struct cs_section_def *cs_data; 1116 u32 clear_state_size; 1117 /* for cp tables */ 1118 struct amdgpu_bo *cp_table_obj; 1119 uint64_t cp_table_gpu_addr; 1120 volatile uint32_t *cp_table_ptr; 1121 u32 cp_table_size; 1122 }; 1123 1124 struct amdgpu_mec { 1125 struct amdgpu_bo *hpd_eop_obj; 1126 u64 hpd_eop_gpu_addr; 1127 u32 num_pipe; 1128 u32 num_mec; 1129 u32 num_queue; 1130 }; 1131 1132 /* 1133 * GPU scratch registers structures, functions & helpers 1134 */ 1135 struct amdgpu_scratch { 1136 unsigned num_reg; 1137 uint32_t reg_base; 1138 bool free[32]; 1139 uint32_t reg[32]; 1140 }; 1141 1142 /* 1143 * GFX configurations 1144 */ 1145 struct amdgpu_gca_config { 1146 unsigned max_shader_engines; 1147 unsigned max_tile_pipes; 1148 unsigned max_cu_per_sh; 1149 unsigned max_sh_per_se; 1150 unsigned max_backends_per_se; 1151 unsigned max_texture_channel_caches; 1152 unsigned max_gprs; 1153 unsigned max_gs_threads; 1154 unsigned max_hw_contexts; 1155 unsigned sc_prim_fifo_size_frontend; 1156 unsigned sc_prim_fifo_size_backend; 1157 unsigned sc_hiz_tile_fifo_size; 1158 unsigned sc_earlyz_tile_fifo_size; 1159 1160 unsigned num_tile_pipes; 1161 unsigned backend_enable_mask; 1162 unsigned mem_max_burst_length_bytes; 1163 unsigned mem_row_size_in_kb; 1164 unsigned shader_engine_tile_size; 1165 unsigned num_gpus; 1166 unsigned multi_gpu_tile_size; 1167 unsigned mc_arb_ramcfg; 1168 unsigned gb_addr_config; 1169 1170 uint32_t tile_mode_array[32]; 1171 uint32_t macrotile_mode_array[16]; 1172 }; 1173 1174 struct amdgpu_gfx { 1175 struct mutex gpu_clock_mutex; 1176 struct amdgpu_gca_config config; 1177 struct amdgpu_rlc rlc; 1178 struct amdgpu_mec mec; 1179 struct amdgpu_scratch scratch; 1180 const struct firmware *me_fw; /* ME firmware */ 1181 uint32_t me_fw_version; 1182 const struct firmware *pfp_fw; /* PFP firmware */ 1183 uint32_t pfp_fw_version; 1184 const struct firmware *ce_fw; /* CE firmware */ 1185 uint32_t ce_fw_version; 1186 const struct firmware *rlc_fw; /* RLC firmware */ 1187 uint32_t rlc_fw_version; 1188 const struct firmware *mec_fw; /* MEC firmware */ 1189 uint32_t mec_fw_version; 1190 const struct firmware *mec2_fw; /* MEC2 firmware */ 1191 uint32_t mec2_fw_version; 1192 uint32_t me_feature_version; 1193 uint32_t ce_feature_version; 1194 uint32_t pfp_feature_version; 1195 uint32_t rlc_feature_version; 1196 uint32_t mec_feature_version; 1197 uint32_t mec2_feature_version; 1198 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1199 unsigned num_gfx_rings; 1200 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1201 unsigned num_compute_rings; 1202 struct amdgpu_irq_src eop_irq; 1203 struct amdgpu_irq_src priv_reg_irq; 1204 struct amdgpu_irq_src priv_inst_irq; 1205 /* gfx status */ 1206 uint32_t gfx_current_status; 1207 /* ce ram size*/ 1208 unsigned ce_ram_size; 1209 }; 1210 1211 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1212 unsigned size, struct amdgpu_ib *ib); 1213 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1214 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1215 struct amdgpu_ib *ib, void *owner); 1216 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1217 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1218 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1219 /* Ring access between begin & end cannot sleep */ 1220 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1221 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1222 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1223 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1224 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1225 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1226 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1227 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1228 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1229 uint32_t **data); 1230 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1231 unsigned size, uint32_t *data); 1232 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1233 unsigned ring_size, u32 nop, u32 align_mask, 1234 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1235 enum amdgpu_ring_type ring_type); 1236 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1237 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1238 1239 /* 1240 * CS. 1241 */ 1242 struct amdgpu_cs_chunk { 1243 uint32_t chunk_id; 1244 uint32_t length_dw; 1245 uint32_t *kdata; 1246 void __user *user_ptr; 1247 }; 1248 1249 struct amdgpu_cs_parser { 1250 struct amdgpu_device *adev; 1251 struct drm_file *filp; 1252 struct amdgpu_ctx *ctx; 1253 struct amdgpu_bo_list *bo_list; 1254 /* chunks */ 1255 unsigned nchunks; 1256 struct amdgpu_cs_chunk *chunks; 1257 /* relocations */ 1258 struct amdgpu_bo_list_entry *vm_bos; 1259 struct list_head validated; 1260 struct fence *fence; 1261 1262 struct amdgpu_ib *ibs; 1263 uint32_t num_ibs; 1264 1265 struct ww_acquire_ctx ticket; 1266 1267 /* user fence */ 1268 struct amdgpu_user_fence uf; 1269 struct amdgpu_bo_list_entry uf_entry; 1270 }; 1271 1272 struct amdgpu_job { 1273 struct amd_sched_job base; 1274 struct amdgpu_device *adev; 1275 struct amdgpu_ib *ibs; 1276 uint32_t num_ibs; 1277 void *owner; 1278 struct amdgpu_user_fence uf; 1279 int (*free_job)(struct amdgpu_job *job); 1280 }; 1281 #define to_amdgpu_job(sched_job) \ 1282 container_of((sched_job), struct amdgpu_job, base) 1283 1284 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1285 { 1286 return p->ibs[ib_idx].ptr[idx]; 1287 } 1288 1289 /* 1290 * Writeback 1291 */ 1292 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1293 1294 struct amdgpu_wb { 1295 struct amdgpu_bo *wb_obj; 1296 volatile uint32_t *wb; 1297 uint64_t gpu_addr; 1298 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1299 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 1300 }; 1301 1302 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1303 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1304 1305 /** 1306 * struct amdgpu_pm - power management datas 1307 * It keeps track of various data needed to take powermanagement decision. 1308 */ 1309 1310 enum amdgpu_pm_state_type { 1311 /* not used for dpm */ 1312 POWER_STATE_TYPE_DEFAULT, 1313 POWER_STATE_TYPE_POWERSAVE, 1314 /* user selectable states */ 1315 POWER_STATE_TYPE_BATTERY, 1316 POWER_STATE_TYPE_BALANCED, 1317 POWER_STATE_TYPE_PERFORMANCE, 1318 /* internal states */ 1319 POWER_STATE_TYPE_INTERNAL_UVD, 1320 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1321 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1322 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1323 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1324 POWER_STATE_TYPE_INTERNAL_BOOT, 1325 POWER_STATE_TYPE_INTERNAL_THERMAL, 1326 POWER_STATE_TYPE_INTERNAL_ACPI, 1327 POWER_STATE_TYPE_INTERNAL_ULV, 1328 POWER_STATE_TYPE_INTERNAL_3DPERF, 1329 }; 1330 1331 enum amdgpu_int_thermal_type { 1332 THERMAL_TYPE_NONE, 1333 THERMAL_TYPE_EXTERNAL, 1334 THERMAL_TYPE_EXTERNAL_GPIO, 1335 THERMAL_TYPE_RV6XX, 1336 THERMAL_TYPE_RV770, 1337 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1338 THERMAL_TYPE_EVERGREEN, 1339 THERMAL_TYPE_SUMO, 1340 THERMAL_TYPE_NI, 1341 THERMAL_TYPE_SI, 1342 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1343 THERMAL_TYPE_CI, 1344 THERMAL_TYPE_KV, 1345 }; 1346 1347 enum amdgpu_dpm_auto_throttle_src { 1348 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1349 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1350 }; 1351 1352 enum amdgpu_dpm_event_src { 1353 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1354 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1355 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1356 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1357 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1358 }; 1359 1360 #define AMDGPU_MAX_VCE_LEVELS 6 1361 1362 enum amdgpu_vce_level { 1363 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1364 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1365 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1366 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1367 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1368 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1369 }; 1370 1371 struct amdgpu_ps { 1372 u32 caps; /* vbios flags */ 1373 u32 class; /* vbios flags */ 1374 u32 class2; /* vbios flags */ 1375 /* UVD clocks */ 1376 u32 vclk; 1377 u32 dclk; 1378 /* VCE clocks */ 1379 u32 evclk; 1380 u32 ecclk; 1381 bool vce_active; 1382 enum amdgpu_vce_level vce_level; 1383 /* asic priv */ 1384 void *ps_priv; 1385 }; 1386 1387 struct amdgpu_dpm_thermal { 1388 /* thermal interrupt work */ 1389 struct work_struct work; 1390 /* low temperature threshold */ 1391 int min_temp; 1392 /* high temperature threshold */ 1393 int max_temp; 1394 /* was last interrupt low to high or high to low */ 1395 bool high_to_low; 1396 /* interrupt source */ 1397 struct amdgpu_irq_src irq; 1398 }; 1399 1400 enum amdgpu_clk_action 1401 { 1402 AMDGPU_SCLK_UP = 1, 1403 AMDGPU_SCLK_DOWN 1404 }; 1405 1406 struct amdgpu_blacklist_clocks 1407 { 1408 u32 sclk; 1409 u32 mclk; 1410 enum amdgpu_clk_action action; 1411 }; 1412 1413 struct amdgpu_clock_and_voltage_limits { 1414 u32 sclk; 1415 u32 mclk; 1416 u16 vddc; 1417 u16 vddci; 1418 }; 1419 1420 struct amdgpu_clock_array { 1421 u32 count; 1422 u32 *values; 1423 }; 1424 1425 struct amdgpu_clock_voltage_dependency_entry { 1426 u32 clk; 1427 u16 v; 1428 }; 1429 1430 struct amdgpu_clock_voltage_dependency_table { 1431 u32 count; 1432 struct amdgpu_clock_voltage_dependency_entry *entries; 1433 }; 1434 1435 union amdgpu_cac_leakage_entry { 1436 struct { 1437 u16 vddc; 1438 u32 leakage; 1439 }; 1440 struct { 1441 u16 vddc1; 1442 u16 vddc2; 1443 u16 vddc3; 1444 }; 1445 }; 1446 1447 struct amdgpu_cac_leakage_table { 1448 u32 count; 1449 union amdgpu_cac_leakage_entry *entries; 1450 }; 1451 1452 struct amdgpu_phase_shedding_limits_entry { 1453 u16 voltage; 1454 u32 sclk; 1455 u32 mclk; 1456 }; 1457 1458 struct amdgpu_phase_shedding_limits_table { 1459 u32 count; 1460 struct amdgpu_phase_shedding_limits_entry *entries; 1461 }; 1462 1463 struct amdgpu_uvd_clock_voltage_dependency_entry { 1464 u32 vclk; 1465 u32 dclk; 1466 u16 v; 1467 }; 1468 1469 struct amdgpu_uvd_clock_voltage_dependency_table { 1470 u8 count; 1471 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1472 }; 1473 1474 struct amdgpu_vce_clock_voltage_dependency_entry { 1475 u32 ecclk; 1476 u32 evclk; 1477 u16 v; 1478 }; 1479 1480 struct amdgpu_vce_clock_voltage_dependency_table { 1481 u8 count; 1482 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1483 }; 1484 1485 struct amdgpu_ppm_table { 1486 u8 ppm_design; 1487 u16 cpu_core_number; 1488 u32 platform_tdp; 1489 u32 small_ac_platform_tdp; 1490 u32 platform_tdc; 1491 u32 small_ac_platform_tdc; 1492 u32 apu_tdp; 1493 u32 dgpu_tdp; 1494 u32 dgpu_ulv_power; 1495 u32 tj_max; 1496 }; 1497 1498 struct amdgpu_cac_tdp_table { 1499 u16 tdp; 1500 u16 configurable_tdp; 1501 u16 tdc; 1502 u16 battery_power_limit; 1503 u16 small_power_limit; 1504 u16 low_cac_leakage; 1505 u16 high_cac_leakage; 1506 u16 maximum_power_delivery_limit; 1507 }; 1508 1509 struct amdgpu_dpm_dynamic_state { 1510 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1511 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1512 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1513 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1514 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1515 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1516 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1517 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1518 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1519 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1520 struct amdgpu_clock_array valid_sclk_values; 1521 struct amdgpu_clock_array valid_mclk_values; 1522 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1523 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1524 u32 mclk_sclk_ratio; 1525 u32 sclk_mclk_delta; 1526 u16 vddc_vddci_delta; 1527 u16 min_vddc_for_pcie_gen2; 1528 struct amdgpu_cac_leakage_table cac_leakage_table; 1529 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1530 struct amdgpu_ppm_table *ppm_table; 1531 struct amdgpu_cac_tdp_table *cac_tdp_table; 1532 }; 1533 1534 struct amdgpu_dpm_fan { 1535 u16 t_min; 1536 u16 t_med; 1537 u16 t_high; 1538 u16 pwm_min; 1539 u16 pwm_med; 1540 u16 pwm_high; 1541 u8 t_hyst; 1542 u32 cycle_delay; 1543 u16 t_max; 1544 u8 control_mode; 1545 u16 default_max_fan_pwm; 1546 u16 default_fan_output_sensitivity; 1547 u16 fan_output_sensitivity; 1548 bool ucode_fan_control; 1549 }; 1550 1551 enum amdgpu_pcie_gen { 1552 AMDGPU_PCIE_GEN1 = 0, 1553 AMDGPU_PCIE_GEN2 = 1, 1554 AMDGPU_PCIE_GEN3 = 2, 1555 AMDGPU_PCIE_GEN_INVALID = 0xffff 1556 }; 1557 1558 enum amdgpu_dpm_forced_level { 1559 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1560 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1561 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1562 }; 1563 1564 struct amdgpu_vce_state { 1565 /* vce clocks */ 1566 u32 evclk; 1567 u32 ecclk; 1568 /* gpu clocks */ 1569 u32 sclk; 1570 u32 mclk; 1571 u8 clk_idx; 1572 u8 pstate; 1573 }; 1574 1575 struct amdgpu_dpm_funcs { 1576 int (*get_temperature)(struct amdgpu_device *adev); 1577 int (*pre_set_power_state)(struct amdgpu_device *adev); 1578 int (*set_power_state)(struct amdgpu_device *adev); 1579 void (*post_set_power_state)(struct amdgpu_device *adev); 1580 void (*display_configuration_changed)(struct amdgpu_device *adev); 1581 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1582 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1583 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1584 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1585 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1586 bool (*vblank_too_short)(struct amdgpu_device *adev); 1587 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1588 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1589 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1590 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1591 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1592 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1593 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1594 }; 1595 1596 struct amdgpu_dpm { 1597 struct amdgpu_ps *ps; 1598 /* number of valid power states */ 1599 int num_ps; 1600 /* current power state that is active */ 1601 struct amdgpu_ps *current_ps; 1602 /* requested power state */ 1603 struct amdgpu_ps *requested_ps; 1604 /* boot up power state */ 1605 struct amdgpu_ps *boot_ps; 1606 /* default uvd power state */ 1607 struct amdgpu_ps *uvd_ps; 1608 /* vce requirements */ 1609 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1610 enum amdgpu_vce_level vce_level; 1611 enum amdgpu_pm_state_type state; 1612 enum amdgpu_pm_state_type user_state; 1613 u32 platform_caps; 1614 u32 voltage_response_time; 1615 u32 backbias_response_time; 1616 void *priv; 1617 u32 new_active_crtcs; 1618 int new_active_crtc_count; 1619 u32 current_active_crtcs; 1620 int current_active_crtc_count; 1621 struct amdgpu_dpm_dynamic_state dyn_state; 1622 struct amdgpu_dpm_fan fan; 1623 u32 tdp_limit; 1624 u32 near_tdp_limit; 1625 u32 near_tdp_limit_adjusted; 1626 u32 sq_ramping_threshold; 1627 u32 cac_leakage; 1628 u16 tdp_od_limit; 1629 u32 tdp_adjustment; 1630 u16 load_line_slope; 1631 bool power_control; 1632 bool ac_power; 1633 /* special states active */ 1634 bool thermal_active; 1635 bool uvd_active; 1636 bool vce_active; 1637 /* thermal handling */ 1638 struct amdgpu_dpm_thermal thermal; 1639 /* forced levels */ 1640 enum amdgpu_dpm_forced_level forced_level; 1641 }; 1642 1643 struct amdgpu_pm { 1644 struct mutex mutex; 1645 u32 current_sclk; 1646 u32 current_mclk; 1647 u32 default_sclk; 1648 u32 default_mclk; 1649 struct amdgpu_i2c_chan *i2c_bus; 1650 /* internal thermal controller on rv6xx+ */ 1651 enum amdgpu_int_thermal_type int_thermal_type; 1652 struct device *int_hwmon_dev; 1653 /* fan control parameters */ 1654 bool no_fan; 1655 u8 fan_pulses_per_revolution; 1656 u8 fan_min_rpm; 1657 u8 fan_max_rpm; 1658 /* dpm */ 1659 bool dpm_enabled; 1660 bool sysfs_initialized; 1661 struct amdgpu_dpm dpm; 1662 const struct firmware *fw; /* SMC firmware */ 1663 uint32_t fw_version; 1664 const struct amdgpu_dpm_funcs *funcs; 1665 }; 1666 1667 /* 1668 * UVD 1669 */ 1670 #define AMDGPU_MAX_UVD_HANDLES 10 1671 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1672 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1673 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1674 1675 struct amdgpu_uvd { 1676 struct amdgpu_bo *vcpu_bo; 1677 void *cpu_addr; 1678 uint64_t gpu_addr; 1679 unsigned fw_version; 1680 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1681 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1682 struct delayed_work idle_work; 1683 const struct firmware *fw; /* UVD firmware */ 1684 struct amdgpu_ring ring; 1685 struct amdgpu_irq_src irq; 1686 bool address_64_bit; 1687 }; 1688 1689 /* 1690 * VCE 1691 */ 1692 #define AMDGPU_MAX_VCE_HANDLES 16 1693 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1694 1695 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1696 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1697 1698 struct amdgpu_vce { 1699 struct amdgpu_bo *vcpu_bo; 1700 uint64_t gpu_addr; 1701 unsigned fw_version; 1702 unsigned fb_version; 1703 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1704 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1705 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1706 struct delayed_work idle_work; 1707 const struct firmware *fw; /* VCE firmware */ 1708 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1709 struct amdgpu_irq_src irq; 1710 unsigned harvest_config; 1711 }; 1712 1713 /* 1714 * SDMA 1715 */ 1716 struct amdgpu_sdma_instance { 1717 /* SDMA firmware */ 1718 const struct firmware *fw; 1719 uint32_t fw_version; 1720 uint32_t feature_version; 1721 1722 struct amdgpu_ring ring; 1723 bool burst_nop; 1724 }; 1725 1726 struct amdgpu_sdma { 1727 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1728 struct amdgpu_irq_src trap_irq; 1729 struct amdgpu_irq_src illegal_inst_irq; 1730 int num_instances; 1731 }; 1732 1733 /* 1734 * Firmware 1735 */ 1736 struct amdgpu_firmware { 1737 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1738 bool smu_load; 1739 struct amdgpu_bo *fw_buf; 1740 unsigned int fw_size; 1741 }; 1742 1743 /* 1744 * Benchmarking 1745 */ 1746 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1747 1748 1749 /* 1750 * Testing 1751 */ 1752 void amdgpu_test_moves(struct amdgpu_device *adev); 1753 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1754 struct amdgpu_ring *cpA, 1755 struct amdgpu_ring *cpB); 1756 void amdgpu_test_syncing(struct amdgpu_device *adev); 1757 1758 /* 1759 * MMU Notifier 1760 */ 1761 #if defined(CONFIG_MMU_NOTIFIER) 1762 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1763 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1764 #else 1765 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1766 { 1767 return -ENODEV; 1768 } 1769 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1770 #endif 1771 1772 /* 1773 * Debugfs 1774 */ 1775 struct amdgpu_debugfs { 1776 struct drm_info_list *files; 1777 unsigned num_files; 1778 }; 1779 1780 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1781 struct drm_info_list *files, 1782 unsigned nfiles); 1783 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1784 1785 #if defined(CONFIG_DEBUG_FS) 1786 int amdgpu_debugfs_init(struct drm_minor *minor); 1787 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1788 #endif 1789 1790 /* 1791 * amdgpu smumgr functions 1792 */ 1793 struct amdgpu_smumgr_funcs { 1794 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1795 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1796 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1797 }; 1798 1799 /* 1800 * amdgpu smumgr 1801 */ 1802 struct amdgpu_smumgr { 1803 struct amdgpu_bo *toc_buf; 1804 struct amdgpu_bo *smu_buf; 1805 /* asic priv smu data */ 1806 void *priv; 1807 spinlock_t smu_lock; 1808 /* smumgr functions */ 1809 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1810 /* ucode loading complete flag */ 1811 uint32_t fw_flags; 1812 }; 1813 1814 /* 1815 * ASIC specific register table accessible by UMD 1816 */ 1817 struct amdgpu_allowed_register_entry { 1818 uint32_t reg_offset; 1819 bool untouched; 1820 bool grbm_indexed; 1821 }; 1822 1823 struct amdgpu_cu_info { 1824 uint32_t number; /* total active CU number */ 1825 uint32_t ao_cu_mask; 1826 uint32_t bitmap[4][4]; 1827 }; 1828 1829 1830 /* 1831 * ASIC specific functions. 1832 */ 1833 struct amdgpu_asic_funcs { 1834 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1835 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1836 u32 sh_num, u32 reg_offset, u32 *value); 1837 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1838 int (*reset)(struct amdgpu_device *adev); 1839 /* wait for mc_idle */ 1840 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1841 /* get the reference clock */ 1842 u32 (*get_xclk)(struct amdgpu_device *adev); 1843 /* get the gpu clock counter */ 1844 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1845 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1846 /* MM block clocks */ 1847 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1848 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1849 }; 1850 1851 /* 1852 * IOCTL. 1853 */ 1854 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1855 struct drm_file *filp); 1856 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1857 struct drm_file *filp); 1858 1859 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1860 struct drm_file *filp); 1861 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1862 struct drm_file *filp); 1863 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1864 struct drm_file *filp); 1865 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1866 struct drm_file *filp); 1867 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1868 struct drm_file *filp); 1869 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1870 struct drm_file *filp); 1871 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1872 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1873 1874 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1875 struct drm_file *filp); 1876 1877 /* VRAM scratch page for HDP bug, default vram page */ 1878 struct amdgpu_vram_scratch { 1879 struct amdgpu_bo *robj; 1880 volatile uint32_t *ptr; 1881 u64 gpu_addr; 1882 }; 1883 1884 /* 1885 * ACPI 1886 */ 1887 struct amdgpu_atif_notification_cfg { 1888 bool enabled; 1889 int command_code; 1890 }; 1891 1892 struct amdgpu_atif_notifications { 1893 bool display_switch; 1894 bool expansion_mode_change; 1895 bool thermal_state; 1896 bool forced_power_state; 1897 bool system_power_state; 1898 bool display_conf_change; 1899 bool px_gfx_switch; 1900 bool brightness_change; 1901 bool dgpu_display_event; 1902 }; 1903 1904 struct amdgpu_atif_functions { 1905 bool system_params; 1906 bool sbios_requests; 1907 bool select_active_disp; 1908 bool lid_state; 1909 bool get_tv_standard; 1910 bool set_tv_standard; 1911 bool get_panel_expansion_mode; 1912 bool set_panel_expansion_mode; 1913 bool temperature_change; 1914 bool graphics_device_types; 1915 }; 1916 1917 struct amdgpu_atif { 1918 struct amdgpu_atif_notifications notifications; 1919 struct amdgpu_atif_functions functions; 1920 struct amdgpu_atif_notification_cfg notification_cfg; 1921 struct amdgpu_encoder *encoder_for_bl; 1922 }; 1923 1924 struct amdgpu_atcs_functions { 1925 bool get_ext_state; 1926 bool pcie_perf_req; 1927 bool pcie_dev_rdy; 1928 bool pcie_bus_width; 1929 }; 1930 1931 struct amdgpu_atcs { 1932 struct amdgpu_atcs_functions functions; 1933 }; 1934 1935 /* 1936 * CGS 1937 */ 1938 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1939 void amdgpu_cgs_destroy_device(void *cgs_device); 1940 1941 1942 /* 1943 * Core structure, functions and helpers. 1944 */ 1945 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1946 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1947 1948 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1949 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 1950 1951 struct amdgpu_ip_block_status { 1952 bool valid; 1953 bool sw; 1954 bool hw; 1955 }; 1956 1957 struct amdgpu_device { 1958 struct device *dev; 1959 struct drm_device *ddev; 1960 struct pci_dev *pdev; 1961 1962 /* ASIC */ 1963 enum amd_asic_type asic_type; 1964 uint32_t family; 1965 uint32_t rev_id; 1966 uint32_t external_rev_id; 1967 unsigned long flags; 1968 int usec_timeout; 1969 const struct amdgpu_asic_funcs *asic_funcs; 1970 bool shutdown; 1971 bool suspend; 1972 bool need_dma32; 1973 bool accel_working; 1974 struct work_struct reset_work; 1975 struct notifier_block acpi_nb; 1976 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 1977 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 1978 unsigned debugfs_count; 1979 #if defined(CONFIG_DEBUG_FS) 1980 struct dentry *debugfs_regs; 1981 #endif 1982 struct amdgpu_atif atif; 1983 struct amdgpu_atcs atcs; 1984 struct mutex srbm_mutex; 1985 /* GRBM index mutex. Protects concurrent access to GRBM index */ 1986 struct mutex grbm_idx_mutex; 1987 struct dev_pm_domain vga_pm_domain; 1988 bool have_disp_power_ref; 1989 1990 /* BIOS */ 1991 uint8_t *bios; 1992 bool is_atom_bios; 1993 uint16_t bios_header_start; 1994 struct amdgpu_bo *stollen_vga_memory; 1995 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 1996 1997 /* Register/doorbell mmio */ 1998 resource_size_t rmmio_base; 1999 resource_size_t rmmio_size; 2000 void __iomem *rmmio; 2001 /* protects concurrent MM_INDEX/DATA based register access */ 2002 spinlock_t mmio_idx_lock; 2003 /* protects concurrent SMC based register access */ 2004 spinlock_t smc_idx_lock; 2005 amdgpu_rreg_t smc_rreg; 2006 amdgpu_wreg_t smc_wreg; 2007 /* protects concurrent PCIE register access */ 2008 spinlock_t pcie_idx_lock; 2009 amdgpu_rreg_t pcie_rreg; 2010 amdgpu_wreg_t pcie_wreg; 2011 /* protects concurrent UVD register access */ 2012 spinlock_t uvd_ctx_idx_lock; 2013 amdgpu_rreg_t uvd_ctx_rreg; 2014 amdgpu_wreg_t uvd_ctx_wreg; 2015 /* protects concurrent DIDT register access */ 2016 spinlock_t didt_idx_lock; 2017 amdgpu_rreg_t didt_rreg; 2018 amdgpu_wreg_t didt_wreg; 2019 /* protects concurrent ENDPOINT (audio) register access */ 2020 spinlock_t audio_endpt_idx_lock; 2021 amdgpu_block_rreg_t audio_endpt_rreg; 2022 amdgpu_block_wreg_t audio_endpt_wreg; 2023 void __iomem *rio_mem; 2024 resource_size_t rio_mem_size; 2025 struct amdgpu_doorbell doorbell; 2026 2027 /* clock/pll info */ 2028 struct amdgpu_clock clock; 2029 2030 /* MC */ 2031 struct amdgpu_mc mc; 2032 struct amdgpu_gart gart; 2033 struct amdgpu_dummy_page dummy_page; 2034 struct amdgpu_vm_manager vm_manager; 2035 2036 /* memory management */ 2037 struct amdgpu_mman mman; 2038 struct amdgpu_gem gem; 2039 struct amdgpu_vram_scratch vram_scratch; 2040 struct amdgpu_wb wb; 2041 atomic64_t vram_usage; 2042 atomic64_t vram_vis_usage; 2043 atomic64_t gtt_usage; 2044 atomic64_t num_bytes_moved; 2045 atomic_t gpu_reset_counter; 2046 2047 /* display */ 2048 struct amdgpu_mode_info mode_info; 2049 struct work_struct hotplug_work; 2050 struct amdgpu_irq_src crtc_irq; 2051 struct amdgpu_irq_src pageflip_irq; 2052 struct amdgpu_irq_src hpd_irq; 2053 2054 /* rings */ 2055 unsigned fence_context; 2056 struct mutex ring_lock; 2057 unsigned num_rings; 2058 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2059 bool ib_pool_ready; 2060 struct amdgpu_sa_manager ring_tmp_bo; 2061 2062 /* interrupts */ 2063 struct amdgpu_irq irq; 2064 2065 /* dpm */ 2066 struct amdgpu_pm pm; 2067 u32 cg_flags; 2068 u32 pg_flags; 2069 2070 /* amdgpu smumgr */ 2071 struct amdgpu_smumgr smu; 2072 2073 /* gfx */ 2074 struct amdgpu_gfx gfx; 2075 2076 /* sdma */ 2077 struct amdgpu_sdma sdma; 2078 2079 /* uvd */ 2080 bool has_uvd; 2081 struct amdgpu_uvd uvd; 2082 2083 /* vce */ 2084 struct amdgpu_vce vce; 2085 2086 /* firmwares */ 2087 struct amdgpu_firmware firmware; 2088 2089 /* GDS */ 2090 struct amdgpu_gds gds; 2091 2092 const struct amdgpu_ip_block_version *ip_blocks; 2093 int num_ip_blocks; 2094 struct amdgpu_ip_block_status *ip_block_status; 2095 struct mutex mn_lock; 2096 DECLARE_HASHTABLE(mn_hash, 7); 2097 2098 /* tracking pinned memory */ 2099 u64 vram_pin_size; 2100 u64 gart_pin_size; 2101 2102 /* amdkfd interface */ 2103 struct kfd_dev *kfd; 2104 2105 /* kernel conext for IB submission */ 2106 struct amdgpu_ctx kernel_ctx; 2107 }; 2108 2109 bool amdgpu_device_is_px(struct drm_device *dev); 2110 int amdgpu_device_init(struct amdgpu_device *adev, 2111 struct drm_device *ddev, 2112 struct pci_dev *pdev, 2113 uint32_t flags); 2114 void amdgpu_device_fini(struct amdgpu_device *adev); 2115 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2116 2117 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2118 bool always_indirect); 2119 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2120 bool always_indirect); 2121 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2122 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2123 2124 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2125 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2126 2127 /* 2128 * Cast helper 2129 */ 2130 extern const struct fence_ops amdgpu_fence_ops; 2131 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2132 { 2133 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2134 2135 if (__f->base.ops == &amdgpu_fence_ops) 2136 return __f; 2137 2138 return NULL; 2139 } 2140 2141 /* 2142 * Registers read & write functions. 2143 */ 2144 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2145 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2146 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2147 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2148 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2149 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2150 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2151 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2152 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2153 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2154 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2155 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2156 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2157 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2158 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2159 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2160 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2161 #define WREG32_P(reg, val, mask) \ 2162 do { \ 2163 uint32_t tmp_ = RREG32(reg); \ 2164 tmp_ &= (mask); \ 2165 tmp_ |= ((val) & ~(mask)); \ 2166 WREG32(reg, tmp_); \ 2167 } while (0) 2168 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2169 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2170 #define WREG32_PLL_P(reg, val, mask) \ 2171 do { \ 2172 uint32_t tmp_ = RREG32_PLL(reg); \ 2173 tmp_ &= (mask); \ 2174 tmp_ |= ((val) & ~(mask)); \ 2175 WREG32_PLL(reg, tmp_); \ 2176 } while (0) 2177 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2178 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2179 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2180 2181 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2182 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2183 2184 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2185 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2186 2187 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2188 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2189 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2190 2191 #define REG_GET_FIELD(value, reg, field) \ 2192 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2193 2194 /* 2195 * BIOS helpers. 2196 */ 2197 #define RBIOS8(i) (adev->bios[i]) 2198 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2199 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2200 2201 /* 2202 * RING helpers. 2203 */ 2204 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2205 { 2206 if (ring->count_dw <= 0) 2207 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2208 ring->ring[ring->wptr++] = v; 2209 ring->wptr &= ring->ptr_mask; 2210 ring->count_dw--; 2211 ring->ring_free_dw--; 2212 } 2213 2214 static inline struct amdgpu_sdma_instance * 2215 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2216 { 2217 struct amdgpu_device *adev = ring->adev; 2218 int i; 2219 2220 for (i = 0; i < adev->sdma.num_instances; i++) 2221 if (&adev->sdma.instance[i].ring == ring) 2222 break; 2223 2224 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2225 return &adev->sdma.instance[i]; 2226 else 2227 return NULL; 2228 } 2229 2230 /* 2231 * ASICs macro. 2232 */ 2233 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2234 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2235 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2236 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2237 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2238 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2239 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2240 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2241 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2242 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2243 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2244 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2245 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2246 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2247 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2248 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2249 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2250 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2251 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2252 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2253 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2254 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2255 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2256 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2257 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2258 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2259 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2260 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2261 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2262 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2263 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2264 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2265 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2266 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2267 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2268 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2269 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2270 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2271 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2272 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2273 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2274 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2275 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2276 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2277 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2278 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2279 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2280 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2281 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2282 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2283 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2284 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2285 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2286 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2287 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2288 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2289 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2290 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2291 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2292 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2293 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2294 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2295 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2296 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2297 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2298 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2299 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2300 2301 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2302 2303 /* Common functions */ 2304 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2305 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2306 bool amdgpu_card_posted(struct amdgpu_device *adev); 2307 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2308 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2309 2310 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2311 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2312 u32 ip_instance, u32 ring, 2313 struct amdgpu_ring **out_ring); 2314 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2315 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2316 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2317 uint32_t flags); 2318 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2319 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2320 unsigned long end); 2321 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2322 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2323 struct ttm_mem_reg *mem); 2324 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2325 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2326 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2327 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2328 const u32 *registers, 2329 const u32 array_size); 2330 2331 bool amdgpu_device_is_px(struct drm_device *dev); 2332 /* atpx handler */ 2333 #if defined(CONFIG_VGA_SWITCHEROO) 2334 void amdgpu_register_atpx_handler(void); 2335 void amdgpu_unregister_atpx_handler(void); 2336 #else 2337 static inline void amdgpu_register_atpx_handler(void) {} 2338 static inline void amdgpu_unregister_atpx_handler(void) {} 2339 #endif 2340 2341 /* 2342 * KMS 2343 */ 2344 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2345 extern int amdgpu_max_kms_ioctl; 2346 2347 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2348 int amdgpu_driver_unload_kms(struct drm_device *dev); 2349 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2350 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2351 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2352 struct drm_file *file_priv); 2353 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2354 struct drm_file *file_priv); 2355 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2356 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2357 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2358 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2359 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2360 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2361 int *max_error, 2362 struct timeval *vblank_time, 2363 unsigned flags); 2364 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2365 unsigned long arg); 2366 2367 /* 2368 * functions used by amdgpu_encoder.c 2369 */ 2370 struct amdgpu_afmt_acr { 2371 u32 clock; 2372 2373 int n_32khz; 2374 int cts_32khz; 2375 2376 int n_44_1khz; 2377 int cts_44_1khz; 2378 2379 int n_48khz; 2380 int cts_48khz; 2381 2382 }; 2383 2384 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2385 2386 /* amdgpu_acpi.c */ 2387 #if defined(CONFIG_ACPI) 2388 int amdgpu_acpi_init(struct amdgpu_device *adev); 2389 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2390 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2391 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2392 u8 perf_req, bool advertise); 2393 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2394 #else 2395 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2396 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2397 #endif 2398 2399 struct amdgpu_bo_va_mapping * 2400 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2401 uint64_t addr, struct amdgpu_bo **bo); 2402 2403 #include "amdgpu_object.h" 2404 2405 #endif 2406
Indexes created Mon Sep 29 21:09:56 GMT 2025