amdgpu.h revision 1.1.1.2
1 /* $NetBSD: amdgpu.h,v 1.1.1.2 2021/12/18 20:11:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #include "amdgpu_ctx.h" 34 35 #include <linux/atomic.h> 36 #include <linux/wait.h> 37 #include <linux/list.h> 38 #include <linux/kref.h> 39 #include <linux/rbtree.h> 40 #include <linux/hashtable.h> 41 #include <linux/dma-fence.h> 42 43 #include <drm/ttm/ttm_bo_api.h> 44 #include <drm/ttm/ttm_bo_driver.h> 45 #include <drm/ttm/ttm_placement.h> 46 #include <drm/ttm/ttm_module.h> 47 #include <drm/ttm/ttm_execbuf_util.h> 48 49 #include <drm/amdgpu_drm.h> 50 #include <drm/drm_gem.h> 51 #include <drm/drm_ioctl.h> 52 #include <drm/gpu_scheduler.h> 53 54 #include <kgd_kfd_interface.h> 55 #include "dm_pp_interface.h" 56 #include "kgd_pp_interface.h" 57 58 #include "amd_shared.h" 59 #include "amdgpu_mode.h" 60 #include "amdgpu_ih.h" 61 #include "amdgpu_irq.h" 62 #include "amdgpu_ucode.h" 63 #include "amdgpu_ttm.h" 64 #include "amdgpu_psp.h" 65 #include "amdgpu_gds.h" 66 #include "amdgpu_sync.h" 67 #include "amdgpu_ring.h" 68 #include "amdgpu_vm.h" 69 #include "amdgpu_dpm.h" 70 #include "amdgpu_acp.h" 71 #include "amdgpu_uvd.h" 72 #include "amdgpu_vce.h" 73 #include "amdgpu_vcn.h" 74 #include "amdgpu_jpeg.h" 75 #include "amdgpu_mn.h" 76 #include "amdgpu_gmc.h" 77 #include "amdgpu_gfx.h" 78 #include "amdgpu_sdma.h" 79 #include "amdgpu_nbio.h" 80 #include "amdgpu_dm.h" 81 #include "amdgpu_virt.h" 82 #include "amdgpu_csa.h" 83 #include "amdgpu_gart.h" 84 #include "amdgpu_debugfs.h" 85 #include "amdgpu_job.h" 86 #include "amdgpu_bo_list.h" 87 #include "amdgpu_gem.h" 88 #include "amdgpu_doorbell.h" 89 #include "amdgpu_amdkfd.h" 90 #include "amdgpu_smu.h" 91 #include "amdgpu_discovery.h" 92 #include "amdgpu_mes.h" 93 #include "amdgpu_umc.h" 94 #include "amdgpu_mmhub.h" 95 #include "amdgpu_df.h" 96 97 #define MAX_GPU_INSTANCE 16 98 99 struct amdgpu_gpu_instance 100 { 101 struct amdgpu_device *adev; 102 int mgpu_fan_enabled; 103 }; 104 105 struct amdgpu_mgpu_info 106 { 107 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 108 struct mutex mutex; 109 uint32_t num_gpu; 110 uint32_t num_dgpu; 111 uint32_t num_apu; 112 }; 113 114 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 115 116 /* 117 * Modules parameters. 118 */ 119 extern int amdgpu_modeset; 120 extern int amdgpu_vram_limit; 121 extern int amdgpu_vis_vram_limit; 122 extern int amdgpu_gart_size; 123 extern int amdgpu_gtt_size; 124 extern int amdgpu_moverate; 125 extern int amdgpu_benchmarking; 126 extern int amdgpu_testing; 127 extern int amdgpu_audio; 128 extern int amdgpu_disp_priority; 129 extern int amdgpu_hw_i2c; 130 extern int amdgpu_pcie_gen2; 131 extern int amdgpu_msi; 132 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 133 extern int amdgpu_dpm; 134 extern int amdgpu_fw_load_type; 135 extern int amdgpu_aspm; 136 extern int amdgpu_runtime_pm; 137 extern uint amdgpu_ip_block_mask; 138 extern int amdgpu_bapm; 139 extern int amdgpu_deep_color; 140 extern int amdgpu_vm_size; 141 extern int amdgpu_vm_block_size; 142 extern int amdgpu_vm_fragment_size; 143 extern int amdgpu_vm_fault_stop; 144 extern int amdgpu_vm_debug; 145 extern int amdgpu_vm_update_mode; 146 extern int amdgpu_exp_hw_support; 147 extern int amdgpu_dc; 148 extern int amdgpu_sched_jobs; 149 extern int amdgpu_sched_hw_submission; 150 extern uint amdgpu_pcie_gen_cap; 151 extern uint amdgpu_pcie_lane_cap; 152 extern uint amdgpu_cg_mask; 153 extern uint amdgpu_pg_mask; 154 extern uint amdgpu_sdma_phase_quantum; 155 extern char *amdgpu_disable_cu; 156 extern char *amdgpu_virtual_display; 157 extern uint amdgpu_pp_feature_mask; 158 extern uint amdgpu_force_long_training; 159 extern int amdgpu_job_hang_limit; 160 extern int amdgpu_lbpw; 161 extern int amdgpu_compute_multipipe; 162 extern int amdgpu_gpu_recovery; 163 extern int amdgpu_emu_mode; 164 extern uint amdgpu_smu_memory_pool_size; 165 extern uint amdgpu_dc_feature_mask; 166 extern uint amdgpu_dm_abm_level; 167 extern struct amdgpu_mgpu_info mgpu_info; 168 extern int amdgpu_ras_enable; 169 extern uint amdgpu_ras_mask; 170 extern int amdgpu_async_gfx_ring; 171 extern int amdgpu_mcbp; 172 extern int amdgpu_discovery; 173 extern int amdgpu_mes; 174 extern int amdgpu_noretry; 175 extern int amdgpu_force_asic_type; 176 #ifdef CONFIG_HSA_AMD 177 extern int sched_policy; 178 #else 179 static const int sched_policy = KFD_SCHED_POLICY_HWS; 180 #endif 181 182 #ifdef CONFIG_DRM_AMDGPU_SI 183 extern int amdgpu_si_support; 184 #endif 185 #ifdef CONFIG_DRM_AMDGPU_CIK 186 extern int amdgpu_cik_support; 187 #endif 188 189 #define AMDGPU_VM_MAX_NUM_CTX 4096 190 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 191 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 192 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 193 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 194 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 195 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 196 #define AMDGPU_IB_POOL_SIZE 16 197 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 198 #define AMDGPUFB_CONN_LIMIT 4 199 #define AMDGPU_BIOS_NUM_SCRATCH 16 200 201 /* hard reset data */ 202 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 203 204 /* reset flags */ 205 #define AMDGPU_RESET_GFX (1 << 0) 206 #define AMDGPU_RESET_COMPUTE (1 << 1) 207 #define AMDGPU_RESET_DMA (1 << 2) 208 #define AMDGPU_RESET_CP (1 << 3) 209 #define AMDGPU_RESET_GRBM (1 << 4) 210 #define AMDGPU_RESET_DMA1 (1 << 5) 211 #define AMDGPU_RESET_RLC (1 << 6) 212 #define AMDGPU_RESET_SEM (1 << 7) 213 #define AMDGPU_RESET_IH (1 << 8) 214 #define AMDGPU_RESET_VMC (1 << 9) 215 #define AMDGPU_RESET_MC (1 << 10) 216 #define AMDGPU_RESET_DISPLAY (1 << 11) 217 #define AMDGPU_RESET_UVD (1 << 12) 218 #define AMDGPU_RESET_VCE (1 << 13) 219 #define AMDGPU_RESET_VCE1 (1 << 14) 220 221 /* max cursor sizes (in pixels) */ 222 #define CIK_CURSOR_WIDTH 128 223 #define CIK_CURSOR_HEIGHT 128 224 225 struct amdgpu_device; 226 struct amdgpu_ib; 227 struct amdgpu_cs_parser; 228 struct amdgpu_job; 229 struct amdgpu_irq_src; 230 struct amdgpu_fpriv; 231 struct amdgpu_bo_va_mapping; 232 struct amdgpu_atif; 233 struct kfd_vm_fault_info; 234 235 enum amdgpu_cp_irq { 236 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 237 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 238 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 239 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 240 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 241 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 242 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 243 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 244 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 245 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 246 247 AMDGPU_CP_IRQ_LAST 248 }; 249 250 enum amdgpu_thermal_irq { 251 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 252 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 253 254 AMDGPU_THERMAL_IRQ_LAST 255 }; 256 257 enum amdgpu_kiq_irq { 258 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 259 AMDGPU_CP_KIQ_IRQ_LAST 260 }; 261 262 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 263 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 264 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 265 266 int amdgpu_device_ip_set_clockgating_state(void *dev, 267 enum amd_ip_block_type block_type, 268 enum amd_clockgating_state state); 269 int amdgpu_device_ip_set_powergating_state(void *dev, 270 enum amd_ip_block_type block_type, 271 enum amd_powergating_state state); 272 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 273 u32 *flags); 274 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 275 enum amd_ip_block_type block_type); 276 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 277 enum amd_ip_block_type block_type); 278 279 #define AMDGPU_MAX_IP_NUM 16 280 281 struct amdgpu_ip_block_status { 282 bool valid; 283 bool sw; 284 bool hw; 285 bool late_initialized; 286 bool hang; 287 }; 288 289 struct amdgpu_ip_block_version { 290 const enum amd_ip_block_type type; 291 const u32 major; 292 const u32 minor; 293 const u32 rev; 294 const struct amd_ip_funcs *funcs; 295 }; 296 297 #define HW_REV(_Major, _Minor, _Rev) \ 298 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 299 300 struct amdgpu_ip_block { 301 struct amdgpu_ip_block_status status; 302 const struct amdgpu_ip_block_version *version; 303 }; 304 305 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 306 enum amd_ip_block_type type, 307 u32 major, u32 minor); 308 309 struct amdgpu_ip_block * 310 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 311 enum amd_ip_block_type type); 312 313 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 314 const struct amdgpu_ip_block_version *ip_block_version); 315 316 /* 317 * BIOS. 318 */ 319 bool amdgpu_get_bios(struct amdgpu_device *adev); 320 bool amdgpu_read_bios(struct amdgpu_device *adev); 321 322 /* 323 * Clocks 324 */ 325 326 #define AMDGPU_MAX_PPLL 3 327 328 struct amdgpu_clock { 329 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 330 struct amdgpu_pll spll; 331 struct amdgpu_pll mpll; 332 /* 10 Khz units */ 333 uint32_t default_mclk; 334 uint32_t default_sclk; 335 uint32_t default_dispclk; 336 uint32_t current_dispclk; 337 uint32_t dp_extclk; 338 uint32_t max_pixel_clock; 339 }; 340 341 /* sub-allocation manager, it has to be protected by another lock. 342 * By conception this is an helper for other part of the driver 343 * like the indirect buffer or semaphore, which both have their 344 * locking. 345 * 346 * Principe is simple, we keep a list of sub allocation in offset 347 * order (first entry has offset == 0, last entry has the highest 348 * offset). 349 * 350 * When allocating new object we first check if there is room at 351 * the end total_size - (last_object_offset + last_object_size) >= 352 * alloc_size. If so we allocate new object there. 353 * 354 * When there is not enough room at the end, we start waiting for 355 * each sub object until we reach object_offset+object_size >= 356 * alloc_size, this object then become the sub object we return. 357 * 358 * Alignment can't be bigger than page size. 359 * 360 * Hole are not considered for allocation to keep things simple. 361 * Assumption is that there won't be hole (all object on same 362 * alignment). 363 */ 364 365 #define AMDGPU_SA_NUM_FENCE_LISTS 32 366 367 struct amdgpu_sa_manager { 368 wait_queue_head_t wq; 369 struct amdgpu_bo *bo; 370 struct list_head *hole; 371 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 372 struct list_head olist; 373 unsigned size; 374 uint64_t gpu_addr; 375 void *cpu_ptr; 376 uint32_t domain; 377 uint32_t align; 378 }; 379 380 /* sub-allocation buffer */ 381 struct amdgpu_sa_bo { 382 struct list_head olist; 383 struct list_head flist; 384 struct amdgpu_sa_manager *manager; 385 unsigned soffset; 386 unsigned eoffset; 387 struct dma_fence *fence; 388 }; 389 390 int amdgpu_fence_slab_init(void); 391 void amdgpu_fence_slab_fini(void); 392 393 /* 394 * IRQS. 395 */ 396 397 struct amdgpu_flip_work { 398 struct delayed_work flip_work; 399 struct work_struct unpin_work; 400 struct amdgpu_device *adev; 401 int crtc_id; 402 u32 target_vblank; 403 uint64_t base; 404 struct drm_pending_vblank_event *event; 405 struct amdgpu_bo *old_abo; 406 struct dma_fence *excl; 407 unsigned shared_count; 408 struct dma_fence **shared; 409 struct dma_fence_cb cb; 410 bool async; 411 }; 412 413 414 /* 415 * CP & rings. 416 */ 417 418 struct amdgpu_ib { 419 struct amdgpu_sa_bo *sa_bo; 420 uint32_t length_dw; 421 uint64_t gpu_addr; 422 uint32_t *ptr; 423 uint32_t flags; 424 }; 425 426 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 427 428 /* 429 * file private structure 430 */ 431 432 struct amdgpu_fpriv { 433 struct amdgpu_vm vm; 434 struct amdgpu_bo_va *prt_va; 435 struct amdgpu_bo_va *csa_va; 436 struct mutex bo_list_lock; 437 struct idr bo_list_handles; 438 struct amdgpu_ctx_mgr ctx_mgr; 439 }; 440 441 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 442 443 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 444 unsigned size, struct amdgpu_ib *ib); 445 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 446 struct dma_fence *f); 447 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 448 struct amdgpu_ib *ibs, struct amdgpu_job *job, 449 struct dma_fence **f); 450 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 451 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 452 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 453 454 /* 455 * CS. 456 */ 457 struct amdgpu_cs_chunk { 458 uint32_t chunk_id; 459 uint32_t length_dw; 460 void *kdata; 461 }; 462 463 struct amdgpu_cs_post_dep { 464 struct drm_syncobj *syncobj; 465 struct dma_fence_chain *chain; 466 u64 point; 467 }; 468 469 struct amdgpu_cs_parser { 470 struct amdgpu_device *adev; 471 struct drm_file *filp; 472 struct amdgpu_ctx *ctx; 473 474 /* chunks */ 475 unsigned nchunks; 476 struct amdgpu_cs_chunk *chunks; 477 478 /* scheduler job object */ 479 struct amdgpu_job *job; 480 struct drm_sched_entity *entity; 481 482 /* buffer objects */ 483 struct ww_acquire_ctx ticket; 484 struct amdgpu_bo_list *bo_list; 485 struct amdgpu_mn *mn; 486 struct amdgpu_bo_list_entry vm_pd; 487 struct list_head validated; 488 struct dma_fence *fence; 489 uint64_t bytes_moved_threshold; 490 uint64_t bytes_moved_vis_threshold; 491 uint64_t bytes_moved; 492 uint64_t bytes_moved_vis; 493 494 /* user fence */ 495 struct amdgpu_bo_list_entry uf_entry; 496 497 unsigned num_post_deps; 498 struct amdgpu_cs_post_dep *post_deps; 499 }; 500 501 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 502 uint32_t ib_idx, int idx) 503 { 504 return p->job->ibs[ib_idx].ptr[idx]; 505 } 506 507 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 508 uint32_t ib_idx, int idx, 509 uint32_t value) 510 { 511 p->job->ibs[ib_idx].ptr[idx] = value; 512 } 513 514 /* 515 * Writeback 516 */ 517 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 518 519 struct amdgpu_wb { 520 struct amdgpu_bo *wb_obj; 521 volatile uint32_t *wb; 522 uint64_t gpu_addr; 523 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 524 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)]; 525 }; 526 527 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 528 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 529 530 /* 531 * Benchmarking 532 */ 533 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 534 535 536 /* 537 * Testing 538 */ 539 void amdgpu_test_moves(struct amdgpu_device *adev); 540 541 /* 542 * ASIC specific register table accessible by UMD 543 */ 544 struct amdgpu_allowed_register_entry { 545 uint32_t reg_offset; 546 bool grbm_indexed; 547 }; 548 549 enum amd_reset_method { 550 AMD_RESET_METHOD_LEGACY = 0, 551 AMD_RESET_METHOD_MODE0, 552 AMD_RESET_METHOD_MODE1, 553 AMD_RESET_METHOD_MODE2, 554 AMD_RESET_METHOD_BACO 555 }; 556 557 /* 558 * ASIC specific functions. 559 */ 560 struct amdgpu_asic_funcs { 561 bool (*read_disabled_bios)(struct amdgpu_device *adev); 562 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 563 u8 *bios, u32 length_bytes); 564 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 565 u32 sh_num, u32 reg_offset, u32 *value); 566 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 567 int (*reset)(struct amdgpu_device *adev); 568 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 569 /* get the reference clock */ 570 u32 (*get_xclk)(struct amdgpu_device *adev); 571 /* MM block clocks */ 572 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 573 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 574 /* static power management */ 575 int (*get_pcie_lanes)(struct amdgpu_device *adev); 576 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 577 /* get config memsize register */ 578 u32 (*get_config_memsize)(struct amdgpu_device *adev); 579 /* flush hdp write queue */ 580 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 581 /* invalidate hdp read cache */ 582 void (*invalidate_hdp)(struct amdgpu_device *adev, 583 struct amdgpu_ring *ring); 584 /* check if the asic needs a full reset of if soft reset will work */ 585 bool (*need_full_reset)(struct amdgpu_device *adev); 586 /* initialize doorbell layout for specific asic*/ 587 void (*init_doorbell_index)(struct amdgpu_device *adev); 588 /* PCIe bandwidth usage */ 589 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 590 uint64_t *count1); 591 /* do we need to reset the asic at init time (e.g., kexec) */ 592 bool (*need_reset_on_init)(struct amdgpu_device *adev); 593 /* PCIe replay counter */ 594 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 595 /* device supports BACO */ 596 bool (*supports_baco)(struct amdgpu_device *adev); 597 }; 598 599 /* 600 * IOCTL. 601 */ 602 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 603 struct drm_file *filp); 604 605 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 606 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 607 struct drm_file *filp); 608 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 609 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 610 struct drm_file *filp); 611 612 /* VRAM scratch page for HDP bug, default vram page */ 613 struct amdgpu_vram_scratch { 614 struct amdgpu_bo *robj; 615 volatile uint32_t *ptr; 616 u64 gpu_addr; 617 }; 618 619 /* 620 * ACPI 621 */ 622 struct amdgpu_atcs_functions { 623 bool get_ext_state; 624 bool pcie_perf_req; 625 bool pcie_dev_rdy; 626 bool pcie_bus_width; 627 }; 628 629 struct amdgpu_atcs { 630 struct amdgpu_atcs_functions functions; 631 }; 632 633 /* 634 * Firmware VRAM reservation 635 */ 636 struct amdgpu_fw_vram_usage { 637 u64 start_offset; 638 u64 size; 639 struct amdgpu_bo *reserved_bo; 640 void *va; 641 642 /* GDDR6 training support flag. 643 */ 644 bool mem_train_support; 645 }; 646 647 /* 648 * CGS 649 */ 650 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 651 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 652 653 /* 654 * Core structure, functions and helpers. 655 */ 656 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 657 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 658 659 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 660 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 661 662 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 663 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 664 665 struct amdgpu_mmio_remap { 666 u32 reg_offset; 667 resource_size_t bus_addr; 668 }; 669 670 /* Define the HW IP blocks will be used in driver , add more if necessary */ 671 enum amd_hw_ip_block_type { 672 GC_HWIP = 1, 673 HDP_HWIP, 674 SDMA0_HWIP, 675 SDMA1_HWIP, 676 SDMA2_HWIP, 677 SDMA3_HWIP, 678 SDMA4_HWIP, 679 SDMA5_HWIP, 680 SDMA6_HWIP, 681 SDMA7_HWIP, 682 MMHUB_HWIP, 683 ATHUB_HWIP, 684 NBIO_HWIP, 685 MP0_HWIP, 686 MP1_HWIP, 687 UVD_HWIP, 688 VCN_HWIP = UVD_HWIP, 689 JPEG_HWIP = VCN_HWIP, 690 VCE_HWIP, 691 DF_HWIP, 692 DCE_HWIP, 693 OSSSYS_HWIP, 694 SMUIO_HWIP, 695 PWR_HWIP, 696 NBIF_HWIP, 697 THM_HWIP, 698 CLK_HWIP, 699 UMC_HWIP, 700 RSMU_HWIP, 701 MAX_HWIP 702 }; 703 704 #define HWIP_MAX_INSTANCE 8 705 706 struct amd_powerplay { 707 void *pp_handle; 708 const struct amd_pm_funcs *pp_funcs; 709 }; 710 711 #define AMDGPU_RESET_MAGIC_NUM 64 712 #define AMDGPU_MAX_DF_PERFMONS 4 713 struct amdgpu_device { 714 struct device *dev; 715 struct drm_device *ddev; 716 struct pci_dev *pdev; 717 718 #ifdef CONFIG_DRM_AMD_ACP 719 struct amdgpu_acp acp; 720 #endif 721 722 /* ASIC */ 723 enum amd_asic_type asic_type; 724 uint32_t family; 725 uint32_t rev_id; 726 uint32_t external_rev_id; 727 unsigned long flags; 728 int usec_timeout; 729 const struct amdgpu_asic_funcs *asic_funcs; 730 bool shutdown; 731 bool need_swiotlb; 732 bool accel_working; 733 struct notifier_block acpi_nb; 734 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 735 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 736 unsigned debugfs_count; 737 #if defined(CONFIG_DEBUG_FS) 738 struct dentry *debugfs_preempt; 739 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 740 #endif 741 struct amdgpu_atif *atif; 742 struct amdgpu_atcs atcs; 743 struct mutex srbm_mutex; 744 /* GRBM index mutex. Protects concurrent access to GRBM index */ 745 struct mutex grbm_idx_mutex; 746 struct dev_pm_domain vga_pm_domain; 747 bool have_disp_power_ref; 748 bool have_atomics_support; 749 750 /* BIOS */ 751 bool is_atom_fw; 752 uint8_t *bios; 753 uint32_t bios_size; 754 struct amdgpu_bo *stolen_vga_memory; 755 struct amdgpu_bo *discovery_memory; 756 uint32_t bios_scratch_reg_offset; 757 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 758 759 /* Register/doorbell mmio */ 760 resource_size_t rmmio_base; 761 resource_size_t rmmio_size; 762 void __iomem *rmmio; 763 /* protects concurrent MM_INDEX/DATA based register access */ 764 spinlock_t mmio_idx_lock; 765 struct amdgpu_mmio_remap rmmio_remap; 766 /* protects concurrent SMC based register access */ 767 spinlock_t smc_idx_lock; 768 amdgpu_rreg_t smc_rreg; 769 amdgpu_wreg_t smc_wreg; 770 /* protects concurrent PCIE register access */ 771 spinlock_t pcie_idx_lock; 772 amdgpu_rreg_t pcie_rreg; 773 amdgpu_wreg_t pcie_wreg; 774 amdgpu_rreg_t pciep_rreg; 775 amdgpu_wreg_t pciep_wreg; 776 amdgpu_rreg64_t pcie_rreg64; 777 amdgpu_wreg64_t pcie_wreg64; 778 /* protects concurrent UVD register access */ 779 spinlock_t uvd_ctx_idx_lock; 780 amdgpu_rreg_t uvd_ctx_rreg; 781 amdgpu_wreg_t uvd_ctx_wreg; 782 /* protects concurrent DIDT register access */ 783 spinlock_t didt_idx_lock; 784 amdgpu_rreg_t didt_rreg; 785 amdgpu_wreg_t didt_wreg; 786 /* protects concurrent gc_cac register access */ 787 spinlock_t gc_cac_idx_lock; 788 amdgpu_rreg_t gc_cac_rreg; 789 amdgpu_wreg_t gc_cac_wreg; 790 /* protects concurrent se_cac register access */ 791 spinlock_t se_cac_idx_lock; 792 amdgpu_rreg_t se_cac_rreg; 793 amdgpu_wreg_t se_cac_wreg; 794 /* protects concurrent ENDPOINT (audio) register access */ 795 spinlock_t audio_endpt_idx_lock; 796 amdgpu_block_rreg_t audio_endpt_rreg; 797 amdgpu_block_wreg_t audio_endpt_wreg; 798 void __iomem *rio_mem; 799 resource_size_t rio_mem_size; 800 struct amdgpu_doorbell doorbell; 801 802 /* clock/pll info */ 803 struct amdgpu_clock clock; 804 805 /* MC */ 806 struct amdgpu_gmc gmc; 807 struct amdgpu_gart gart; 808 dma_addr_t dummy_page_addr; 809 struct amdgpu_vm_manager vm_manager; 810 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 811 unsigned num_vmhubs; 812 813 /* memory management */ 814 struct amdgpu_mman mman; 815 struct amdgpu_vram_scratch vram_scratch; 816 struct amdgpu_wb wb; 817 atomic64_t num_bytes_moved; 818 atomic64_t num_evictions; 819 atomic64_t num_vram_cpu_page_faults; 820 atomic_t gpu_reset_counter; 821 atomic_t vram_lost_counter; 822 823 /* data for buffer migration throttling */ 824 struct { 825 spinlock_t lock; 826 s64 last_update_us; 827 s64 accum_us; /* accumulated microseconds */ 828 s64 accum_us_vis; /* for visible VRAM */ 829 u32 log2_max_MBps; 830 } mm_stats; 831 832 /* display */ 833 bool enable_virtual_display; 834 struct amdgpu_mode_info mode_info; 835 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 836 struct work_struct hotplug_work; 837 struct amdgpu_irq_src crtc_irq; 838 struct amdgpu_irq_src vupdate_irq; 839 struct amdgpu_irq_src pageflip_irq; 840 struct amdgpu_irq_src hpd_irq; 841 842 /* rings */ 843 u64 fence_context; 844 unsigned num_rings; 845 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 846 bool ib_pool_ready; 847 struct amdgpu_sa_manager ring_tmp_bo; 848 849 /* interrupts */ 850 struct amdgpu_irq irq; 851 852 /* powerplay */ 853 struct amd_powerplay powerplay; 854 bool pp_force_state_enabled; 855 856 /* smu */ 857 struct smu_context smu; 858 859 /* dpm */ 860 struct amdgpu_pm pm; 861 u32 cg_flags; 862 u32 pg_flags; 863 864 /* nbio */ 865 struct amdgpu_nbio nbio; 866 867 /* mmhub */ 868 struct amdgpu_mmhub mmhub; 869 870 /* gfx */ 871 struct amdgpu_gfx gfx; 872 873 /* sdma */ 874 struct amdgpu_sdma sdma; 875 876 /* uvd */ 877 struct amdgpu_uvd uvd; 878 879 /* vce */ 880 struct amdgpu_vce vce; 881 882 /* vcn */ 883 struct amdgpu_vcn vcn; 884 885 /* jpeg */ 886 struct amdgpu_jpeg jpeg; 887 888 /* firmwares */ 889 struct amdgpu_firmware firmware; 890 891 /* PSP */ 892 struct psp_context psp; 893 894 /* GDS */ 895 struct amdgpu_gds gds; 896 897 /* KFD */ 898 struct amdgpu_kfd_dev kfd; 899 900 /* UMC */ 901 struct amdgpu_umc umc; 902 903 /* display related functionality */ 904 struct amdgpu_display_manager dm; 905 906 /* discovery */ 907 uint8_t *discovery; 908 909 /* mes */ 910 bool enable_mes; 911 struct amdgpu_mes mes; 912 913 /* df */ 914 struct amdgpu_df df; 915 916 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 917 int num_ip_blocks; 918 struct mutex mn_lock; 919 DECLARE_HASHTABLE(mn_hash, 7); 920 921 /* tracking pinned memory */ 922 atomic64_t vram_pin_size; 923 atomic64_t visible_pin_size; 924 atomic64_t gart_pin_size; 925 926 /* soc15 register offset based on ip, instance and segment */ 927 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 928 929 /* delayed work_func for deferring clockgating during resume */ 930 struct delayed_work delayed_init_work; 931 932 struct amdgpu_virt virt; 933 /* firmware VRAM reservation */ 934 struct amdgpu_fw_vram_usage fw_vram_usage; 935 936 /* link all shadow bo */ 937 struct list_head shadow_list; 938 struct mutex shadow_list_lock; 939 /* keep an lru list of rings by HW IP */ 940 struct list_head ring_lru_list; 941 spinlock_t ring_lru_list_lock; 942 943 /* record hw reset is performed */ 944 bool has_hw_reset; 945 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 946 947 /* s3/s4 mask */ 948 bool in_suspend; 949 950 /* record last mm index being written through WREG32*/ 951 unsigned long last_mm_index; 952 bool in_gpu_reset; 953 enum pp_mp1_state mp1_state; 954 struct mutex lock_reset; 955 struct amdgpu_doorbell_index doorbell_index; 956 957 struct mutex notifier_lock; 958 959 int asic_reset_res; 960 struct work_struct xgmi_reset_work; 961 962 long gfx_timeout; 963 long sdma_timeout; 964 long video_timeout; 965 long compute_timeout; 966 967 uint64_t unique_id; 968 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 969 970 /* device pstate */ 971 int pstate; 972 /* enable runtime pm on the device */ 973 bool runpm; 974 975 bool pm_sysfs_en; 976 bool ucode_sysfs_en; 977 }; 978 979 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 980 { 981 return container_of(bdev, struct amdgpu_device, mman.bdev); 982 } 983 984 int amdgpu_device_init(struct amdgpu_device *adev, 985 struct drm_device *ddev, 986 struct pci_dev *pdev, 987 uint32_t flags); 988 void amdgpu_device_fini(struct amdgpu_device *adev); 989 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 990 991 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 992 uint32_t *buf, size_t size, bool write); 993 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 994 uint32_t acc_flags); 995 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 996 uint32_t acc_flags); 997 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 998 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 999 1000 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1001 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1002 1003 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1004 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1005 1006 int emu_soc_asic_init(struct amdgpu_device *adev); 1007 1008 /* 1009 * Registers read & write functions. 1010 */ 1011 1012 #define AMDGPU_REGS_IDX (1<<0) 1013 #define AMDGPU_REGS_NO_KIQ (1<<1) 1014 #define AMDGPU_REGS_KIQ (1<<2) 1015 1016 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1017 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1018 1019 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1020 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1021 1022 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1023 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1024 1025 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1026 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1027 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1028 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1029 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1030 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1031 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1032 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1033 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1034 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1035 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1036 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1037 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1038 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1039 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1040 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1041 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1042 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1043 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1044 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1045 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1046 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1047 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1048 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1049 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1050 #define WREG32_P(reg, val, mask) \ 1051 do { \ 1052 uint32_t tmp_ = RREG32(reg); \ 1053 tmp_ &= (mask); \ 1054 tmp_ |= ((val) & ~(mask)); \ 1055 WREG32(reg, tmp_); \ 1056 } while (0) 1057 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1058 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1059 #define WREG32_PLL_P(reg, val, mask) \ 1060 do { \ 1061 uint32_t tmp_ = RREG32_PLL(reg); \ 1062 tmp_ &= (mask); \ 1063 tmp_ |= ((val) & ~(mask)); \ 1064 WREG32_PLL(reg, tmp_); \ 1065 } while (0) 1066 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1067 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1068 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1069 1070 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1071 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1072 1073 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1074 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1075 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1076 1077 #define REG_GET_FIELD(value, reg, field) \ 1078 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1079 1080 #define WREG32_FIELD(reg, field, val) \ 1081 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1082 1083 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1084 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1085 1086 /* 1087 * BIOS helpers. 1088 */ 1089 #define RBIOS8(i) (adev->bios[i]) 1090 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1091 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1092 1093 /* 1094 * ASICs macro. 1095 */ 1096 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1097 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1098 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1099 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1100 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1101 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1102 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1103 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1104 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1105 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1106 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1107 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1108 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1109 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1110 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1111 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1112 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1113 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1114 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1115 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1116 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1117 1118 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1119 1120 /* Common functions */ 1121 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1122 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1123 struct amdgpu_job* job); 1124 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1125 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1126 1127 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1128 u64 num_vis_bytes); 1129 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1130 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1131 const u32 *registers, 1132 const u32 array_size); 1133 1134 bool amdgpu_device_supports_boco(struct drm_device *dev); 1135 bool amdgpu_device_supports_baco(struct drm_device *dev); 1136 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1137 struct amdgpu_device *peer_adev); 1138 int amdgpu_device_baco_enter(struct drm_device *dev); 1139 int amdgpu_device_baco_exit(struct drm_device *dev); 1140 1141 /* atpx handler */ 1142 #if defined(CONFIG_VGA_SWITCHEROO) 1143 void amdgpu_register_atpx_handler(void); 1144 void amdgpu_unregister_atpx_handler(void); 1145 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1146 bool amdgpu_is_atpx_hybrid(void); 1147 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1148 bool amdgpu_has_atpx(void); 1149 #else 1150 static inline void amdgpu_register_atpx_handler(void) {} 1151 static inline void amdgpu_unregister_atpx_handler(void) {} 1152 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1153 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1154 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1155 static inline bool amdgpu_has_atpx(void) { return false; } 1156 #endif 1157 1158 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1159 void *amdgpu_atpx_get_dhandle(void); 1160 #else 1161 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1162 #endif 1163 1164 /* 1165 * KMS 1166 */ 1167 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1168 extern const int amdgpu_max_kms_ioctl; 1169 1170 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1171 void amdgpu_driver_unload_kms(struct drm_device *dev); 1172 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1173 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1174 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1175 struct drm_file *file_priv); 1176 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1177 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1178 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1179 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1180 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1181 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1182 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1183 unsigned long arg); 1184 1185 /* 1186 * functions used by amdgpu_encoder.c 1187 */ 1188 struct amdgpu_afmt_acr { 1189 u32 clock; 1190 1191 int n_32khz; 1192 int cts_32khz; 1193 1194 int n_44_1khz; 1195 int cts_44_1khz; 1196 1197 int n_48khz; 1198 int cts_48khz; 1199 1200 }; 1201 1202 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1203 1204 /* amdgpu_acpi.c */ 1205 #if defined(CONFIG_ACPI) 1206 int amdgpu_acpi_init(struct amdgpu_device *adev); 1207 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1208 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1209 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1210 u8 perf_req, bool advertise); 1211 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1212 1213 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1214 struct amdgpu_dm_backlight_caps *caps); 1215 #else 1216 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1217 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1218 #endif 1219 1220 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1221 uint64_t addr, struct amdgpu_bo **bo, 1222 struct amdgpu_bo_va_mapping **mapping); 1223 1224 #if defined(CONFIG_DRM_AMD_DC) 1225 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1226 #else 1227 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1228 #endif 1229 1230 1231 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1232 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1233 1234 #include "amdgpu_object.h" 1235 1236 /* used by df_v3_6.c and amdgpu_pmu.c */ 1237 #define AMDGPU_PMU_ATTR(_name, _object) \ 1238 static ssize_t \ 1239 _name##_show(struct device *dev, \ 1240 struct device_attribute *attr, \ 1241 char *page) \ 1242 { \ 1243 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1244 return sprintf(page, _object "\n"); \ 1245 } \ 1246 \ 1247 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1248 1249 #endif 1250 1251
Indexes created Mon Sep 29 21:09:56 GMT 2025