amdgpu.h revision 1.4.6.2
1 /* $NetBSD: amdgpu.h,v 1.4.6.2 2019/06/10 22:07:57 christos Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #ifdef _KERNEL_OPT 34 #include "opt_amdgpu_cik.h" 35 #endif 36 37 #ifdef AMDGPU_CIK 38 #define CONFIG_DRM_AMDGPU_CIK 1 39 #endif 40 41 #include <linux/atomic.h> 42 #include <linux/wait.h> 43 #include <linux/list.h> 44 #include <linux/kref.h> 45 #include <linux/interval_tree.h> 46 #include <linux/hashtable.h> 47 #include <linux/fence.h> 48 49 #include <ttm/ttm_bo_api.h> 50 #include <ttm/ttm_bo_driver.h> 51 #include <ttm/ttm_placement.h> 52 #include <ttm/ttm_module.h> 53 #include <ttm/ttm_execbuf_util.h> 54 55 #include <drm/drmP.h> 56 #include <drm/drm_gem.h> 57 #include <drm/amdgpu_drm.h> 58 59 #include "amd_shared.h" 60 #include "amdgpu_mode.h" 61 #include "amdgpu_ih.h" 62 #include "amdgpu_irq.h" 63 #include "amdgpu_ucode.h" 64 #include "amdgpu_gds.h" 65 66 #include "gpu_scheduler.h" 67 68 /* 69 * Modules parameters. 70 */ 71 extern int amdgpu_modeset; 72 extern int amdgpu_vram_limit; 73 extern int amdgpu_gart_size; 74 extern int amdgpu_benchmarking; 75 extern int amdgpu_testing; 76 extern int amdgpu_audio; 77 extern int amdgpu_disp_priority; 78 extern int amdgpu_hw_i2c; 79 extern int amdgpu_pcie_gen2; 80 extern int amdgpu_msi; 81 extern int amdgpu_lockup_timeout; 82 extern int amdgpu_dpm; 83 extern int amdgpu_smc_load_fw; 84 extern int amdgpu_aspm; 85 extern int amdgpu_runtime_pm; 86 extern int amdgpu_hard_reset; 87 extern unsigned amdgpu_ip_block_mask; 88 extern int amdgpu_bapm; 89 extern int amdgpu_deep_color; 90 extern int amdgpu_vm_size; 91 extern int amdgpu_vm_block_size; 92 extern int amdgpu_vm_fault_stop; 93 extern int amdgpu_vm_debug; 94 extern int amdgpu_enable_scheduler; 95 extern int amdgpu_sched_jobs; 96 extern int amdgpu_sched_hw_submission; 97 extern int amdgpu_enable_semaphores; 98 99 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 100 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 101 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 102 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 103 #define AMDGPU_IB_POOL_SIZE 16 104 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 105 #define AMDGPUFB_CONN_LIMIT 4 106 #define AMDGPU_BIOS_NUM_SCRATCH 8 107 108 /* max number of rings */ 109 #define AMDGPU_MAX_RINGS 16 110 #define AMDGPU_MAX_GFX_RINGS 1 111 #define AMDGPU_MAX_COMPUTE_RINGS 8 112 #define AMDGPU_MAX_VCE_RINGS 2 113 114 /* max number of IP instances */ 115 #define AMDGPU_MAX_SDMA_INSTANCES 2 116 117 /* number of hw syncs before falling back on blocking */ 118 #define AMDGPU_NUM_SYNCS 4 119 120 /* hardcode that limit for now */ 121 #define AMDGPU_VA_RESERVED_SIZE (8 << 20) 122 123 /* hard reset data */ 124 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 125 126 /* reset flags */ 127 #define AMDGPU_RESET_GFX (1 << 0) 128 #define AMDGPU_RESET_COMPUTE (1 << 1) 129 #define AMDGPU_RESET_DMA (1 << 2) 130 #define AMDGPU_RESET_CP (1 << 3) 131 #define AMDGPU_RESET_GRBM (1 << 4) 132 #define AMDGPU_RESET_DMA1 (1 << 5) 133 #define AMDGPU_RESET_RLC (1 << 6) 134 #define AMDGPU_RESET_SEM (1 << 7) 135 #define AMDGPU_RESET_IH (1 << 8) 136 #define AMDGPU_RESET_VMC (1 << 9) 137 #define AMDGPU_RESET_MC (1 << 10) 138 #define AMDGPU_RESET_DISPLAY (1 << 11) 139 #define AMDGPU_RESET_UVD (1 << 12) 140 #define AMDGPU_RESET_VCE (1 << 13) 141 #define AMDGPU_RESET_VCE1 (1 << 14) 142 143 /* CG block flags */ 144 #define AMDGPU_CG_BLOCK_GFX (1 << 0) 145 #define AMDGPU_CG_BLOCK_MC (1 << 1) 146 #define AMDGPU_CG_BLOCK_SDMA (1 << 2) 147 #define AMDGPU_CG_BLOCK_UVD (1 << 3) 148 #define AMDGPU_CG_BLOCK_VCE (1 << 4) 149 #define AMDGPU_CG_BLOCK_HDP (1 << 5) 150 #define AMDGPU_CG_BLOCK_BIF (1 << 6) 151 152 /* CG flags */ 153 #define AMDGPU_CG_SUPPORT_GFX_MGCG (1 << 0) 154 #define AMDGPU_CG_SUPPORT_GFX_MGLS (1 << 1) 155 #define AMDGPU_CG_SUPPORT_GFX_CGCG (1 << 2) 156 #define AMDGPU_CG_SUPPORT_GFX_CGLS (1 << 3) 157 #define AMDGPU_CG_SUPPORT_GFX_CGTS (1 << 4) 158 #define AMDGPU_CG_SUPPORT_GFX_CGTS_LS (1 << 5) 159 #define AMDGPU_CG_SUPPORT_GFX_CP_LS (1 << 6) 160 #define AMDGPU_CG_SUPPORT_GFX_RLC_LS (1 << 7) 161 #define AMDGPU_CG_SUPPORT_MC_LS (1 << 8) 162 #define AMDGPU_CG_SUPPORT_MC_MGCG (1 << 9) 163 #define AMDGPU_CG_SUPPORT_SDMA_LS (1 << 10) 164 #define AMDGPU_CG_SUPPORT_SDMA_MGCG (1 << 11) 165 #define AMDGPU_CG_SUPPORT_BIF_LS (1 << 12) 166 #define AMDGPU_CG_SUPPORT_UVD_MGCG (1 << 13) 167 #define AMDGPU_CG_SUPPORT_VCE_MGCG (1 << 14) 168 #define AMDGPU_CG_SUPPORT_HDP_LS (1 << 15) 169 #define AMDGPU_CG_SUPPORT_HDP_MGCG (1 << 16) 170 171 /* PG flags */ 172 #define AMDGPU_PG_SUPPORT_GFX_PG (1 << 0) 173 #define AMDGPU_PG_SUPPORT_GFX_SMG (1 << 1) 174 #define AMDGPU_PG_SUPPORT_GFX_DMG (1 << 2) 175 #define AMDGPU_PG_SUPPORT_UVD (1 << 3) 176 #define AMDGPU_PG_SUPPORT_VCE (1 << 4) 177 #define AMDGPU_PG_SUPPORT_CP (1 << 5) 178 #define AMDGPU_PG_SUPPORT_GDS (1 << 6) 179 #define AMDGPU_PG_SUPPORT_RLC_SMU_HS (1 << 7) 180 #define AMDGPU_PG_SUPPORT_SDMA (1 << 8) 181 #define AMDGPU_PG_SUPPORT_ACP (1 << 9) 182 #define AMDGPU_PG_SUPPORT_SAMU (1 << 10) 183 184 /* GFX current status */ 185 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L 186 #define AMDGPU_GFX_SAFE_MODE 0x00000001L 187 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L 188 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L 189 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L 190 191 /* max cursor sizes (in pixels) */ 192 #define CIK_CURSOR_WIDTH 128 193 #define CIK_CURSOR_HEIGHT 128 194 195 struct amdgpu_device; 196 struct amdgpu_fence; 197 struct amdgpu_ib; 198 struct amdgpu_vm; 199 struct amdgpu_ring; 200 struct amdgpu_semaphore; 201 struct amdgpu_cs_parser; 202 struct amdgpu_job; 203 struct amdgpu_irq_src; 204 struct amdgpu_fpriv; 205 206 enum amdgpu_cp_irq { 207 AMDGPU_CP_IRQ_GFX_EOP = 0, 208 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 209 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 210 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 211 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 212 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 213 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 214 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 215 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 216 217 AMDGPU_CP_IRQ_LAST 218 }; 219 220 enum amdgpu_sdma_irq { 221 AMDGPU_SDMA_IRQ_TRAP0 = 0, 222 AMDGPU_SDMA_IRQ_TRAP1, 223 224 AMDGPU_SDMA_IRQ_LAST 225 }; 226 227 enum amdgpu_thermal_irq { 228 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 229 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 230 231 AMDGPU_THERMAL_IRQ_LAST 232 }; 233 234 int amdgpu_set_clockgating_state(struct amdgpu_device *adev, 235 enum amd_ip_block_type block_type, 236 enum amd_clockgating_state state); 237 int amdgpu_set_powergating_state(struct amdgpu_device *adev, 238 enum amd_ip_block_type block_type, 239 enum amd_powergating_state state); 240 241 struct amdgpu_ip_block_version { 242 enum amd_ip_block_type type; 243 u32 major; 244 u32 minor; 245 u32 rev; 246 const struct amd_ip_funcs *funcs; 247 }; 248 249 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev, 250 enum amd_ip_block_type type, 251 u32 major, u32 minor); 252 253 const struct amdgpu_ip_block_version * amdgpu_get_ip_block( 254 struct amdgpu_device *adev, 255 enum amd_ip_block_type type); 256 257 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */ 258 struct amdgpu_buffer_funcs { 259 /* maximum bytes in a single operation */ 260 uint32_t copy_max_bytes; 261 262 /* number of dw to reserve per operation */ 263 unsigned copy_num_dw; 264 265 /* used for buffer migration */ 266 void (*emit_copy_buffer)(struct amdgpu_ib *ib, 267 /* src addr in bytes */ 268 uint64_t src_offset, 269 /* dst addr in bytes */ 270 uint64_t dst_offset, 271 /* number of byte to transfer */ 272 uint32_t byte_count); 273 274 /* maximum bytes in a single operation */ 275 uint32_t fill_max_bytes; 276 277 /* number of dw to reserve per operation */ 278 unsigned fill_num_dw; 279 280 /* used for buffer clearing */ 281 void (*emit_fill_buffer)(struct amdgpu_ib *ib, 282 /* value to write to memory */ 283 uint32_t src_data, 284 /* dst addr in bytes */ 285 uint64_t dst_offset, 286 /* number of byte to fill */ 287 uint32_t byte_count); 288 }; 289 290 /* provided by hw blocks that can write ptes, e.g., sdma */ 291 struct amdgpu_vm_pte_funcs { 292 /* copy pte entries from GART */ 293 void (*copy_pte)(struct amdgpu_ib *ib, 294 uint64_t pe, uint64_t src, 295 unsigned count); 296 /* write pte one entry at a time with addr mapping */ 297 void (*write_pte)(struct amdgpu_ib *ib, 298 uint64_t pe, 299 uint64_t addr, unsigned count, 300 uint32_t incr, uint32_t flags); 301 /* for linear pte/pde updates without addr mapping */ 302 void (*set_pte_pde)(struct amdgpu_ib *ib, 303 uint64_t pe, 304 uint64_t addr, unsigned count, 305 uint32_t incr, uint32_t flags); 306 /* pad the indirect buffer to the necessary number of dw */ 307 void (*pad_ib)(struct amdgpu_ib *ib); 308 }; 309 310 /* provided by the gmc block */ 311 struct amdgpu_gart_funcs { 312 /* flush the vm tlb via mmio */ 313 void (*flush_gpu_tlb)(struct amdgpu_device *adev, 314 uint32_t vmid); 315 /* write pte/pde updates using the cpu */ 316 int (*set_pte_pde)(struct amdgpu_device *adev, 317 void *cpu_pt_addr, /* cpu addr of page table */ 318 uint32_t gpu_page_idx, /* pte/pde to update */ 319 uint64_t addr, /* addr to write into pte/pde */ 320 uint32_t flags); /* access flags */ 321 }; 322 323 /* provided by the ih block */ 324 struct amdgpu_ih_funcs { 325 /* ring read/write ptr handling, called from interrupt context */ 326 u32 (*get_wptr)(struct amdgpu_device *adev); 327 void (*decode_iv)(struct amdgpu_device *adev, 328 struct amdgpu_iv_entry *entry); 329 void (*set_rptr)(struct amdgpu_device *adev); 330 }; 331 332 /* provided by hw blocks that expose a ring buffer for commands */ 333 struct amdgpu_ring_funcs { 334 /* ring read/write ptr handling */ 335 u32 (*get_rptr)(struct amdgpu_ring *ring); 336 u32 (*get_wptr)(struct amdgpu_ring *ring); 337 void (*set_wptr)(struct amdgpu_ring *ring); 338 /* validating and patching of IBs */ 339 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 340 /* command emit functions */ 341 void (*emit_ib)(struct amdgpu_ring *ring, 342 struct amdgpu_ib *ib); 343 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 344 uint64_t seq, unsigned flags); 345 bool (*emit_semaphore)(struct amdgpu_ring *ring, 346 struct amdgpu_semaphore *semaphore, 347 bool emit_wait); 348 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id, 349 uint64_t pd_addr); 350 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 351 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 352 uint32_t gds_base, uint32_t gds_size, 353 uint32_t gws_base, uint32_t gws_size, 354 uint32_t oa_base, uint32_t oa_size); 355 /* testing functions */ 356 int (*test_ring)(struct amdgpu_ring *ring); 357 int (*test_ib)(struct amdgpu_ring *ring); 358 /* insert NOP packets */ 359 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 360 }; 361 362 /* 363 * BIOS. 364 */ 365 bool amdgpu_get_bios(struct amdgpu_device *adev); 366 bool amdgpu_read_bios(struct amdgpu_device *adev); 367 368 /* 369 * Dummy page 370 */ 371 struct amdgpu_dummy_page { 372 #ifdef __NetBSD__ 373 bus_dma_segment_t adp_seg; 374 bus_dmamap_t adp_map; 375 #else 376 struct page *page; 377 #endif 378 dma_addr_t addr; 379 }; 380 int amdgpu_dummy_page_init(struct amdgpu_device *adev); 381 void amdgpu_dummy_page_fini(struct amdgpu_device *adev); 382 383 384 /* 385 * Clocks 386 */ 387 388 #define AMDGPU_MAX_PPLL 3 389 390 struct amdgpu_clock { 391 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 392 struct amdgpu_pll spll; 393 struct amdgpu_pll mpll; 394 /* 10 Khz units */ 395 uint32_t default_mclk; 396 uint32_t default_sclk; 397 uint32_t default_dispclk; 398 uint32_t current_dispclk; 399 uint32_t dp_extclk; 400 uint32_t max_pixel_clock; 401 }; 402 403 /* 404 * Fences. 405 */ 406 struct amdgpu_fence_driver { 407 uint64_t gpu_addr; 408 volatile uint32_t *cpu_addr; 409 /* sync_seq is protected by ring emission lock */ 410 uint64_t sync_seq[AMDGPU_MAX_RINGS]; 411 atomic64_t last_seq; 412 bool initialized; 413 struct amdgpu_irq_src *irq_src; 414 unsigned irq_type; 415 struct timer_list fallback_timer; 416 #ifdef __NetBSD__ 417 spinlock_t fence_lock; 418 drm_waitqueue_t fence_queue; 419 TAILQ_HEAD(, amdgpu_fence) fence_check; 420 #else 421 wait_queue_head_t fence_queue; 422 #endif 423 }; 424 425 /* some special values for the owner field */ 426 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void*)0ul) 427 #define AMDGPU_FENCE_OWNER_VM ((void*)1ul) 428 429 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 430 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 431 432 struct amdgpu_fence { 433 struct fence base; 434 435 /* RB, DMA, etc. */ 436 struct amdgpu_ring *ring; 437 uint64_t seq; 438 439 /* filp or special value for fence creator */ 440 void *owner; 441 442 #ifdef __NetBSD__ 443 TAILQ_ENTRY(amdgpu_fence) fence_check; 444 #else 445 wait_queue_t fence_wake; 446 #endif 447 }; 448 449 struct amdgpu_user_fence { 450 /* write-back bo */ 451 struct amdgpu_bo *bo; 452 /* write-back address offset to bo start */ 453 uint32_t offset; 454 }; 455 456 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 457 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 458 void amdgpu_fence_driver_force_completion(struct amdgpu_device *adev); 459 460 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring); 461 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 462 struct amdgpu_irq_src *irq_src, 463 unsigned irq_type); 464 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 465 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 466 int amdgpu_fence_emit(struct amdgpu_ring *ring, void *owner, 467 struct amdgpu_fence **fence); 468 void amdgpu_fence_process(struct amdgpu_ring *ring); 469 int amdgpu_fence_wait_next(struct amdgpu_ring *ring); 470 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 471 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 472 473 bool amdgpu_fence_need_sync(struct amdgpu_fence *fence, 474 struct amdgpu_ring *ring); 475 void amdgpu_fence_note_sync(struct amdgpu_fence *fence, 476 struct amdgpu_ring *ring); 477 478 /* 479 * TTM. 480 */ 481 struct amdgpu_mman { 482 struct ttm_bo_global_ref bo_global_ref; 483 struct drm_global_reference mem_global_ref; 484 struct ttm_bo_device bdev; 485 bool mem_global_referenced; 486 bool initialized; 487 488 #if defined(CONFIG_DEBUG_FS) 489 struct dentry *vram; 490 struct dentry *gtt; 491 #endif 492 493 /* buffer handling */ 494 const struct amdgpu_buffer_funcs *buffer_funcs; 495 struct amdgpu_ring *buffer_funcs_ring; 496 }; 497 498 int amdgpu_copy_buffer(struct amdgpu_ring *ring, 499 uint64_t src_offset, 500 uint64_t dst_offset, 501 uint32_t byte_count, 502 struct reservation_object *resv, 503 struct fence **fence); 504 #ifdef __NetBSD__ 505 int amdgpu_mmap_object(struct drm_device *, off_t, size_t, vm_prot_t, 506 struct uvm_object **, voff_t *, struct file *); 507 #else 508 int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); 509 #endif 510 511 struct amdgpu_bo_list_entry { 512 struct amdgpu_bo *robj; 513 struct ttm_validate_buffer tv; 514 struct amdgpu_bo_va *bo_va; 515 unsigned prefered_domains; 516 unsigned allowed_domains; 517 uint32_t priority; 518 }; 519 520 struct amdgpu_bo_va_mapping { 521 struct list_head list; 522 struct interval_tree_node it; 523 uint64_t offset; 524 uint32_t flags; 525 }; 526 527 /* bo virtual addresses in a specific vm */ 528 struct amdgpu_bo_va { 529 struct mutex mutex; 530 /* protected by bo being reserved */ 531 struct list_head bo_list; 532 struct fence *last_pt_update; 533 unsigned ref_count; 534 535 /* protected by vm mutex and spinlock */ 536 struct list_head vm_status; 537 538 /* mappings for this bo_va */ 539 struct list_head invalids; 540 struct list_head valids; 541 542 /* constant after initialization */ 543 struct amdgpu_vm *vm; 544 struct amdgpu_bo *bo; 545 }; 546 547 #define AMDGPU_GEM_DOMAIN_MAX 0x3 548 549 struct amdgpu_bo { 550 /* Protected by gem.mutex */ 551 struct list_head list; 552 /* Protected by tbo.reserved */ 553 u32 initial_domain; 554 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 555 struct ttm_placement placement; 556 struct ttm_buffer_object tbo; 557 struct ttm_bo_kmap_obj kmap; 558 u64 flags; 559 unsigned pin_count; 560 void *kptr; 561 u64 tiling_flags; 562 u64 metadata_flags; 563 void *metadata; 564 u32 metadata_size; 565 unsigned prime_shared_count; 566 /* list of all virtual address to which this bo 567 * is associated to 568 */ 569 struct list_head va; 570 /* Constant after initialization */ 571 struct amdgpu_device *adev; 572 struct drm_gem_object gem_base; 573 struct amdgpu_bo *parent; 574 575 struct ttm_bo_kmap_obj dma_buf_vmap; 576 pid_t pid; 577 struct amdgpu_mn *mn; 578 struct list_head mn_list; 579 }; 580 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base) 581 582 void amdgpu_gem_object_free(struct drm_gem_object *obj); 583 int amdgpu_gem_object_open(struct drm_gem_object *obj, 584 struct drm_file *file_priv); 585 void amdgpu_gem_object_close(struct drm_gem_object *obj, 586 struct drm_file *file_priv); 587 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns); 588 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); 589 struct drm_gem_object *amdgpu_gem_prime_import_sg_table(struct drm_device *dev, 590 struct dma_buf_attachment *attach, 591 struct sg_table *sg); 592 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, 593 struct drm_gem_object *gobj, 594 int flags); 595 int amdgpu_gem_prime_pin(struct drm_gem_object *obj); 596 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); 597 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); 598 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); 599 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr); 600 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev); 601 602 /* sub-allocation manager, it has to be protected by another lock. 603 * By conception this is an helper for other part of the driver 604 * like the indirect buffer or semaphore, which both have their 605 * locking. 606 * 607 * Principe is simple, we keep a list of sub allocation in offset 608 * order (first entry has offset == 0, last entry has the highest 609 * offset). 610 * 611 * When allocating new object we first check if there is room at 612 * the end total_size - (last_object_offset + last_object_size) >= 613 * alloc_size. If so we allocate new object there. 614 * 615 * When there is not enough room at the end, we start waiting for 616 * each sub object until we reach object_offset+object_size >= 617 * alloc_size, this object then become the sub object we return. 618 * 619 * Alignment can't be bigger than page size. 620 * 621 * Hole are not considered for allocation to keep things simple. 622 * Assumption is that there won't be hole (all object on same 623 * alignment). 624 */ 625 struct amdgpu_sa_manager { 626 #ifdef __NetBSD__ 627 spinlock_t wq_lock; 628 drm_waitqueue_t wq; 629 #else 630 wait_queue_head_t wq; 631 #endif 632 struct amdgpu_bo *bo; 633 struct list_head *hole; 634 struct list_head flist[AMDGPU_MAX_RINGS]; 635 struct list_head olist; 636 unsigned size; 637 uint64_t gpu_addr; 638 void *cpu_ptr; 639 uint32_t domain; 640 uint32_t align; 641 }; 642 643 /* sub-allocation buffer */ 644 struct amdgpu_sa_bo { 645 struct list_head olist; 646 struct list_head flist; 647 struct amdgpu_sa_manager *manager; 648 unsigned soffset; 649 unsigned eoffset; 650 struct fence *fence; 651 }; 652 653 /* 654 * GEM objects. 655 */ 656 struct amdgpu_gem { 657 struct mutex mutex; 658 struct list_head objects; 659 }; 660 661 int amdgpu_gem_init(struct amdgpu_device *adev); 662 void amdgpu_gem_fini(struct amdgpu_device *adev); 663 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 664 int alignment, u32 initial_domain, 665 u64 flags, bool kernel, 666 struct drm_gem_object **obj); 667 668 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 669 struct drm_device *dev, 670 struct drm_mode_create_dumb *args); 671 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 672 struct drm_device *dev, 673 uint32_t handle, uint64_t *offset_p); 674 675 /* 676 * Semaphores. 677 */ 678 struct amdgpu_semaphore { 679 struct amdgpu_sa_bo *sa_bo; 680 signed waiters; 681 uint64_t gpu_addr; 682 }; 683 684 int amdgpu_semaphore_create(struct amdgpu_device *adev, 685 struct amdgpu_semaphore **semaphore); 686 bool amdgpu_semaphore_emit_signal(struct amdgpu_ring *ring, 687 struct amdgpu_semaphore *semaphore); 688 bool amdgpu_semaphore_emit_wait(struct amdgpu_ring *ring, 689 struct amdgpu_semaphore *semaphore); 690 void amdgpu_semaphore_free(struct amdgpu_device *adev, 691 struct amdgpu_semaphore **semaphore, 692 struct fence *fence); 693 694 /* 695 * Synchronization 696 */ 697 struct amdgpu_sync { 698 struct amdgpu_semaphore *semaphores[AMDGPU_NUM_SYNCS]; 699 struct fence *sync_to[AMDGPU_MAX_RINGS]; 700 DECLARE_HASHTABLE(fences, 4); 701 struct fence *last_vm_update; 702 }; 703 704 void amdgpu_sync_create(struct amdgpu_sync *sync); 705 int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync, 706 struct fence *f); 707 int amdgpu_sync_resv(struct amdgpu_device *adev, 708 struct amdgpu_sync *sync, 709 struct reservation_object *resv, 710 void *owner); 711 int amdgpu_sync_rings(struct amdgpu_sync *sync, 712 struct amdgpu_ring *ring); 713 struct fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); 714 int amdgpu_sync_wait(struct amdgpu_sync *sync); 715 void amdgpu_sync_free(struct amdgpu_device *adev, struct amdgpu_sync *sync, 716 struct fence *fence); 717 718 /* 719 * GART structures, functions & helpers 720 */ 721 struct amdgpu_mc; 722 723 #define AMDGPU_GPU_PAGE_SIZE 4096 724 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 725 #define AMDGPU_GPU_PAGE_SHIFT 12 726 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 727 728 struct amdgpu_gart { 729 #ifdef __NetBSD__ 730 bus_dma_segment_t ag_table_seg; 731 bus_dmamap_t ag_table_map; 732 #endif 733 dma_addr_t table_addr; 734 struct amdgpu_bo *robj; 735 void *ptr; 736 unsigned num_gpu_pages; 737 unsigned num_cpu_pages; 738 unsigned table_size; 739 struct page **pages; 740 dma_addr_t *pages_addr; 741 bool ready; 742 const struct amdgpu_gart_funcs *gart_funcs; 743 }; 744 745 int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); 746 void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); 747 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 748 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 749 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 750 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 751 int amdgpu_gart_init(struct amdgpu_device *adev); 752 void amdgpu_gart_fini(struct amdgpu_device *adev); 753 #ifdef __NetBSD__ 754 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t gpu_start, 755 unsigned npages); 756 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t gpu_start, 757 unsigned npages, struct page **pagelist, bus_dmamap_t dmamap, 758 uint32_t flags); 759 #else 760 void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 761 int pages); 762 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 763 int pages, struct page **pagelist, 764 dma_addr_t *dma_addr, uint32_t flags); 765 #endif 766 767 /* 768 * GPU MC structures, functions & helpers 769 */ 770 struct amdgpu_mc { 771 resource_size_t aper_size; 772 resource_size_t aper_base; 773 resource_size_t agp_base; 774 /* for some chips with <= 32MB we need to lie 775 * about vram size near mc fb location */ 776 u64 mc_vram_size; 777 u64 visible_vram_size; 778 u64 gtt_size; 779 u64 gtt_start; 780 u64 gtt_end; 781 u64 vram_start; 782 u64 vram_end; 783 unsigned vram_width; 784 u64 real_vram_size; 785 int vram_mtrr; 786 u64 gtt_base_align; 787 u64 mc_mask; 788 const struct firmware *fw; /* MC firmware */ 789 uint32_t fw_version; 790 struct amdgpu_irq_src vm_fault; 791 uint32_t vram_type; 792 }; 793 794 /* 795 * GPU doorbell structures, functions & helpers 796 */ 797 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT 798 { 799 AMDGPU_DOORBELL_KIQ = 0x000, 800 AMDGPU_DOORBELL_HIQ = 0x001, 801 AMDGPU_DOORBELL_DIQ = 0x002, 802 AMDGPU_DOORBELL_MEC_RING0 = 0x010, 803 AMDGPU_DOORBELL_MEC_RING1 = 0x011, 804 AMDGPU_DOORBELL_MEC_RING2 = 0x012, 805 AMDGPU_DOORBELL_MEC_RING3 = 0x013, 806 AMDGPU_DOORBELL_MEC_RING4 = 0x014, 807 AMDGPU_DOORBELL_MEC_RING5 = 0x015, 808 AMDGPU_DOORBELL_MEC_RING6 = 0x016, 809 AMDGPU_DOORBELL_MEC_RING7 = 0x017, 810 AMDGPU_DOORBELL_GFX_RING0 = 0x020, 811 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0, 812 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1, 813 AMDGPU_DOORBELL_IH = 0x1E8, 814 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF, 815 AMDGPU_DOORBELL_INVALID = 0xFFFF 816 } AMDGPU_DOORBELL_ASSIGNMENT; 817 818 struct amdgpu_doorbell { 819 /* doorbell mmio */ 820 resource_size_t base; 821 resource_size_t size; 822 #ifdef __NetBSD__ 823 bus_space_tag_t bst; 824 bus_space_handle_t bsh; 825 #else 826 u32 __iomem *ptr; 827 #endif 828 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */ 829 }; 830 831 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev, 832 phys_addr_t *aperture_base, 833 size_t *aperture_size, 834 size_t *start_offset); 835 836 /* 837 * IRQS. 838 */ 839 840 struct amdgpu_flip_work { 841 struct work_struct flip_work; 842 struct work_struct unpin_work; 843 struct amdgpu_device *adev; 844 int crtc_id; 845 uint64_t base; 846 struct drm_pending_vblank_event *event; 847 struct amdgpu_bo *old_rbo; 848 struct fence *excl; 849 unsigned shared_count; 850 struct fence **shared; 851 }; 852 853 854 /* 855 * CP & rings. 856 */ 857 858 struct amdgpu_ib { 859 struct amdgpu_sa_bo *sa_bo; 860 uint32_t length_dw; 861 uint64_t gpu_addr; 862 uint32_t *ptr; 863 struct amdgpu_ring *ring; 864 struct amdgpu_fence *fence; 865 struct amdgpu_user_fence *user; 866 struct amdgpu_vm *vm; 867 struct amdgpu_ctx *ctx; 868 struct amdgpu_sync sync; 869 uint32_t gds_base, gds_size; 870 uint32_t gws_base, gws_size; 871 uint32_t oa_base, oa_size; 872 uint32_t flags; 873 /* resulting sequence number */ 874 uint64_t sequence; 875 }; 876 877 enum amdgpu_ring_type { 878 AMDGPU_RING_TYPE_GFX, 879 AMDGPU_RING_TYPE_COMPUTE, 880 AMDGPU_RING_TYPE_SDMA, 881 AMDGPU_RING_TYPE_UVD, 882 AMDGPU_RING_TYPE_VCE 883 }; 884 885 extern struct amd_sched_backend_ops amdgpu_sched_ops; 886 887 int amdgpu_sched_ib_submit_kernel_helper(struct amdgpu_device *adev, 888 struct amdgpu_ring *ring, 889 struct amdgpu_ib *ibs, 890 unsigned num_ibs, 891 int (*free_job)(struct amdgpu_job *), 892 void *owner, 893 struct fence **fence); 894 895 struct amdgpu_ring { 896 struct amdgpu_device *adev; 897 const struct amdgpu_ring_funcs *funcs; 898 struct amdgpu_fence_driver fence_drv; 899 struct amd_gpu_scheduler sched; 900 901 spinlock_t fence_lock; 902 struct mutex *ring_lock; 903 struct amdgpu_bo *ring_obj; 904 volatile uint32_t *ring; 905 unsigned rptr_offs; 906 u64 next_rptr_gpu_addr; 907 volatile u32 *next_rptr_cpu_addr; 908 unsigned wptr; 909 unsigned wptr_old; 910 unsigned ring_size; 911 unsigned ring_free_dw; 912 int count_dw; 913 uint64_t gpu_addr; 914 uint32_t align_mask; 915 uint32_t ptr_mask; 916 bool ready; 917 u32 nop; 918 u32 idx; 919 u64 last_semaphore_signal_addr; 920 u64 last_semaphore_wait_addr; 921 u32 me; 922 u32 pipe; 923 u32 queue; 924 struct amdgpu_bo *mqd_obj; 925 u32 doorbell_index; 926 bool use_doorbell; 927 unsigned wptr_offs; 928 unsigned next_rptr_offs; 929 unsigned fence_offs; 930 struct amdgpu_ctx *current_ctx; 931 enum amdgpu_ring_type type; 932 char name[16]; 933 bool is_pte_ring; 934 }; 935 936 /* 937 * VM 938 */ 939 940 /* maximum number of VMIDs */ 941 #define AMDGPU_NUM_VM 16 942 943 /* number of entries in page table */ 944 #define AMDGPU_VM_PTE_COUNT (1 << amdgpu_vm_block_size) 945 946 /* PTBs (Page Table Blocks) need to be aligned to 32K */ 947 #define AMDGPU_VM_PTB_ALIGN_SIZE 32768 948 #define AMDGPU_VM_PTB_ALIGN_MASK (AMDGPU_VM_PTB_ALIGN_SIZE - 1) 949 #define AMDGPU_VM_PTB_ALIGN(a) (((a) + AMDGPU_VM_PTB_ALIGN_MASK) & ~AMDGPU_VM_PTB_ALIGN_MASK) 950 951 #define AMDGPU_PTE_VALID (1 << 0) 952 #define AMDGPU_PTE_SYSTEM (1 << 1) 953 #define AMDGPU_PTE_SNOOPED (1 << 2) 954 955 /* VI only */ 956 #define AMDGPU_PTE_EXECUTABLE (1 << 4) 957 958 #define AMDGPU_PTE_READABLE (1 << 5) 959 #define AMDGPU_PTE_WRITEABLE (1 << 6) 960 961 /* PTE (Page Table Entry) fragment field for different page sizes */ 962 #define AMDGPU_PTE_FRAG_4KB (0 << 7) 963 #define AMDGPU_PTE_FRAG_64KB (4 << 7) 964 #define AMDGPU_LOG2_PAGES_PER_FRAG 4 965 966 /* How to programm VM fault handling */ 967 #define AMDGPU_VM_FAULT_STOP_NEVER 0 968 #define AMDGPU_VM_FAULT_STOP_FIRST 1 969 #define AMDGPU_VM_FAULT_STOP_ALWAYS 2 970 971 struct amdgpu_vm_pt { 972 struct amdgpu_bo *bo; 973 uint64_t addr; 974 }; 975 976 struct amdgpu_vm_id { 977 unsigned id; 978 uint64_t pd_gpu_addr; 979 /* last flushed PD/PT update */ 980 struct fence *flushed_updates; 981 }; 982 983 struct amdgpu_vm { 984 struct rb_root va; 985 986 /* protecting invalidated */ 987 spinlock_t status_lock; 988 989 /* BOs moved, but not yet updated in the PT */ 990 struct list_head invalidated; 991 992 /* BOs cleared in the PT because of a move */ 993 struct list_head cleared; 994 995 /* BO mappings freed, but not yet updated in the PT */ 996 struct list_head freed; 997 998 /* contains the page directory */ 999 struct amdgpu_bo *page_directory; 1000 unsigned max_pde_used; 1001 struct fence *page_directory_fence; 1002 1003 /* array of page tables, one for each page directory entry */ 1004 struct amdgpu_vm_pt *page_tables; 1005 1006 /* for id and flush management per ring */ 1007 struct amdgpu_vm_id ids[AMDGPU_MAX_RINGS]; 1008 /* for interval tree */ 1009 spinlock_t it_lock; 1010 /* protecting freed */ 1011 spinlock_t freed_lock; 1012 }; 1013 1014 struct amdgpu_vm_manager { 1015 struct { 1016 struct fence *active; 1017 atomic_long_t owner; 1018 } ids[AMDGPU_NUM_VM]; 1019 1020 uint32_t max_pfn; 1021 /* number of VMIDs */ 1022 unsigned nvm; 1023 /* vram base address for page table entry */ 1024 u64 vram_base_offset; 1025 /* is vm enabled? */ 1026 bool enabled; 1027 /* vm pte handling */ 1028 const struct amdgpu_vm_pte_funcs *vm_pte_funcs; 1029 struct amdgpu_ring *vm_pte_funcs_ring; 1030 }; 1031 1032 void amdgpu_vm_manager_fini(struct amdgpu_device *adev); 1033 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm); 1034 void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm); 1035 struct amdgpu_bo_list_entry *amdgpu_vm_get_bos(struct amdgpu_device *adev, 1036 struct amdgpu_vm *vm, 1037 struct list_head *head); 1038 int amdgpu_vm_grab_id(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 1039 struct amdgpu_sync *sync); 1040 void amdgpu_vm_flush(struct amdgpu_ring *ring, 1041 struct amdgpu_vm *vm, 1042 struct fence *updates); 1043 void amdgpu_vm_fence(struct amdgpu_device *adev, 1044 struct amdgpu_vm *vm, 1045 struct fence *fence); 1046 uint64_t amdgpu_vm_map_gart(struct amdgpu_device *adev, uint64_t addr); 1047 int amdgpu_vm_update_page_directory(struct amdgpu_device *adev, 1048 struct amdgpu_vm *vm); 1049 int amdgpu_vm_clear_freed(struct amdgpu_device *adev, 1050 struct amdgpu_vm *vm); 1051 int amdgpu_vm_clear_invalids(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1052 struct amdgpu_sync *sync); 1053 int amdgpu_vm_bo_update(struct amdgpu_device *adev, 1054 struct amdgpu_bo_va *bo_va, 1055 struct ttm_mem_reg *mem); 1056 void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, 1057 struct amdgpu_bo *bo); 1058 struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm, 1059 struct amdgpu_bo *bo); 1060 struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, 1061 struct amdgpu_vm *vm, 1062 struct amdgpu_bo *bo); 1063 int amdgpu_vm_bo_map(struct amdgpu_device *adev, 1064 struct amdgpu_bo_va *bo_va, 1065 uint64_t addr, uint64_t offset, 1066 uint64_t size, uint32_t flags); 1067 int amdgpu_vm_bo_unmap(struct amdgpu_device *adev, 1068 struct amdgpu_bo_va *bo_va, 1069 uint64_t addr); 1070 void amdgpu_vm_bo_rmv(struct amdgpu_device *adev, 1071 struct amdgpu_bo_va *bo_va); 1072 int amdgpu_vm_free_job(struct amdgpu_job *job); 1073 1074 /* 1075 * context related structures 1076 */ 1077 1078 #define AMDGPU_CTX_MAX_CS_PENDING 16 1079 1080 struct amdgpu_ctx_ring { 1081 uint64_t sequence; 1082 struct fence *fences[AMDGPU_CTX_MAX_CS_PENDING]; 1083 struct amd_sched_entity entity; 1084 }; 1085 1086 struct amdgpu_ctx { 1087 struct kref refcount; 1088 struct amdgpu_device *adev; 1089 unsigned reset_counter; 1090 spinlock_t ring_lock; 1091 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 1092 }; 1093 1094 struct amdgpu_ctx_mgr { 1095 struct amdgpu_device *adev; 1096 struct mutex lock; 1097 /* protected by lock */ 1098 struct idr ctx_handles; 1099 }; 1100 1101 int amdgpu_ctx_init(struct amdgpu_device *adev, bool kernel, 1102 struct amdgpu_ctx *ctx); 1103 void amdgpu_ctx_fini(struct amdgpu_ctx *ctx); 1104 1105 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id); 1106 int amdgpu_ctx_put(struct amdgpu_ctx *ctx); 1107 1108 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring, 1109 struct fence *fence); 1110 struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 1111 struct amdgpu_ring *ring, uint64_t seq); 1112 1113 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 1114 struct drm_file *filp); 1115 1116 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 1117 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 1118 1119 /* 1120 * file private structure 1121 */ 1122 1123 struct amdgpu_fpriv { 1124 struct amdgpu_vm vm; 1125 struct mutex bo_list_lock; 1126 struct idr bo_list_handles; 1127 struct amdgpu_ctx_mgr ctx_mgr; 1128 }; 1129 1130 /* 1131 * residency list 1132 */ 1133 1134 struct amdgpu_bo_list { 1135 struct mutex lock; 1136 struct amdgpu_bo *gds_obj; 1137 struct amdgpu_bo *gws_obj; 1138 struct amdgpu_bo *oa_obj; 1139 bool has_userptr; 1140 unsigned num_entries; 1141 struct amdgpu_bo_list_entry *array; 1142 }; 1143 1144 struct amdgpu_bo_list * 1145 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id); 1146 void amdgpu_bo_list_put(struct amdgpu_bo_list *list); 1147 void amdgpu_bo_list_free(struct amdgpu_bo_list *list); 1148 1149 /* 1150 * GFX stuff 1151 */ 1152 #include "clearstate_defs.h" 1153 1154 struct amdgpu_rlc { 1155 /* for power gating */ 1156 struct amdgpu_bo *save_restore_obj; 1157 uint64_t save_restore_gpu_addr; 1158 volatile uint32_t *sr_ptr; 1159 const u32 *reg_list; 1160 u32 reg_list_size; 1161 /* for clear state */ 1162 struct amdgpu_bo *clear_state_obj; 1163 uint64_t clear_state_gpu_addr; 1164 volatile uint32_t *cs_ptr; 1165 const struct cs_section_def *cs_data; 1166 u32 clear_state_size; 1167 /* for cp tables */ 1168 struct amdgpu_bo *cp_table_obj; 1169 uint64_t cp_table_gpu_addr; 1170 volatile uint32_t *cp_table_ptr; 1171 u32 cp_table_size; 1172 }; 1173 1174 struct amdgpu_mec { 1175 struct amdgpu_bo *hpd_eop_obj; 1176 u64 hpd_eop_gpu_addr; 1177 u32 num_pipe; 1178 u32 num_mec; 1179 u32 num_queue; 1180 }; 1181 1182 /* 1183 * GPU scratch registers structures, functions & helpers 1184 */ 1185 struct amdgpu_scratch { 1186 unsigned num_reg; 1187 uint32_t reg_base; 1188 bool free[32]; 1189 uint32_t reg[32]; 1190 }; 1191 1192 /* 1193 * GFX configurations 1194 */ 1195 struct amdgpu_gca_config { 1196 unsigned max_shader_engines; 1197 unsigned max_tile_pipes; 1198 unsigned max_cu_per_sh; 1199 unsigned max_sh_per_se; 1200 unsigned max_backends_per_se; 1201 unsigned max_texture_channel_caches; 1202 unsigned max_gprs; 1203 unsigned max_gs_threads; 1204 unsigned max_hw_contexts; 1205 unsigned sc_prim_fifo_size_frontend; 1206 unsigned sc_prim_fifo_size_backend; 1207 unsigned sc_hiz_tile_fifo_size; 1208 unsigned sc_earlyz_tile_fifo_size; 1209 1210 unsigned num_tile_pipes; 1211 unsigned backend_enable_mask; 1212 unsigned mem_max_burst_length_bytes; 1213 unsigned mem_row_size_in_kb; 1214 unsigned shader_engine_tile_size; 1215 unsigned num_gpus; 1216 unsigned multi_gpu_tile_size; 1217 unsigned mc_arb_ramcfg; 1218 unsigned gb_addr_config; 1219 1220 uint32_t tile_mode_array[32]; 1221 uint32_t macrotile_mode_array[16]; 1222 }; 1223 1224 struct amdgpu_gfx { 1225 struct mutex gpu_clock_mutex; 1226 struct amdgpu_gca_config config; 1227 struct amdgpu_rlc rlc; 1228 struct amdgpu_mec mec; 1229 struct amdgpu_scratch scratch; 1230 const struct firmware *me_fw; /* ME firmware */ 1231 uint32_t me_fw_version; 1232 const struct firmware *pfp_fw; /* PFP firmware */ 1233 uint32_t pfp_fw_version; 1234 const struct firmware *ce_fw; /* CE firmware */ 1235 uint32_t ce_fw_version; 1236 const struct firmware *rlc_fw; /* RLC firmware */ 1237 uint32_t rlc_fw_version; 1238 const struct firmware *mec_fw; /* MEC firmware */ 1239 uint32_t mec_fw_version; 1240 const struct firmware *mec2_fw; /* MEC2 firmware */ 1241 uint32_t mec2_fw_version; 1242 uint32_t me_feature_version; 1243 uint32_t ce_feature_version; 1244 uint32_t pfp_feature_version; 1245 uint32_t rlc_feature_version; 1246 uint32_t mec_feature_version; 1247 uint32_t mec2_feature_version; 1248 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS]; 1249 unsigned num_gfx_rings; 1250 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS]; 1251 unsigned num_compute_rings; 1252 struct amdgpu_irq_src eop_irq; 1253 struct amdgpu_irq_src priv_reg_irq; 1254 struct amdgpu_irq_src priv_inst_irq; 1255 /* gfx status */ 1256 uint32_t gfx_current_status; 1257 /* ce ram size*/ 1258 unsigned ce_ram_size; 1259 }; 1260 1261 int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm, 1262 unsigned size, struct amdgpu_ib *ib); 1263 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib); 1264 int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs, 1265 struct amdgpu_ib *ib, void *owner); 1266 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 1267 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 1268 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 1269 /* Ring access between begin & end cannot sleep */ 1270 void amdgpu_ring_free_size(struct amdgpu_ring *ring); 1271 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 1272 int amdgpu_ring_lock(struct amdgpu_ring *ring, unsigned ndw); 1273 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 1274 void amdgpu_ring_commit(struct amdgpu_ring *ring); 1275 void amdgpu_ring_unlock_commit(struct amdgpu_ring *ring); 1276 void amdgpu_ring_undo(struct amdgpu_ring *ring); 1277 void amdgpu_ring_unlock_undo(struct amdgpu_ring *ring); 1278 unsigned amdgpu_ring_backup(struct amdgpu_ring *ring, 1279 uint32_t **data); 1280 int amdgpu_ring_restore(struct amdgpu_ring *ring, 1281 unsigned size, uint32_t *data); 1282 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 1283 unsigned ring_size, u32 nop, u32 align_mask, 1284 struct amdgpu_irq_src *irq_src, unsigned irq_type, 1285 enum amdgpu_ring_type ring_type); 1286 void amdgpu_ring_fini(struct amdgpu_ring *ring); 1287 struct amdgpu_ring *amdgpu_ring_from_fence(struct fence *f); 1288 1289 /* 1290 * CS. 1291 */ 1292 struct amdgpu_cs_chunk { 1293 uint32_t chunk_id; 1294 uint32_t length_dw; 1295 uint32_t *kdata; 1296 void __user *user_ptr; 1297 }; 1298 1299 struct amdgpu_cs_parser { 1300 struct amdgpu_device *adev; 1301 struct drm_file *filp; 1302 struct amdgpu_ctx *ctx; 1303 struct amdgpu_bo_list *bo_list; 1304 /* chunks */ 1305 unsigned nchunks; 1306 struct amdgpu_cs_chunk *chunks; 1307 /* relocations */ 1308 struct amdgpu_bo_list_entry *vm_bos; 1309 struct list_head validated; 1310 struct fence *fence; 1311 1312 struct amdgpu_ib *ibs; 1313 uint32_t num_ibs; 1314 1315 struct ww_acquire_ctx ticket; 1316 1317 /* user fence */ 1318 struct amdgpu_user_fence uf; 1319 struct amdgpu_bo_list_entry uf_entry; 1320 }; 1321 1322 struct amdgpu_job { 1323 struct amd_sched_job base; 1324 struct amdgpu_device *adev; 1325 struct amdgpu_ib *ibs; 1326 uint32_t num_ibs; 1327 void *owner; 1328 struct amdgpu_user_fence uf; 1329 int (*free_job)(struct amdgpu_job *job); 1330 }; 1331 #define to_amdgpu_job(sched_job) \ 1332 container_of((sched_job), struct amdgpu_job, base) 1333 1334 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx) 1335 { 1336 return p->ibs[ib_idx].ptr[idx]; 1337 } 1338 1339 /* 1340 * Writeback 1341 */ 1342 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1343 1344 struct amdgpu_wb { 1345 struct amdgpu_bo *wb_obj; 1346 volatile uint32_t *wb; 1347 uint64_t gpu_addr; 1348 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 1349 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, NBBY*sizeof(unsigned long))]; 1350 }; 1351 1352 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb); 1353 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb); 1354 1355 /** 1356 * struct amdgpu_pm - power management datas 1357 * It keeps track of various data needed to take powermanagement decision. 1358 */ 1359 1360 enum amdgpu_pm_state_type { 1361 /* not used for dpm */ 1362 POWER_STATE_TYPE_DEFAULT, 1363 POWER_STATE_TYPE_POWERSAVE, 1364 /* user selectable states */ 1365 POWER_STATE_TYPE_BATTERY, 1366 POWER_STATE_TYPE_BALANCED, 1367 POWER_STATE_TYPE_PERFORMANCE, 1368 /* internal states */ 1369 POWER_STATE_TYPE_INTERNAL_UVD, 1370 POWER_STATE_TYPE_INTERNAL_UVD_SD, 1371 POWER_STATE_TYPE_INTERNAL_UVD_HD, 1372 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 1373 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 1374 POWER_STATE_TYPE_INTERNAL_BOOT, 1375 POWER_STATE_TYPE_INTERNAL_THERMAL, 1376 POWER_STATE_TYPE_INTERNAL_ACPI, 1377 POWER_STATE_TYPE_INTERNAL_ULV, 1378 POWER_STATE_TYPE_INTERNAL_3DPERF, 1379 }; 1380 1381 enum amdgpu_int_thermal_type { 1382 THERMAL_TYPE_NONE, 1383 THERMAL_TYPE_EXTERNAL, 1384 THERMAL_TYPE_EXTERNAL_GPIO, 1385 THERMAL_TYPE_RV6XX, 1386 THERMAL_TYPE_RV770, 1387 THERMAL_TYPE_ADT7473_WITH_INTERNAL, 1388 THERMAL_TYPE_EVERGREEN, 1389 THERMAL_TYPE_SUMO, 1390 THERMAL_TYPE_NI, 1391 THERMAL_TYPE_SI, 1392 THERMAL_TYPE_EMC2103_WITH_INTERNAL, 1393 THERMAL_TYPE_CI, 1394 THERMAL_TYPE_KV, 1395 }; 1396 1397 enum amdgpu_dpm_auto_throttle_src { 1398 AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, 1399 AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL 1400 }; 1401 1402 enum amdgpu_dpm_event_src { 1403 AMDGPU_DPM_EVENT_SRC_ANALOG = 0, 1404 AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1, 1405 AMDGPU_DPM_EVENT_SRC_DIGITAL = 2, 1406 AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, 1407 AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4 1408 }; 1409 1410 #define AMDGPU_MAX_VCE_LEVELS 6 1411 1412 enum amdgpu_vce_level { 1413 AMDGPU_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 1414 AMDGPU_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 1415 AMDGPU_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 1416 AMDGPU_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 1417 AMDGPU_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 1418 AMDGPU_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 1419 }; 1420 1421 struct amdgpu_ps { 1422 u32 caps; /* vbios flags */ 1423 u32 class; /* vbios flags */ 1424 u32 class2; /* vbios flags */ 1425 /* UVD clocks */ 1426 u32 vclk; 1427 u32 dclk; 1428 /* VCE clocks */ 1429 u32 evclk; 1430 u32 ecclk; 1431 bool vce_active; 1432 enum amdgpu_vce_level vce_level; 1433 /* asic priv */ 1434 void *ps_priv; 1435 }; 1436 1437 struct amdgpu_dpm_thermal { 1438 /* thermal interrupt work */ 1439 struct work_struct work; 1440 /* low temperature threshold */ 1441 int min_temp; 1442 /* high temperature threshold */ 1443 int max_temp; 1444 /* was last interrupt low to high or high to low */ 1445 bool high_to_low; 1446 /* interrupt source */ 1447 struct amdgpu_irq_src irq; 1448 }; 1449 1450 enum amdgpu_clk_action 1451 { 1452 AMDGPU_SCLK_UP = 1, 1453 AMDGPU_SCLK_DOWN 1454 }; 1455 1456 struct amdgpu_blacklist_clocks 1457 { 1458 u32 sclk; 1459 u32 mclk; 1460 enum amdgpu_clk_action action; 1461 }; 1462 1463 struct amdgpu_clock_and_voltage_limits { 1464 u32 sclk; 1465 u32 mclk; 1466 u16 vddc; 1467 u16 vddci; 1468 }; 1469 1470 struct amdgpu_clock_array { 1471 u32 count; 1472 u32 *values; 1473 }; 1474 1475 struct amdgpu_clock_voltage_dependency_entry { 1476 u32 clk; 1477 u16 v; 1478 }; 1479 1480 struct amdgpu_clock_voltage_dependency_table { 1481 u32 count; 1482 struct amdgpu_clock_voltage_dependency_entry *entries; 1483 }; 1484 1485 union amdgpu_cac_leakage_entry { 1486 struct { 1487 u16 vddc; 1488 u32 leakage; 1489 }; 1490 struct { 1491 u16 vddc1; 1492 u16 vddc2; 1493 u16 vddc3; 1494 }; 1495 }; 1496 1497 struct amdgpu_cac_leakage_table { 1498 u32 count; 1499 union amdgpu_cac_leakage_entry *entries; 1500 }; 1501 1502 struct amdgpu_phase_shedding_limits_entry { 1503 u16 voltage; 1504 u32 sclk; 1505 u32 mclk; 1506 }; 1507 1508 struct amdgpu_phase_shedding_limits_table { 1509 u32 count; 1510 struct amdgpu_phase_shedding_limits_entry *entries; 1511 }; 1512 1513 struct amdgpu_uvd_clock_voltage_dependency_entry { 1514 u32 vclk; 1515 u32 dclk; 1516 u16 v; 1517 }; 1518 1519 struct amdgpu_uvd_clock_voltage_dependency_table { 1520 u8 count; 1521 struct amdgpu_uvd_clock_voltage_dependency_entry *entries; 1522 }; 1523 1524 struct amdgpu_vce_clock_voltage_dependency_entry { 1525 u32 ecclk; 1526 u32 evclk; 1527 u16 v; 1528 }; 1529 1530 struct amdgpu_vce_clock_voltage_dependency_table { 1531 u8 count; 1532 struct amdgpu_vce_clock_voltage_dependency_entry *entries; 1533 }; 1534 1535 struct amdgpu_ppm_table { 1536 u8 ppm_design; 1537 u16 cpu_core_number; 1538 u32 platform_tdp; 1539 u32 small_ac_platform_tdp; 1540 u32 platform_tdc; 1541 u32 small_ac_platform_tdc; 1542 u32 apu_tdp; 1543 u32 dgpu_tdp; 1544 u32 dgpu_ulv_power; 1545 u32 tj_max; 1546 }; 1547 1548 struct amdgpu_cac_tdp_table { 1549 u16 tdp; 1550 u16 configurable_tdp; 1551 u16 tdc; 1552 u16 battery_power_limit; 1553 u16 small_power_limit; 1554 u16 low_cac_leakage; 1555 u16 high_cac_leakage; 1556 u16 maximum_power_delivery_limit; 1557 }; 1558 1559 struct amdgpu_dpm_dynamic_state { 1560 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk; 1561 struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk; 1562 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk; 1563 struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk; 1564 struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk; 1565 struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table; 1566 struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table; 1567 struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table; 1568 struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table; 1569 struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk; 1570 struct amdgpu_clock_array valid_sclk_values; 1571 struct amdgpu_clock_array valid_mclk_values; 1572 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc; 1573 struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac; 1574 u32 mclk_sclk_ratio; 1575 u32 sclk_mclk_delta; 1576 u16 vddc_vddci_delta; 1577 u16 min_vddc_for_pcie_gen2; 1578 struct amdgpu_cac_leakage_table cac_leakage_table; 1579 struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table; 1580 struct amdgpu_ppm_table *ppm_table; 1581 struct amdgpu_cac_tdp_table *cac_tdp_table; 1582 }; 1583 1584 struct amdgpu_dpm_fan { 1585 u16 t_min; 1586 u16 t_med; 1587 u16 t_high; 1588 u16 pwm_min; 1589 u16 pwm_med; 1590 u16 pwm_high; 1591 u8 t_hyst; 1592 u32 cycle_delay; 1593 u16 t_max; 1594 u8 control_mode; 1595 u16 default_max_fan_pwm; 1596 u16 default_fan_output_sensitivity; 1597 u16 fan_output_sensitivity; 1598 bool ucode_fan_control; 1599 }; 1600 1601 enum amdgpu_pcie_gen { 1602 AMDGPU_PCIE_GEN1 = 0, 1603 AMDGPU_PCIE_GEN2 = 1, 1604 AMDGPU_PCIE_GEN3 = 2, 1605 AMDGPU_PCIE_GEN_INVALID = 0xffff 1606 }; 1607 1608 enum amdgpu_dpm_forced_level { 1609 AMDGPU_DPM_FORCED_LEVEL_AUTO = 0, 1610 AMDGPU_DPM_FORCED_LEVEL_LOW = 1, 1611 AMDGPU_DPM_FORCED_LEVEL_HIGH = 2, 1612 }; 1613 1614 struct amdgpu_vce_state { 1615 /* vce clocks */ 1616 u32 evclk; 1617 u32 ecclk; 1618 /* gpu clocks */ 1619 u32 sclk; 1620 u32 mclk; 1621 u8 clk_idx; 1622 u8 pstate; 1623 }; 1624 1625 struct amdgpu_dpm_funcs { 1626 int (*get_temperature)(struct amdgpu_device *adev); 1627 int (*pre_set_power_state)(struct amdgpu_device *adev); 1628 int (*set_power_state)(struct amdgpu_device *adev); 1629 void (*post_set_power_state)(struct amdgpu_device *adev); 1630 void (*display_configuration_changed)(struct amdgpu_device *adev); 1631 u32 (*get_sclk)(struct amdgpu_device *adev, bool low); 1632 u32 (*get_mclk)(struct amdgpu_device *adev, bool low); 1633 void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps); 1634 void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m); 1635 int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level); 1636 bool (*vblank_too_short)(struct amdgpu_device *adev); 1637 void (*powergate_uvd)(struct amdgpu_device *adev, bool gate); 1638 void (*powergate_vce)(struct amdgpu_device *adev, bool gate); 1639 void (*enable_bapm)(struct amdgpu_device *adev, bool enable); 1640 void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode); 1641 u32 (*get_fan_control_mode)(struct amdgpu_device *adev); 1642 int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed); 1643 int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed); 1644 }; 1645 1646 struct amdgpu_dpm { 1647 struct amdgpu_ps *ps; 1648 /* number of valid power states */ 1649 int num_ps; 1650 /* current power state that is active */ 1651 struct amdgpu_ps *current_ps; 1652 /* requested power state */ 1653 struct amdgpu_ps *requested_ps; 1654 /* boot up power state */ 1655 struct amdgpu_ps *boot_ps; 1656 /* default uvd power state */ 1657 struct amdgpu_ps *uvd_ps; 1658 /* vce requirements */ 1659 struct amdgpu_vce_state vce_states[AMDGPU_MAX_VCE_LEVELS]; 1660 enum amdgpu_vce_level vce_level; 1661 enum amdgpu_pm_state_type state; 1662 enum amdgpu_pm_state_type user_state; 1663 u32 platform_caps; 1664 u32 voltage_response_time; 1665 u32 backbias_response_time; 1666 void *priv; 1667 u32 new_active_crtcs; 1668 int new_active_crtc_count; 1669 u32 current_active_crtcs; 1670 int current_active_crtc_count; 1671 struct amdgpu_dpm_dynamic_state dyn_state; 1672 struct amdgpu_dpm_fan fan; 1673 u32 tdp_limit; 1674 u32 near_tdp_limit; 1675 u32 near_tdp_limit_adjusted; 1676 u32 sq_ramping_threshold; 1677 u32 cac_leakage; 1678 u16 tdp_od_limit; 1679 u32 tdp_adjustment; 1680 u16 load_line_slope; 1681 bool power_control; 1682 bool ac_power; 1683 /* special states active */ 1684 bool thermal_active; 1685 bool uvd_active; 1686 bool vce_active; 1687 /* thermal handling */ 1688 struct amdgpu_dpm_thermal thermal; 1689 /* forced levels */ 1690 enum amdgpu_dpm_forced_level forced_level; 1691 }; 1692 1693 struct amdgpu_pm { 1694 struct mutex mutex; 1695 u32 current_sclk; 1696 u32 current_mclk; 1697 u32 default_sclk; 1698 u32 default_mclk; 1699 struct amdgpu_i2c_chan *i2c_bus; 1700 /* internal thermal controller on rv6xx+ */ 1701 enum amdgpu_int_thermal_type int_thermal_type; 1702 struct device *int_hwmon_dev; 1703 /* fan control parameters */ 1704 bool no_fan; 1705 u8 fan_pulses_per_revolution; 1706 u8 fan_min_rpm; 1707 u8 fan_max_rpm; 1708 /* dpm */ 1709 bool dpm_enabled; 1710 bool sysfs_initialized; 1711 struct amdgpu_dpm dpm; 1712 const struct firmware *fw; /* SMC firmware */ 1713 uint32_t fw_version; 1714 const struct amdgpu_dpm_funcs *funcs; 1715 }; 1716 1717 /* 1718 * UVD 1719 */ 1720 #define AMDGPU_MAX_UVD_HANDLES 10 1721 #define AMDGPU_UVD_STACK_SIZE (1024*1024) 1722 #define AMDGPU_UVD_HEAP_SIZE (1024*1024) 1723 #define AMDGPU_UVD_FIRMWARE_OFFSET 256 1724 1725 struct amdgpu_uvd { 1726 struct amdgpu_bo *vcpu_bo; 1727 void *cpu_addr; 1728 uint64_t gpu_addr; 1729 unsigned fw_version; 1730 atomic_t handles[AMDGPU_MAX_UVD_HANDLES]; 1731 struct drm_file *filp[AMDGPU_MAX_UVD_HANDLES]; 1732 struct delayed_work idle_work; 1733 const struct firmware *fw; /* UVD firmware */ 1734 struct amdgpu_ring ring; 1735 struct amdgpu_irq_src irq; 1736 bool address_64_bit; 1737 }; 1738 1739 /* 1740 * VCE 1741 */ 1742 #define AMDGPU_MAX_VCE_HANDLES 16 1743 #define AMDGPU_VCE_FIRMWARE_OFFSET 256 1744 1745 #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 1746 #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 1747 1748 struct amdgpu_vce { 1749 struct amdgpu_bo *vcpu_bo; 1750 uint64_t gpu_addr; 1751 unsigned fw_version; 1752 unsigned fb_version; 1753 atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 1754 struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 1755 uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 1756 struct delayed_work idle_work; 1757 const struct firmware *fw; /* VCE firmware */ 1758 struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 1759 struct amdgpu_irq_src irq; 1760 unsigned harvest_config; 1761 }; 1762 1763 /* 1764 * SDMA 1765 */ 1766 struct amdgpu_sdma_instance { 1767 /* SDMA firmware */ 1768 const struct firmware *fw; 1769 uint32_t fw_version; 1770 uint32_t feature_version; 1771 1772 struct amdgpu_ring ring; 1773 bool burst_nop; 1774 }; 1775 1776 struct amdgpu_sdma { 1777 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES]; 1778 struct amdgpu_irq_src trap_irq; 1779 struct amdgpu_irq_src illegal_inst_irq; 1780 int num_instances; 1781 }; 1782 1783 /* 1784 * Firmware 1785 */ 1786 struct amdgpu_firmware { 1787 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM]; 1788 bool smu_load; 1789 struct amdgpu_bo *fw_buf; 1790 unsigned int fw_size; 1791 }; 1792 1793 /* 1794 * Benchmarking 1795 */ 1796 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 1797 1798 1799 /* 1800 * Testing 1801 */ 1802 void amdgpu_test_moves(struct amdgpu_device *adev); 1803 void amdgpu_test_ring_sync(struct amdgpu_device *adev, 1804 struct amdgpu_ring *cpA, 1805 struct amdgpu_ring *cpB); 1806 void amdgpu_test_syncing(struct amdgpu_device *adev); 1807 1808 /* 1809 * MMU Notifier 1810 */ 1811 #if defined(CONFIG_MMU_NOTIFIER) 1812 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); 1813 void amdgpu_mn_unregister(struct amdgpu_bo *bo); 1814 #else 1815 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) 1816 { 1817 return -ENODEV; 1818 } 1819 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} 1820 #endif 1821 1822 /* 1823 * Debugfs 1824 */ 1825 struct amdgpu_debugfs { 1826 struct drm_info_list *files; 1827 unsigned num_files; 1828 }; 1829 1830 int amdgpu_debugfs_add_files(struct amdgpu_device *adev, 1831 struct drm_info_list *files, 1832 unsigned nfiles); 1833 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev); 1834 1835 #if defined(CONFIG_DEBUG_FS) 1836 int amdgpu_debugfs_init(struct drm_minor *minor); 1837 void amdgpu_debugfs_cleanup(struct drm_minor *minor); 1838 #endif 1839 1840 /* 1841 * amdgpu smumgr functions 1842 */ 1843 struct amdgpu_smumgr_funcs { 1844 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype); 1845 int (*request_smu_load_fw)(struct amdgpu_device *adev); 1846 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype); 1847 }; 1848 1849 /* 1850 * amdgpu smumgr 1851 */ 1852 struct amdgpu_smumgr { 1853 struct amdgpu_bo *toc_buf; 1854 struct amdgpu_bo *smu_buf; 1855 /* asic priv smu data */ 1856 void *priv; 1857 spinlock_t smu_lock; 1858 /* smumgr functions */ 1859 const struct amdgpu_smumgr_funcs *smumgr_funcs; 1860 /* ucode loading complete flag */ 1861 uint32_t fw_flags; 1862 }; 1863 1864 /* 1865 * ASIC specific register table accessible by UMD 1866 */ 1867 struct amdgpu_allowed_register_entry { 1868 uint32_t reg_offset; 1869 bool untouched; 1870 bool grbm_indexed; 1871 }; 1872 1873 struct amdgpu_cu_info { 1874 uint32_t number; /* total active CU number */ 1875 uint32_t ao_cu_mask; 1876 uint32_t bitmap[4][4]; 1877 }; 1878 1879 1880 /* 1881 * ASIC specific functions. 1882 */ 1883 struct amdgpu_asic_funcs { 1884 bool (*read_disabled_bios)(struct amdgpu_device *adev); 1885 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 1886 u32 sh_num, u32 reg_offset, u32 *value); 1887 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 1888 int (*reset)(struct amdgpu_device *adev); 1889 /* wait for mc_idle */ 1890 int (*wait_for_mc_idle)(struct amdgpu_device *adev); 1891 /* get the reference clock */ 1892 u32 (*get_xclk)(struct amdgpu_device *adev); 1893 /* get the gpu clock counter */ 1894 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev); 1895 int (*get_cu_info)(struct amdgpu_device *adev, struct amdgpu_cu_info *info); 1896 /* MM block clocks */ 1897 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 1898 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 1899 }; 1900 1901 /* 1902 * IOCTL. 1903 */ 1904 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 1905 struct drm_file *filp); 1906 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 1907 struct drm_file *filp); 1908 1909 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data, 1910 struct drm_file *filp); 1911 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 1912 struct drm_file *filp); 1913 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 1914 struct drm_file *filp); 1915 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 1916 struct drm_file *filp); 1917 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 1918 struct drm_file *filp); 1919 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 1920 struct drm_file *filp); 1921 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1922 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 1923 1924 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 1925 struct drm_file *filp); 1926 1927 /* VRAM scratch page for HDP bug, default vram page */ 1928 struct amdgpu_vram_scratch { 1929 struct amdgpu_bo *robj; 1930 volatile uint32_t *ptr; 1931 u64 gpu_addr; 1932 }; 1933 1934 /* 1935 * ACPI 1936 */ 1937 struct amdgpu_atif_notification_cfg { 1938 bool enabled; 1939 int command_code; 1940 }; 1941 1942 struct amdgpu_atif_notifications { 1943 bool display_switch; 1944 bool expansion_mode_change; 1945 bool thermal_state; 1946 bool forced_power_state; 1947 bool system_power_state; 1948 bool display_conf_change; 1949 bool px_gfx_switch; 1950 bool brightness_change; 1951 bool dgpu_display_event; 1952 }; 1953 1954 struct amdgpu_atif_functions { 1955 bool system_params; 1956 bool sbios_requests; 1957 bool select_active_disp; 1958 bool lid_state; 1959 bool get_tv_standard; 1960 bool set_tv_standard; 1961 bool get_panel_expansion_mode; 1962 bool set_panel_expansion_mode; 1963 bool temperature_change; 1964 bool graphics_device_types; 1965 }; 1966 1967 struct amdgpu_atif { 1968 struct amdgpu_atif_notifications notifications; 1969 struct amdgpu_atif_functions functions; 1970 struct amdgpu_atif_notification_cfg notification_cfg; 1971 struct amdgpu_encoder *encoder_for_bl; 1972 }; 1973 1974 struct amdgpu_atcs_functions { 1975 bool get_ext_state; 1976 bool pcie_perf_req; 1977 bool pcie_dev_rdy; 1978 bool pcie_bus_width; 1979 }; 1980 1981 struct amdgpu_atcs { 1982 struct amdgpu_atcs_functions functions; 1983 }; 1984 1985 /* 1986 * CGS 1987 */ 1988 void *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1989 void amdgpu_cgs_destroy_device(void *cgs_device); 1990 1991 1992 /* 1993 * Core structure, functions and helpers. 1994 */ 1995 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 1996 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1997 1998 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 1999 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 2000 2001 struct amdgpu_ip_block_status { 2002 bool valid; 2003 bool sw; 2004 bool hw; 2005 }; 2006 2007 struct amdgpu_device { 2008 struct device *dev; 2009 struct drm_device *ddev; 2010 struct pci_dev *pdev; 2011 2012 /* ASIC */ 2013 enum amd_asic_type asic_type; 2014 uint32_t family; 2015 uint32_t rev_id; 2016 uint32_t external_rev_id; 2017 unsigned long flags; 2018 int usec_timeout; 2019 const struct amdgpu_asic_funcs *asic_funcs; 2020 bool shutdown; 2021 bool suspend; 2022 bool need_dma32; 2023 bool accel_working; 2024 struct work_struct reset_work; 2025 struct notifier_block acpi_nb; 2026 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 2027 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 2028 unsigned debugfs_count; 2029 #if defined(CONFIG_DEBUG_FS) 2030 struct dentry *debugfs_regs; 2031 #endif 2032 struct amdgpu_atif atif; 2033 struct amdgpu_atcs atcs; 2034 struct mutex srbm_mutex; 2035 /* GRBM index mutex. Protects concurrent access to GRBM index */ 2036 struct mutex grbm_idx_mutex; 2037 struct dev_pm_domain vga_pm_domain; 2038 bool have_disp_power_ref; 2039 2040 /* BIOS */ 2041 uint8_t *bios; 2042 bool is_atom_bios; 2043 uint16_t bios_header_start; 2044 struct amdgpu_bo *stollen_vga_memory; 2045 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 2046 2047 /* Register/doorbell mmio */ 2048 #ifdef __NetBSD__ 2049 bus_space_tag_t rmmiot; 2050 bus_space_handle_t rmmioh; 2051 bus_addr_t rmmio_base; 2052 bus_size_t rmmio_size; 2053 #else 2054 resource_size_t rmmio_base; 2055 resource_size_t rmmio_size; 2056 void __iomem *rmmio; 2057 #endif 2058 /* protects concurrent MM_INDEX/DATA based register access */ 2059 spinlock_t mmio_idx_lock; 2060 /* protects concurrent SMC based register access */ 2061 spinlock_t smc_idx_lock; 2062 amdgpu_rreg_t smc_rreg; 2063 amdgpu_wreg_t smc_wreg; 2064 /* protects concurrent PCIE register access */ 2065 spinlock_t pcie_idx_lock; 2066 amdgpu_rreg_t pcie_rreg; 2067 amdgpu_wreg_t pcie_wreg; 2068 /* protects concurrent UVD register access */ 2069 spinlock_t uvd_ctx_idx_lock; 2070 amdgpu_rreg_t uvd_ctx_rreg; 2071 amdgpu_wreg_t uvd_ctx_wreg; 2072 /* protects concurrent DIDT register access */ 2073 spinlock_t didt_idx_lock; 2074 amdgpu_rreg_t didt_rreg; 2075 amdgpu_wreg_t didt_wreg; 2076 /* protects concurrent ENDPOINT (audio) register access */ 2077 spinlock_t audio_endpt_idx_lock; 2078 amdgpu_block_rreg_t audio_endpt_rreg; 2079 amdgpu_block_wreg_t audio_endpt_wreg; 2080 #ifdef __NetBSD__ 2081 bus_space_tag_t rio_memt; 2082 bus_space_handle_t rio_memh; 2083 bus_size_t rio_mem_size; 2084 #else 2085 void __iomem *rio_mem; 2086 resource_size_t rio_mem_size; 2087 #endif 2088 struct amdgpu_doorbell doorbell; 2089 2090 /* clock/pll info */ 2091 struct amdgpu_clock clock; 2092 2093 /* MC */ 2094 struct amdgpu_mc mc; 2095 struct amdgpu_gart gart; 2096 struct amdgpu_dummy_page dummy_page; 2097 struct amdgpu_vm_manager vm_manager; 2098 2099 /* memory management */ 2100 struct amdgpu_mman mman; 2101 struct amdgpu_gem gem; 2102 struct amdgpu_vram_scratch vram_scratch; 2103 struct amdgpu_wb wb; 2104 atomic64_t vram_usage; 2105 atomic64_t vram_vis_usage; 2106 atomic64_t gtt_usage; 2107 atomic64_t num_bytes_moved; 2108 atomic_t gpu_reset_counter; 2109 2110 /* display */ 2111 struct amdgpu_mode_info mode_info; 2112 struct work_struct hotplug_work; 2113 struct amdgpu_irq_src crtc_irq; 2114 struct amdgpu_irq_src pageflip_irq; 2115 struct amdgpu_irq_src hpd_irq; 2116 2117 /* rings */ 2118 unsigned fence_context; 2119 struct mutex ring_lock; 2120 unsigned num_rings; 2121 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 2122 bool ib_pool_ready; 2123 struct amdgpu_sa_manager ring_tmp_bo; 2124 2125 /* interrupts */ 2126 struct amdgpu_irq irq; 2127 2128 /* dpm */ 2129 struct amdgpu_pm pm; 2130 u32 cg_flags; 2131 u32 pg_flags; 2132 2133 /* amdgpu smumgr */ 2134 struct amdgpu_smumgr smu; 2135 2136 /* gfx */ 2137 struct amdgpu_gfx gfx; 2138 2139 /* sdma */ 2140 struct amdgpu_sdma sdma; 2141 2142 /* uvd */ 2143 bool has_uvd; 2144 struct amdgpu_uvd uvd; 2145 2146 /* vce */ 2147 struct amdgpu_vce vce; 2148 2149 /* firmwares */ 2150 struct amdgpu_firmware firmware; 2151 2152 /* GDS */ 2153 struct amdgpu_gds gds; 2154 2155 const struct amdgpu_ip_block_version *ip_blocks; 2156 int num_ip_blocks; 2157 struct amdgpu_ip_block_status *ip_block_status; 2158 struct mutex mn_lock; 2159 DECLARE_HASHTABLE(mn_hash, 7); 2160 2161 /* tracking pinned memory */ 2162 u64 vram_pin_size; 2163 u64 gart_pin_size; 2164 2165 /* amdkfd interface */ 2166 struct kfd_dev *kfd; 2167 2168 /* kernel conext for IB submission */ 2169 struct amdgpu_ctx kernel_ctx; 2170 }; 2171 2172 bool amdgpu_device_is_px(struct drm_device *dev); 2173 int amdgpu_device_init(struct amdgpu_device *adev, 2174 struct drm_device *ddev, 2175 struct pci_dev *pdev, 2176 uint32_t flags); 2177 void amdgpu_device_fini(struct amdgpu_device *adev); 2178 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 2179 2180 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 2181 bool always_indirect); 2182 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 2183 bool always_indirect); 2184 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 2185 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 2186 2187 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index); 2188 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v); 2189 2190 /* 2191 * Cast helper 2192 */ 2193 extern const struct fence_ops amdgpu_fence_ops; 2194 static inline struct amdgpu_fence *to_amdgpu_fence(struct fence *f) 2195 { 2196 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base); 2197 2198 if (__f->base.ops == &amdgpu_fence_ops) 2199 return __f; 2200 2201 return NULL; 2202 } 2203 2204 /* 2205 * Registers read & write functions. 2206 */ 2207 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), false) 2208 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), true) 2209 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), false)) 2210 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) 2211 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) 2212 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2213 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 2214 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 2215 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 2216 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 2217 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 2218 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 2219 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 2220 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 2221 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 2222 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 2223 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 2224 #define WREG32_P(reg, val, mask) \ 2225 do { \ 2226 uint32_t tmp_ = RREG32(reg); \ 2227 tmp_ &= (mask); \ 2228 tmp_ |= ((val) & ~(mask)); \ 2229 WREG32(reg, tmp_); \ 2230 } while (0) 2231 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 2232 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 2233 #define WREG32_PLL_P(reg, val, mask) \ 2234 do { \ 2235 uint32_t tmp_ = RREG32_PLL(reg); \ 2236 tmp_ &= (mask); \ 2237 tmp_ |= ((val) & ~(mask)); \ 2238 WREG32_PLL(reg, tmp_); \ 2239 } while (0) 2240 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 2241 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 2242 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 2243 2244 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index)) 2245 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v)) 2246 2247 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 2248 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 2249 2250 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 2251 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 2252 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 2253 2254 #define REG_GET_FIELD(value, reg, field) \ 2255 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 2256 2257 /* 2258 * BIOS helpers. 2259 */ 2260 #define RBIOS8(i) (adev->bios[i]) 2261 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 2262 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 2263 2264 /* 2265 * RING helpers. 2266 */ 2267 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 2268 { 2269 if (ring->count_dw <= 0) 2270 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 2271 ring->ring[ring->wptr++] = v; 2272 ring->wptr &= ring->ptr_mask; 2273 ring->count_dw--; 2274 ring->ring_free_dw--; 2275 } 2276 2277 static inline struct amdgpu_sdma_instance * 2278 amdgpu_get_sdma_instance(struct amdgpu_ring *ring) 2279 { 2280 struct amdgpu_device *adev = ring->adev; 2281 int i; 2282 2283 for (i = 0; i < adev->sdma.num_instances; i++) 2284 if (&adev->sdma.instance[i].ring == ring) 2285 break; 2286 2287 if (i < AMDGPU_MAX_SDMA_INSTANCES) 2288 return &adev->sdma.instance[i]; 2289 else 2290 return NULL; 2291 } 2292 2293 /* 2294 * ASICs macro. 2295 */ 2296 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 2297 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 2298 #define amdgpu_asic_wait_for_mc_idle(adev) (adev)->asic_funcs->wait_for_mc_idle((adev)) 2299 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 2300 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 2301 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 2302 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 2303 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 2304 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 2305 #define amdgpu_asic_get_cu_info(adev, info) (adev)->asic_funcs->get_cu_info((adev), (info)) 2306 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid)) 2307 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags)) 2308 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count))) 2309 #define amdgpu_vm_write_pte(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (addr), (count), (incr), (flags))) 2310 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags))) 2311 #define amdgpu_vm_pad_ib(adev, ib) ((adev)->vm_manager.vm_pte_funcs->pad_ib((ib))) 2312 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 2313 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 2314 #define amdgpu_ring_test_ib(r) (r)->funcs->test_ib((r)) 2315 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 2316 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 2317 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 2318 #define amdgpu_ring_emit_ib(r, ib) (r)->funcs->emit_ib((r), (ib)) 2319 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 2320 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 2321 #define amdgpu_ring_emit_semaphore(r, semaphore, emit_wait) (r)->funcs->emit_semaphore((r), (semaphore), (emit_wait)) 2322 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 2323 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 2324 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev)) 2325 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv)) 2326 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev)) 2327 #define amdgpu_display_set_vga_render_state(adev, r) (adev)->mode_info.funcs->set_vga_render_state((adev), (r)) 2328 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc)) 2329 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc)) 2330 #define amdgpu_display_is_display_hung(adev) (adev)->mode_info.funcs->is_display_hung((adev)) 2331 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l)) 2332 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e)) 2333 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h)) 2334 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h)) 2335 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev)) 2336 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev)) 2337 #define amdgpu_display_page_flip(adev, crtc, base) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base)) 2338 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos)) 2339 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c)) 2340 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r)) 2341 #define amdgpu_display_stop_mc_access(adev, s) (adev)->mode_info.funcs->stop_mc_access((adev), (s)) 2342 #define amdgpu_display_resume_mc_access(adev, s) (adev)->mode_info.funcs->resume_mc_access((adev), (s)) 2343 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b)) 2344 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b)) 2345 #define amdgpu_dpm_get_temperature(adev) (adev)->pm.funcs->get_temperature((adev)) 2346 #define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev)) 2347 #define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev)) 2348 #define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev)) 2349 #define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev)) 2350 #define amdgpu_dpm_get_sclk(adev, l) (adev)->pm.funcs->get_sclk((adev), (l)) 2351 #define amdgpu_dpm_get_mclk(adev, l) (adev)->pm.funcs->get_mclk((adev), (l)) 2352 #define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps)) 2353 #define amdgpu_dpm_debugfs_print_current_performance_level(adev, m) (adev)->pm.funcs->debugfs_print_current_performance_level((adev), (m)) 2354 #define amdgpu_dpm_force_performance_level(adev, l) (adev)->pm.funcs->force_performance_level((adev), (l)) 2355 #define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev)) 2356 #define amdgpu_dpm_powergate_uvd(adev, g) (adev)->pm.funcs->powergate_uvd((adev), (g)) 2357 #define amdgpu_dpm_powergate_vce(adev, g) (adev)->pm.funcs->powergate_vce((adev), (g)) 2358 #define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e)) 2359 #define amdgpu_dpm_set_fan_control_mode(adev, m) (adev)->pm.funcs->set_fan_control_mode((adev), (m)) 2360 #define amdgpu_dpm_get_fan_control_mode(adev) (adev)->pm.funcs->get_fan_control_mode((adev)) 2361 #define amdgpu_dpm_set_fan_speed_percent(adev, s) (adev)->pm.funcs->set_fan_speed_percent((adev), (s)) 2362 #define amdgpu_dpm_get_fan_speed_percent(adev, s) (adev)->pm.funcs->get_fan_speed_percent((adev), (s)) 2363 2364 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a)) 2365 2366 /* Common functions */ 2367 int amdgpu_gpu_reset(struct amdgpu_device *adev); 2368 void amdgpu_pci_config_reset(struct amdgpu_device *adev); 2369 bool amdgpu_card_posted(struct amdgpu_device *adev); 2370 void amdgpu_update_display_priority(struct amdgpu_device *adev); 2371 bool amdgpu_boot_test_post_card(struct amdgpu_device *adev); 2372 2373 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data); 2374 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type, 2375 u32 ip_instance, u32 ring, 2376 struct amdgpu_ring **out_ring); 2377 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain); 2378 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); 2379 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr, 2380 uint32_t flags); 2381 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); 2382 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, 2383 unsigned long end); 2384 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); 2385 uint32_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, 2386 struct ttm_mem_reg *mem); 2387 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base); 2388 void amdgpu_gtt_location(struct amdgpu_device *adev, struct amdgpu_mc *mc); 2389 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); 2390 void amdgpu_program_register_sequence(struct amdgpu_device *adev, 2391 const u32 *registers, 2392 const u32 array_size); 2393 int amdgpu_ttm_init(struct amdgpu_device *adev); 2394 void amdgpu_ttm_fini(struct amdgpu_device *adev); 2395 2396 bool amdgpu_device_is_px(struct drm_device *dev); 2397 /* atpx handler */ 2398 #if defined(CONFIG_VGA_SWITCHEROO) 2399 void amdgpu_register_atpx_handler(void); 2400 void amdgpu_unregister_atpx_handler(void); 2401 #else 2402 static inline void amdgpu_register_atpx_handler(void) {} 2403 static inline void amdgpu_unregister_atpx_handler(void) {} 2404 #endif 2405 2406 /* 2407 * KMS 2408 */ 2409 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 2410 extern int amdgpu_max_kms_ioctl; 2411 2412 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 2413 int amdgpu_driver_unload_kms(struct drm_device *dev); 2414 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 2415 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 2416 void amdgpu_driver_postclose_kms(struct drm_device *dev, 2417 struct drm_file *file_priv); 2418 void amdgpu_driver_preclose_kms(struct drm_device *dev, 2419 struct drm_file *file_priv); 2420 int amdgpu_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon); 2421 int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon); 2422 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 2423 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2424 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 2425 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 2426 int *max_error, 2427 struct timeval *vblank_time, 2428 unsigned flags); 2429 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 2430 unsigned long arg); 2431 2432 /* 2433 * functions used by amdgpu_encoder.c 2434 */ 2435 struct amdgpu_afmt_acr { 2436 u32 clock; 2437 2438 int n_32khz; 2439 int cts_32khz; 2440 2441 int n_44_1khz; 2442 int cts_44_1khz; 2443 2444 int n_48khz; 2445 int cts_48khz; 2446 2447 }; 2448 2449 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 2450 2451 /* amdgpu_acpi.c */ 2452 #if defined(CONFIG_ACPI) 2453 int amdgpu_acpi_init(struct amdgpu_device *adev); 2454 void amdgpu_acpi_fini(struct amdgpu_device *adev); 2455 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 2456 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 2457 u8 perf_req, bool advertise); 2458 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 2459 #else 2460 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 2461 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 2462 #endif 2463 2464 struct amdgpu_bo_va_mapping * 2465 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 2466 uint64_t addr, struct amdgpu_bo **bo); 2467 2468 #include "amdgpu_object.h" 2469 2470 #endif 2471
Indexes created Tue Sep 30 07:10:03 GMT 2025