amdgpu.h revision 1.5
1 /* $NetBSD: amdgpu.h,v 1.5 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_H__ 31 #define __AMDGPU_H__ 32 33 #ifdef _KERNEL_OPT 34 #include "opt_amdgpu_cik.h" 35 #endif 36 37 #ifdef AMDGPU_CIK 38 #define CONFIG_DRM_AMDGPU_CIK 1 39 #endif 40 #include "amdgpu_ctx.h" 41 42 #include <linux/atomic.h> 43 #include <linux/wait.h> 44 #include <linux/list.h> 45 #include <linux/kref.h> 46 #include <linux/rbtree.h> 47 #include <linux/hashtable.h> 48 #include <linux/dma-fence.h> 49 50 #include <drm/ttm/ttm_bo_api.h> 51 #include <drm/ttm/ttm_bo_driver.h> 52 #include <drm/ttm/ttm_placement.h> 53 #include <drm/ttm/ttm_module.h> 54 #include <drm/ttm/ttm_execbuf_util.h> 55 56 #include <drm/amdgpu_drm.h> 57 #include <drm/drm_gem.h> 58 #include <drm/drm_ioctl.h> 59 #include <drm/gpu_scheduler.h> 60 61 #include <kgd_kfd_interface.h> 62 #include "dm_pp_interface.h" 63 #include "kgd_pp_interface.h" 64 65 #include "amd_shared.h" 66 #include "amdgpu_mode.h" 67 #include "amdgpu_ih.h" 68 #include "amdgpu_irq.h" 69 #include "amdgpu_ucode.h" 70 #include "amdgpu_ttm.h" 71 #include "amdgpu_psp.h" 72 #include "amdgpu_gds.h" 73 #include "amdgpu_sync.h" 74 #include "amdgpu_ring.h" 75 #include "amdgpu_vm.h" 76 #include "amdgpu_dpm.h" 77 #include "amdgpu_acp.h" 78 #include "amdgpu_uvd.h" 79 #include "amdgpu_vce.h" 80 #include "amdgpu_vcn.h" 81 #include "amdgpu_jpeg.h" 82 #include "amdgpu_mn.h" 83 #include "amdgpu_gmc.h" 84 #include "amdgpu_gfx.h" 85 #include "amdgpu_sdma.h" 86 #include "amdgpu_nbio.h" 87 #include "amdgpu_dm.h" 88 #include "amdgpu_virt.h" 89 #include "amdgpu_csa.h" 90 #include "amdgpu_gart.h" 91 #include "amdgpu_debugfs.h" 92 #include "amdgpu_job.h" 93 #include "amdgpu_bo_list.h" 94 #include "amdgpu_gem.h" 95 #include "amdgpu_doorbell.h" 96 #include "amdgpu_amdkfd.h" 97 #include "amdgpu_smu.h" 98 #include "amdgpu_discovery.h" 99 #include "amdgpu_mes.h" 100 #include "amdgpu_umc.h" 101 #include "amdgpu_mmhub.h" 102 #include "amdgpu_df.h" 103 104 #define MAX_GPU_INSTANCE 16 105 106 struct amdgpu_gpu_instance 107 { 108 struct amdgpu_device *adev; 109 int mgpu_fan_enabled; 110 }; 111 112 struct amdgpu_mgpu_info 113 { 114 struct amdgpu_gpu_instance gpu_ins[MAX_GPU_INSTANCE]; 115 struct mutex mutex; 116 uint32_t num_gpu; 117 uint32_t num_dgpu; 118 uint32_t num_apu; 119 }; 120 121 #define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256 122 123 /* 124 * Modules parameters. 125 */ 126 extern int amdgpu_modeset; 127 extern int amdgpu_vram_limit; 128 extern int amdgpu_vis_vram_limit; 129 extern int amdgpu_gart_size; 130 extern int amdgpu_gtt_size; 131 extern int amdgpu_moverate; 132 extern int amdgpu_benchmarking; 133 extern int amdgpu_testing; 134 extern int amdgpu_audio; 135 extern int amdgpu_disp_priority; 136 extern int amdgpu_hw_i2c; 137 extern int amdgpu_pcie_gen2; 138 extern int amdgpu_msi; 139 extern char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 140 extern int amdgpu_dpm; 141 extern int amdgpu_fw_load_type; 142 extern int amdgpu_aspm; 143 extern int amdgpu_runtime_pm; 144 extern uint amdgpu_ip_block_mask; 145 extern int amdgpu_bapm; 146 extern int amdgpu_deep_color; 147 extern int amdgpu_vm_size; 148 extern int amdgpu_vm_block_size; 149 extern int amdgpu_vm_fragment_size; 150 extern int amdgpu_vm_fault_stop; 151 extern int amdgpu_vm_debug; 152 extern int amdgpu_vm_update_mode; 153 extern int amdgpu_exp_hw_support; 154 extern int amdgpu_dc; 155 extern int amdgpu_sched_jobs; 156 extern int amdgpu_sched_hw_submission; 157 extern uint amdgpu_pcie_gen_cap; 158 extern uint amdgpu_pcie_lane_cap; 159 extern uint amdgpu_cg_mask; 160 extern uint amdgpu_pg_mask; 161 extern uint amdgpu_sdma_phase_quantum; 162 extern char *amdgpu_disable_cu; 163 extern char *amdgpu_virtual_display; 164 extern uint amdgpu_pp_feature_mask; 165 extern uint amdgpu_force_long_training; 166 extern int amdgpu_job_hang_limit; 167 extern int amdgpu_lbpw; 168 extern int amdgpu_compute_multipipe; 169 extern int amdgpu_gpu_recovery; 170 extern int amdgpu_emu_mode; 171 extern uint amdgpu_smu_memory_pool_size; 172 extern uint amdgpu_dc_feature_mask; 173 extern uint amdgpu_dm_abm_level; 174 extern struct amdgpu_mgpu_info mgpu_info; 175 extern int amdgpu_ras_enable; 176 extern uint amdgpu_ras_mask; 177 extern int amdgpu_async_gfx_ring; 178 extern int amdgpu_mcbp; 179 extern int amdgpu_discovery; 180 extern int amdgpu_mes; 181 extern int amdgpu_noretry; 182 extern int amdgpu_force_asic_type; 183 #ifdef CONFIG_HSA_AMD 184 extern int sched_policy; 185 #else 186 static const int sched_policy = KFD_SCHED_POLICY_HWS; 187 #endif 188 189 #ifdef CONFIG_DRM_AMDGPU_SI 190 extern int amdgpu_si_support; 191 #endif 192 #ifdef CONFIG_DRM_AMDGPU_CIK 193 extern int amdgpu_cik_support; 194 #endif 195 196 #define AMDGPU_VM_MAX_NUM_CTX 4096 197 #define AMDGPU_SG_THRESHOLD (256*1024*1024) 198 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */ 199 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000 200 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */ 201 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2) 202 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */ 203 #define AMDGPU_IB_POOL_SIZE 16 204 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32 205 #define AMDGPUFB_CONN_LIMIT 4 206 #define AMDGPU_BIOS_NUM_SCRATCH 16 207 208 /* hard reset data */ 209 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b 210 211 /* reset flags */ 212 #define AMDGPU_RESET_GFX (1 << 0) 213 #define AMDGPU_RESET_COMPUTE (1 << 1) 214 #define AMDGPU_RESET_DMA (1 << 2) 215 #define AMDGPU_RESET_CP (1 << 3) 216 #define AMDGPU_RESET_GRBM (1 << 4) 217 #define AMDGPU_RESET_DMA1 (1 << 5) 218 #define AMDGPU_RESET_RLC (1 << 6) 219 #define AMDGPU_RESET_SEM (1 << 7) 220 #define AMDGPU_RESET_IH (1 << 8) 221 #define AMDGPU_RESET_VMC (1 << 9) 222 #define AMDGPU_RESET_MC (1 << 10) 223 #define AMDGPU_RESET_DISPLAY (1 << 11) 224 #define AMDGPU_RESET_UVD (1 << 12) 225 #define AMDGPU_RESET_VCE (1 << 13) 226 #define AMDGPU_RESET_VCE1 (1 << 14) 227 228 /* max cursor sizes (in pixels) */ 229 #define CIK_CURSOR_WIDTH 128 230 #define CIK_CURSOR_HEIGHT 128 231 232 struct amdgpu_device; 233 struct amdgpu_ib; 234 struct amdgpu_cs_parser; 235 struct amdgpu_job; 236 struct amdgpu_irq_src; 237 struct amdgpu_fpriv; 238 struct amdgpu_bo_va_mapping; 239 struct amdgpu_atif; 240 struct kfd_vm_fault_info; 241 242 enum amdgpu_cp_irq { 243 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP = 0, 244 AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP, 245 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP, 246 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP, 247 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP, 248 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP, 249 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP, 250 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP, 251 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP, 252 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP, 253 254 AMDGPU_CP_IRQ_LAST 255 }; 256 257 enum amdgpu_thermal_irq { 258 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0, 259 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW, 260 261 AMDGPU_THERMAL_IRQ_LAST 262 }; 263 264 enum amdgpu_kiq_irq { 265 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0, 266 AMDGPU_CP_KIQ_IRQ_LAST 267 }; 268 269 #define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */ 270 #define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */ 271 #define MAX_KIQ_REG_TRY 80 /* 20 -> 80 */ 272 273 int amdgpu_device_ip_set_clockgating_state(void *dev, 274 enum amd_ip_block_type block_type, 275 enum amd_clockgating_state state); 276 int amdgpu_device_ip_set_powergating_state(void *dev, 277 enum amd_ip_block_type block_type, 278 enum amd_powergating_state state); 279 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, 280 u32 *flags); 281 int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, 282 enum amd_ip_block_type block_type); 283 bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, 284 enum amd_ip_block_type block_type); 285 286 #define AMDGPU_MAX_IP_NUM 16 287 288 struct amdgpu_ip_block_status { 289 bool valid; 290 bool sw; 291 bool hw; 292 bool late_initialized; 293 bool hang; 294 }; 295 296 struct amdgpu_ip_block_version { 297 const enum amd_ip_block_type type; 298 const u32 major; 299 const u32 minor; 300 const u32 rev; 301 const struct amd_ip_funcs *funcs; 302 }; 303 304 #define HW_REV(_Major, _Minor, _Rev) \ 305 ((((uint32_t) (_Major)) << 16) | ((uint32_t) (_Minor) << 8) | ((uint32_t) (_Rev))) 306 307 struct amdgpu_ip_block { 308 struct amdgpu_ip_block_status status; 309 const struct amdgpu_ip_block_version *version; 310 }; 311 312 int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, 313 enum amd_ip_block_type type, 314 u32 major, u32 minor); 315 316 struct amdgpu_ip_block * 317 amdgpu_device_ip_get_ip_block(struct amdgpu_device *adev, 318 enum amd_ip_block_type type); 319 320 int amdgpu_device_ip_block_add(struct amdgpu_device *adev, 321 const struct amdgpu_ip_block_version *ip_block_version); 322 323 /* 324 * BIOS. 325 */ 326 bool amdgpu_get_bios(struct amdgpu_device *adev); 327 bool amdgpu_read_bios(struct amdgpu_device *adev); 328 329 /* 330 * Clocks 331 */ 332 333 #define AMDGPU_MAX_PPLL 3 334 335 struct amdgpu_clock { 336 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL]; 337 struct amdgpu_pll spll; 338 struct amdgpu_pll mpll; 339 /* 10 Khz units */ 340 uint32_t default_mclk; 341 uint32_t default_sclk; 342 uint32_t default_dispclk; 343 uint32_t current_dispclk; 344 uint32_t dp_extclk; 345 uint32_t max_pixel_clock; 346 }; 347 348 /* sub-allocation manager, it has to be protected by another lock. 349 * By conception this is an helper for other part of the driver 350 * like the indirect buffer or semaphore, which both have their 351 * locking. 352 * 353 * Principe is simple, we keep a list of sub allocation in offset 354 * order (first entry has offset == 0, last entry has the highest 355 * offset). 356 * 357 * When allocating new object we first check if there is room at 358 * the end total_size - (last_object_offset + last_object_size) >= 359 * alloc_size. If so we allocate new object there. 360 * 361 * When there is not enough room at the end, we start waiting for 362 * each sub object until we reach object_offset+object_size >= 363 * alloc_size, this object then become the sub object we return. 364 * 365 * Alignment can't be bigger than page size. 366 * 367 * Hole are not considered for allocation to keep things simple. 368 * Assumption is that there won't be hole (all object on same 369 * alignment). 370 */ 371 372 #define AMDGPU_SA_NUM_FENCE_LISTS 32 373 374 struct amdgpu_sa_manager { 375 #ifdef __NetBSD__ 376 spinlock_t wq_lock; 377 drm_waitqueue_t wq; 378 #else 379 wait_queue_head_t wq; 380 #endif 381 struct amdgpu_bo *bo; 382 struct list_head *hole; 383 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS]; 384 struct list_head olist; 385 unsigned size; 386 uint64_t gpu_addr; 387 void *cpu_ptr; 388 uint32_t domain; 389 uint32_t align; 390 }; 391 392 /* sub-allocation buffer */ 393 struct amdgpu_sa_bo { 394 struct list_head olist; 395 struct list_head flist; 396 struct amdgpu_sa_manager *manager; 397 unsigned soffset; 398 unsigned eoffset; 399 struct dma_fence *fence; 400 }; 401 402 int amdgpu_fence_slab_init(void); 403 void amdgpu_fence_slab_fini(void); 404 405 /* 406 * IRQS. 407 */ 408 409 struct amdgpu_flip_work { 410 struct delayed_work flip_work; 411 struct work_struct unpin_work; 412 struct amdgpu_device *adev; 413 int crtc_id; 414 u32 target_vblank; 415 uint64_t base; 416 struct drm_pending_vblank_event *event; 417 struct amdgpu_bo *old_abo; 418 struct dma_fence *excl; 419 unsigned shared_count; 420 struct dma_fence **shared; 421 struct dma_fence_cb cb; 422 bool async; 423 }; 424 425 426 /* 427 * CP & rings. 428 */ 429 430 struct amdgpu_ib { 431 struct amdgpu_sa_bo *sa_bo; 432 uint32_t length_dw; 433 uint64_t gpu_addr; 434 uint32_t *ptr; 435 uint32_t flags; 436 }; 437 438 extern const struct drm_sched_backend_ops amdgpu_sched_ops; 439 440 /* 441 * file private structure 442 */ 443 444 struct amdgpu_fpriv { 445 struct amdgpu_vm vm; 446 struct amdgpu_bo_va *prt_va; 447 struct amdgpu_bo_va *csa_va; 448 struct mutex bo_list_lock; 449 struct idr bo_list_handles; 450 struct amdgpu_ctx_mgr ctx_mgr; 451 }; 452 453 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv); 454 455 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 456 unsigned size, struct amdgpu_ib *ib); 457 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, 458 struct dma_fence *f); 459 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, 460 struct amdgpu_ib *ibs, struct amdgpu_job *job, 461 struct dma_fence **f); 462 int amdgpu_ib_pool_init(struct amdgpu_device *adev); 463 void amdgpu_ib_pool_fini(struct amdgpu_device *adev); 464 int amdgpu_ib_ring_tests(struct amdgpu_device *adev); 465 466 /* 467 * CS. 468 */ 469 struct amdgpu_cs_chunk { 470 uint32_t chunk_id; 471 uint32_t length_dw; 472 void *kdata; 473 }; 474 475 struct amdgpu_cs_post_dep { 476 struct drm_syncobj *syncobj; 477 struct dma_fence_chain *chain; 478 u64 point; 479 }; 480 481 struct amdgpu_cs_parser { 482 struct amdgpu_device *adev; 483 struct drm_file *filp; 484 struct amdgpu_ctx *ctx; 485 486 /* chunks */ 487 unsigned nchunks; 488 struct amdgpu_cs_chunk *chunks; 489 490 /* scheduler job object */ 491 struct amdgpu_job *job; 492 struct drm_sched_entity *entity; 493 494 /* buffer objects */ 495 struct ww_acquire_ctx ticket; 496 struct amdgpu_bo_list *bo_list; 497 struct amdgpu_mn *mn; 498 struct amdgpu_bo_list_entry vm_pd; 499 struct list_head validated; 500 struct dma_fence *fence; 501 uint64_t bytes_moved_threshold; 502 uint64_t bytes_moved_vis_threshold; 503 uint64_t bytes_moved; 504 uint64_t bytes_moved_vis; 505 506 /* user fence */ 507 struct amdgpu_bo_list_entry uf_entry; 508 509 unsigned num_post_deps; 510 struct amdgpu_cs_post_dep *post_deps; 511 }; 512 513 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, 514 uint32_t ib_idx, int idx) 515 { 516 return p->job->ibs[ib_idx].ptr[idx]; 517 } 518 519 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p, 520 uint32_t ib_idx, int idx, 521 uint32_t value) 522 { 523 p->job->ibs[ib_idx].ptr[idx] = value; 524 } 525 526 /* 527 * Writeback 528 */ 529 #define AMDGPU_MAX_WB 128 /* Reserve at most 128 WB slots for amdgpu-owned rings. */ 530 531 struct amdgpu_wb { 532 struct amdgpu_bo *wb_obj; 533 volatile uint32_t *wb; 534 uint64_t gpu_addr; 535 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */ 536 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, NBBY*sizeof(unsigned long))]; 537 }; 538 539 int amdgpu_device_wb_get(struct amdgpu_device *adev, u32 *wb); 540 void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb); 541 542 /* 543 * Benchmarking 544 */ 545 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number); 546 547 548 /* 549 * Testing 550 */ 551 void amdgpu_test_moves(struct amdgpu_device *adev); 552 553 /* 554 * ASIC specific register table accessible by UMD 555 */ 556 struct amdgpu_allowed_register_entry { 557 uint32_t reg_offset; 558 bool grbm_indexed; 559 }; 560 561 enum amd_reset_method { 562 AMD_RESET_METHOD_LEGACY = 0, 563 AMD_RESET_METHOD_MODE0, 564 AMD_RESET_METHOD_MODE1, 565 AMD_RESET_METHOD_MODE2, 566 AMD_RESET_METHOD_BACO 567 }; 568 569 /* 570 * ASIC specific functions. 571 */ 572 struct amdgpu_asic_funcs { 573 bool (*read_disabled_bios)(struct amdgpu_device *adev); 574 bool (*read_bios_from_rom)(struct amdgpu_device *adev, 575 u8 *bios, u32 length_bytes); 576 int (*read_register)(struct amdgpu_device *adev, u32 se_num, 577 u32 sh_num, u32 reg_offset, u32 *value); 578 void (*set_vga_state)(struct amdgpu_device *adev, bool state); 579 int (*reset)(struct amdgpu_device *adev); 580 enum amd_reset_method (*reset_method)(struct amdgpu_device *adev); 581 /* get the reference clock */ 582 u32 (*get_xclk)(struct amdgpu_device *adev); 583 /* MM block clocks */ 584 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk); 585 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk); 586 /* static power management */ 587 int (*get_pcie_lanes)(struct amdgpu_device *adev); 588 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes); 589 /* get config memsize register */ 590 u32 (*get_config_memsize)(struct amdgpu_device *adev); 591 /* flush hdp write queue */ 592 void (*flush_hdp)(struct amdgpu_device *adev, struct amdgpu_ring *ring); 593 /* invalidate hdp read cache */ 594 void (*invalidate_hdp)(struct amdgpu_device *adev, 595 struct amdgpu_ring *ring); 596 /* check if the asic needs a full reset of if soft reset will work */ 597 bool (*need_full_reset)(struct amdgpu_device *adev); 598 /* initialize doorbell layout for specific asic*/ 599 void (*init_doorbell_index)(struct amdgpu_device *adev); 600 /* PCIe bandwidth usage */ 601 void (*get_pcie_usage)(struct amdgpu_device *adev, uint64_t *count0, 602 uint64_t *count1); 603 /* do we need to reset the asic at init time (e.g., kexec) */ 604 bool (*need_reset_on_init)(struct amdgpu_device *adev); 605 /* PCIe replay counter */ 606 uint64_t (*get_pcie_replay_count)(struct amdgpu_device *adev); 607 /* device supports BACO */ 608 bool (*supports_baco)(struct amdgpu_device *adev); 609 }; 610 611 /* 612 * IOCTL. 613 */ 614 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data, 615 struct drm_file *filp); 616 617 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 618 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data, 619 struct drm_file *filp); 620 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); 621 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, 622 struct drm_file *filp); 623 624 /* VRAM scratch page for HDP bug, default vram page */ 625 struct amdgpu_vram_scratch { 626 struct amdgpu_bo *robj; 627 volatile uint32_t *ptr; 628 u64 gpu_addr; 629 }; 630 631 /* 632 * ACPI 633 */ 634 struct amdgpu_atcs_functions { 635 bool get_ext_state; 636 bool pcie_perf_req; 637 bool pcie_dev_rdy; 638 bool pcie_bus_width; 639 }; 640 641 struct amdgpu_atcs { 642 struct amdgpu_atcs_functions functions; 643 }; 644 645 /* 646 * Firmware VRAM reservation 647 */ 648 struct amdgpu_fw_vram_usage { 649 u64 start_offset; 650 u64 size; 651 struct amdgpu_bo *reserved_bo; 652 void *va; 653 654 /* GDDR6 training support flag. 655 */ 656 bool mem_train_support; 657 }; 658 659 /* 660 * CGS 661 */ 662 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 663 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device); 664 665 /* 666 * Core structure, functions and helpers. 667 */ 668 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t); 669 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 670 671 typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device*, uint32_t); 672 typedef void (*amdgpu_wreg64_t)(struct amdgpu_device*, uint32_t, uint64_t); 673 674 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t); 675 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t); 676 677 struct amdgpu_mmio_remap { 678 u32 reg_offset; 679 resource_size_t bus_addr; 680 }; 681 682 /* Define the HW IP blocks will be used in driver , add more if necessary */ 683 enum amd_hw_ip_block_type { 684 GC_HWIP = 1, 685 HDP_HWIP, 686 SDMA0_HWIP, 687 SDMA1_HWIP, 688 SDMA2_HWIP, 689 SDMA3_HWIP, 690 SDMA4_HWIP, 691 SDMA5_HWIP, 692 SDMA6_HWIP, 693 SDMA7_HWIP, 694 MMHUB_HWIP, 695 ATHUB_HWIP, 696 NBIO_HWIP, 697 MP0_HWIP, 698 MP1_HWIP, 699 UVD_HWIP, 700 VCN_HWIP = UVD_HWIP, 701 JPEG_HWIP = VCN_HWIP, 702 VCE_HWIP, 703 DF_HWIP, 704 DCE_HWIP, 705 OSSSYS_HWIP, 706 SMUIO_HWIP, 707 PWR_HWIP, 708 NBIF_HWIP, 709 THM_HWIP, 710 CLK_HWIP, 711 UMC_HWIP, 712 RSMU_HWIP, 713 MAX_HWIP 714 }; 715 716 #define HWIP_MAX_INSTANCE 8 717 718 struct amd_powerplay { 719 void *pp_handle; 720 const struct amd_pm_funcs *pp_funcs; 721 }; 722 723 #define AMDGPU_RESET_MAGIC_NUM 64 724 #define AMDGPU_MAX_DF_PERFMONS 4 725 struct amdgpu_device { 726 struct device *dev; 727 struct drm_device *ddev; 728 struct pci_dev *pdev; 729 730 #ifdef CONFIG_DRM_AMD_ACP 731 struct amdgpu_acp acp; 732 #endif 733 734 /* ASIC */ 735 enum amd_asic_type asic_type; 736 uint32_t family; 737 uint32_t rev_id; 738 uint32_t external_rev_id; 739 unsigned long flags; 740 int usec_timeout; 741 const struct amdgpu_asic_funcs *asic_funcs; 742 bool shutdown; 743 bool need_swiotlb; 744 bool accel_working; 745 struct notifier_block acpi_nb; 746 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS]; 747 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 748 unsigned debugfs_count; 749 #if defined(CONFIG_DEBUG_FS) 750 struct dentry *debugfs_preempt; 751 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS]; 752 #endif 753 struct amdgpu_atif *atif; 754 struct amdgpu_atcs atcs; 755 struct mutex srbm_mutex; 756 /* GRBM index mutex. Protects concurrent access to GRBM index */ 757 struct mutex grbm_idx_mutex; 758 struct dev_pm_domain vga_pm_domain; 759 bool have_disp_power_ref; 760 bool have_atomics_support; 761 762 /* BIOS */ 763 bool is_atom_fw; 764 uint8_t *bios; 765 uint32_t bios_size; 766 struct amdgpu_bo *stolen_vga_memory; 767 struct amdgpu_bo *discovery_memory; 768 uint32_t bios_scratch_reg_offset; 769 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; 770 771 /* Register/doorbell mmio */ 772 #ifdef __NetBSD__ 773 bus_space_tag_t rmmiot; 774 bus_space_handle_t rmmioh; 775 bus_addr_t rmmio_base; 776 bus_size_t rmmio_size; 777 #else 778 resource_size_t rmmio_base; 779 resource_size_t rmmio_size; 780 void __iomem *rmmio; 781 #endif 782 /* protects concurrent MM_INDEX/DATA based register access */ 783 spinlock_t mmio_idx_lock; 784 struct amdgpu_mmio_remap rmmio_remap; 785 /* protects concurrent SMC based register access */ 786 spinlock_t smc_idx_lock; 787 amdgpu_rreg_t smc_rreg; 788 amdgpu_wreg_t smc_wreg; 789 /* protects concurrent PCIE register access */ 790 spinlock_t pcie_idx_lock; 791 amdgpu_rreg_t pcie_rreg; 792 amdgpu_wreg_t pcie_wreg; 793 amdgpu_rreg_t pciep_rreg; 794 amdgpu_wreg_t pciep_wreg; 795 amdgpu_rreg64_t pcie_rreg64; 796 amdgpu_wreg64_t pcie_wreg64; 797 /* protects concurrent UVD register access */ 798 spinlock_t uvd_ctx_idx_lock; 799 amdgpu_rreg_t uvd_ctx_rreg; 800 amdgpu_wreg_t uvd_ctx_wreg; 801 /* protects concurrent DIDT register access */ 802 spinlock_t didt_idx_lock; 803 amdgpu_rreg_t didt_rreg; 804 amdgpu_wreg_t didt_wreg; 805 /* protects concurrent gc_cac register access */ 806 spinlock_t gc_cac_idx_lock; 807 amdgpu_rreg_t gc_cac_rreg; 808 amdgpu_wreg_t gc_cac_wreg; 809 /* protects concurrent se_cac register access */ 810 spinlock_t se_cac_idx_lock; 811 amdgpu_rreg_t se_cac_rreg; 812 amdgpu_wreg_t se_cac_wreg; 813 /* protects concurrent ENDPOINT (audio) register access */ 814 spinlock_t audio_endpt_idx_lock; 815 amdgpu_block_rreg_t audio_endpt_rreg; 816 amdgpu_block_wreg_t audio_endpt_wreg; 817 #ifdef __NetBSD__ 818 bus_space_tag_t rio_memt; 819 bus_space_handle_t rio_memh; 820 bus_size_t rio_mem_size; 821 #else 822 void __iomem *rio_mem; 823 resource_size_t rio_mem_size; 824 #endif 825 struct amdgpu_doorbell doorbell; 826 827 /* clock/pll info */ 828 struct amdgpu_clock clock; 829 830 /* MC */ 831 struct amdgpu_gmc gmc; 832 struct amdgpu_gart gart; 833 #ifdef __NetBSD__ 834 bus_dma_segment_t dummy_page_seg; 835 bus_dmamap_t dummy_page_map; 836 #endif 837 dma_addr_t dummy_page_addr; 838 struct amdgpu_vm_manager vm_manager; 839 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS]; 840 unsigned num_vmhubs; 841 842 /* memory management */ 843 struct amdgpu_mman mman; 844 struct amdgpu_vram_scratch vram_scratch; 845 struct amdgpu_wb wb; 846 atomic64_t num_bytes_moved; 847 atomic64_t num_evictions; 848 atomic64_t num_vram_cpu_page_faults; 849 atomic_t gpu_reset_counter; 850 atomic_t vram_lost_counter; 851 852 /* data for buffer migration throttling */ 853 struct { 854 spinlock_t lock; 855 s64 last_update_us; 856 s64 accum_us; /* accumulated microseconds */ 857 s64 accum_us_vis; /* for visible VRAM */ 858 u32 log2_max_MBps; 859 } mm_stats; 860 861 /* display */ 862 bool enable_virtual_display; 863 struct amdgpu_mode_info mode_info; 864 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */ 865 struct work_struct hotplug_work; 866 struct amdgpu_irq_src crtc_irq; 867 struct amdgpu_irq_src vupdate_irq; 868 struct amdgpu_irq_src pageflip_irq; 869 struct amdgpu_irq_src hpd_irq; 870 871 /* rings */ 872 u64 fence_context; 873 unsigned num_rings; 874 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS]; 875 bool ib_pool_ready; 876 struct amdgpu_sa_manager ring_tmp_bo; 877 878 /* interrupts */ 879 struct amdgpu_irq irq; 880 881 /* powerplay */ 882 struct amd_powerplay powerplay; 883 bool pp_force_state_enabled; 884 885 /* smu */ 886 struct smu_context smu; 887 888 /* dpm */ 889 struct amdgpu_pm pm; 890 u32 cg_flags; 891 u32 pg_flags; 892 893 /* nbio */ 894 struct amdgpu_nbio nbio; 895 896 /* mmhub */ 897 struct amdgpu_mmhub mmhub; 898 899 /* gfx */ 900 struct amdgpu_gfx gfx; 901 902 /* sdma */ 903 struct amdgpu_sdma sdma; 904 905 /* uvd */ 906 struct amdgpu_uvd uvd; 907 908 /* vce */ 909 struct amdgpu_vce vce; 910 911 /* vcn */ 912 struct amdgpu_vcn vcn; 913 914 /* jpeg */ 915 struct amdgpu_jpeg jpeg; 916 917 /* firmwares */ 918 struct amdgpu_firmware firmware; 919 920 /* PSP */ 921 struct psp_context psp; 922 923 /* GDS */ 924 struct amdgpu_gds gds; 925 926 /* KFD */ 927 struct amdgpu_kfd_dev kfd; 928 929 /* UMC */ 930 struct amdgpu_umc umc; 931 932 /* display related functionality */ 933 struct amdgpu_display_manager dm; 934 935 /* discovery */ 936 uint8_t *discovery; 937 938 /* mes */ 939 bool enable_mes; 940 struct amdgpu_mes mes; 941 942 /* df */ 943 struct amdgpu_df df; 944 945 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM]; 946 int num_ip_blocks; 947 struct mutex mn_lock; 948 DECLARE_HASHTABLE(mn_hash, 7); 949 950 /* tracking pinned memory */ 951 atomic64_t vram_pin_size; 952 atomic64_t visible_pin_size; 953 atomic64_t gart_pin_size; 954 955 /* soc15 register offset based on ip, instance and segment */ 956 uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE]; 957 958 /* delayed work_func for deferring clockgating during resume */ 959 struct delayed_work delayed_init_work; 960 961 struct amdgpu_virt virt; 962 /* firmware VRAM reservation */ 963 struct amdgpu_fw_vram_usage fw_vram_usage; 964 965 /* link all shadow bo */ 966 struct list_head shadow_list; 967 struct mutex shadow_list_lock; 968 /* keep an lru list of rings by HW IP */ 969 struct list_head ring_lru_list; 970 spinlock_t ring_lru_list_lock; 971 972 /* record hw reset is performed */ 973 bool has_hw_reset; 974 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; 975 976 /* s3/s4 mask */ 977 bool in_suspend; 978 979 /* record last mm index being written through WREG32*/ 980 unsigned long last_mm_index; 981 bool in_gpu_reset; 982 enum pp_mp1_state mp1_state; 983 struct mutex lock_reset; 984 struct amdgpu_doorbell_index doorbell_index; 985 986 struct mutex notifier_lock; 987 988 int asic_reset_res; 989 struct work_struct xgmi_reset_work; 990 991 long gfx_timeout; 992 long sdma_timeout; 993 long video_timeout; 994 long compute_timeout; 995 996 uint64_t unique_id; 997 uint64_t df_perfmon_config_assign_mask[AMDGPU_MAX_DF_PERFMONS]; 998 999 /* device pstate */ 1000 int pstate; 1001 /* enable runtime pm on the device */ 1002 bool runpm; 1003 1004 bool pm_sysfs_en; 1005 bool ucode_sysfs_en; 1006 }; 1007 1008 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev) 1009 { 1010 return container_of(bdev, struct amdgpu_device, mman.bdev); 1011 } 1012 1013 int amdgpu_device_init(struct amdgpu_device *adev, 1014 struct drm_device *ddev, 1015 struct pci_dev *pdev, 1016 uint32_t flags); 1017 void amdgpu_device_fini(struct amdgpu_device *adev); 1018 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev); 1019 1020 void amdgpu_device_vram_access(struct amdgpu_device *adev, loff_t pos, 1021 uint32_t *buf, size_t size, bool write); 1022 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg, 1023 uint32_t acc_flags); 1024 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v, 1025 uint32_t acc_flags); 1026 void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value); 1027 uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset); 1028 1029 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg); 1030 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v); 1031 1032 bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type); 1033 bool amdgpu_device_has_dc_support(struct amdgpu_device *adev); 1034 1035 int emu_soc_asic_init(struct amdgpu_device *adev); 1036 1037 /* 1038 * Registers read & write functions. 1039 */ 1040 1041 #define AMDGPU_REGS_IDX (1<<0) 1042 #define AMDGPU_REGS_NO_KIQ (1<<1) 1043 #define AMDGPU_REGS_KIQ (1<<2) 1044 1045 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ) 1046 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ) 1047 1048 #define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ) 1049 #define WREG32_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_KIQ) 1050 1051 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg)) 1052 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v)) 1053 1054 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0) 1055 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX) 1056 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0)) 1057 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0) 1058 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX) 1059 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1060 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) 1061 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg)) 1062 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v)) 1063 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg)) 1064 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v)) 1065 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg)) 1066 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v)) 1067 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg)) 1068 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v)) 1069 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg)) 1070 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) 1071 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg)) 1072 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v)) 1073 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1074 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1075 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1076 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1077 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg)) 1078 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v)) 1079 #define WREG32_P(reg, val, mask) \ 1080 do { \ 1081 uint32_t tmp_ = RREG32(reg); \ 1082 tmp_ &= (mask); \ 1083 tmp_ |= ((val) & ~(mask)); \ 1084 WREG32(reg, tmp_); \ 1085 } while (0) 1086 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) 1087 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) 1088 #define WREG32_PLL_P(reg, val, mask) \ 1089 do { \ 1090 uint32_t tmp_ = RREG32_PLL(reg); \ 1091 tmp_ &= (mask); \ 1092 tmp_ |= ((val) & ~(mask)); \ 1093 WREG32_PLL(reg, tmp_); \ 1094 } while (0) 1095 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false)) 1096 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg)) 1097 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v)) 1098 1099 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 1100 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK 1101 1102 #define REG_SET_FIELD(orig_val, reg, field, field_val) \ 1103 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \ 1104 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field)))) 1105 1106 #define REG_GET_FIELD(value, reg, field) \ 1107 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field)) 1108 1109 #define WREG32_FIELD(reg, field, val) \ 1110 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1111 1112 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \ 1113 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field)) 1114 1115 /* 1116 * BIOS helpers. 1117 */ 1118 #define RBIOS8(i) (adev->bios[i]) 1119 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) 1120 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) 1121 1122 /* 1123 * ASICs macro. 1124 */ 1125 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state)) 1126 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev)) 1127 #define amdgpu_asic_reset_method(adev) (adev)->asic_funcs->reset_method((adev)) 1128 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev)) 1129 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d)) 1130 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec)) 1131 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev)) 1132 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l)) 1133 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev)) 1134 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev)) 1135 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l)) 1136 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v))) 1137 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev)) 1138 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r)) 1139 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r)) 1140 #define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev)) 1141 #define amdgpu_asic_init_doorbell_index(adev) (adev)->asic_funcs->init_doorbell_index((adev)) 1142 #define amdgpu_asic_get_pcie_usage(adev, cnt0, cnt1) ((adev)->asic_funcs->get_pcie_usage((adev), (cnt0), (cnt1))) 1143 #define amdgpu_asic_need_reset_on_init(adev) (adev)->asic_funcs->need_reset_on_init((adev)) 1144 #define amdgpu_asic_get_pcie_replay_count(adev) ((adev)->asic_funcs->get_pcie_replay_count((adev))) 1145 #define amdgpu_asic_supports_baco(adev) (adev)->asic_funcs->supports_baco((adev)) 1146 1147 #define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter)); 1148 1149 /* Common functions */ 1150 bool amdgpu_device_should_recover_gpu(struct amdgpu_device *adev); 1151 int amdgpu_device_gpu_recover(struct amdgpu_device *adev, 1152 struct amdgpu_job* job); 1153 void amdgpu_device_pci_config_reset(struct amdgpu_device *adev); 1154 bool amdgpu_device_need_post(struct amdgpu_device *adev); 1155 1156 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, 1157 u64 num_vis_bytes); 1158 int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); 1159 void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 1160 const u32 *registers, 1161 const u32 array_size); 1162 int amdgpu_ttm_init(struct amdgpu_device *adev); 1163 void amdgpu_ttm_fini(struct amdgpu_device *adev); 1164 1165 bool amdgpu_device_supports_boco(struct drm_device *dev); 1166 bool amdgpu_device_supports_baco(struct drm_device *dev); 1167 bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, 1168 struct amdgpu_device *peer_adev); 1169 int amdgpu_device_baco_enter(struct drm_device *dev); 1170 int amdgpu_device_baco_exit(struct drm_device *dev); 1171 1172 /* atpx handler */ 1173 #if defined(CONFIG_VGA_SWITCHEROO) 1174 void amdgpu_register_atpx_handler(void); 1175 void amdgpu_unregister_atpx_handler(void); 1176 bool amdgpu_has_atpx_dgpu_power_cntl(void); 1177 bool amdgpu_is_atpx_hybrid(void); 1178 bool amdgpu_atpx_dgpu_req_power_for_displays(void); 1179 bool amdgpu_has_atpx(void); 1180 #else 1181 static inline void amdgpu_register_atpx_handler(void) {} 1182 static inline void amdgpu_unregister_atpx_handler(void) {} 1183 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } 1184 static inline bool amdgpu_is_atpx_hybrid(void) { return false; } 1185 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } 1186 static inline bool amdgpu_has_atpx(void) { return false; } 1187 #endif 1188 1189 #if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) 1190 void *amdgpu_atpx_get_dhandle(void); 1191 #else 1192 static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } 1193 #endif 1194 1195 /* 1196 * KMS 1197 */ 1198 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1199 extern const int amdgpu_max_kms_ioctl; 1200 1201 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1202 void amdgpu_driver_unload_kms(struct drm_device *dev); 1203 void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1204 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv); 1205 void amdgpu_driver_postclose_kms(struct drm_device *dev, 1206 struct drm_file *file_priv); 1207 int amdgpu_device_ip_suspend(struct amdgpu_device *adev); 1208 int amdgpu_device_suspend(struct drm_device *dev, bool fbcon); 1209 int amdgpu_device_resume(struct drm_device *dev, bool fbcon); 1210 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe); 1211 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1212 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe); 1213 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd, 1214 unsigned long arg); 1215 1216 /* 1217 * functions used by amdgpu_encoder.c 1218 */ 1219 struct amdgpu_afmt_acr { 1220 u32 clock; 1221 1222 int n_32khz; 1223 int cts_32khz; 1224 1225 int n_44_1khz; 1226 int cts_44_1khz; 1227 1228 int n_48khz; 1229 int cts_48khz; 1230 1231 }; 1232 1233 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); 1234 1235 /* amdgpu_acpi.c */ 1236 #if defined(CONFIG_ACPI) 1237 int amdgpu_acpi_init(struct amdgpu_device *adev); 1238 void amdgpu_acpi_fini(struct amdgpu_device *adev); 1239 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev); 1240 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev, 1241 u8 perf_req, bool advertise); 1242 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); 1243 1244 void amdgpu_acpi_get_backlight_caps(struct amdgpu_device *adev, 1245 struct amdgpu_dm_backlight_caps *caps); 1246 #else 1247 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } 1248 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } 1249 #endif 1250 1251 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, 1252 uint64_t addr, struct amdgpu_bo **bo, 1253 struct amdgpu_bo_va_mapping **mapping); 1254 1255 #if defined(CONFIG_DRM_AMD_DC) 1256 int amdgpu_dm_display_resume(struct amdgpu_device *adev ); 1257 #else 1258 static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } 1259 #endif 1260 1261 1262 void amdgpu_register_gpu_instance(struct amdgpu_device *adev); 1263 void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); 1264 1265 #include "amdgpu_object.h" 1266 1267 /* used by df_v3_6.c and amdgpu_pmu.c */ 1268 #define AMDGPU_PMU_ATTR(_name, _object) \ 1269 static ssize_t \ 1270 _name##_show(struct device *dev, \ 1271 struct device_attribute *attr, \ 1272 char *page) \ 1273 { \ 1274 BUILD_BUG_ON(sizeof(_object) >= PAGE_SIZE - 1); \ 1275 return sprintf(page, _object "\n"); \ 1276 } \ 1277 \ 1278 static struct device_attribute pmu_attr_##_name = __ATTR_RO(_name) 1279 1280 #endif 1281 1282
Indexes created Mon Sep 29 21:09:56 GMT 2025