amdgpu_atom.c revision 1.3
1 /* $NetBSD: amdgpu_atom.c,v 1.3 2020/02/14 14:34:57 maya Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Author: Stanislaw Skowronek 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atom.c,v 1.3 2020/02/14 14:34:57 maya Exp $"); 29 30 #include <linux/module.h> 31 #include <linux/sched.h> 32 #include <linux/slab.h> 33 #include <asm/unaligned.h> 34 35 #define ATOM_DEBUG 36 37 #include "atom.h" 38 #include "atom-names.h" 39 #include "atom-bits.h" 40 #include "amdgpu.h" 41 42 #define ATOM_COND_ABOVE 0 43 #define ATOM_COND_ABOVEOREQUAL 1 44 #define ATOM_COND_ALWAYS 2 45 #define ATOM_COND_BELOW 3 46 #define ATOM_COND_BELOWOREQUAL 4 47 #define ATOM_COND_EQUAL 5 48 #define ATOM_COND_NOTEQUAL 6 49 50 #define ATOM_PORT_ATI 0 51 #define ATOM_PORT_PCI 1 52 #define ATOM_PORT_SYSIO 2 53 54 #define ATOM_UNIT_MICROSEC 0 55 #define ATOM_UNIT_MILLISEC 1 56 57 #define PLL_INDEX 2 58 #define PLL_DATA 3 59 60 typedef struct { 61 struct atom_context *ctx; 62 uint32_t *ps, *ws; 63 int ps_shift; 64 uint16_t start; 65 unsigned last_jump; 66 unsigned long last_jump_jiffies; 67 bool abort; 68 } atom_exec_context; 69 70 int amdgpu_atom_debug = 0; 71 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params); 72 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params); 73 74 static uint32_t atom_arg_mask[8] = 75 { 0xFFFFFFFF, 0xFFFF, 0xFFFF00, 0xFFFF0000, 0xFF, 0xFF00, 0xFF0000, 76 0xFF000000 }; 77 static int atom_arg_shift[8] = { 0, 0, 8, 16, 0, 8, 16, 24 }; 78 79 static int atom_dst_to_src[8][4] = { 80 /* translate destination alignment field to the source alignment encoding */ 81 {0, 0, 0, 0}, 82 {1, 2, 3, 0}, 83 {1, 2, 3, 0}, 84 {1, 2, 3, 0}, 85 {4, 5, 6, 7}, 86 {4, 5, 6, 7}, 87 {4, 5, 6, 7}, 88 {4, 5, 6, 7}, 89 }; 90 static int atom_def_dst[8] = { 0, 0, 1, 2, 0, 1, 2, 3 }; 91 92 static int debug_depth = 0; 93 #undef DEBUG /* XXX NetBSD kludge */ 94 #ifdef ATOM_DEBUG 95 static void debug_print_spaces(int n) 96 { 97 while (n--) 98 printk(" "); 99 } 100 101 #define DEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG __VA_ARGS__); } while (0) 102 #define SDEBUG(...) do if (amdgpu_atom_debug) { printk(KERN_DEBUG); debug_print_spaces(debug_depth); printk(__VA_ARGS__); } while (0) 103 #else 104 #define DEBUG(...) do { } while (0) 105 #define SDEBUG(...) do { } while (0) 106 #endif 107 108 static uint32_t atom_iio_execute(struct atom_context *ctx, int base, 109 uint32_t index, uint32_t data) 110 { 111 uint32_t temp = 0xCDCDCDCD; 112 113 while (1) 114 switch (CU8(base)) { 115 case ATOM_IIO_NOP: 116 base++; 117 break; 118 case ATOM_IIO_READ: 119 temp = ctx->card->ioreg_read(ctx->card, CU16(base + 1)); 120 base += 3; 121 break; 122 case ATOM_IIO_WRITE: 123 ctx->card->ioreg_write(ctx->card, CU16(base + 1), temp); 124 base += 3; 125 break; 126 case ATOM_IIO_CLEAR: 127 temp &= 128 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 129 CU8(base + 2)); 130 base += 3; 131 break; 132 case ATOM_IIO_SET: 133 temp |= 134 (0xFFFFFFFF >> (32 - CU8(base + 1))) << CU8(base + 135 2); 136 base += 3; 137 break; 138 case ATOM_IIO_MOVE_INDEX: 139 temp &= 140 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 141 CU8(base + 3)); 142 temp |= 143 ((index >> CU8(base + 2)) & 144 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 145 3); 146 base += 4; 147 break; 148 case ATOM_IIO_MOVE_DATA: 149 temp &= 150 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 151 CU8(base + 3)); 152 temp |= 153 ((data >> CU8(base + 2)) & 154 (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + 155 3); 156 base += 4; 157 break; 158 case ATOM_IIO_MOVE_ATTR: 159 temp &= 160 ~((0xFFFFFFFF >> (32 - CU8(base + 1))) << 161 CU8(base + 3)); 162 temp |= 163 ((ctx-> 164 io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - 165 CU8 166 (base 167 + 168 1)))) 169 << CU8(base + 3); 170 base += 4; 171 break; 172 case ATOM_IIO_END: 173 return temp; 174 default: 175 printk(KERN_INFO "Unknown IIO opcode.\n"); 176 return 0; 177 } 178 } 179 180 static uint32_t atom_get_src_int(atom_exec_context *ctx, uint8_t attr, 181 int *ptr, uint32_t *saved, int print) 182 { 183 uint32_t idx, val = 0xCDCDCDCD, align, arg; 184 struct atom_context *gctx = ctx->ctx; 185 arg = attr & 7; 186 align = (attr >> 3) & 7; 187 switch (arg) { 188 case ATOM_ARG_REG: 189 idx = U16(*ptr); 190 (*ptr) += 2; 191 if (print) 192 DEBUG("REG[0x%04X]", idx); 193 idx += gctx->reg_block; 194 switch (gctx->io_mode) { 195 case ATOM_IO_MM: 196 val = gctx->card->reg_read(gctx->card, idx); 197 break; 198 case ATOM_IO_PCI: 199 printk(KERN_INFO 200 "PCI registers are not implemented.\n"); 201 return 0; 202 case ATOM_IO_SYSIO: 203 printk(KERN_INFO 204 "SYSIO registers are not implemented.\n"); 205 return 0; 206 default: 207 if (!(gctx->io_mode & 0x80)) { 208 printk(KERN_INFO "Bad IO mode.\n"); 209 return 0; 210 } 211 if (!gctx->iio[gctx->io_mode & 0x7F]) { 212 printk(KERN_INFO 213 "Undefined indirect IO read method %d.\n", 214 gctx->io_mode & 0x7F); 215 return 0; 216 } 217 val = 218 atom_iio_execute(gctx, 219 gctx->iio[gctx->io_mode & 0x7F], 220 idx, 0); 221 } 222 break; 223 case ATOM_ARG_PS: 224 idx = U8(*ptr); 225 (*ptr)++; 226 /* get_unaligned_le32 avoids unaligned accesses from atombios 227 * tables, noticed on a DEC Alpha. */ 228 val = get_unaligned_le32((u32 *)&ctx->ps[idx]); 229 if (print) 230 DEBUG("PS[0x%02X,0x%04X]", idx, val); 231 break; 232 case ATOM_ARG_WS: 233 idx = U8(*ptr); 234 (*ptr)++; 235 if (print) 236 DEBUG("WS[0x%02X]", idx); 237 switch (idx) { 238 case ATOM_WS_QUOTIENT: 239 val = gctx->divmul[0]; 240 break; 241 case ATOM_WS_REMAINDER: 242 val = gctx->divmul[1]; 243 break; 244 case ATOM_WS_DATAPTR: 245 val = gctx->data_block; 246 break; 247 case ATOM_WS_SHIFT: 248 val = gctx->shift; 249 break; 250 case ATOM_WS_OR_MASK: 251 val = 1 << gctx->shift; 252 break; 253 case ATOM_WS_AND_MASK: 254 val = ~(1 << gctx->shift); 255 break; 256 case ATOM_WS_FB_WINDOW: 257 val = gctx->fb_base; 258 break; 259 case ATOM_WS_ATTRIBUTES: 260 val = gctx->io_attr; 261 break; 262 case ATOM_WS_REGPTR: 263 val = gctx->reg_block; 264 break; 265 default: 266 val = ctx->ws[idx]; 267 } 268 break; 269 case ATOM_ARG_ID: 270 idx = U16(*ptr); 271 (*ptr) += 2; 272 if (print) { 273 if (gctx->data_block) 274 DEBUG("ID[0x%04X+%04X]", idx, gctx->data_block); 275 else 276 DEBUG("ID[0x%04X]", idx); 277 } 278 val = U32(idx + gctx->data_block); 279 break; 280 case ATOM_ARG_FB: 281 idx = U8(*ptr); 282 (*ptr)++; 283 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 284 DRM_ERROR("ATOM: fb read beyond scratch region: %d vs. %d\n", 285 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 286 val = 0; 287 } else 288 val = gctx->scratch[(gctx->fb_base / 4) + idx]; 289 if (print) 290 DEBUG("FB[0x%02X]", idx); 291 break; 292 case ATOM_ARG_IMM: 293 switch (align) { 294 case ATOM_SRC_DWORD: 295 val = U32(*ptr); 296 (*ptr) += 4; 297 if (print) 298 DEBUG("IMM 0x%08X\n", val); 299 return val; 300 case ATOM_SRC_WORD0: 301 case ATOM_SRC_WORD8: 302 case ATOM_SRC_WORD16: 303 val = U16(*ptr); 304 (*ptr) += 2; 305 if (print) 306 DEBUG("IMM 0x%04X\n", val); 307 return val; 308 case ATOM_SRC_BYTE0: 309 case ATOM_SRC_BYTE8: 310 case ATOM_SRC_BYTE16: 311 case ATOM_SRC_BYTE24: 312 val = U8(*ptr); 313 (*ptr)++; 314 if (print) 315 DEBUG("IMM 0x%02X\n", val); 316 return val; 317 } 318 return 0; 319 case ATOM_ARG_PLL: 320 idx = U8(*ptr); 321 (*ptr)++; 322 if (print) 323 DEBUG("PLL[0x%02X]", idx); 324 val = gctx->card->pll_read(gctx->card, idx); 325 break; 326 case ATOM_ARG_MC: 327 idx = U8(*ptr); 328 (*ptr)++; 329 if (print) 330 DEBUG("MC[0x%02X]", idx); 331 val = gctx->card->mc_read(gctx->card, idx); 332 break; 333 } 334 if (saved) 335 *saved = val; 336 val &= atom_arg_mask[align]; 337 val >>= atom_arg_shift[align]; 338 if (print) 339 switch (align) { 340 case ATOM_SRC_DWORD: 341 DEBUG(".[31:0] -> 0x%08X\n", val); 342 break; 343 case ATOM_SRC_WORD0: 344 DEBUG(".[15:0] -> 0x%04X\n", val); 345 break; 346 case ATOM_SRC_WORD8: 347 DEBUG(".[23:8] -> 0x%04X\n", val); 348 break; 349 case ATOM_SRC_WORD16: 350 DEBUG(".[31:16] -> 0x%04X\n", val); 351 break; 352 case ATOM_SRC_BYTE0: 353 DEBUG(".[7:0] -> 0x%02X\n", val); 354 break; 355 case ATOM_SRC_BYTE8: 356 DEBUG(".[15:8] -> 0x%02X\n", val); 357 break; 358 case ATOM_SRC_BYTE16: 359 DEBUG(".[23:16] -> 0x%02X\n", val); 360 break; 361 case ATOM_SRC_BYTE24: 362 DEBUG(".[31:24] -> 0x%02X\n", val); 363 break; 364 } 365 return val; 366 } 367 368 static void atom_skip_src_int(atom_exec_context *ctx, uint8_t attr, int *ptr) 369 { 370 uint32_t align = (attr >> 3) & 7, arg = attr & 7; 371 switch (arg) { 372 case ATOM_ARG_REG: 373 case ATOM_ARG_ID: 374 (*ptr) += 2; 375 break; 376 case ATOM_ARG_PLL: 377 case ATOM_ARG_MC: 378 case ATOM_ARG_PS: 379 case ATOM_ARG_WS: 380 case ATOM_ARG_FB: 381 (*ptr)++; 382 break; 383 case ATOM_ARG_IMM: 384 switch (align) { 385 case ATOM_SRC_DWORD: 386 (*ptr) += 4; 387 return; 388 case ATOM_SRC_WORD0: 389 case ATOM_SRC_WORD8: 390 case ATOM_SRC_WORD16: 391 (*ptr) += 2; 392 return; 393 case ATOM_SRC_BYTE0: 394 case ATOM_SRC_BYTE8: 395 case ATOM_SRC_BYTE16: 396 case ATOM_SRC_BYTE24: 397 (*ptr)++; 398 return; 399 } 400 return; 401 } 402 } 403 404 static uint32_t atom_get_src(atom_exec_context *ctx, uint8_t attr, int *ptr) 405 { 406 return atom_get_src_int(ctx, attr, ptr, NULL, 1); 407 } 408 409 static uint32_t atom_get_src_direct(atom_exec_context *ctx, uint8_t align, int *ptr) 410 { 411 uint32_t val = 0xCDCDCDCD; 412 413 switch (align) { 414 case ATOM_SRC_DWORD: 415 val = U32(*ptr); 416 (*ptr) += 4; 417 break; 418 case ATOM_SRC_WORD0: 419 case ATOM_SRC_WORD8: 420 case ATOM_SRC_WORD16: 421 val = U16(*ptr); 422 (*ptr) += 2; 423 break; 424 case ATOM_SRC_BYTE0: 425 case ATOM_SRC_BYTE8: 426 case ATOM_SRC_BYTE16: 427 case ATOM_SRC_BYTE24: 428 val = U8(*ptr); 429 (*ptr)++; 430 break; 431 } 432 return val; 433 } 434 435 static uint32_t atom_get_dst(atom_exec_context *ctx, int arg, uint8_t attr, 436 int *ptr, uint32_t *saved, int print) 437 { 438 return atom_get_src_int(ctx, 439 arg | atom_dst_to_src[(attr >> 3) & 440 7][(attr >> 6) & 3] << 3, 441 ptr, saved, print); 442 } 443 444 static void atom_skip_dst(atom_exec_context *ctx, int arg, uint8_t attr, int *ptr) 445 { 446 atom_skip_src_int(ctx, 447 arg | atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 448 3] << 3, ptr); 449 } 450 451 static void atom_put_dst(atom_exec_context *ctx, int arg, uint8_t attr, 452 int *ptr, uint32_t val, uint32_t saved) 453 { 454 uint32_t align = 455 atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3], old_val = 456 val, idx; 457 struct atom_context *gctx = ctx->ctx; 458 old_val &= atom_arg_mask[align] >> atom_arg_shift[align]; 459 val <<= atom_arg_shift[align]; 460 val &= atom_arg_mask[align]; 461 saved &= ~atom_arg_mask[align]; 462 val |= saved; 463 switch (arg) { 464 case ATOM_ARG_REG: 465 idx = U16(*ptr); 466 (*ptr) += 2; 467 DEBUG("REG[0x%04X]", idx); 468 idx += gctx->reg_block; 469 switch (gctx->io_mode) { 470 case ATOM_IO_MM: 471 if (idx == 0) 472 gctx->card->reg_write(gctx->card, idx, 473 val << 2); 474 else 475 gctx->card->reg_write(gctx->card, idx, val); 476 break; 477 case ATOM_IO_PCI: 478 printk(KERN_INFO 479 "PCI registers are not implemented.\n"); 480 return; 481 case ATOM_IO_SYSIO: 482 printk(KERN_INFO 483 "SYSIO registers are not implemented.\n"); 484 return; 485 default: 486 if (!(gctx->io_mode & 0x80)) { 487 printk(KERN_INFO "Bad IO mode.\n"); 488 return; 489 } 490 if (!gctx->iio[gctx->io_mode & 0xFF]) { 491 printk(KERN_INFO 492 "Undefined indirect IO write method %d.\n", 493 gctx->io_mode & 0x7F); 494 return; 495 } 496 atom_iio_execute(gctx, gctx->iio[gctx->io_mode & 0xFF], 497 idx, val); 498 } 499 break; 500 case ATOM_ARG_PS: 501 idx = U8(*ptr); 502 (*ptr)++; 503 DEBUG("PS[0x%02X]", idx); 504 ctx->ps[idx] = cpu_to_le32(val); 505 break; 506 case ATOM_ARG_WS: 507 idx = U8(*ptr); 508 (*ptr)++; 509 DEBUG("WS[0x%02X]", idx); 510 switch (idx) { 511 case ATOM_WS_QUOTIENT: 512 gctx->divmul[0] = val; 513 break; 514 case ATOM_WS_REMAINDER: 515 gctx->divmul[1] = val; 516 break; 517 case ATOM_WS_DATAPTR: 518 gctx->data_block = val; 519 break; 520 case ATOM_WS_SHIFT: 521 gctx->shift = val; 522 break; 523 case ATOM_WS_OR_MASK: 524 case ATOM_WS_AND_MASK: 525 break; 526 case ATOM_WS_FB_WINDOW: 527 gctx->fb_base = val; 528 break; 529 case ATOM_WS_ATTRIBUTES: 530 gctx->io_attr = val; 531 break; 532 case ATOM_WS_REGPTR: 533 gctx->reg_block = val; 534 break; 535 default: 536 ctx->ws[idx] = val; 537 } 538 break; 539 case ATOM_ARG_FB: 540 idx = U8(*ptr); 541 (*ptr)++; 542 if ((gctx->fb_base + (idx * 4)) > gctx->scratch_size_bytes) { 543 DRM_ERROR("ATOM: fb write beyond scratch region: %d vs. %d\n", 544 gctx->fb_base + (idx * 4), gctx->scratch_size_bytes); 545 } else 546 gctx->scratch[(gctx->fb_base / 4) + idx] = val; 547 DEBUG("FB[0x%02X]", idx); 548 break; 549 case ATOM_ARG_PLL: 550 idx = U8(*ptr); 551 (*ptr)++; 552 DEBUG("PLL[0x%02X]", idx); 553 gctx->card->pll_write(gctx->card, idx, val); 554 break; 555 case ATOM_ARG_MC: 556 idx = U8(*ptr); 557 (*ptr)++; 558 DEBUG("MC[0x%02X]", idx); 559 gctx->card->mc_write(gctx->card, idx, val); 560 return; 561 } 562 switch (align) { 563 case ATOM_SRC_DWORD: 564 DEBUG(".[31:0] <- 0x%08X\n", old_val); 565 break; 566 case ATOM_SRC_WORD0: 567 DEBUG(".[15:0] <- 0x%04X\n", old_val); 568 break; 569 case ATOM_SRC_WORD8: 570 DEBUG(".[23:8] <- 0x%04X\n", old_val); 571 break; 572 case ATOM_SRC_WORD16: 573 DEBUG(".[31:16] <- 0x%04X\n", old_val); 574 break; 575 case ATOM_SRC_BYTE0: 576 DEBUG(".[7:0] <- 0x%02X\n", old_val); 577 break; 578 case ATOM_SRC_BYTE8: 579 DEBUG(".[15:8] <- 0x%02X\n", old_val); 580 break; 581 case ATOM_SRC_BYTE16: 582 DEBUG(".[23:16] <- 0x%02X\n", old_val); 583 break; 584 case ATOM_SRC_BYTE24: 585 DEBUG(".[31:24] <- 0x%02X\n", old_val); 586 break; 587 } 588 } 589 590 static void atom_op_add(atom_exec_context *ctx, int *ptr, int arg) 591 { 592 uint8_t attr = U8((*ptr)++); 593 uint32_t dst, src, saved; 594 int dptr = *ptr; 595 SDEBUG(" dst: "); 596 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 597 SDEBUG(" src: "); 598 src = atom_get_src(ctx, attr, ptr); 599 dst += src; 600 SDEBUG(" dst: "); 601 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 602 } 603 604 static void atom_op_and(atom_exec_context *ctx, int *ptr, int arg) 605 { 606 uint8_t attr = U8((*ptr)++); 607 uint32_t dst, src, saved; 608 int dptr = *ptr; 609 SDEBUG(" dst: "); 610 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 611 SDEBUG(" src: "); 612 src = atom_get_src(ctx, attr, ptr); 613 dst &= src; 614 SDEBUG(" dst: "); 615 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 616 } 617 618 static void atom_op_beep(atom_exec_context *ctx, int *ptr, int arg) 619 { 620 printk("ATOM BIOS beeped!\n"); 621 } 622 623 static void atom_op_calltable(atom_exec_context *ctx, int *ptr, int arg) 624 { 625 int idx = U8((*ptr)++); 626 int r = 0; 627 628 if (idx < ATOM_TABLE_NAMES_CNT) 629 SDEBUG(" table: %d (%s)\n", idx, atom_table_names[idx]); 630 else 631 SDEBUG(" table: %d\n", idx); 632 if (U16(ctx->ctx->cmd_table + 4 + 2 * idx)) 633 r = amdgpu_atom_execute_table_locked(ctx->ctx, idx, ctx->ps + ctx->ps_shift); 634 if (r) { 635 ctx->abort = true; 636 } 637 } 638 639 static void atom_op_clear(atom_exec_context *ctx, int *ptr, int arg) 640 { 641 uint8_t attr = U8((*ptr)++); 642 uint32_t saved; 643 int dptr = *ptr; 644 attr &= 0x38; 645 attr |= atom_def_dst[attr >> 3] << 6; 646 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 647 SDEBUG(" dst: "); 648 atom_put_dst(ctx, arg, attr, &dptr, 0, saved); 649 } 650 651 static void atom_op_compare(atom_exec_context *ctx, int *ptr, int arg) 652 { 653 uint8_t attr = U8((*ptr)++); 654 uint32_t dst, src; 655 SDEBUG(" src1: "); 656 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 657 SDEBUG(" src2: "); 658 src = atom_get_src(ctx, attr, ptr); 659 ctx->ctx->cs_equal = (dst == src); 660 ctx->ctx->cs_above = (dst > src); 661 SDEBUG(" result: %s %s\n", ctx->ctx->cs_equal ? "EQ" : "NE", 662 ctx->ctx->cs_above ? "GT" : "LE"); 663 } 664 665 static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg) 666 { 667 unsigned count = U8((*ptr)++); 668 SDEBUG(" count: %d\n", count); 669 if (arg == ATOM_UNIT_MICROSEC) 670 udelay(count); 671 else if (!drm_can_sleep()) 672 mdelay(count); 673 else 674 msleep(count); 675 } 676 677 static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg) 678 { 679 uint8_t attr = U8((*ptr)++); 680 uint32_t dst, src; 681 SDEBUG(" src1: "); 682 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 683 SDEBUG(" src2: "); 684 src = atom_get_src(ctx, attr, ptr); 685 if (src != 0) { 686 ctx->ctx->divmul[0] = dst / src; 687 ctx->ctx->divmul[1] = dst % src; 688 } else { 689 ctx->ctx->divmul[0] = 0; 690 ctx->ctx->divmul[1] = 0; 691 } 692 } 693 694 static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg) 695 { 696 uint64_t val64; 697 uint8_t attr = U8((*ptr)++); 698 uint32_t dst, src; 699 SDEBUG(" src1: "); 700 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 701 SDEBUG(" src2: "); 702 src = atom_get_src(ctx, attr, ptr); 703 if (src != 0) { 704 val64 = dst; 705 val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32; 706 do_div(val64, src); 707 ctx->ctx->divmul[0] = lower_32_bits(val64); 708 ctx->ctx->divmul[1] = upper_32_bits(val64); 709 } else { 710 ctx->ctx->divmul[0] = 0; 711 ctx->ctx->divmul[1] = 0; 712 } 713 } 714 715 static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg) 716 { 717 /* functionally, a nop */ 718 } 719 720 static void atom_op_jump(atom_exec_context *ctx, int *ptr, int arg) 721 { 722 int execute = 0, target = U16(*ptr); 723 unsigned long cjiffies; 724 725 (*ptr) += 2; 726 switch (arg) { 727 case ATOM_COND_ABOVE: 728 execute = ctx->ctx->cs_above; 729 break; 730 case ATOM_COND_ABOVEOREQUAL: 731 execute = ctx->ctx->cs_above || ctx->ctx->cs_equal; 732 break; 733 case ATOM_COND_ALWAYS: 734 execute = 1; 735 break; 736 case ATOM_COND_BELOW: 737 execute = !(ctx->ctx->cs_above || ctx->ctx->cs_equal); 738 break; 739 case ATOM_COND_BELOWOREQUAL: 740 execute = !ctx->ctx->cs_above; 741 break; 742 case ATOM_COND_EQUAL: 743 execute = ctx->ctx->cs_equal; 744 break; 745 case ATOM_COND_NOTEQUAL: 746 execute = !ctx->ctx->cs_equal; 747 break; 748 } 749 if (arg != ATOM_COND_ALWAYS) 750 SDEBUG(" taken: %s\n", execute ? "yes" : "no"); 751 SDEBUG(" target: 0x%04X\n", target); 752 if (execute) { 753 if (ctx->last_jump == (ctx->start + target)) { 754 cjiffies = jiffies; 755 if (time_after(cjiffies, ctx->last_jump_jiffies)) { 756 cjiffies -= ctx->last_jump_jiffies; 757 if ((jiffies_to_msecs(cjiffies) > 5000)) { 758 DRM_ERROR("atombios stuck in loop for more than 5secs aborting\n"); 759 ctx->abort = true; 760 } 761 } else { 762 /* jiffies wrap around we will just wait a little longer */ 763 ctx->last_jump_jiffies = jiffies; 764 } 765 } else { 766 ctx->last_jump = ctx->start + target; 767 ctx->last_jump_jiffies = jiffies; 768 } 769 *ptr = ctx->start + target; 770 } 771 } 772 773 static void atom_op_mask(atom_exec_context *ctx, int *ptr, int arg) 774 { 775 uint8_t attr = U8((*ptr)++); 776 uint32_t dst, mask, src, saved; 777 int dptr = *ptr; 778 SDEBUG(" dst: "); 779 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 780 mask = atom_get_src_direct(ctx, ((attr >> 3) & 7), ptr); 781 SDEBUG(" mask: 0x%08x", mask); 782 SDEBUG(" src: "); 783 src = atom_get_src(ctx, attr, ptr); 784 dst &= mask; 785 dst |= src; 786 SDEBUG(" dst: "); 787 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 788 } 789 790 static void atom_op_move(atom_exec_context *ctx, int *ptr, int arg) 791 { 792 uint8_t attr = U8((*ptr)++); 793 uint32_t src, saved; 794 int dptr = *ptr; 795 if (((attr >> 3) & 7) != ATOM_SRC_DWORD) 796 atom_get_dst(ctx, arg, attr, ptr, &saved, 0); 797 else { 798 atom_skip_dst(ctx, arg, attr, ptr); 799 saved = 0xCDCDCDCD; 800 } 801 SDEBUG(" src: "); 802 src = atom_get_src(ctx, attr, ptr); 803 SDEBUG(" dst: "); 804 atom_put_dst(ctx, arg, attr, &dptr, src, saved); 805 } 806 807 static void atom_op_mul(atom_exec_context *ctx, int *ptr, int arg) 808 { 809 uint8_t attr = U8((*ptr)++); 810 uint32_t dst, src; 811 SDEBUG(" src1: "); 812 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 813 SDEBUG(" src2: "); 814 src = atom_get_src(ctx, attr, ptr); 815 ctx->ctx->divmul[0] = dst * src; 816 } 817 818 static void atom_op_mul32(atom_exec_context *ctx, int *ptr, int arg) 819 { 820 uint64_t val64; 821 uint8_t attr = U8((*ptr)++); 822 uint32_t dst, src; 823 SDEBUG(" src1: "); 824 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 825 SDEBUG(" src2: "); 826 src = atom_get_src(ctx, attr, ptr); 827 val64 = (uint64_t)dst * (uint64_t)src; 828 ctx->ctx->divmul[0] = lower_32_bits(val64); 829 ctx->ctx->divmul[1] = upper_32_bits(val64); 830 } 831 832 static void atom_op_nop(atom_exec_context *ctx, int *ptr, int arg) 833 { 834 /* nothing */ 835 } 836 837 static void atom_op_or(atom_exec_context *ctx, int *ptr, int arg) 838 { 839 uint8_t attr = U8((*ptr)++); 840 uint32_t dst, src, saved; 841 int dptr = *ptr; 842 SDEBUG(" dst: "); 843 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 844 SDEBUG(" src: "); 845 src = atom_get_src(ctx, attr, ptr); 846 dst |= src; 847 SDEBUG(" dst: "); 848 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 849 } 850 851 static void atom_op_postcard(atom_exec_context *ctx, int *ptr, int arg) 852 { 853 uint8_t val = U8((*ptr)++); 854 SDEBUG("POST card output: 0x%02X\n", val); 855 } 856 857 static void atom_op_repeat(atom_exec_context *ctx, int *ptr, int arg) 858 { 859 printk(KERN_INFO "unimplemented!\n"); 860 } 861 862 static void atom_op_restorereg(atom_exec_context *ctx, int *ptr, int arg) 863 { 864 printk(KERN_INFO "unimplemented!\n"); 865 } 866 867 static void atom_op_savereg(atom_exec_context *ctx, int *ptr, int arg) 868 { 869 printk(KERN_INFO "unimplemented!\n"); 870 } 871 872 static void atom_op_setdatablock(atom_exec_context *ctx, int *ptr, int arg) 873 { 874 int idx = U8(*ptr); 875 (*ptr)++; 876 SDEBUG(" block: %d\n", idx); 877 if (!idx) 878 ctx->ctx->data_block = 0; 879 else if (idx == 255) 880 ctx->ctx->data_block = ctx->start; 881 else 882 ctx->ctx->data_block = U16(ctx->ctx->data_table + 4 + 2 * idx); 883 SDEBUG(" base: 0x%04X\n", ctx->ctx->data_block); 884 } 885 886 static void atom_op_setfbbase(atom_exec_context *ctx, int *ptr, int arg) 887 { 888 uint8_t attr = U8((*ptr)++); 889 SDEBUG(" fb_base: "); 890 ctx->ctx->fb_base = atom_get_src(ctx, attr, ptr); 891 } 892 893 static void atom_op_setport(atom_exec_context *ctx, int *ptr, int arg) 894 { 895 int port; 896 switch (arg) { 897 case ATOM_PORT_ATI: 898 port = U16(*ptr); 899 if (port < ATOM_IO_NAMES_CNT) 900 SDEBUG(" port: %d (%s)\n", port, atom_io_names[port]); 901 else 902 SDEBUG(" port: %d\n", port); 903 if (!port) 904 ctx->ctx->io_mode = ATOM_IO_MM; 905 else 906 ctx->ctx->io_mode = ATOM_IO_IIO | port; 907 (*ptr) += 2; 908 break; 909 case ATOM_PORT_PCI: 910 ctx->ctx->io_mode = ATOM_IO_PCI; 911 (*ptr)++; 912 break; 913 case ATOM_PORT_SYSIO: 914 ctx->ctx->io_mode = ATOM_IO_SYSIO; 915 (*ptr)++; 916 break; 917 } 918 } 919 920 static void atom_op_setregblock(atom_exec_context *ctx, int *ptr, int arg) 921 { 922 ctx->ctx->reg_block = U16(*ptr); 923 (*ptr) += 2; 924 SDEBUG(" base: 0x%04X\n", ctx->ctx->reg_block); 925 } 926 927 static void atom_op_shift_left(atom_exec_context *ctx, int *ptr, int arg) 928 { 929 uint8_t attr = U8((*ptr)++), shift; 930 uint32_t saved, dst; 931 int dptr = *ptr; 932 attr &= 0x38; 933 attr |= atom_def_dst[attr >> 3] << 6; 934 SDEBUG(" dst: "); 935 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 936 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 937 SDEBUG(" shift: %d\n", shift); 938 dst <<= shift; 939 SDEBUG(" dst: "); 940 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 941 } 942 943 static void atom_op_shift_right(atom_exec_context *ctx, int *ptr, int arg) 944 { 945 uint8_t attr = U8((*ptr)++), shift; 946 uint32_t saved, dst; 947 int dptr = *ptr; 948 attr &= 0x38; 949 attr |= atom_def_dst[attr >> 3] << 6; 950 SDEBUG(" dst: "); 951 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 952 shift = atom_get_src_direct(ctx, ATOM_SRC_BYTE0, ptr); 953 SDEBUG(" shift: %d\n", shift); 954 dst >>= shift; 955 SDEBUG(" dst: "); 956 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 957 } 958 959 static void atom_op_shl(atom_exec_context *ctx, int *ptr, int arg) 960 { 961 uint8_t attr = U8((*ptr)++), shift; 962 uint32_t saved, dst; 963 int dptr = *ptr; 964 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 965 SDEBUG(" dst: "); 966 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 967 /* op needs to full dst value */ 968 dst = saved; 969 shift = atom_get_src(ctx, attr, ptr); 970 SDEBUG(" shift: %d\n", shift); 971 dst <<= shift; 972 dst &= atom_arg_mask[dst_align]; 973 dst >>= atom_arg_shift[dst_align]; 974 SDEBUG(" dst: "); 975 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 976 } 977 978 static void atom_op_shr(atom_exec_context *ctx, int *ptr, int arg) 979 { 980 uint8_t attr = U8((*ptr)++), shift; 981 uint32_t saved, dst; 982 int dptr = *ptr; 983 uint32_t dst_align = atom_dst_to_src[(attr >> 3) & 7][(attr >> 6) & 3]; 984 SDEBUG(" dst: "); 985 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 986 /* op needs to full dst value */ 987 dst = saved; 988 shift = atom_get_src(ctx, attr, ptr); 989 SDEBUG(" shift: %d\n", shift); 990 dst >>= shift; 991 dst &= atom_arg_mask[dst_align]; 992 dst >>= atom_arg_shift[dst_align]; 993 SDEBUG(" dst: "); 994 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 995 } 996 997 static void atom_op_sub(atom_exec_context *ctx, int *ptr, int arg) 998 { 999 uint8_t attr = U8((*ptr)++); 1000 uint32_t dst, src, saved; 1001 int dptr = *ptr; 1002 SDEBUG(" dst: "); 1003 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1004 SDEBUG(" src: "); 1005 src = atom_get_src(ctx, attr, ptr); 1006 dst -= src; 1007 SDEBUG(" dst: "); 1008 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1009 } 1010 1011 static void atom_op_switch(atom_exec_context *ctx, int *ptr, int arg) 1012 { 1013 uint8_t attr = U8((*ptr)++); 1014 uint32_t src, val, target; 1015 SDEBUG(" switch: "); 1016 src = atom_get_src(ctx, attr, ptr); 1017 while (U16(*ptr) != ATOM_CASE_END) 1018 if (U8(*ptr) == ATOM_CASE_MAGIC) { 1019 (*ptr)++; 1020 SDEBUG(" case: "); 1021 val = 1022 atom_get_src(ctx, (attr & 0x38) | ATOM_ARG_IMM, 1023 ptr); 1024 target = U16(*ptr); 1025 if (val == src) { 1026 SDEBUG(" target: %04X\n", target); 1027 *ptr = ctx->start + target; 1028 return; 1029 } 1030 (*ptr) += 2; 1031 } else { 1032 printk(KERN_INFO "Bad case.\n"); 1033 return; 1034 } 1035 (*ptr) += 2; 1036 } 1037 1038 static void atom_op_test(atom_exec_context *ctx, int *ptr, int arg) 1039 { 1040 uint8_t attr = U8((*ptr)++); 1041 uint32_t dst, src; 1042 SDEBUG(" src1: "); 1043 dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1); 1044 SDEBUG(" src2: "); 1045 src = atom_get_src(ctx, attr, ptr); 1046 ctx->ctx->cs_equal = ((dst & src) == 0); 1047 SDEBUG(" result: %s\n", ctx->ctx->cs_equal ? "EQ" : "NE"); 1048 } 1049 1050 static void atom_op_xor(atom_exec_context *ctx, int *ptr, int arg) 1051 { 1052 uint8_t attr = U8((*ptr)++); 1053 uint32_t dst, src, saved; 1054 int dptr = *ptr; 1055 SDEBUG(" dst: "); 1056 dst = atom_get_dst(ctx, arg, attr, ptr, &saved, 1); 1057 SDEBUG(" src: "); 1058 src = atom_get_src(ctx, attr, ptr); 1059 dst ^= src; 1060 SDEBUG(" dst: "); 1061 atom_put_dst(ctx, arg, attr, &dptr, dst, saved); 1062 } 1063 1064 static void atom_op_debug(atom_exec_context *ctx, int *ptr, int arg) 1065 { 1066 uint8_t val = U8((*ptr)++); 1067 SDEBUG("DEBUG output: 0x%02X\n", val); 1068 } 1069 1070 static void atom_op_processds(atom_exec_context *ctx, int *ptr, int arg) 1071 { 1072 uint16_t val = U16(*ptr); 1073 (*ptr) += val + 2; 1074 SDEBUG("PROCESSDS output: 0x%02X\n", val); 1075 } 1076 1077 static struct { 1078 void (*func) (atom_exec_context *, int *, int); 1079 int arg; 1080 } opcode_table[ATOM_OP_CNT] = { 1081 { 1082 NULL, 0}, { 1083 atom_op_move, ATOM_ARG_REG}, { 1084 atom_op_move, ATOM_ARG_PS}, { 1085 atom_op_move, ATOM_ARG_WS}, { 1086 atom_op_move, ATOM_ARG_FB}, { 1087 atom_op_move, ATOM_ARG_PLL}, { 1088 atom_op_move, ATOM_ARG_MC}, { 1089 atom_op_and, ATOM_ARG_REG}, { 1090 atom_op_and, ATOM_ARG_PS}, { 1091 atom_op_and, ATOM_ARG_WS}, { 1092 atom_op_and, ATOM_ARG_FB}, { 1093 atom_op_and, ATOM_ARG_PLL}, { 1094 atom_op_and, ATOM_ARG_MC}, { 1095 atom_op_or, ATOM_ARG_REG}, { 1096 atom_op_or, ATOM_ARG_PS}, { 1097 atom_op_or, ATOM_ARG_WS}, { 1098 atom_op_or, ATOM_ARG_FB}, { 1099 atom_op_or, ATOM_ARG_PLL}, { 1100 atom_op_or, ATOM_ARG_MC}, { 1101 atom_op_shift_left, ATOM_ARG_REG}, { 1102 atom_op_shift_left, ATOM_ARG_PS}, { 1103 atom_op_shift_left, ATOM_ARG_WS}, { 1104 atom_op_shift_left, ATOM_ARG_FB}, { 1105 atom_op_shift_left, ATOM_ARG_PLL}, { 1106 atom_op_shift_left, ATOM_ARG_MC}, { 1107 atom_op_shift_right, ATOM_ARG_REG}, { 1108 atom_op_shift_right, ATOM_ARG_PS}, { 1109 atom_op_shift_right, ATOM_ARG_WS}, { 1110 atom_op_shift_right, ATOM_ARG_FB}, { 1111 atom_op_shift_right, ATOM_ARG_PLL}, { 1112 atom_op_shift_right, ATOM_ARG_MC}, { 1113 atom_op_mul, ATOM_ARG_REG}, { 1114 atom_op_mul, ATOM_ARG_PS}, { 1115 atom_op_mul, ATOM_ARG_WS}, { 1116 atom_op_mul, ATOM_ARG_FB}, { 1117 atom_op_mul, ATOM_ARG_PLL}, { 1118 atom_op_mul, ATOM_ARG_MC}, { 1119 atom_op_div, ATOM_ARG_REG}, { 1120 atom_op_div, ATOM_ARG_PS}, { 1121 atom_op_div, ATOM_ARG_WS}, { 1122 atom_op_div, ATOM_ARG_FB}, { 1123 atom_op_div, ATOM_ARG_PLL}, { 1124 atom_op_div, ATOM_ARG_MC}, { 1125 atom_op_add, ATOM_ARG_REG}, { 1126 atom_op_add, ATOM_ARG_PS}, { 1127 atom_op_add, ATOM_ARG_WS}, { 1128 atom_op_add, ATOM_ARG_FB}, { 1129 atom_op_add, ATOM_ARG_PLL}, { 1130 atom_op_add, ATOM_ARG_MC}, { 1131 atom_op_sub, ATOM_ARG_REG}, { 1132 atom_op_sub, ATOM_ARG_PS}, { 1133 atom_op_sub, ATOM_ARG_WS}, { 1134 atom_op_sub, ATOM_ARG_FB}, { 1135 atom_op_sub, ATOM_ARG_PLL}, { 1136 atom_op_sub, ATOM_ARG_MC}, { 1137 atom_op_setport, ATOM_PORT_ATI}, { 1138 atom_op_setport, ATOM_PORT_PCI}, { 1139 atom_op_setport, ATOM_PORT_SYSIO}, { 1140 atom_op_setregblock, 0}, { 1141 atom_op_setfbbase, 0}, { 1142 atom_op_compare, ATOM_ARG_REG}, { 1143 atom_op_compare, ATOM_ARG_PS}, { 1144 atom_op_compare, ATOM_ARG_WS}, { 1145 atom_op_compare, ATOM_ARG_FB}, { 1146 atom_op_compare, ATOM_ARG_PLL}, { 1147 atom_op_compare, ATOM_ARG_MC}, { 1148 atom_op_switch, 0}, { 1149 atom_op_jump, ATOM_COND_ALWAYS}, { 1150 atom_op_jump, ATOM_COND_EQUAL}, { 1151 atom_op_jump, ATOM_COND_BELOW}, { 1152 atom_op_jump, ATOM_COND_ABOVE}, { 1153 atom_op_jump, ATOM_COND_BELOWOREQUAL}, { 1154 atom_op_jump, ATOM_COND_ABOVEOREQUAL}, { 1155 atom_op_jump, ATOM_COND_NOTEQUAL}, { 1156 atom_op_test, ATOM_ARG_REG}, { 1157 atom_op_test, ATOM_ARG_PS}, { 1158 atom_op_test, ATOM_ARG_WS}, { 1159 atom_op_test, ATOM_ARG_FB}, { 1160 atom_op_test, ATOM_ARG_PLL}, { 1161 atom_op_test, ATOM_ARG_MC}, { 1162 atom_op_delay, ATOM_UNIT_MILLISEC}, { 1163 atom_op_delay, ATOM_UNIT_MICROSEC}, { 1164 atom_op_calltable, 0}, { 1165 atom_op_repeat, 0}, { 1166 atom_op_clear, ATOM_ARG_REG}, { 1167 atom_op_clear, ATOM_ARG_PS}, { 1168 atom_op_clear, ATOM_ARG_WS}, { 1169 atom_op_clear, ATOM_ARG_FB}, { 1170 atom_op_clear, ATOM_ARG_PLL}, { 1171 atom_op_clear, ATOM_ARG_MC}, { 1172 atom_op_nop, 0}, { 1173 atom_op_eot, 0}, { 1174 atom_op_mask, ATOM_ARG_REG}, { 1175 atom_op_mask, ATOM_ARG_PS}, { 1176 atom_op_mask, ATOM_ARG_WS}, { 1177 atom_op_mask, ATOM_ARG_FB}, { 1178 atom_op_mask, ATOM_ARG_PLL}, { 1179 atom_op_mask, ATOM_ARG_MC}, { 1180 atom_op_postcard, 0}, { 1181 atom_op_beep, 0}, { 1182 atom_op_savereg, 0}, { 1183 atom_op_restorereg, 0}, { 1184 atom_op_setdatablock, 0}, { 1185 atom_op_xor, ATOM_ARG_REG}, { 1186 atom_op_xor, ATOM_ARG_PS}, { 1187 atom_op_xor, ATOM_ARG_WS}, { 1188 atom_op_xor, ATOM_ARG_FB}, { 1189 atom_op_xor, ATOM_ARG_PLL}, { 1190 atom_op_xor, ATOM_ARG_MC}, { 1191 atom_op_shl, ATOM_ARG_REG}, { 1192 atom_op_shl, ATOM_ARG_PS}, { 1193 atom_op_shl, ATOM_ARG_WS}, { 1194 atom_op_shl, ATOM_ARG_FB}, { 1195 atom_op_shl, ATOM_ARG_PLL}, { 1196 atom_op_shl, ATOM_ARG_MC}, { 1197 atom_op_shr, ATOM_ARG_REG}, { 1198 atom_op_shr, ATOM_ARG_PS}, { 1199 atom_op_shr, ATOM_ARG_WS}, { 1200 atom_op_shr, ATOM_ARG_FB}, { 1201 atom_op_shr, ATOM_ARG_PLL}, { 1202 atom_op_shr, ATOM_ARG_MC}, { 1203 atom_op_debug, 0}, { 1204 atom_op_processds, 0}, { 1205 atom_op_mul32, ATOM_ARG_PS}, { 1206 atom_op_mul32, ATOM_ARG_WS}, { 1207 atom_op_div32, ATOM_ARG_PS}, { 1208 atom_op_div32, ATOM_ARG_WS}, 1209 }; 1210 1211 static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params) 1212 { 1213 int base = CU16(ctx->cmd_table + 4 + 2 * index); 1214 int len, ws, ps, ptr; 1215 unsigned char op; 1216 atom_exec_context ectx; 1217 int ret = 0; 1218 1219 if (!base) 1220 return -EINVAL; 1221 1222 len = CU16(base + ATOM_CT_SIZE_PTR); 1223 ws = CU8(base + ATOM_CT_WS_PTR); 1224 ps = CU8(base + ATOM_CT_PS_PTR) & ATOM_CT_PS_MASK; 1225 ptr = base + ATOM_CT_CODE_PTR; 1226 1227 SDEBUG(">> execute %04X (len %d, WS %d, PS %d)\n", base, len, ws, ps); 1228 1229 ectx.ctx = ctx; 1230 ectx.ps_shift = ps / 4; 1231 ectx.start = base; 1232 ectx.ps = params; 1233 ectx.abort = false; 1234 ectx.last_jump = 0; 1235 if (ws) 1236 ectx.ws = kzalloc(4 * ws, GFP_KERNEL); 1237 else 1238 ectx.ws = NULL; 1239 1240 debug_depth++; 1241 while (1) { 1242 op = CU8(ptr++); 1243 if (op < ATOM_OP_NAMES_CNT) 1244 SDEBUG("%s @ 0x%04X\n", atom_op_names[op], ptr - 1); 1245 else 1246 SDEBUG("[%d] @ 0x%04X\n", op, ptr - 1); 1247 if (ectx.abort) { 1248 DRM_ERROR("atombios stuck executing %04X (len %d, WS %d, PS %d) @ 0x%04X\n", 1249 base, len, ws, ps, ptr - 1); 1250 ret = -EINVAL; 1251 goto free; 1252 } 1253 1254 if (op < ATOM_OP_CNT && op > 0) 1255 opcode_table[op].func(&ectx, &ptr, 1256 opcode_table[op].arg); 1257 else 1258 break; 1259 1260 if (op == ATOM_OP_EOT) 1261 break; 1262 } 1263 debug_depth--; 1264 SDEBUG("<<\n"); 1265 1266 free: 1267 if (ws) 1268 kfree(ectx.ws); 1269 return ret; 1270 } 1271 1272 int amdgpu_atom_execute_table(struct atom_context *ctx, int index, uint32_t * params) 1273 { 1274 int r; 1275 1276 mutex_lock(&ctx->mutex); 1277 /* reset data block */ 1278 ctx->data_block = 0; 1279 /* reset reg block */ 1280 ctx->reg_block = 0; 1281 /* reset fb window */ 1282 ctx->fb_base = 0; 1283 /* reset io mode */ 1284 ctx->io_mode = ATOM_IO_MM; 1285 /* reset divmul */ 1286 ctx->divmul[0] = 0; 1287 ctx->divmul[1] = 0; 1288 r = amdgpu_atom_execute_table_locked(ctx, index, params); 1289 mutex_unlock(&ctx->mutex); 1290 return r; 1291 } 1292 1293 static int atom_iio_len[] = { 1, 2, 3, 3, 3, 3, 4, 4, 4, 3 }; 1294 1295 static void atom_index_iio(struct atom_context *ctx, int base) 1296 { 1297 ctx->iio = kzalloc(2 * 256, GFP_KERNEL); 1298 if (!ctx->iio) 1299 return; 1300 while (CU8(base) == ATOM_IIO_START) { 1301 ctx->iio[CU8(base + 1)] = base + 2; 1302 base += 2; 1303 while (CU8(base) != ATOM_IIO_END) 1304 base += atom_iio_len[CU8(base)]; 1305 base += 3; 1306 } 1307 } 1308 1309 struct atom_context *amdgpu_atom_parse(struct card_info *card, void *bios) 1310 { 1311 int base; 1312 struct atom_context *ctx = 1313 kzalloc(sizeof(struct atom_context), GFP_KERNEL); 1314 char *str; 1315 char name[512]; 1316 int i; 1317 1318 if (!ctx) 1319 return NULL; 1320 1321 ctx->card = card; 1322 ctx->bios = bios; 1323 1324 if (CU16(0) != ATOM_BIOS_MAGIC) { 1325 printk(KERN_INFO "Invalid BIOS magic.\n"); 1326 kfree(ctx); 1327 return NULL; 1328 } 1329 if (strncmp 1330 (CSTR(ATOM_ATI_MAGIC_PTR), ATOM_ATI_MAGIC, 1331 strlen(ATOM_ATI_MAGIC))) { 1332 printk(KERN_INFO "Invalid ATI magic.\n"); 1333 kfree(ctx); 1334 return NULL; 1335 } 1336 1337 base = CU16(ATOM_ROM_TABLE_PTR); 1338 if (strncmp 1339 (CSTR(base + ATOM_ROM_MAGIC_PTR), ATOM_ROM_MAGIC, 1340 strlen(ATOM_ROM_MAGIC))) { 1341 printk(KERN_INFO "Invalid ATOM magic.\n"); 1342 kfree(ctx); 1343 return NULL; 1344 } 1345 1346 ctx->cmd_table = CU16(base + ATOM_ROM_CMD_PTR); 1347 ctx->data_table = CU16(base + ATOM_ROM_DATA_PTR); 1348 atom_index_iio(ctx, CU16(ctx->data_table + ATOM_DATA_IIO_PTR) + 4); 1349 if (!ctx->iio) { 1350 amdgpu_atom_destroy(ctx); 1351 return NULL; 1352 } 1353 1354 str = CSTR(CU16(base + ATOM_ROM_MSG_PTR)); 1355 while (*str && ((*str == '\n') || (*str == '\r'))) 1356 str++; 1357 /* name string isn't always 0 terminated */ 1358 for (i = 0; i < 511; i++) { 1359 name[i] = str[i]; 1360 if (name[i] < '.' || name[i] > 'z') { 1361 name[i] = 0; 1362 break; 1363 } 1364 } 1365 printk(KERN_INFO "ATOM BIOS: %s\n", name); 1366 1367 return ctx; 1368 } 1369 1370 int amdgpu_atom_asic_init(struct atom_context *ctx) 1371 { 1372 int hwi = CU16(ctx->data_table + ATOM_DATA_FWI_PTR); 1373 uint32_t ps[16]; 1374 int ret; 1375 1376 memset(ps, 0, 64); 1377 1378 ps[0] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFSCLK_PTR)); 1379 ps[1] = cpu_to_le32(CU32(hwi + ATOM_FWI_DEFMCLK_PTR)); 1380 if (!ps[0] || !ps[1]) 1381 return 1; 1382 1383 if (!CU16(ctx->cmd_table + 4 + 2 * ATOM_CMD_INIT)) 1384 return 1; 1385 ret = amdgpu_atom_execute_table(ctx, ATOM_CMD_INIT, ps); 1386 if (ret) 1387 return ret; 1388 1389 memset(ps, 0, 64); 1390 1391 return ret; 1392 } 1393 1394 void amdgpu_atom_destroy(struct atom_context *ctx) 1395 { 1396 kfree(ctx->iio); 1397 kfree(ctx); 1398 } 1399 1400 bool amdgpu_atom_parse_data_header(struct atom_context *ctx, int index, 1401 uint16_t * size, uint8_t * frev, uint8_t * crev, 1402 uint16_t * data_start) 1403 { 1404 int offset = index * 2 + 4; 1405 int idx = CU16(ctx->data_table + offset); 1406 u16 *mdt = (u16 *)(ctx->bios + ctx->data_table + 4); 1407 1408 if (!mdt[index]) 1409 return false; 1410 1411 if (size) 1412 *size = CU16(idx); 1413 if (frev) 1414 *frev = CU8(idx + 2); 1415 if (crev) 1416 *crev = CU8(idx + 3); 1417 *data_start = idx; 1418 return true; 1419 } 1420 1421 bool amdgpu_atom_parse_cmd_header(struct atom_context *ctx, int index, uint8_t * frev, 1422 uint8_t * crev) 1423 { 1424 int offset = index * 2 + 4; 1425 int idx = CU16(ctx->cmd_table + offset); 1426 u16 *mct = (u16 *)(ctx->bios + ctx->cmd_table + 4); 1427 1428 if (!mct[index]) 1429 return false; 1430 1431 if (frev) 1432 *frev = CU8(idx + 2); 1433 if (crev) 1434 *crev = CU8(idx + 3); 1435 return true; 1436 } 1437 1438 int amdgpu_atom_allocate_fb_scratch(struct atom_context *ctx) 1439 { 1440 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); 1441 uint16_t data_offset; 1442 int usage_bytes = 0; 1443 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; 1444 1445 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 1446 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1447 1448 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1449 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), 1450 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); 1451 1452 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; 1453 } 1454 ctx->scratch_size_bytes = 0; 1455 if (usage_bytes == 0) 1456 usage_bytes = 20 * 1024; 1457 /* allocate some scratch memory */ 1458 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 1459 if (!ctx->scratch) 1460 return -ENOMEM; 1461 ctx->scratch_size_bytes = usage_bytes; 1462 return 0; 1463 } 1464
Indexes created Fri Sep 26 08:10:20 GMT 2025