amdgpu_atombios.c revision 1.1
1 /* $NetBSD: amdgpu_atombios.c,v 1.1 2018/08/27 01:34:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atombios.c,v 1.1 2018/08/27 01:34:43 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "amdgpu_atombios.h" 35 #include "amdgpu_i2c.h" 36 37 #include "atom.h" 38 #include "atom-bits.h" 39 #include "atombios_encoders.h" 40 #include "bif/bif_4_1_d.h" 41 42 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, 43 ATOM_GPIO_I2C_ASSIGMENT *gpio, 44 u8 index) 45 { 46 47 } 48 49 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 50 { 51 struct amdgpu_i2c_bus_rec i2c; 52 53 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 54 55 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); 56 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); 57 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); 58 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); 59 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); 60 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); 61 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); 62 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); 63 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 64 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 65 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 66 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 67 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 68 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 69 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 70 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 71 72 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 73 i2c.hw_capable = true; 74 else 75 i2c.hw_capable = false; 76 77 if (gpio->sucI2cId.ucAccess == 0xa0) 78 i2c.mm_i2c = true; 79 else 80 i2c.mm_i2c = false; 81 82 i2c.i2c_id = gpio->sucI2cId.ucAccess; 83 84 if (i2c.mask_clk_reg) 85 i2c.valid = true; 86 else 87 i2c.valid = false; 88 89 return i2c; 90 } 91 92 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, 93 uint8_t id) 94 { 95 struct atom_context *ctx = adev->mode_info.atom_context; 96 ATOM_GPIO_I2C_ASSIGMENT *gpio; 97 struct amdgpu_i2c_bus_rec i2c; 98 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 99 struct _ATOM_GPIO_I2C_INFO *i2c_info; 100 uint16_t data_offset, size; 101 int i, num_indices; 102 103 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 104 i2c.valid = false; 105 106 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 107 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 108 109 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 110 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 111 112 gpio = &i2c_info->asGPIO_Info[0]; 113 for (i = 0; i < num_indices; i++) { 114 115 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 116 117 if (gpio->sucI2cId.ucAccess == id) { 118 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 119 break; 120 } 121 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 122 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 123 } 124 } 125 126 return i2c; 127 } 128 129 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) 130 { 131 struct atom_context *ctx = adev->mode_info.atom_context; 132 ATOM_GPIO_I2C_ASSIGMENT *gpio; 133 struct amdgpu_i2c_bus_rec i2c; 134 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 135 struct _ATOM_GPIO_I2C_INFO *i2c_info; 136 uint16_t data_offset, size; 137 int i, num_indices; 138 char stmp[32]; 139 140 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 141 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 142 143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 144 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 145 146 gpio = &i2c_info->asGPIO_Info[0]; 147 for (i = 0; i < num_indices; i++) { 148 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 149 150 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 151 152 if (i2c.valid) { 153 sprintf(stmp, "0x%x", i2c.i2c_id); 154 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); 155 } 156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 158 } 159 } 160 } 161 162 struct amdgpu_gpio_rec 163 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, 164 u8 id) 165 { 166 struct atom_context *ctx = adev->mode_info.atom_context; 167 struct amdgpu_gpio_rec gpio; 168 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 169 struct _ATOM_GPIO_PIN_LUT *gpio_info; 170 ATOM_GPIO_PIN_ASSIGNMENT *pin; 171 u16 data_offset, size; 172 int i, num_indices; 173 174 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); 175 gpio.valid = false; 176 177 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 178 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 179 180 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 181 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 182 183 pin = gpio_info->asGPIO_Pin; 184 for (i = 0; i < num_indices; i++) { 185 if (id == pin->ucGPIO_ID) { 186 gpio.id = pin->ucGPIO_ID; 187 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); 188 gpio.shift = pin->ucGpioPinBitShift; 189 gpio.mask = (1 << pin->ucGpioPinBitShift); 190 gpio.valid = true; 191 break; 192 } 193 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 194 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 195 } 196 } 197 198 return gpio; 199 } 200 201 static struct amdgpu_hpd 202 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, 203 struct amdgpu_gpio_rec *gpio) 204 { 205 struct amdgpu_hpd hpd; 206 u32 reg; 207 208 memset(&hpd, 0, sizeof(struct amdgpu_hpd)); 209 210 reg = amdgpu_display_hpd_get_gpio_reg(adev); 211 212 hpd.gpio = *gpio; 213 if (gpio->reg == reg) { 214 switch(gpio->mask) { 215 case (1 << 0): 216 hpd.hpd = AMDGPU_HPD_1; 217 break; 218 case (1 << 8): 219 hpd.hpd = AMDGPU_HPD_2; 220 break; 221 case (1 << 16): 222 hpd.hpd = AMDGPU_HPD_3; 223 break; 224 case (1 << 24): 225 hpd.hpd = AMDGPU_HPD_4; 226 break; 227 case (1 << 26): 228 hpd.hpd = AMDGPU_HPD_5; 229 break; 230 case (1 << 28): 231 hpd.hpd = AMDGPU_HPD_6; 232 break; 233 default: 234 hpd.hpd = AMDGPU_HPD_NONE; 235 break; 236 } 237 } else 238 hpd.hpd = AMDGPU_HPD_NONE; 239 return hpd; 240 } 241 242 static bool amdgpu_atombios_apply_quirks(struct amdgpu_device *adev, 243 uint32_t supported_device, 244 int *connector_type, 245 struct amdgpu_i2c_bus_rec *i2c_bus, 246 uint16_t *line_mux, 247 struct amdgpu_hpd *hpd) 248 { 249 return true; 250 } 251 252 static const int object_connector_convert[] = { 253 DRM_MODE_CONNECTOR_Unknown, 254 DRM_MODE_CONNECTOR_DVII, 255 DRM_MODE_CONNECTOR_DVII, 256 DRM_MODE_CONNECTOR_DVID, 257 DRM_MODE_CONNECTOR_DVID, 258 DRM_MODE_CONNECTOR_VGA, 259 DRM_MODE_CONNECTOR_Composite, 260 DRM_MODE_CONNECTOR_SVIDEO, 261 DRM_MODE_CONNECTOR_Unknown, 262 DRM_MODE_CONNECTOR_Unknown, 263 DRM_MODE_CONNECTOR_9PinDIN, 264 DRM_MODE_CONNECTOR_Unknown, 265 DRM_MODE_CONNECTOR_HDMIA, 266 DRM_MODE_CONNECTOR_HDMIB, 267 DRM_MODE_CONNECTOR_LVDS, 268 DRM_MODE_CONNECTOR_9PinDIN, 269 DRM_MODE_CONNECTOR_Unknown, 270 DRM_MODE_CONNECTOR_Unknown, 271 DRM_MODE_CONNECTOR_Unknown, 272 DRM_MODE_CONNECTOR_DisplayPort, 273 DRM_MODE_CONNECTOR_eDP, 274 DRM_MODE_CONNECTOR_Unknown 275 }; 276 277 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) 278 { 279 struct amdgpu_mode_info *mode_info = &adev->mode_info; 280 struct atom_context *ctx = mode_info->atom_context; 281 int index = GetIndexIntoMasterTable(DATA, Object_Header); 282 u16 size, data_offset; 283 u8 frev, crev; 284 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 285 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 286 ATOM_OBJECT_TABLE *router_obj; 287 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 288 ATOM_OBJECT_HEADER *obj_header; 289 int i, j, k, path_size, device_support; 290 int connector_type; 291 u16 conn_id, connector_object_id; 292 struct amdgpu_i2c_bus_rec ddc_bus; 293 struct amdgpu_router router; 294 struct amdgpu_gpio_rec gpio; 295 struct amdgpu_hpd hpd; 296 297 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 298 return false; 299 300 if (crev < 2) 301 return false; 302 303 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 304 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 305 (ctx->bios + data_offset + 306 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 307 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 308 (ctx->bios + data_offset + 309 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 310 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 311 (ctx->bios + data_offset + 312 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 313 router_obj = (ATOM_OBJECT_TABLE *) 314 (ctx->bios + data_offset + 315 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 316 device_support = le16_to_cpu(obj_header->usDeviceSupport); 317 318 path_size = 0; 319 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 320 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 321 ATOM_DISPLAY_OBJECT_PATH *path; 322 addr += path_size; 323 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 324 path_size += le16_to_cpu(path->usSize); 325 326 if (device_support & le16_to_cpu(path->usDeviceTag)) { 327 uint8_t con_obj_id, con_obj_num, con_obj_type; 328 329 con_obj_id = 330 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 331 >> OBJECT_ID_SHIFT; 332 con_obj_num = 333 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) 334 >> ENUM_ID_SHIFT; 335 con_obj_type = 336 (le16_to_cpu(path->usConnObjectId) & 337 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 338 339 /* Skip TV/CV support */ 340 if ((le16_to_cpu(path->usDeviceTag) == 341 ATOM_DEVICE_TV1_SUPPORT) || 342 (le16_to_cpu(path->usDeviceTag) == 343 ATOM_DEVICE_CV_SUPPORT)) 344 continue; 345 346 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { 347 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", 348 con_obj_id, le16_to_cpu(path->usDeviceTag)); 349 continue; 350 } 351 352 connector_type = 353 object_connector_convert[con_obj_id]; 354 connector_object_id = con_obj_id; 355 356 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 357 continue; 358 359 router.ddc_valid = false; 360 router.cd_valid = false; 361 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 362 uint8_t grph_obj_id, grph_obj_num, grph_obj_type; 363 364 grph_obj_id = 365 (le16_to_cpu(path->usGraphicObjIds[j]) & 366 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 367 grph_obj_num = 368 (le16_to_cpu(path->usGraphicObjIds[j]) & 369 ENUM_ID_MASK) >> ENUM_ID_SHIFT; 370 grph_obj_type = 371 (le16_to_cpu(path->usGraphicObjIds[j]) & 372 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 373 374 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 375 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 376 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 377 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 378 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 379 (ctx->bios + data_offset + 380 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 381 ATOM_ENCODER_CAP_RECORD *cap_record; 382 u16 caps = 0; 383 384 while (record->ucRecordSize > 0 && 385 record->ucRecordType > 0 && 386 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 387 switch (record->ucRecordType) { 388 case ATOM_ENCODER_CAP_RECORD_TYPE: 389 cap_record =(ATOM_ENCODER_CAP_RECORD *) 390 record; 391 caps = le16_to_cpu(cap_record->usEncoderCap); 392 break; 393 } 394 record = (ATOM_COMMON_RECORD_HEADER *) 395 ((char *)record + record->ucRecordSize); 396 } 397 amdgpu_display_add_encoder(adev, encoder_obj, 398 le16_to_cpu(path->usDeviceTag), 399 caps); 400 } 401 } 402 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 403 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 404 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 405 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 406 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 407 (ctx->bios + data_offset + 408 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 409 ATOM_I2C_RECORD *i2c_record; 410 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 411 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 412 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 413 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 414 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 415 (ctx->bios + data_offset + 416 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 417 u8 *num_dst_objs = (u8 *) 418 ((u8 *)router_src_dst_table + 1 + 419 (router_src_dst_table->ucNumberOfSrc * 2)); 420 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 421 int enum_id; 422 423 router.router_id = router_obj_id; 424 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 425 if (le16_to_cpu(path->usConnObjectId) == 426 le16_to_cpu(dst_objs[enum_id])) 427 break; 428 } 429 430 while (record->ucRecordSize > 0 && 431 record->ucRecordType > 0 && 432 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 433 switch (record->ucRecordType) { 434 case ATOM_I2C_RECORD_TYPE: 435 i2c_record = 436 (ATOM_I2C_RECORD *) 437 record; 438 i2c_config = 439 (ATOM_I2C_ID_CONFIG_ACCESS *) 440 &i2c_record->sucI2cId; 441 router.i2c_info = 442 amdgpu_atombios_lookup_i2c_gpio(adev, 443 i2c_config-> 444 ucAccess); 445 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 446 break; 447 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 448 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 449 record; 450 router.ddc_valid = true; 451 router.ddc_mux_type = ddc_path->ucMuxType; 452 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 453 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 454 break; 455 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 456 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 457 record; 458 router.cd_valid = true; 459 router.cd_mux_type = cd_path->ucMuxType; 460 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 461 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 462 break; 463 } 464 record = (ATOM_COMMON_RECORD_HEADER *) 465 ((char *)record + record->ucRecordSize); 466 } 467 } 468 } 469 } 470 } 471 472 /* look up gpio for ddc, hpd */ 473 ddc_bus.valid = false; 474 hpd.hpd = AMDGPU_HPD_NONE; 475 if ((le16_to_cpu(path->usDeviceTag) & 476 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 477 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 478 if (le16_to_cpu(path->usConnObjectId) == 479 le16_to_cpu(con_obj->asObjects[j]. 480 usObjectID)) { 481 ATOM_COMMON_RECORD_HEADER 482 *record = 483 (ATOM_COMMON_RECORD_HEADER 484 *) 485 (ctx->bios + data_offset + 486 le16_to_cpu(con_obj-> 487 asObjects[j]. 488 usRecordOffset)); 489 ATOM_I2C_RECORD *i2c_record; 490 ATOM_HPD_INT_RECORD *hpd_record; 491 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 492 493 while (record->ucRecordSize > 0 && 494 record->ucRecordType > 0 && 495 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 496 switch (record->ucRecordType) { 497 case ATOM_I2C_RECORD_TYPE: 498 i2c_record = 499 (ATOM_I2C_RECORD *) 500 record; 501 i2c_config = 502 (ATOM_I2C_ID_CONFIG_ACCESS *) 503 &i2c_record->sucI2cId; 504 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, 505 i2c_config-> 506 ucAccess); 507 break; 508 case ATOM_HPD_INT_RECORD_TYPE: 509 hpd_record = 510 (ATOM_HPD_INT_RECORD *) 511 record; 512 gpio = amdgpu_atombios_lookup_gpio(adev, 513 hpd_record->ucHPDIntGPIOID); 514 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); 515 hpd.plugged_state = hpd_record->ucPlugged_PinState; 516 break; 517 } 518 record = 519 (ATOM_COMMON_RECORD_HEADER 520 *) ((char *)record 521 + 522 record-> 523 ucRecordSize); 524 } 525 break; 526 } 527 } 528 } 529 530 /* needed for aux chan transactions */ 531 ddc_bus.hpd = hpd.hpd; 532 533 conn_id = le16_to_cpu(path->usConnObjectId); 534 535 if (!amdgpu_atombios_apply_quirks 536 (adev, le16_to_cpu(path->usDeviceTag), &connector_type, 537 &ddc_bus, &conn_id, &hpd)) 538 continue; 539 540 amdgpu_display_add_connector(adev, 541 conn_id, 542 le16_to_cpu(path->usDeviceTag), 543 connector_type, &ddc_bus, 544 connector_object_id, 545 &hpd, 546 &router); 547 548 } 549 } 550 551 amdgpu_link_encoder_connector(adev->ddev); 552 553 return true; 554 } 555 556 union firmware_info { 557 ATOM_FIRMWARE_INFO info; 558 ATOM_FIRMWARE_INFO_V1_2 info_12; 559 ATOM_FIRMWARE_INFO_V1_3 info_13; 560 ATOM_FIRMWARE_INFO_V1_4 info_14; 561 ATOM_FIRMWARE_INFO_V2_1 info_21; 562 ATOM_FIRMWARE_INFO_V2_2 info_22; 563 }; 564 565 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 566 { 567 struct amdgpu_mode_info *mode_info = &adev->mode_info; 568 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 569 uint8_t frev, crev; 570 uint16_t data_offset; 571 int ret = -EINVAL; 572 573 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 574 &frev, &crev, &data_offset)) { 575 int i; 576 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; 577 struct amdgpu_pll *spll = &adev->clock.spll; 578 struct amdgpu_pll *mpll = &adev->clock.mpll; 579 union firmware_info *firmware_info = 580 (union firmware_info *)(mode_info->atom_context->bios + 581 data_offset); 582 /* pixel clocks */ 583 ppll->reference_freq = 584 le16_to_cpu(firmware_info->info.usReferenceClock); 585 ppll->reference_div = 0; 586 587 ppll->pll_out_min = 588 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 589 ppll->pll_out_max = 590 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 591 592 ppll->lcd_pll_out_min = 593 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 594 if (ppll->lcd_pll_out_min == 0) 595 ppll->lcd_pll_out_min = ppll->pll_out_min; 596 ppll->lcd_pll_out_max = 597 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 598 if (ppll->lcd_pll_out_max == 0) 599 ppll->lcd_pll_out_max = ppll->pll_out_max; 600 601 if (ppll->pll_out_min == 0) 602 ppll->pll_out_min = 64800; 603 604 ppll->pll_in_min = 605 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 606 ppll->pll_in_max = 607 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 608 609 ppll->min_post_div = 2; 610 ppll->max_post_div = 0x7f; 611 ppll->min_frac_feedback_div = 0; 612 ppll->max_frac_feedback_div = 9; 613 ppll->min_ref_div = 2; 614 ppll->max_ref_div = 0x3ff; 615 ppll->min_feedback_div = 4; 616 ppll->max_feedback_div = 0xfff; 617 ppll->best_vco = 0; 618 619 for (i = 1; i < AMDGPU_MAX_PPLL; i++) 620 adev->clock.ppll[i] = *ppll; 621 622 /* system clock */ 623 spll->reference_freq = 624 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 625 spll->reference_div = 0; 626 627 spll->pll_out_min = 628 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 629 spll->pll_out_max = 630 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 631 632 /* ??? */ 633 if (spll->pll_out_min == 0) 634 spll->pll_out_min = 64800; 635 636 spll->pll_in_min = 637 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 638 spll->pll_in_max = 639 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 640 641 spll->min_post_div = 1; 642 spll->max_post_div = 1; 643 spll->min_ref_div = 2; 644 spll->max_ref_div = 0xff; 645 spll->min_feedback_div = 4; 646 spll->max_feedback_div = 0xff; 647 spll->best_vco = 0; 648 649 /* memory clock */ 650 mpll->reference_freq = 651 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 652 mpll->reference_div = 0; 653 654 mpll->pll_out_min = 655 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 656 mpll->pll_out_max = 657 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 658 659 /* ??? */ 660 if (mpll->pll_out_min == 0) 661 mpll->pll_out_min = 64800; 662 663 mpll->pll_in_min = 664 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 665 mpll->pll_in_max = 666 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 667 668 adev->clock.default_sclk = 669 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 670 adev->clock.default_mclk = 671 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 672 673 mpll->min_post_div = 1; 674 mpll->max_post_div = 1; 675 mpll->min_ref_div = 2; 676 mpll->max_ref_div = 0xff; 677 mpll->min_feedback_div = 4; 678 mpll->max_feedback_div = 0xff; 679 mpll->best_vco = 0; 680 681 /* disp clock */ 682 adev->clock.default_dispclk = 683 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 684 /* set a reasonable default for DP */ 685 if (adev->clock.default_dispclk < 53900) { 686 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n", 687 adev->clock.default_dispclk / 100); 688 adev->clock.default_dispclk = 60000; 689 } else if (adev->clock.default_dispclk <= 60000) { 690 DRM_INFO("Changing default dispclk from %dMhz to 625Mhz\n", 691 adev->clock.default_dispclk / 100); 692 adev->clock.default_dispclk = 62500; 693 } 694 adev->clock.dp_extclk = 695 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 696 adev->clock.current_dispclk = adev->clock.default_dispclk; 697 698 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 699 if (adev->clock.max_pixel_clock == 0) 700 adev->clock.max_pixel_clock = 40000; 701 702 /* not technically a clock, but... */ 703 adev->mode_info.firmware_flags = 704 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 705 706 ret = 0; 707 } 708 709 adev->pm.current_sclk = adev->clock.default_sclk; 710 adev->pm.current_mclk = adev->clock.default_mclk; 711 712 return ret; 713 } 714 715 union igp_info { 716 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 717 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 718 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 719 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 720 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 721 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; 722 }; 723 724 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, 725 struct amdgpu_atom_ss *ss, 726 int id) 727 { 728 struct amdgpu_mode_info *mode_info = &adev->mode_info; 729 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 730 u16 data_offset, size; 731 union igp_info *igp_info; 732 u8 frev, crev; 733 u16 percentage = 0, rate = 0; 734 735 /* get any igp specific overrides */ 736 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 737 &frev, &crev, &data_offset)) { 738 igp_info = (union igp_info *) 739 (mode_info->atom_context->bios + data_offset); 740 switch (crev) { 741 case 6: 742 switch (id) { 743 case ASIC_INTERNAL_SS_ON_TMDS: 744 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 745 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 746 break; 747 case ASIC_INTERNAL_SS_ON_HDMI: 748 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 749 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 750 break; 751 case ASIC_INTERNAL_SS_ON_LVDS: 752 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 753 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 754 break; 755 } 756 break; 757 case 7: 758 switch (id) { 759 case ASIC_INTERNAL_SS_ON_TMDS: 760 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 761 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 762 break; 763 case ASIC_INTERNAL_SS_ON_HDMI: 764 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 765 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 766 break; 767 case ASIC_INTERNAL_SS_ON_LVDS: 768 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 769 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 770 break; 771 } 772 break; 773 case 8: 774 switch (id) { 775 case ASIC_INTERNAL_SS_ON_TMDS: 776 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 777 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 778 break; 779 case ASIC_INTERNAL_SS_ON_HDMI: 780 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 781 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 782 break; 783 case ASIC_INTERNAL_SS_ON_LVDS: 784 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 785 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 786 break; 787 } 788 break; 789 case 9: 790 switch (id) { 791 case ASIC_INTERNAL_SS_ON_TMDS: 792 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); 793 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); 794 break; 795 case ASIC_INTERNAL_SS_ON_HDMI: 796 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); 797 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); 798 break; 799 case ASIC_INTERNAL_SS_ON_LVDS: 800 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); 801 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); 802 break; 803 } 804 break; 805 default: 806 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 807 break; 808 } 809 if (percentage) 810 ss->percentage = percentage; 811 if (rate) 812 ss->rate = rate; 813 } 814 } 815 816 union asic_ss_info { 817 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 818 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 819 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 820 }; 821 822 union asic_ss_assignment { 823 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 824 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 825 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 826 }; 827 828 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, 829 struct amdgpu_atom_ss *ss, 830 int id, u32 clock) 831 { 832 struct amdgpu_mode_info *mode_info = &adev->mode_info; 833 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 834 uint16_t data_offset, size; 835 union asic_ss_info *ss_info; 836 union asic_ss_assignment *ss_assign; 837 uint8_t frev, crev; 838 int i, num_indices; 839 840 if (id == ASIC_INTERNAL_MEMORY_SS) { 841 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 842 return false; 843 } 844 if (id == ASIC_INTERNAL_ENGINE_SS) { 845 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 846 return false; 847 } 848 849 memset(ss, 0, sizeof(struct amdgpu_atom_ss)); 850 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 851 &frev, &crev, &data_offset)) { 852 853 ss_info = 854 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 855 856 switch (frev) { 857 case 1: 858 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 859 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 860 861 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 862 for (i = 0; i < num_indices; i++) { 863 if ((ss_assign->v1.ucClockIndication == id) && 864 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 865 ss->percentage = 866 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 867 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 868 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 869 ss->percentage_divider = 100; 870 return true; 871 } 872 ss_assign = (union asic_ss_assignment *) 873 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 874 } 875 break; 876 case 2: 877 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 878 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 879 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 880 for (i = 0; i < num_indices; i++) { 881 if ((ss_assign->v2.ucClockIndication == id) && 882 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 883 ss->percentage = 884 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 885 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 886 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 887 ss->percentage_divider = 100; 888 if ((crev == 2) && 889 ((id == ASIC_INTERNAL_ENGINE_SS) || 890 (id == ASIC_INTERNAL_MEMORY_SS))) 891 ss->rate /= 100; 892 return true; 893 } 894 ss_assign = (union asic_ss_assignment *) 895 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 896 } 897 break; 898 case 3: 899 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 900 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 901 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 902 for (i = 0; i < num_indices; i++) { 903 if ((ss_assign->v3.ucClockIndication == id) && 904 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 905 ss->percentage = 906 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 907 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 908 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 909 if (ss_assign->v3.ucSpreadSpectrumMode & 910 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 911 ss->percentage_divider = 1000; 912 else 913 ss->percentage_divider = 100; 914 if ((id == ASIC_INTERNAL_ENGINE_SS) || 915 (id == ASIC_INTERNAL_MEMORY_SS)) 916 ss->rate /= 100; 917 if (adev->flags & AMD_IS_APU) 918 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 919 return true; 920 } 921 ss_assign = (union asic_ss_assignment *) 922 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 923 } 924 break; 925 default: 926 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 927 break; 928 } 929 930 } 931 return false; 932 } 933 934 union get_clock_dividers { 935 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 936 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 937 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 938 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 939 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 940 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 941 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 942 }; 943 944 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 945 u8 clock_type, 946 u32 clock, 947 bool strobe_mode, 948 struct atom_clock_dividers *dividers) 949 { 950 union get_clock_dividers args; 951 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 952 u8 frev, crev; 953 954 memset(&args, 0, sizeof(args)); 955 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 956 957 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 958 return -EINVAL; 959 960 switch (crev) { 961 case 4: 962 /* fusion */ 963 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 964 965 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 966 967 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 968 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 969 break; 970 case 6: 971 /* CI */ 972 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 973 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 974 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 975 976 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 977 978 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 979 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 980 dividers->ref_div = args.v6_out.ucPllRefDiv; 981 dividers->post_div = args.v6_out.ucPllPostDiv; 982 dividers->flags = args.v6_out.ucPllCntlFlag; 983 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 984 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 985 break; 986 default: 987 return -EINVAL; 988 } 989 return 0; 990 } 991 992 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, 993 u32 clock, 994 bool strobe_mode, 995 struct atom_mpll_param *mpll_param) 996 { 997 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 998 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 999 u8 frev, crev; 1000 1001 memset(&args, 0, sizeof(args)); 1002 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 1003 1004 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1005 return -EINVAL; 1006 1007 switch (frev) { 1008 case 2: 1009 switch (crev) { 1010 case 1: 1011 /* SI */ 1012 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 1013 args.ucInputFlag = 0; 1014 if (strobe_mode) 1015 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 1016 1017 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1018 1019 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 1020 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 1021 mpll_param->post_div = args.ucPostDiv; 1022 mpll_param->dll_speed = args.ucDllSpeed; 1023 mpll_param->bwcntl = args.ucBWCntl; 1024 mpll_param->vco_mode = 1025 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 1026 mpll_param->yclk_sel = 1027 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 1028 mpll_param->qdr = 1029 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 1030 mpll_param->half_rate = 1031 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 1032 break; 1033 default: 1034 return -EINVAL; 1035 } 1036 break; 1037 default: 1038 return -EINVAL; 1039 } 1040 return 0; 1041 } 1042 1043 uint32_t amdgpu_atombios_get_engine_clock(struct amdgpu_device *adev) 1044 { 1045 GET_ENGINE_CLOCK_PS_ALLOCATION args; 1046 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock); 1047 1048 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1049 return le32_to_cpu(args.ulReturnEngineClock); 1050 } 1051 1052 uint32_t amdgpu_atombios_get_memory_clock(struct amdgpu_device *adev) 1053 { 1054 GET_MEMORY_CLOCK_PS_ALLOCATION args; 1055 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock); 1056 1057 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1058 return le32_to_cpu(args.ulReturnMemoryClock); 1059 } 1060 1061 void amdgpu_atombios_set_engine_clock(struct amdgpu_device *adev, 1062 uint32_t eng_clock) 1063 { 1064 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1065 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock); 1066 1067 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */ 1068 1069 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1070 } 1071 1072 void amdgpu_atombios_set_memory_clock(struct amdgpu_device *adev, 1073 uint32_t mem_clock) 1074 { 1075 SET_MEMORY_CLOCK_PS_ALLOCATION args; 1076 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock); 1077 1078 if (adev->flags & AMD_IS_APU) 1079 return; 1080 1081 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */ 1082 1083 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1084 } 1085 1086 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 1087 u32 eng_clock, u32 mem_clock) 1088 { 1089 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1090 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 1091 u32 tmp; 1092 1093 memset(&args, 0, sizeof(args)); 1094 1095 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 1096 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 1097 1098 args.ulTargetEngineClock = cpu_to_le32(tmp); 1099 if (mem_clock) 1100 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 1101 1102 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1103 } 1104 1105 union set_voltage { 1106 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 1107 struct _SET_VOLTAGE_PARAMETERS v1; 1108 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 1109 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 1110 }; 1111 1112 void amdgpu_atombios_set_voltage(struct amdgpu_device *adev, 1113 u16 voltage_level, 1114 u8 voltage_type) 1115 { 1116 union set_voltage args; 1117 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1118 u8 frev, crev, volt_index = voltage_level; 1119 1120 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1121 return; 1122 1123 /* 0xff01 is a flag rather then an actual voltage */ 1124 if (voltage_level == 0xff01) 1125 return; 1126 1127 switch (crev) { 1128 case 1: 1129 args.v1.ucVoltageType = voltage_type; 1130 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE; 1131 args.v1.ucVoltageIndex = volt_index; 1132 break; 1133 case 2: 1134 args.v2.ucVoltageType = voltage_type; 1135 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE; 1136 args.v2.usVoltageLevel = cpu_to_le16(voltage_level); 1137 break; 1138 case 3: 1139 args.v3.ucVoltageType = voltage_type; 1140 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE; 1141 args.v3.usVoltageLevel = cpu_to_le16(voltage_level); 1142 break; 1143 default: 1144 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1145 return; 1146 } 1147 1148 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1149 } 1150 1151 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, 1152 u16 *leakage_id) 1153 { 1154 union set_voltage args; 1155 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1156 u8 frev, crev; 1157 1158 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1159 return -EINVAL; 1160 1161 switch (crev) { 1162 case 3: 1163 case 4: 1164 args.v3.ucVoltageType = 0; 1165 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 1166 args.v3.usVoltageLevel = 0; 1167 1168 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1169 1170 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 1171 break; 1172 default: 1173 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1174 return -EINVAL; 1175 } 1176 1177 return 0; 1178 } 1179 1180 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, 1181 u16 *vddc, u16 *vddci, 1182 u16 virtual_voltage_id, 1183 u16 vbios_voltage_id) 1184 { 1185 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 1186 u8 frev, crev; 1187 u16 data_offset, size; 1188 int i, j; 1189 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 1190 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 1191 1192 *vddc = 0; 1193 *vddci = 0; 1194 1195 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1196 &frev, &crev, &data_offset)) 1197 return -EINVAL; 1198 1199 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 1200 (adev->mode_info.atom_context->bios + data_offset); 1201 1202 switch (frev) { 1203 case 1: 1204 return -EINVAL; 1205 case 2: 1206 switch (crev) { 1207 case 1: 1208 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 1209 return -EINVAL; 1210 leakage_bin = (u16 *) 1211 (adev->mode_info.atom_context->bios + data_offset + 1212 le16_to_cpu(profile->usLeakageBinArrayOffset)); 1213 vddc_id_buf = (u16 *) 1214 (adev->mode_info.atom_context->bios + data_offset + 1215 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 1216 vddc_buf = (u16 *) 1217 (adev->mode_info.atom_context->bios + data_offset + 1218 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 1219 vddci_id_buf = (u16 *) 1220 (adev->mode_info.atom_context->bios + data_offset + 1221 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 1222 vddci_buf = (u16 *) 1223 (adev->mode_info.atom_context->bios + data_offset + 1224 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 1225 1226 if (profile->ucElbVDDC_Num > 0) { 1227 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 1228 if (vddc_id_buf[i] == virtual_voltage_id) { 1229 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1230 if (vbios_voltage_id <= leakage_bin[j]) { 1231 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 1232 break; 1233 } 1234 } 1235 break; 1236 } 1237 } 1238 } 1239 if (profile->ucElbVDDCI_Num > 0) { 1240 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 1241 if (vddci_id_buf[i] == virtual_voltage_id) { 1242 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1243 if (vbios_voltage_id <= leakage_bin[j]) { 1244 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 1245 break; 1246 } 1247 } 1248 break; 1249 } 1250 } 1251 } 1252 break; 1253 default: 1254 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1255 return -EINVAL; 1256 } 1257 break; 1258 default: 1259 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1260 return -EINVAL; 1261 } 1262 1263 return 0; 1264 } 1265 1266 union get_voltage_info { 1267 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 1268 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 1269 }; 1270 1271 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, 1272 u16 virtual_voltage_id, 1273 u16 *voltage) 1274 { 1275 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 1276 u32 entry_id; 1277 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 1278 union get_voltage_info args; 1279 1280 for (entry_id = 0; entry_id < count; entry_id++) { 1281 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 1282 virtual_voltage_id) 1283 break; 1284 } 1285 1286 if (entry_id >= count) 1287 return -EINVAL; 1288 1289 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 1290 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1291 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 1292 args.in.ulSCLKFreq = 1293 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 1294 1295 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1296 1297 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 1298 1299 return 0; 1300 } 1301 1302 union voltage_object_info { 1303 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 1304 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 1305 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 1306 }; 1307 1308 union voltage_object { 1309 struct _ATOM_VOLTAGE_OBJECT v1; 1310 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 1311 union _ATOM_VOLTAGE_OBJECT_V3 v3; 1312 }; 1313 1314 1315 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 1316 u8 voltage_type, u8 voltage_mode) 1317 { 1318 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 1319 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 1320 u8 *start = (u8*)v3; 1321 1322 while (offset < size) { 1323 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 1324 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 1325 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 1326 return vo; 1327 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 1328 } 1329 return NULL; 1330 } 1331 1332 bool 1333 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, 1334 u8 voltage_type, u8 voltage_mode) 1335 { 1336 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1337 u8 frev, crev; 1338 u16 data_offset, size; 1339 union voltage_object_info *voltage_info; 1340 1341 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1342 &frev, &crev, &data_offset)) { 1343 voltage_info = (union voltage_object_info *) 1344 (adev->mode_info.atom_context->bios + data_offset); 1345 1346 switch (frev) { 1347 case 3: 1348 switch (crev) { 1349 case 1: 1350 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1351 voltage_type, voltage_mode)) 1352 return true; 1353 break; 1354 default: 1355 DRM_ERROR("unknown voltage object table\n"); 1356 return false; 1357 } 1358 break; 1359 default: 1360 DRM_ERROR("unknown voltage object table\n"); 1361 return false; 1362 } 1363 1364 } 1365 return false; 1366 } 1367 1368 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, 1369 u8 voltage_type, u8 voltage_mode, 1370 struct atom_voltage_table *voltage_table) 1371 { 1372 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1373 u8 frev, crev; 1374 u16 data_offset, size; 1375 int i; 1376 union voltage_object_info *voltage_info; 1377 union voltage_object *voltage_object = NULL; 1378 1379 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1380 &frev, &crev, &data_offset)) { 1381 voltage_info = (union voltage_object_info *) 1382 (adev->mode_info.atom_context->bios + data_offset); 1383 1384 switch (frev) { 1385 case 3: 1386 switch (crev) { 1387 case 1: 1388 voltage_object = (union voltage_object *) 1389 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1390 voltage_type, voltage_mode); 1391 if (voltage_object) { 1392 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 1393 &voltage_object->v3.asGpioVoltageObj; 1394 VOLTAGE_LUT_ENTRY_V2 *lut; 1395 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 1396 return -EINVAL; 1397 lut = &gpio->asVolGpioLut[0]; 1398 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 1399 voltage_table->entries[i].value = 1400 le16_to_cpu(lut->usVoltageValue); 1401 voltage_table->entries[i].smio_low = 1402 le32_to_cpu(lut->ulVoltageId); 1403 lut = (VOLTAGE_LUT_ENTRY_V2 *) 1404 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 1405 } 1406 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 1407 voltage_table->count = gpio->ucGpioEntryNum; 1408 voltage_table->phase_delay = gpio->ucPhaseDelay; 1409 return 0; 1410 } 1411 break; 1412 default: 1413 DRM_ERROR("unknown voltage object table\n"); 1414 return -EINVAL; 1415 } 1416 break; 1417 default: 1418 DRM_ERROR("unknown voltage object table\n"); 1419 return -EINVAL; 1420 } 1421 } 1422 return -EINVAL; 1423 } 1424 1425 union vram_info { 1426 struct _ATOM_VRAM_INFO_V3 v1_3; 1427 struct _ATOM_VRAM_INFO_V4 v1_4; 1428 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 1429 }; 1430 1431 #define MEM_ID_MASK 0xff000000 1432 #define MEM_ID_SHIFT 24 1433 #define CLOCK_RANGE_MASK 0x00ffffff 1434 #define CLOCK_RANGE_SHIFT 0 1435 #define LOW_NIBBLE_MASK 0xf 1436 #define DATA_EQU_PREV 0 1437 #define DATA_FROM_TABLE 4 1438 1439 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, 1440 u8 module_index, 1441 struct atom_mc_reg_table *reg_table) 1442 { 1443 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 1444 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 1445 u32 i = 0, j; 1446 u16 data_offset, size; 1447 union vram_info *vram_info; 1448 1449 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 1450 1451 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1452 &frev, &crev, &data_offset)) { 1453 vram_info = (union vram_info *) 1454 (adev->mode_info.atom_context->bios + data_offset); 1455 switch (frev) { 1456 case 1: 1457 DRM_ERROR("old table version %d, %d\n", frev, crev); 1458 return -EINVAL; 1459 case 2: 1460 switch (crev) { 1461 case 1: 1462 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 1463 ATOM_INIT_REG_BLOCK *reg_block = 1464 (ATOM_INIT_REG_BLOCK *) 1465 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 1466 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 1467 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1468 ((u8 *)reg_block + (2 * sizeof(u16)) + 1469 le16_to_cpu(reg_block->usRegIndexTblSize)); 1470 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 1471 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 1472 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 1473 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 1474 return -EINVAL; 1475 while (i < num_entries) { 1476 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 1477 break; 1478 reg_table->mc_reg_address[i].s1 = 1479 (u16)(le16_to_cpu(format->usRegIndex)); 1480 reg_table->mc_reg_address[i].pre_reg_data = 1481 (u8)(format->ucPreRegDataLength); 1482 i++; 1483 format = (ATOM_INIT_REG_INDEX_FORMAT *) 1484 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 1485 } 1486 reg_table->last = i; 1487 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1488 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 1489 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1490 >> MEM_ID_SHIFT); 1491 if (module_index == t_mem_id) { 1492 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 1493 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1494 >> CLOCK_RANGE_SHIFT); 1495 for (i = 0, j = 1; i < reg_table->last; i++) { 1496 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 1497 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1498 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1499 j++; 1500 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 1501 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1502 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 1503 } 1504 } 1505 num_ranges++; 1506 } 1507 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1508 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1509 } 1510 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 1511 return -EINVAL; 1512 reg_table->num_entries = num_ranges; 1513 } else 1514 return -EINVAL; 1515 break; 1516 default: 1517 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1518 return -EINVAL; 1519 } 1520 break; 1521 default: 1522 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1523 return -EINVAL; 1524 } 1525 return 0; 1526 } 1527 return -EINVAL; 1528 } 1529 1530 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) 1531 { 1532 uint32_t bios_6_scratch; 1533 1534 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1535 1536 if (lock) { 1537 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1538 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 1539 } else { 1540 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1541 bios_6_scratch |= ATOM_S6_ACC_MODE; 1542 } 1543 1544 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1545 } 1546 1547 void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) 1548 { 1549 uint32_t bios_2_scratch, bios_6_scratch; 1550 1551 bios_2_scratch = RREG32(mmBIOS_SCRATCH_2); 1552 bios_6_scratch = RREG32(mmBIOS_SCRATCH_6); 1553 1554 /* let the bios control the backlight */ 1555 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1556 1557 /* tell the bios not to handle mode switching */ 1558 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 1559 1560 /* clear the vbios dpms state */ 1561 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 1562 1563 WREG32(mmBIOS_SCRATCH_2, bios_2_scratch); 1564 WREG32(mmBIOS_SCRATCH_6, bios_6_scratch); 1565 } 1566 1567 void amdgpu_atombios_scratch_regs_save(struct amdgpu_device *adev) 1568 { 1569 int i; 1570 1571 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1572 adev->bios_scratch[i] = RREG32(mmBIOS_SCRATCH_0 + i); 1573 } 1574 1575 void amdgpu_atombios_scratch_regs_restore(struct amdgpu_device *adev) 1576 { 1577 int i; 1578 1579 for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++) 1580 WREG32(mmBIOS_SCRATCH_0 + i, adev->bios_scratch[i]); 1581 } 1582 1583 /* Atom needs data in little endian format so swap as appropriate when copying 1584 * data to or from atom. Note that atom operates on dw units. 1585 * 1586 * Use to_le=true when sending data to atom and provide at least 1587 * ALIGN(num_bytes,4) bytes in the dst buffer. 1588 * 1589 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4) 1590 * byes in the src buffer. 1591 */ 1592 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 1593 { 1594 #ifdef __BIG_ENDIAN 1595 u32 src_tmp[5], dst_tmp[5]; 1596 int i; 1597 u8 align_num_bytes = ALIGN(num_bytes, 4); 1598 1599 if (to_le) { 1600 memcpy(src_tmp, src, num_bytes); 1601 for (i = 0; i < align_num_bytes / 4; i++) 1602 dst_tmp[i] = cpu_to_le32(src_tmp[i]); 1603 memcpy(dst, dst_tmp, align_num_bytes); 1604 } else { 1605 memcpy(src_tmp, src, align_num_bytes); 1606 for (i = 0; i < align_num_bytes / 4; i++) 1607 dst_tmp[i] = le32_to_cpu(src_tmp[i]); 1608 memcpy(dst, dst_tmp, num_bytes); 1609 } 1610 #else 1611 memcpy(dst, src, num_bytes); 1612 #endif 1613 } 1614
Indexes created Tue Sep 30 11:09:46 GMT 2025