amdgpu_atombios.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_atombios.c,v 1.1.1.2 2021/12/18 20:11:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_atombios.c,v 1.1.1.2 2021/12/18 20:11:04 riastradh Exp $"); 31 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "amdgpu_atombios.h" 35 #include "amdgpu_atomfirmware.h" 36 #include "amdgpu_i2c.h" 37 #include "amdgpu_display.h" 38 39 #include "atom.h" 40 #include "atom-bits.h" 41 #include "atombios_encoders.h" 42 #include "bif/bif_4_1_d.h" 43 44 static void amdgpu_atombios_lookup_i2c_gpio_quirks(struct amdgpu_device *adev, 45 ATOM_GPIO_I2C_ASSIGMENT *gpio, 46 u8 index) 47 { 48 49 } 50 51 static struct amdgpu_i2c_bus_rec amdgpu_atombios_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio) 52 { 53 struct amdgpu_i2c_bus_rec i2c; 54 55 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 56 57 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex); 58 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex); 59 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex); 60 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex); 61 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex); 62 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex); 63 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex); 64 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex); 65 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift); 66 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift); 67 i2c.en_clk_mask = (1 << gpio->ucClkEnShift); 68 i2c.en_data_mask = (1 << gpio->ucDataEnShift); 69 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift); 70 i2c.y_data_mask = (1 << gpio->ucDataY_Shift); 71 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift); 72 i2c.a_data_mask = (1 << gpio->ucDataA_Shift); 73 74 if (gpio->sucI2cId.sbfAccess.bfHW_Capable) 75 i2c.hw_capable = true; 76 else 77 i2c.hw_capable = false; 78 79 if (gpio->sucI2cId.ucAccess == 0xa0) 80 i2c.mm_i2c = true; 81 else 82 i2c.mm_i2c = false; 83 84 i2c.i2c_id = gpio->sucI2cId.ucAccess; 85 86 if (i2c.mask_clk_reg) 87 i2c.valid = true; 88 else 89 i2c.valid = false; 90 91 return i2c; 92 } 93 94 struct amdgpu_i2c_bus_rec amdgpu_atombios_lookup_i2c_gpio(struct amdgpu_device *adev, 95 uint8_t id) 96 { 97 struct atom_context *ctx = adev->mode_info.atom_context; 98 ATOM_GPIO_I2C_ASSIGMENT *gpio; 99 struct amdgpu_i2c_bus_rec i2c; 100 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 101 struct _ATOM_GPIO_I2C_INFO *i2c_info; 102 uint16_t data_offset, size; 103 int i, num_indices; 104 105 memset(&i2c, 0, sizeof(struct amdgpu_i2c_bus_rec)); 106 i2c.valid = false; 107 108 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 109 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 110 111 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 112 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 113 114 gpio = &i2c_info->asGPIO_Info[0]; 115 for (i = 0; i < num_indices; i++) { 116 117 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 118 119 if (gpio->sucI2cId.ucAccess == id) { 120 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 121 break; 122 } 123 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 124 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 125 } 126 } 127 128 return i2c; 129 } 130 131 void amdgpu_atombios_i2c_init(struct amdgpu_device *adev) 132 { 133 struct atom_context *ctx = adev->mode_info.atom_context; 134 ATOM_GPIO_I2C_ASSIGMENT *gpio; 135 struct amdgpu_i2c_bus_rec i2c; 136 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info); 137 struct _ATOM_GPIO_I2C_INFO *i2c_info; 138 uint16_t data_offset, size; 139 int i, num_indices; 140 char stmp[32]; 141 142 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 143 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset); 144 145 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 146 sizeof(ATOM_GPIO_I2C_ASSIGMENT); 147 148 gpio = &i2c_info->asGPIO_Info[0]; 149 for (i = 0; i < num_indices; i++) { 150 amdgpu_atombios_lookup_i2c_gpio_quirks(adev, gpio, i); 151 152 i2c = amdgpu_atombios_get_bus_rec_for_i2c_gpio(gpio); 153 154 if (i2c.valid) { 155 sprintf(stmp, "0x%x", i2c.i2c_id); 156 adev->i2c_bus[i] = amdgpu_i2c_create(adev->ddev, &i2c, stmp); 157 } 158 gpio = (ATOM_GPIO_I2C_ASSIGMENT *) 159 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT)); 160 } 161 } 162 } 163 164 struct amdgpu_gpio_rec 165 amdgpu_atombios_lookup_gpio(struct amdgpu_device *adev, 166 u8 id) 167 { 168 struct atom_context *ctx = adev->mode_info.atom_context; 169 struct amdgpu_gpio_rec gpio; 170 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT); 171 struct _ATOM_GPIO_PIN_LUT *gpio_info; 172 ATOM_GPIO_PIN_ASSIGNMENT *pin; 173 u16 data_offset, size; 174 int i, num_indices; 175 176 memset(&gpio, 0, sizeof(struct amdgpu_gpio_rec)); 177 gpio.valid = false; 178 179 if (amdgpu_atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) { 180 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset); 181 182 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 183 sizeof(ATOM_GPIO_PIN_ASSIGNMENT); 184 185 pin = gpio_info->asGPIO_Pin; 186 for (i = 0; i < num_indices; i++) { 187 if (id == pin->ucGPIO_ID) { 188 gpio.id = pin->ucGPIO_ID; 189 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex); 190 gpio.shift = pin->ucGpioPinBitShift; 191 gpio.mask = (1 << pin->ucGpioPinBitShift); 192 gpio.valid = true; 193 break; 194 } 195 pin = (ATOM_GPIO_PIN_ASSIGNMENT *) 196 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT)); 197 } 198 } 199 200 return gpio; 201 } 202 203 static struct amdgpu_hpd 204 amdgpu_atombios_get_hpd_info_from_gpio(struct amdgpu_device *adev, 205 struct amdgpu_gpio_rec *gpio) 206 { 207 struct amdgpu_hpd hpd; 208 u32 reg; 209 210 memset(&hpd, 0, sizeof(struct amdgpu_hpd)); 211 212 reg = amdgpu_display_hpd_get_gpio_reg(adev); 213 214 hpd.gpio = *gpio; 215 if (gpio->reg == reg) { 216 switch(gpio->mask) { 217 case (1 << 0): 218 hpd.hpd = AMDGPU_HPD_1; 219 break; 220 case (1 << 8): 221 hpd.hpd = AMDGPU_HPD_2; 222 break; 223 case (1 << 16): 224 hpd.hpd = AMDGPU_HPD_3; 225 break; 226 case (1 << 24): 227 hpd.hpd = AMDGPU_HPD_4; 228 break; 229 case (1 << 26): 230 hpd.hpd = AMDGPU_HPD_5; 231 break; 232 case (1 << 28): 233 hpd.hpd = AMDGPU_HPD_6; 234 break; 235 default: 236 hpd.hpd = AMDGPU_HPD_NONE; 237 break; 238 } 239 } else 240 hpd.hpd = AMDGPU_HPD_NONE; 241 return hpd; 242 } 243 244 static const int object_connector_convert[] = { 245 DRM_MODE_CONNECTOR_Unknown, 246 DRM_MODE_CONNECTOR_DVII, 247 DRM_MODE_CONNECTOR_DVII, 248 DRM_MODE_CONNECTOR_DVID, 249 DRM_MODE_CONNECTOR_DVID, 250 DRM_MODE_CONNECTOR_VGA, 251 DRM_MODE_CONNECTOR_Composite, 252 DRM_MODE_CONNECTOR_SVIDEO, 253 DRM_MODE_CONNECTOR_Unknown, 254 DRM_MODE_CONNECTOR_Unknown, 255 DRM_MODE_CONNECTOR_9PinDIN, 256 DRM_MODE_CONNECTOR_Unknown, 257 DRM_MODE_CONNECTOR_HDMIA, 258 DRM_MODE_CONNECTOR_HDMIB, 259 DRM_MODE_CONNECTOR_LVDS, 260 DRM_MODE_CONNECTOR_9PinDIN, 261 DRM_MODE_CONNECTOR_Unknown, 262 DRM_MODE_CONNECTOR_Unknown, 263 DRM_MODE_CONNECTOR_Unknown, 264 DRM_MODE_CONNECTOR_DisplayPort, 265 DRM_MODE_CONNECTOR_eDP, 266 DRM_MODE_CONNECTOR_Unknown 267 }; 268 269 bool amdgpu_atombios_has_dce_engine_info(struct amdgpu_device *adev) 270 { 271 struct amdgpu_mode_info *mode_info = &adev->mode_info; 272 struct atom_context *ctx = mode_info->atom_context; 273 int index = GetIndexIntoMasterTable(DATA, Object_Header); 274 u16 size, data_offset; 275 u8 frev, crev; 276 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 277 ATOM_OBJECT_HEADER *obj_header; 278 279 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 280 return false; 281 282 if (crev < 2) 283 return false; 284 285 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 286 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 287 (ctx->bios + data_offset + 288 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 289 290 if (path_obj->ucNumOfDispPath) 291 return true; 292 else 293 return false; 294 } 295 296 bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device *adev) 297 { 298 struct amdgpu_mode_info *mode_info = &adev->mode_info; 299 struct atom_context *ctx = mode_info->atom_context; 300 int index = GetIndexIntoMasterTable(DATA, Object_Header); 301 u16 size, data_offset; 302 u8 frev, crev; 303 ATOM_CONNECTOR_OBJECT_TABLE *con_obj; 304 ATOM_ENCODER_OBJECT_TABLE *enc_obj; 305 ATOM_OBJECT_TABLE *router_obj; 306 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj; 307 ATOM_OBJECT_HEADER *obj_header; 308 int i, j, k, path_size, device_support; 309 int connector_type; 310 u16 conn_id, connector_object_id; 311 struct amdgpu_i2c_bus_rec ddc_bus; 312 struct amdgpu_router router; 313 struct amdgpu_gpio_rec gpio; 314 struct amdgpu_hpd hpd; 315 316 if (!amdgpu_atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) 317 return false; 318 319 if (crev < 2) 320 return false; 321 322 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset); 323 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *) 324 (ctx->bios + data_offset + 325 le16_to_cpu(obj_header->usDisplayPathTableOffset)); 326 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *) 327 (ctx->bios + data_offset + 328 le16_to_cpu(obj_header->usConnectorObjectTableOffset)); 329 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *) 330 (ctx->bios + data_offset + 331 le16_to_cpu(obj_header->usEncoderObjectTableOffset)); 332 router_obj = (ATOM_OBJECT_TABLE *) 333 (ctx->bios + data_offset + 334 le16_to_cpu(obj_header->usRouterObjectTableOffset)); 335 device_support = le16_to_cpu(obj_header->usDeviceSupport); 336 337 path_size = 0; 338 for (i = 0; i < path_obj->ucNumOfDispPath; i++) { 339 uint8_t *addr = (uint8_t *) path_obj->asDispPath; 340 ATOM_DISPLAY_OBJECT_PATH *path; 341 addr += path_size; 342 path = (ATOM_DISPLAY_OBJECT_PATH *) addr; 343 path_size += le16_to_cpu(path->usSize); 344 345 if (device_support & le16_to_cpu(path->usDeviceTag)) { 346 uint8_t con_obj_id = 347 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) 348 >> OBJECT_ID_SHIFT; 349 350 /* Skip TV/CV support */ 351 if ((le16_to_cpu(path->usDeviceTag) == 352 ATOM_DEVICE_TV1_SUPPORT) || 353 (le16_to_cpu(path->usDeviceTag) == 354 ATOM_DEVICE_CV_SUPPORT)) 355 continue; 356 357 if (con_obj_id >= ARRAY_SIZE(object_connector_convert)) { 358 DRM_ERROR("invalid con_obj_id %d for device tag 0x%04x\n", 359 con_obj_id, le16_to_cpu(path->usDeviceTag)); 360 continue; 361 } 362 363 connector_type = 364 object_connector_convert[con_obj_id]; 365 connector_object_id = con_obj_id; 366 367 if (connector_type == DRM_MODE_CONNECTOR_Unknown) 368 continue; 369 370 router.ddc_valid = false; 371 router.cd_valid = false; 372 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { 373 uint8_t grph_obj_type = 374 (le16_to_cpu(path->usGraphicObjIds[j]) & 375 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; 376 377 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) { 378 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) { 379 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID); 380 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) { 381 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 382 (ctx->bios + data_offset + 383 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset)); 384 ATOM_ENCODER_CAP_RECORD *cap_record; 385 u16 caps = 0; 386 387 while (record->ucRecordSize > 0 && 388 record->ucRecordType > 0 && 389 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 390 switch (record->ucRecordType) { 391 case ATOM_ENCODER_CAP_RECORD_TYPE: 392 cap_record =(ATOM_ENCODER_CAP_RECORD *) 393 record; 394 caps = le16_to_cpu(cap_record->usEncoderCap); 395 break; 396 } 397 record = (ATOM_COMMON_RECORD_HEADER *) 398 ((char *)record + record->ucRecordSize); 399 } 400 amdgpu_display_add_encoder(adev, encoder_obj, 401 le16_to_cpu(path->usDeviceTag), 402 caps); 403 } 404 } 405 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) { 406 for (k = 0; k < router_obj->ucNumberOfObjects; k++) { 407 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID); 408 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) { 409 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *) 410 (ctx->bios + data_offset + 411 le16_to_cpu(router_obj->asObjects[k].usRecordOffset)); 412 ATOM_I2C_RECORD *i2c_record; 413 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 414 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path; 415 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path; 416 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table = 417 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *) 418 (ctx->bios + data_offset + 419 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset)); 420 u8 *num_dst_objs = (u8 *) 421 ((u8 *)router_src_dst_table + 1 + 422 (router_src_dst_table->ucNumberOfSrc * 2)); 423 u16 *dst_objs = (u16 *)(num_dst_objs + 1); 424 int enum_id; 425 426 router.router_id = router_obj_id; 427 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) { 428 if (le16_to_cpu(path->usConnObjectId) == 429 le16_to_cpu(dst_objs[enum_id])) 430 break; 431 } 432 433 while (record->ucRecordSize > 0 && 434 record->ucRecordType > 0 && 435 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 436 switch (record->ucRecordType) { 437 case ATOM_I2C_RECORD_TYPE: 438 i2c_record = 439 (ATOM_I2C_RECORD *) 440 record; 441 i2c_config = 442 (ATOM_I2C_ID_CONFIG_ACCESS *) 443 &i2c_record->sucI2cId; 444 router.i2c_info = 445 amdgpu_atombios_lookup_i2c_gpio(adev, 446 i2c_config-> 447 ucAccess); 448 router.i2c_addr = i2c_record->ucI2CAddr >> 1; 449 break; 450 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE: 451 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *) 452 record; 453 router.ddc_valid = true; 454 router.ddc_mux_type = ddc_path->ucMuxType; 455 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin; 456 router.ddc_mux_state = ddc_path->ucMuxState[enum_id]; 457 break; 458 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE: 459 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *) 460 record; 461 router.cd_valid = true; 462 router.cd_mux_type = cd_path->ucMuxType; 463 router.cd_mux_control_pin = cd_path->ucMuxControlPin; 464 router.cd_mux_state = cd_path->ucMuxState[enum_id]; 465 break; 466 } 467 record = (ATOM_COMMON_RECORD_HEADER *) 468 ((char *)record + record->ucRecordSize); 469 } 470 } 471 } 472 } 473 } 474 475 /* look up gpio for ddc, hpd */ 476 ddc_bus.valid = false; 477 hpd.hpd = AMDGPU_HPD_NONE; 478 if ((le16_to_cpu(path->usDeviceTag) & 479 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) { 480 for (j = 0; j < con_obj->ucNumberOfObjects; j++) { 481 if (le16_to_cpu(path->usConnObjectId) == 482 le16_to_cpu(con_obj->asObjects[j]. 483 usObjectID)) { 484 ATOM_COMMON_RECORD_HEADER 485 *record = 486 (ATOM_COMMON_RECORD_HEADER 487 *) 488 (ctx->bios + data_offset + 489 le16_to_cpu(con_obj-> 490 asObjects[j]. 491 usRecordOffset)); 492 ATOM_I2C_RECORD *i2c_record; 493 ATOM_HPD_INT_RECORD *hpd_record; 494 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config; 495 496 while (record->ucRecordSize > 0 && 497 record->ucRecordType > 0 && 498 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) { 499 switch (record->ucRecordType) { 500 case ATOM_I2C_RECORD_TYPE: 501 i2c_record = 502 (ATOM_I2C_RECORD *) 503 record; 504 i2c_config = 505 (ATOM_I2C_ID_CONFIG_ACCESS *) 506 &i2c_record->sucI2cId; 507 ddc_bus = amdgpu_atombios_lookup_i2c_gpio(adev, 508 i2c_config-> 509 ucAccess); 510 break; 511 case ATOM_HPD_INT_RECORD_TYPE: 512 hpd_record = 513 (ATOM_HPD_INT_RECORD *) 514 record; 515 gpio = amdgpu_atombios_lookup_gpio(adev, 516 hpd_record->ucHPDIntGPIOID); 517 hpd = amdgpu_atombios_get_hpd_info_from_gpio(adev, &gpio); 518 hpd.plugged_state = hpd_record->ucPlugged_PinState; 519 break; 520 } 521 record = 522 (ATOM_COMMON_RECORD_HEADER 523 *) ((char *)record 524 + 525 record-> 526 ucRecordSize); 527 } 528 break; 529 } 530 } 531 } 532 533 /* needed for aux chan transactions */ 534 ddc_bus.hpd = hpd.hpd; 535 536 conn_id = le16_to_cpu(path->usConnObjectId); 537 538 amdgpu_display_add_connector(adev, 539 conn_id, 540 le16_to_cpu(path->usDeviceTag), 541 connector_type, &ddc_bus, 542 connector_object_id, 543 &hpd, 544 &router); 545 546 } 547 } 548 549 amdgpu_link_encoder_connector(adev->ddev); 550 551 return true; 552 } 553 554 union firmware_info { 555 ATOM_FIRMWARE_INFO info; 556 ATOM_FIRMWARE_INFO_V1_2 info_12; 557 ATOM_FIRMWARE_INFO_V1_3 info_13; 558 ATOM_FIRMWARE_INFO_V1_4 info_14; 559 ATOM_FIRMWARE_INFO_V2_1 info_21; 560 ATOM_FIRMWARE_INFO_V2_2 info_22; 561 }; 562 563 int amdgpu_atombios_get_clock_info(struct amdgpu_device *adev) 564 { 565 struct amdgpu_mode_info *mode_info = &adev->mode_info; 566 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 567 uint8_t frev, crev; 568 uint16_t data_offset; 569 int ret = -EINVAL; 570 571 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 572 &frev, &crev, &data_offset)) { 573 int i; 574 struct amdgpu_pll *ppll = &adev->clock.ppll[0]; 575 struct amdgpu_pll *spll = &adev->clock.spll; 576 struct amdgpu_pll *mpll = &adev->clock.mpll; 577 union firmware_info *firmware_info = 578 (union firmware_info *)(mode_info->atom_context->bios + 579 data_offset); 580 /* pixel clocks */ 581 ppll->reference_freq = 582 le16_to_cpu(firmware_info->info.usReferenceClock); 583 ppll->reference_div = 0; 584 585 ppll->pll_out_min = 586 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output); 587 ppll->pll_out_max = 588 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output); 589 590 ppll->lcd_pll_out_min = 591 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100; 592 if (ppll->lcd_pll_out_min == 0) 593 ppll->lcd_pll_out_min = ppll->pll_out_min; 594 ppll->lcd_pll_out_max = 595 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100; 596 if (ppll->lcd_pll_out_max == 0) 597 ppll->lcd_pll_out_max = ppll->pll_out_max; 598 599 if (ppll->pll_out_min == 0) 600 ppll->pll_out_min = 64800; 601 602 ppll->pll_in_min = 603 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input); 604 ppll->pll_in_max = 605 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input); 606 607 ppll->min_post_div = 2; 608 ppll->max_post_div = 0x7f; 609 ppll->min_frac_feedback_div = 0; 610 ppll->max_frac_feedback_div = 9; 611 ppll->min_ref_div = 2; 612 ppll->max_ref_div = 0x3ff; 613 ppll->min_feedback_div = 4; 614 ppll->max_feedback_div = 0xfff; 615 ppll->best_vco = 0; 616 617 for (i = 1; i < AMDGPU_MAX_PPLL; i++) 618 adev->clock.ppll[i] = *ppll; 619 620 /* system clock */ 621 spll->reference_freq = 622 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock); 623 spll->reference_div = 0; 624 625 spll->pll_out_min = 626 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output); 627 spll->pll_out_max = 628 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output); 629 630 /* ??? */ 631 if (spll->pll_out_min == 0) 632 spll->pll_out_min = 64800; 633 634 spll->pll_in_min = 635 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input); 636 spll->pll_in_max = 637 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input); 638 639 spll->min_post_div = 1; 640 spll->max_post_div = 1; 641 spll->min_ref_div = 2; 642 spll->max_ref_div = 0xff; 643 spll->min_feedback_div = 4; 644 spll->max_feedback_div = 0xff; 645 spll->best_vco = 0; 646 647 /* memory clock */ 648 mpll->reference_freq = 649 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock); 650 mpll->reference_div = 0; 651 652 mpll->pll_out_min = 653 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output); 654 mpll->pll_out_max = 655 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output); 656 657 /* ??? */ 658 if (mpll->pll_out_min == 0) 659 mpll->pll_out_min = 64800; 660 661 mpll->pll_in_min = 662 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input); 663 mpll->pll_in_max = 664 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input); 665 666 adev->clock.default_sclk = 667 le32_to_cpu(firmware_info->info.ulDefaultEngineClock); 668 adev->clock.default_mclk = 669 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock); 670 671 mpll->min_post_div = 1; 672 mpll->max_post_div = 1; 673 mpll->min_ref_div = 2; 674 mpll->max_ref_div = 0xff; 675 mpll->min_feedback_div = 4; 676 mpll->max_feedback_div = 0xff; 677 mpll->best_vco = 0; 678 679 /* disp clock */ 680 adev->clock.default_dispclk = 681 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq); 682 /* set a reasonable default for DP */ 683 if (adev->clock.default_dispclk < 53900) { 684 DRM_DEBUG("Changing default dispclk from %dMhz to 600Mhz\n", 685 adev->clock.default_dispclk / 100); 686 adev->clock.default_dispclk = 60000; 687 } else if (adev->clock.default_dispclk <= 60000) { 688 DRM_DEBUG("Changing default dispclk from %dMhz to 625Mhz\n", 689 adev->clock.default_dispclk / 100); 690 adev->clock.default_dispclk = 62500; 691 } 692 adev->clock.dp_extclk = 693 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq); 694 adev->clock.current_dispclk = adev->clock.default_dispclk; 695 696 adev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock); 697 if (adev->clock.max_pixel_clock == 0) 698 adev->clock.max_pixel_clock = 40000; 699 700 /* not technically a clock, but... */ 701 adev->mode_info.firmware_flags = 702 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess); 703 704 ret = 0; 705 } 706 707 adev->pm.current_sclk = adev->clock.default_sclk; 708 adev->pm.current_mclk = adev->clock.default_mclk; 709 710 return ret; 711 } 712 713 union gfx_info { 714 ATOM_GFX_INFO_V2_1 info; 715 }; 716 717 int amdgpu_atombios_get_gfx_info(struct amdgpu_device *adev) 718 { 719 struct amdgpu_mode_info *mode_info = &adev->mode_info; 720 int index = GetIndexIntoMasterTable(DATA, GFX_Info); 721 uint8_t frev, crev; 722 uint16_t data_offset; 723 int ret = -EINVAL; 724 725 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 726 &frev, &crev, &data_offset)) { 727 union gfx_info *gfx_info = (union gfx_info *) 728 (mode_info->atom_context->bios + data_offset); 729 730 adev->gfx.config.max_shader_engines = gfx_info->info.max_shader_engines; 731 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; 732 adev->gfx.config.max_cu_per_sh = gfx_info->info.max_cu_per_sh; 733 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; 734 adev->gfx.config.max_backends_per_se = gfx_info->info.max_backends_per_se; 735 adev->gfx.config.max_texture_channel_caches = 736 gfx_info->info.max_texture_channel_caches; 737 738 ret = 0; 739 } 740 return ret; 741 } 742 743 union igp_info { 744 struct _ATOM_INTEGRATED_SYSTEM_INFO info; 745 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2; 746 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6; 747 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7; 748 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8; 749 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 info_9; 750 }; 751 752 /* 753 * Return vram width from integrated system info table, if available, 754 * or 0 if not. 755 */ 756 int amdgpu_atombios_get_vram_width(struct amdgpu_device *adev) 757 { 758 struct amdgpu_mode_info *mode_info = &adev->mode_info; 759 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 760 u16 data_offset, size; 761 union igp_info *igp_info; 762 u8 frev, crev; 763 764 /* get any igp specific overrides */ 765 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 766 &frev, &crev, &data_offset)) { 767 igp_info = (union igp_info *) 768 (mode_info->atom_context->bios + data_offset); 769 switch (crev) { 770 case 8: 771 case 9: 772 return igp_info->info_8.ucUMAChannelNumber * 64; 773 default: 774 return 0; 775 } 776 } 777 778 return 0; 779 } 780 781 static void amdgpu_atombios_get_igp_ss_overrides(struct amdgpu_device *adev, 782 struct amdgpu_atom_ss *ss, 783 int id) 784 { 785 struct amdgpu_mode_info *mode_info = &adev->mode_info; 786 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo); 787 u16 data_offset, size; 788 union igp_info *igp_info; 789 u8 frev, crev; 790 u16 percentage = 0, rate = 0; 791 792 /* get any igp specific overrides */ 793 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 794 &frev, &crev, &data_offset)) { 795 igp_info = (union igp_info *) 796 (mode_info->atom_context->bios + data_offset); 797 switch (crev) { 798 case 6: 799 switch (id) { 800 case ASIC_INTERNAL_SS_ON_TMDS: 801 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage); 802 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz); 803 break; 804 case ASIC_INTERNAL_SS_ON_HDMI: 805 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage); 806 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz); 807 break; 808 case ASIC_INTERNAL_SS_ON_LVDS: 809 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage); 810 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz); 811 break; 812 } 813 break; 814 case 7: 815 switch (id) { 816 case ASIC_INTERNAL_SS_ON_TMDS: 817 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage); 818 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz); 819 break; 820 case ASIC_INTERNAL_SS_ON_HDMI: 821 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage); 822 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz); 823 break; 824 case ASIC_INTERNAL_SS_ON_LVDS: 825 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage); 826 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz); 827 break; 828 } 829 break; 830 case 8: 831 switch (id) { 832 case ASIC_INTERNAL_SS_ON_TMDS: 833 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage); 834 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz); 835 break; 836 case ASIC_INTERNAL_SS_ON_HDMI: 837 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage); 838 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz); 839 break; 840 case ASIC_INTERNAL_SS_ON_LVDS: 841 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage); 842 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz); 843 break; 844 } 845 break; 846 case 9: 847 switch (id) { 848 case ASIC_INTERNAL_SS_ON_TMDS: 849 percentage = le16_to_cpu(igp_info->info_9.usDVISSPercentage); 850 rate = le16_to_cpu(igp_info->info_9.usDVISSpreadRateIn10Hz); 851 break; 852 case ASIC_INTERNAL_SS_ON_HDMI: 853 percentage = le16_to_cpu(igp_info->info_9.usHDMISSPercentage); 854 rate = le16_to_cpu(igp_info->info_9.usHDMISSpreadRateIn10Hz); 855 break; 856 case ASIC_INTERNAL_SS_ON_LVDS: 857 percentage = le16_to_cpu(igp_info->info_9.usLvdsSSPercentage); 858 rate = le16_to_cpu(igp_info->info_9.usLvdsSSpreadRateIn10Hz); 859 break; 860 } 861 break; 862 default: 863 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev); 864 break; 865 } 866 if (percentage) 867 ss->percentage = percentage; 868 if (rate) 869 ss->rate = rate; 870 } 871 } 872 873 union asic_ss_info { 874 struct _ATOM_ASIC_INTERNAL_SS_INFO info; 875 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2; 876 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3; 877 }; 878 879 union asic_ss_assignment { 880 struct _ATOM_ASIC_SS_ASSIGNMENT v1; 881 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2; 882 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3; 883 }; 884 885 bool amdgpu_atombios_get_asic_ss_info(struct amdgpu_device *adev, 886 struct amdgpu_atom_ss *ss, 887 int id, u32 clock) 888 { 889 struct amdgpu_mode_info *mode_info = &adev->mode_info; 890 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info); 891 uint16_t data_offset, size; 892 union asic_ss_info *ss_info; 893 union asic_ss_assignment *ss_assign; 894 uint8_t frev, crev; 895 int i, num_indices; 896 897 if (id == ASIC_INTERNAL_MEMORY_SS) { 898 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT)) 899 return false; 900 } 901 if (id == ASIC_INTERNAL_ENGINE_SS) { 902 if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT)) 903 return false; 904 } 905 906 memset(ss, 0, sizeof(struct amdgpu_atom_ss)); 907 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, &size, 908 &frev, &crev, &data_offset)) { 909 910 ss_info = 911 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset); 912 913 switch (frev) { 914 case 1: 915 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 916 sizeof(ATOM_ASIC_SS_ASSIGNMENT); 917 918 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]); 919 for (i = 0; i < num_indices; i++) { 920 if ((ss_assign->v1.ucClockIndication == id) && 921 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) { 922 ss->percentage = 923 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage); 924 ss->type = ss_assign->v1.ucSpreadSpectrumMode; 925 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz); 926 ss->percentage_divider = 100; 927 return true; 928 } 929 ss_assign = (union asic_ss_assignment *) 930 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT)); 931 } 932 break; 933 case 2: 934 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 935 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2); 936 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]); 937 for (i = 0; i < num_indices; i++) { 938 if ((ss_assign->v2.ucClockIndication == id) && 939 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) { 940 ss->percentage = 941 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage); 942 ss->type = ss_assign->v2.ucSpreadSpectrumMode; 943 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz); 944 ss->percentage_divider = 100; 945 if ((crev == 2) && 946 ((id == ASIC_INTERNAL_ENGINE_SS) || 947 (id == ASIC_INTERNAL_MEMORY_SS))) 948 ss->rate /= 100; 949 return true; 950 } 951 ss_assign = (union asic_ss_assignment *) 952 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2)); 953 } 954 break; 955 case 3: 956 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) / 957 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3); 958 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]); 959 for (i = 0; i < num_indices; i++) { 960 if ((ss_assign->v3.ucClockIndication == id) && 961 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) { 962 ss->percentage = 963 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage); 964 ss->type = ss_assign->v3.ucSpreadSpectrumMode; 965 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz); 966 if (ss_assign->v3.ucSpreadSpectrumMode & 967 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK) 968 ss->percentage_divider = 1000; 969 else 970 ss->percentage_divider = 100; 971 if ((id == ASIC_INTERNAL_ENGINE_SS) || 972 (id == ASIC_INTERNAL_MEMORY_SS)) 973 ss->rate /= 100; 974 if (adev->flags & AMD_IS_APU) 975 amdgpu_atombios_get_igp_ss_overrides(adev, ss, id); 976 return true; 977 } 978 ss_assign = (union asic_ss_assignment *) 979 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3)); 980 } 981 break; 982 default: 983 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev); 984 break; 985 } 986 987 } 988 return false; 989 } 990 991 union get_clock_dividers { 992 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1; 993 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2; 994 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3; 995 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4; 996 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5; 997 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in; 998 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out; 999 }; 1000 1001 int amdgpu_atombios_get_clock_dividers(struct amdgpu_device *adev, 1002 u8 clock_type, 1003 u32 clock, 1004 bool strobe_mode, 1005 struct atom_clock_dividers *dividers) 1006 { 1007 union get_clock_dividers args; 1008 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL); 1009 u8 frev, crev; 1010 1011 memset(&args, 0, sizeof(args)); 1012 memset(dividers, 0, sizeof(struct atom_clock_dividers)); 1013 1014 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1015 return -EINVAL; 1016 1017 switch (crev) { 1018 case 2: 1019 case 3: 1020 case 5: 1021 /* r6xx, r7xx, evergreen, ni, si. 1022 * TODO: add support for asic_type <= CHIP_RV770*/ 1023 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) { 1024 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1025 1026 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1027 1028 dividers->post_div = args.v3.ucPostDiv; 1029 dividers->enable_post_div = (args.v3.ucCntlFlag & 1030 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1031 dividers->enable_dithen = (args.v3.ucCntlFlag & 1032 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1033 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); 1034 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac); 1035 dividers->ref_div = args.v3.ucRefDiv; 1036 dividers->vco_mode = (args.v3.ucCntlFlag & 1037 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1038 } else { 1039 /* for SI we use ComputeMemoryClockParam for memory plls */ 1040 if (adev->asic_type >= CHIP_TAHITI) 1041 return -EINVAL; 1042 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock); 1043 if (strobe_mode) 1044 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN; 1045 1046 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1047 1048 dividers->post_div = args.v5.ucPostDiv; 1049 dividers->enable_post_div = (args.v5.ucCntlFlag & 1050 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false; 1051 dividers->enable_dithen = (args.v5.ucCntlFlag & 1052 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true; 1053 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv); 1054 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac); 1055 dividers->ref_div = args.v5.ucRefDiv; 1056 dividers->vco_mode = (args.v5.ucCntlFlag & 1057 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0; 1058 } 1059 break; 1060 case 4: 1061 /* fusion */ 1062 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */ 1063 1064 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1065 1066 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv; 1067 dividers->real_clock = le32_to_cpu(args.v4.ulClock); 1068 break; 1069 case 6: 1070 /* CI */ 1071 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */ 1072 args.v6_in.ulClock.ulComputeClockFlag = clock_type; 1073 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */ 1074 1075 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1076 1077 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv); 1078 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac); 1079 dividers->ref_div = args.v6_out.ucPllRefDiv; 1080 dividers->post_div = args.v6_out.ucPllPostDiv; 1081 dividers->flags = args.v6_out.ucPllCntlFlag; 1082 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock); 1083 dividers->post_divider = args.v6_out.ulClock.ucPostDiv; 1084 break; 1085 default: 1086 return -EINVAL; 1087 } 1088 return 0; 1089 } 1090 1091 int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, 1092 u32 clock, 1093 bool strobe_mode, 1094 struct atom_mpll_param *mpll_param) 1095 { 1096 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args; 1097 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam); 1098 u8 frev, crev; 1099 1100 memset(&args, 0, sizeof(args)); 1101 memset(mpll_param, 0, sizeof(struct atom_mpll_param)); 1102 1103 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1104 return -EINVAL; 1105 1106 switch (frev) { 1107 case 2: 1108 switch (crev) { 1109 case 1: 1110 /* SI */ 1111 args.ulClock = cpu_to_le32(clock); /* 10 khz */ 1112 args.ucInputFlag = 0; 1113 if (strobe_mode) 1114 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN; 1115 1116 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1117 1118 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac); 1119 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv); 1120 mpll_param->post_div = args.ucPostDiv; 1121 mpll_param->dll_speed = args.ucDllSpeed; 1122 mpll_param->bwcntl = args.ucBWCntl; 1123 mpll_param->vco_mode = 1124 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK); 1125 mpll_param->yclk_sel = 1126 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0; 1127 mpll_param->qdr = 1128 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0; 1129 mpll_param->half_rate = 1130 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0; 1131 break; 1132 default: 1133 return -EINVAL; 1134 } 1135 break; 1136 default: 1137 return -EINVAL; 1138 } 1139 return 0; 1140 } 1141 1142 void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, 1143 u32 eng_clock, u32 mem_clock) 1144 { 1145 SET_ENGINE_CLOCK_PS_ALLOCATION args; 1146 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); 1147 u32 tmp; 1148 1149 memset(&args, 0, sizeof(args)); 1150 1151 tmp = eng_clock & SET_CLOCK_FREQ_MASK; 1152 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24); 1153 1154 args.ulTargetEngineClock = cpu_to_le32(tmp); 1155 if (mem_clock) 1156 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); 1157 1158 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1159 } 1160 1161 void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, 1162 u16 *vddc, u16 *vddci, u16 *mvdd) 1163 { 1164 struct amdgpu_mode_info *mode_info = &adev->mode_info; 1165 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo); 1166 u8 frev, crev; 1167 u16 data_offset; 1168 union firmware_info *firmware_info; 1169 1170 *vddc = 0; 1171 *vddci = 0; 1172 *mvdd = 0; 1173 1174 if (amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL, 1175 &frev, &crev, &data_offset)) { 1176 firmware_info = 1177 (union firmware_info *)(mode_info->atom_context->bios + 1178 data_offset); 1179 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage); 1180 if ((frev == 2) && (crev >= 2)) { 1181 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage); 1182 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage); 1183 } 1184 } 1185 } 1186 1187 union set_voltage { 1188 struct _SET_VOLTAGE_PS_ALLOCATION alloc; 1189 struct _SET_VOLTAGE_PARAMETERS v1; 1190 struct _SET_VOLTAGE_PARAMETERS_V2 v2; 1191 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3; 1192 }; 1193 1194 int amdgpu_atombios_get_max_vddc(struct amdgpu_device *adev, u8 voltage_type, 1195 u16 voltage_id, u16 *voltage) 1196 { 1197 union set_voltage args; 1198 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1199 u8 frev, crev; 1200 1201 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1202 return -EINVAL; 1203 1204 switch (crev) { 1205 case 1: 1206 return -EINVAL; 1207 case 2: 1208 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE; 1209 args.v2.ucVoltageMode = 0; 1210 args.v2.usVoltageLevel = 0; 1211 1212 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1213 1214 *voltage = le16_to_cpu(args.v2.usVoltageLevel); 1215 break; 1216 case 3: 1217 args.v3.ucVoltageType = voltage_type; 1218 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL; 1219 args.v3.usVoltageLevel = cpu_to_le16(voltage_id); 1220 1221 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1222 1223 *voltage = le16_to_cpu(args.v3.usVoltageLevel); 1224 break; 1225 default: 1226 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1227 return -EINVAL; 1228 } 1229 1230 return 0; 1231 } 1232 1233 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(struct amdgpu_device *adev, 1234 u16 *voltage, 1235 u16 leakage_idx) 1236 { 1237 return amdgpu_atombios_get_max_vddc(adev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage); 1238 } 1239 1240 int amdgpu_atombios_get_leakage_id_from_vbios(struct amdgpu_device *adev, 1241 u16 *leakage_id) 1242 { 1243 union set_voltage args; 1244 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage); 1245 u8 frev, crev; 1246 1247 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev, &crev)) 1248 return -EINVAL; 1249 1250 switch (crev) { 1251 case 3: 1252 case 4: 1253 args.v3.ucVoltageType = 0; 1254 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID; 1255 args.v3.usVoltageLevel = 0; 1256 1257 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1258 1259 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel); 1260 break; 1261 default: 1262 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1263 return -EINVAL; 1264 } 1265 1266 return 0; 1267 } 1268 1269 int amdgpu_atombios_get_leakage_vddc_based_on_leakage_params(struct amdgpu_device *adev, 1270 u16 *vddc, u16 *vddci, 1271 u16 virtual_voltage_id, 1272 u16 vbios_voltage_id) 1273 { 1274 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 1275 u8 frev, crev; 1276 u16 data_offset, size; 1277 int i, j; 1278 ATOM_ASIC_PROFILING_INFO_V2_1 *profile; 1279 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf; 1280 1281 *vddc = 0; 1282 *vddci = 0; 1283 1284 if (!amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1285 &frev, &crev, &data_offset)) 1286 return -EINVAL; 1287 1288 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 1289 (adev->mode_info.atom_context->bios + data_offset); 1290 1291 switch (frev) { 1292 case 1: 1293 return -EINVAL; 1294 case 2: 1295 switch (crev) { 1296 case 1: 1297 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1)) 1298 return -EINVAL; 1299 leakage_bin = (u16 *) 1300 (adev->mode_info.atom_context->bios + data_offset + 1301 le16_to_cpu(profile->usLeakageBinArrayOffset)); 1302 vddc_id_buf = (u16 *) 1303 (adev->mode_info.atom_context->bios + data_offset + 1304 le16_to_cpu(profile->usElbVDDC_IdArrayOffset)); 1305 vddc_buf = (u16 *) 1306 (adev->mode_info.atom_context->bios + data_offset + 1307 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset)); 1308 vddci_id_buf = (u16 *) 1309 (adev->mode_info.atom_context->bios + data_offset + 1310 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset)); 1311 vddci_buf = (u16 *) 1312 (adev->mode_info.atom_context->bios + data_offset + 1313 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset)); 1314 1315 if (profile->ucElbVDDC_Num > 0) { 1316 for (i = 0; i < profile->ucElbVDDC_Num; i++) { 1317 if (vddc_id_buf[i] == virtual_voltage_id) { 1318 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1319 if (vbios_voltage_id <= leakage_bin[j]) { 1320 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i]; 1321 break; 1322 } 1323 } 1324 break; 1325 } 1326 } 1327 } 1328 if (profile->ucElbVDDCI_Num > 0) { 1329 for (i = 0; i < profile->ucElbVDDCI_Num; i++) { 1330 if (vddci_id_buf[i] == virtual_voltage_id) { 1331 for (j = 0; j < profile->ucLeakageBinNum; j++) { 1332 if (vbios_voltage_id <= leakage_bin[j]) { 1333 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i]; 1334 break; 1335 } 1336 } 1337 break; 1338 } 1339 } 1340 } 1341 break; 1342 default: 1343 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1344 return -EINVAL; 1345 } 1346 break; 1347 default: 1348 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1349 return -EINVAL; 1350 } 1351 1352 return 0; 1353 } 1354 1355 union get_voltage_info { 1356 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in; 1357 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out; 1358 }; 1359 1360 int amdgpu_atombios_get_voltage_evv(struct amdgpu_device *adev, 1361 u16 virtual_voltage_id, 1362 u16 *voltage) 1363 { 1364 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo); 1365 u32 entry_id; 1366 u32 count = adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; 1367 union get_voltage_info args; 1368 1369 for (entry_id = 0; entry_id < count; entry_id++) { 1370 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v == 1371 virtual_voltage_id) 1372 break; 1373 } 1374 1375 if (entry_id >= count) 1376 return -EINVAL; 1377 1378 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC; 1379 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE; 1380 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id); 1381 args.in.ulSCLKFreq = 1382 cpu_to_le32(adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk); 1383 1384 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args); 1385 1386 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel); 1387 1388 return 0; 1389 } 1390 1391 union voltage_object_info { 1392 struct _ATOM_VOLTAGE_OBJECT_INFO v1; 1393 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2; 1394 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3; 1395 }; 1396 1397 union voltage_object { 1398 struct _ATOM_VOLTAGE_OBJECT v1; 1399 struct _ATOM_VOLTAGE_OBJECT_V2 v2; 1400 union _ATOM_VOLTAGE_OBJECT_V3 v3; 1401 }; 1402 1403 1404 static ATOM_VOLTAGE_OBJECT_V3 *amdgpu_atombios_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3, 1405 u8 voltage_type, u8 voltage_mode) 1406 { 1407 u32 size = le16_to_cpu(v3->sHeader.usStructureSize); 1408 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]); 1409 u8 *start = (u8*)v3; 1410 1411 while (offset < size) { 1412 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset); 1413 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) && 1414 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode)) 1415 return vo; 1416 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize); 1417 } 1418 return NULL; 1419 } 1420 1421 int amdgpu_atombios_get_svi2_info(struct amdgpu_device *adev, 1422 u8 voltage_type, 1423 u8 *svd_gpio_id, u8 *svc_gpio_id) 1424 { 1425 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1426 u8 frev, crev; 1427 u16 data_offset, size; 1428 union voltage_object_info *voltage_info; 1429 union voltage_object *voltage_object = NULL; 1430 1431 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1432 &frev, &crev, &data_offset)) { 1433 voltage_info = (union voltage_object_info *) 1434 (adev->mode_info.atom_context->bios + data_offset); 1435 1436 switch (frev) { 1437 case 3: 1438 switch (crev) { 1439 case 1: 1440 voltage_object = (union voltage_object *) 1441 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1442 voltage_type, 1443 VOLTAGE_OBJ_SVID2); 1444 if (voltage_object) { 1445 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId; 1446 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId; 1447 } else { 1448 return -EINVAL; 1449 } 1450 break; 1451 default: 1452 DRM_ERROR("unknown voltage object table\n"); 1453 return -EINVAL; 1454 } 1455 break; 1456 default: 1457 DRM_ERROR("unknown voltage object table\n"); 1458 return -EINVAL; 1459 } 1460 1461 } 1462 return 0; 1463 } 1464 1465 bool 1466 amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, 1467 u8 voltage_type, u8 voltage_mode) 1468 { 1469 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1470 u8 frev, crev; 1471 u16 data_offset, size; 1472 union voltage_object_info *voltage_info; 1473 1474 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1475 &frev, &crev, &data_offset)) { 1476 voltage_info = (union voltage_object_info *) 1477 (adev->mode_info.atom_context->bios + data_offset); 1478 1479 switch (frev) { 1480 case 3: 1481 switch (crev) { 1482 case 1: 1483 if (amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1484 voltage_type, voltage_mode)) 1485 return true; 1486 break; 1487 default: 1488 DRM_ERROR("unknown voltage object table\n"); 1489 return false; 1490 } 1491 break; 1492 default: 1493 DRM_ERROR("unknown voltage object table\n"); 1494 return false; 1495 } 1496 1497 } 1498 return false; 1499 } 1500 1501 int amdgpu_atombios_get_voltage_table(struct amdgpu_device *adev, 1502 u8 voltage_type, u8 voltage_mode, 1503 struct atom_voltage_table *voltage_table) 1504 { 1505 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo); 1506 u8 frev, crev; 1507 u16 data_offset, size; 1508 int i; 1509 union voltage_object_info *voltage_info; 1510 union voltage_object *voltage_object = NULL; 1511 1512 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1513 &frev, &crev, &data_offset)) { 1514 voltage_info = (union voltage_object_info *) 1515 (adev->mode_info.atom_context->bios + data_offset); 1516 1517 switch (frev) { 1518 case 3: 1519 switch (crev) { 1520 case 1: 1521 voltage_object = (union voltage_object *) 1522 amdgpu_atombios_lookup_voltage_object_v3(&voltage_info->v3, 1523 voltage_type, voltage_mode); 1524 if (voltage_object) { 1525 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio = 1526 &voltage_object->v3.asGpioVoltageObj; 1527 VOLTAGE_LUT_ENTRY_V2 *lut; 1528 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES) 1529 return -EINVAL; 1530 lut = &gpio->asVolGpioLut[0]; 1531 for (i = 0; i < gpio->ucGpioEntryNum; i++) { 1532 voltage_table->entries[i].value = 1533 le16_to_cpu(lut->usVoltageValue); 1534 voltage_table->entries[i].smio_low = 1535 le32_to_cpu(lut->ulVoltageId); 1536 lut = (VOLTAGE_LUT_ENTRY_V2 *) 1537 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2)); 1538 } 1539 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal); 1540 voltage_table->count = gpio->ucGpioEntryNum; 1541 voltage_table->phase_delay = gpio->ucPhaseDelay; 1542 return 0; 1543 } 1544 break; 1545 default: 1546 DRM_ERROR("unknown voltage object table\n"); 1547 return -EINVAL; 1548 } 1549 break; 1550 default: 1551 DRM_ERROR("unknown voltage object table\n"); 1552 return -EINVAL; 1553 } 1554 } 1555 return -EINVAL; 1556 } 1557 1558 union vram_info { 1559 struct _ATOM_VRAM_INFO_V3 v1_3; 1560 struct _ATOM_VRAM_INFO_V4 v1_4; 1561 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1; 1562 }; 1563 1564 #define MEM_ID_MASK 0xff000000 1565 #define MEM_ID_SHIFT 24 1566 #define CLOCK_RANGE_MASK 0x00ffffff 1567 #define CLOCK_RANGE_SHIFT 0 1568 #define LOW_NIBBLE_MASK 0xf 1569 #define DATA_EQU_PREV 0 1570 #define DATA_FROM_TABLE 4 1571 1572 int amdgpu_atombios_init_mc_reg_table(struct amdgpu_device *adev, 1573 u8 module_index, 1574 struct atom_mc_reg_table *reg_table) 1575 { 1576 int index = GetIndexIntoMasterTable(DATA, VRAM_Info); 1577 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0; 1578 u32 i = 0, j; 1579 u16 data_offset, size; 1580 union vram_info *vram_info; 1581 1582 memset(reg_table, 0, sizeof(struct atom_mc_reg_table)); 1583 1584 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1585 &frev, &crev, &data_offset)) { 1586 vram_info = (union vram_info *) 1587 (adev->mode_info.atom_context->bios + data_offset); 1588 switch (frev) { 1589 case 1: 1590 DRM_ERROR("old table version %d, %d\n", frev, crev); 1591 return -EINVAL; 1592 case 2: 1593 switch (crev) { 1594 case 1: 1595 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) { 1596 ATOM_INIT_REG_BLOCK *reg_block = 1597 (ATOM_INIT_REG_BLOCK *) 1598 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset)); 1599 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data = 1600 (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1601 ((u8 *)reg_block + (2 * sizeof(u16)) + 1602 le16_to_cpu(reg_block->usRegIndexTblSize)); 1603 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0]; 1604 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) / 1605 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1; 1606 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE) 1607 return -EINVAL; 1608 while (i < num_entries) { 1609 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER) 1610 break; 1611 reg_table->mc_reg_address[i].s1 = 1612 (u16)(le16_to_cpu(format->usRegIndex)); 1613 reg_table->mc_reg_address[i].pre_reg_data = 1614 (u8)(format->ucPreRegDataLength); 1615 i++; 1616 format = (ATOM_INIT_REG_INDEX_FORMAT *) 1617 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT)); 1618 } 1619 reg_table->last = i; 1620 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) && 1621 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) { 1622 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK) 1623 >> MEM_ID_SHIFT); 1624 if (module_index == t_mem_id) { 1625 reg_table->mc_reg_table_entry[num_ranges].mclk_max = 1626 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK) 1627 >> CLOCK_RANGE_SHIFT); 1628 for (i = 0, j = 1; i < reg_table->last; i++) { 1629 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) { 1630 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1631 (u32)le32_to_cpu(*((u32 *)reg_data + j)); 1632 j++; 1633 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) { 1634 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] = 1635 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1]; 1636 } 1637 } 1638 num_ranges++; 1639 } 1640 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *) 1641 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize)); 1642 } 1643 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) 1644 return -EINVAL; 1645 reg_table->num_entries = num_ranges; 1646 } else 1647 return -EINVAL; 1648 break; 1649 default: 1650 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1651 return -EINVAL; 1652 } 1653 break; 1654 default: 1655 DRM_ERROR("Unknown table version %d, %d\n", frev, crev); 1656 return -EINVAL; 1657 } 1658 return 0; 1659 } 1660 return -EINVAL; 1661 } 1662 1663 bool amdgpu_atombios_has_gpu_virtualization_table(struct amdgpu_device *adev) 1664 { 1665 int index = GetIndexIntoMasterTable(DATA, GPUVirtualizationInfo); 1666 u8 frev, crev; 1667 u16 data_offset, size; 1668 1669 if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, &size, 1670 &frev, &crev, &data_offset)) 1671 return true; 1672 1673 return false; 1674 } 1675 1676 void amdgpu_atombios_scratch_regs_lock(struct amdgpu_device *adev, bool lock) 1677 { 1678 uint32_t bios_6_scratch; 1679 1680 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); 1681 1682 if (lock) { 1683 bios_6_scratch |= ATOM_S6_CRITICAL_STATE; 1684 bios_6_scratch &= ~ATOM_S6_ACC_MODE; 1685 } else { 1686 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE; 1687 bios_6_scratch |= ATOM_S6_ACC_MODE; 1688 } 1689 1690 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); 1691 } 1692 1693 static void amdgpu_atombios_scratch_regs_init(struct amdgpu_device *adev) 1694 { 1695 uint32_t bios_2_scratch, bios_6_scratch; 1696 1697 adev->bios_scratch_reg_offset = mmBIOS_SCRATCH_0; 1698 1699 bios_2_scratch = RREG32(adev->bios_scratch_reg_offset + 2); 1700 bios_6_scratch = RREG32(adev->bios_scratch_reg_offset + 6); 1701 1702 /* let the bios control the backlight */ 1703 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE; 1704 1705 /* tell the bios not to handle mode switching */ 1706 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH; 1707 1708 /* clear the vbios dpms state */ 1709 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE; 1710 1711 WREG32(adev->bios_scratch_reg_offset + 2, bios_2_scratch); 1712 WREG32(adev->bios_scratch_reg_offset + 6, bios_6_scratch); 1713 } 1714 1715 void amdgpu_atombios_scratch_regs_engine_hung(struct amdgpu_device *adev, 1716 bool hung) 1717 { 1718 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 3); 1719 1720 if (hung) 1721 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1722 else 1723 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1724 1725 WREG32(adev->bios_scratch_reg_offset + 3, tmp); 1726 } 1727 1728 bool amdgpu_atombios_scratch_need_asic_init(struct amdgpu_device *adev) 1729 { 1730 u32 tmp = RREG32(adev->bios_scratch_reg_offset + 7); 1731 1732 if (tmp & ATOM_S7_ASIC_INIT_COMPLETE_MASK) 1733 return false; 1734 else 1735 return true; 1736 } 1737 1738 /* Atom needs data in little endian format so swap as appropriate when copying 1739 * data to or from atom. Note that atom operates on dw units. 1740 * 1741 * Use to_le=true when sending data to atom and provide at least 1742 * ALIGN(num_bytes,4) bytes in the dst buffer. 1743 * 1744 * Use to_le=false when receiving data from atom and provide ALIGN(num_bytes,4) 1745 * byes in the src buffer. 1746 */ 1747 void amdgpu_atombios_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le) 1748 { 1749 #ifdef __BIG_ENDIAN 1750 u32 src_tmp[5], dst_tmp[5]; 1751 int i; 1752 u8 align_num_bytes = ALIGN(num_bytes, 4); 1753 1754 if (to_le) { 1755 memcpy(src_tmp, src, num_bytes); 1756 for (i = 0; i < align_num_bytes / 4; i++) 1757 dst_tmp[i] = cpu_to_le32(src_tmp[i]); 1758 memcpy(dst, dst_tmp, align_num_bytes); 1759 } else { 1760 memcpy(src_tmp, src, align_num_bytes); 1761 for (i = 0; i < align_num_bytes / 4; i++) 1762 dst_tmp[i] = le32_to_cpu(src_tmp[i]); 1763 memcpy(dst, dst_tmp, num_bytes); 1764 } 1765 #else 1766 memcpy(dst, src, num_bytes); 1767 #endif 1768 } 1769 1770 static int amdgpu_atombios_allocate_fb_scratch(struct amdgpu_device *adev) 1771 { 1772 struct atom_context *ctx = adev->mode_info.atom_context; 1773 int index = GetIndexIntoMasterTable(DATA, VRAM_UsageByFirmware); 1774 uint16_t data_offset; 1775 int usage_bytes = 0; 1776 struct _ATOM_VRAM_USAGE_BY_FIRMWARE *firmware_usage; 1777 u64 start_addr; 1778 u64 size; 1779 1780 if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) { 1781 firmware_usage = (struct _ATOM_VRAM_USAGE_BY_FIRMWARE *)(ctx->bios + data_offset); 1782 1783 DRM_DEBUG("atom firmware requested %08x %dkb\n", 1784 le32_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware), 1785 le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb)); 1786 1787 start_addr = firmware_usage->asFirmwareVramReserveInfo[0].ulStartAddrUsedByFirmware; 1788 size = firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb; 1789 1790 if ((uint32_t)(start_addr & ATOM_VRAM_OPERATION_FLAGS_MASK) == 1791 (uint32_t)(ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION << 1792 ATOM_VRAM_OPERATION_FLAGS_SHIFT)) { 1793 /* Firmware request VRAM reservation for SR-IOV */ 1794 adev->fw_vram_usage.start_offset = (start_addr & 1795 (~ATOM_VRAM_OPERATION_FLAGS_MASK)) << 10; 1796 adev->fw_vram_usage.size = size << 10; 1797 /* Use the default scratch size */ 1798 usage_bytes = 0; 1799 } else { 1800 usage_bytes = le16_to_cpu(firmware_usage->asFirmwareVramReserveInfo[0].usFirmwareUseInKb) * 1024; 1801 } 1802 } 1803 ctx->scratch_size_bytes = 0; 1804 if (usage_bytes == 0) 1805 usage_bytes = 20 * 1024; 1806 /* allocate some scratch memory */ 1807 ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL); 1808 if (!ctx->scratch) 1809 return -ENOMEM; 1810 ctx->scratch_size_bytes = usage_bytes; 1811 return 0; 1812 } 1813 1814 /* ATOM accessor methods */ 1815 /* 1816 * ATOM is an interpreted byte code stored in tables in the vbios. The 1817 * driver registers callbacks to access registers and the interpreter 1818 * in the driver parses the tables and executes then to program specific 1819 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c, 1820 * atombios.h, and atom.c 1821 */ 1822 1823 /** 1824 * cail_pll_read - read PLL register 1825 * 1826 * @info: atom card_info pointer 1827 * @reg: PLL register offset 1828 * 1829 * Provides a PLL register accessor for the atom interpreter (r4xx+). 1830 * Returns the value of the PLL register. 1831 */ 1832 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) 1833 { 1834 return 0; 1835 } 1836 1837 /** 1838 * cail_pll_write - write PLL register 1839 * 1840 * @info: atom card_info pointer 1841 * @reg: PLL register offset 1842 * @val: value to write to the pll register 1843 * 1844 * Provides a PLL register accessor for the atom interpreter (r4xx+). 1845 */ 1846 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) 1847 { 1848 1849 } 1850 1851 /** 1852 * cail_mc_read - read MC (Memory Controller) register 1853 * 1854 * @info: atom card_info pointer 1855 * @reg: MC register offset 1856 * 1857 * Provides an MC register accessor for the atom interpreter (r4xx+). 1858 * Returns the value of the MC register. 1859 */ 1860 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) 1861 { 1862 return 0; 1863 } 1864 1865 /** 1866 * cail_mc_write - write MC (Memory Controller) register 1867 * 1868 * @info: atom card_info pointer 1869 * @reg: MC register offset 1870 * @val: value to write to the pll register 1871 * 1872 * Provides a MC register accessor for the atom interpreter (r4xx+). 1873 */ 1874 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) 1875 { 1876 1877 } 1878 1879 /** 1880 * cail_reg_write - write MMIO register 1881 * 1882 * @info: atom card_info pointer 1883 * @reg: MMIO register offset 1884 * @val: value to write to the pll register 1885 * 1886 * Provides a MMIO register accessor for the atom interpreter (r4xx+). 1887 */ 1888 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) 1889 { 1890 struct amdgpu_device *adev = info->dev->dev_private; 1891 1892 WREG32(reg, val); 1893 } 1894 1895 /** 1896 * cail_reg_read - read MMIO register 1897 * 1898 * @info: atom card_info pointer 1899 * @reg: MMIO register offset 1900 * 1901 * Provides an MMIO register accessor for the atom interpreter (r4xx+). 1902 * Returns the value of the MMIO register. 1903 */ 1904 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) 1905 { 1906 struct amdgpu_device *adev = info->dev->dev_private; 1907 uint32_t r; 1908 1909 r = RREG32(reg); 1910 return r; 1911 } 1912 1913 /** 1914 * cail_ioreg_write - write IO register 1915 * 1916 * @info: atom card_info pointer 1917 * @reg: IO register offset 1918 * @val: value to write to the pll register 1919 * 1920 * Provides a IO register accessor for the atom interpreter (r4xx+). 1921 */ 1922 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) 1923 { 1924 struct amdgpu_device *adev = info->dev->dev_private; 1925 1926 WREG32_IO(reg, val); 1927 } 1928 1929 /** 1930 * cail_ioreg_read - read IO register 1931 * 1932 * @info: atom card_info pointer 1933 * @reg: IO register offset 1934 * 1935 * Provides an IO register accessor for the atom interpreter (r4xx+). 1936 * Returns the value of the IO register. 1937 */ 1938 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) 1939 { 1940 struct amdgpu_device *adev = info->dev->dev_private; 1941 uint32_t r; 1942 1943 r = RREG32_IO(reg); 1944 return r; 1945 } 1946 1947 static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, 1948 struct device_attribute *attr, 1949 char *buf) 1950 { 1951 struct drm_device *ddev = dev_get_drvdata(dev); 1952 struct amdgpu_device *adev = ddev->dev_private; 1953 struct atom_context *ctx = adev->mode_info.atom_context; 1954 1955 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version); 1956 } 1957 1958 static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, 1959 NULL); 1960 1961 /** 1962 * amdgpu_atombios_fini - free the driver info and callbacks for atombios 1963 * 1964 * @adev: amdgpu_device pointer 1965 * 1966 * Frees the driver info and register access callbacks for the ATOM 1967 * interpreter (r4xx+). 1968 * Called at driver shutdown. 1969 */ 1970 void amdgpu_atombios_fini(struct amdgpu_device *adev) 1971 { 1972 if (adev->mode_info.atom_context) { 1973 kfree(adev->mode_info.atom_context->scratch); 1974 kfree(adev->mode_info.atom_context->iio); 1975 } 1976 kfree(adev->mode_info.atom_context); 1977 adev->mode_info.atom_context = NULL; 1978 kfree(adev->mode_info.atom_card_info); 1979 adev->mode_info.atom_card_info = NULL; 1980 device_remove_file(adev->dev, &dev_attr_vbios_version); 1981 } 1982 1983 /** 1984 * amdgpu_atombios_init - init the driver info and callbacks for atombios 1985 * 1986 * @adev: amdgpu_device pointer 1987 * 1988 * Initializes the driver info and register access callbacks for the 1989 * ATOM interpreter (r4xx+). 1990 * Returns 0 on sucess, -ENOMEM on failure. 1991 * Called at driver startup. 1992 */ 1993 int amdgpu_atombios_init(struct amdgpu_device *adev) 1994 { 1995 struct card_info *atom_card_info = 1996 kzalloc(sizeof(struct card_info), GFP_KERNEL); 1997 int ret; 1998 1999 if (!atom_card_info) 2000 return -ENOMEM; 2001 2002 adev->mode_info.atom_card_info = atom_card_info; 2003 atom_card_info->dev = adev->ddev; 2004 atom_card_info->reg_read = cail_reg_read; 2005 atom_card_info->reg_write = cail_reg_write; 2006 /* needed for iio ops */ 2007 if (adev->rio_mem) { 2008 atom_card_info->ioreg_read = cail_ioreg_read; 2009 atom_card_info->ioreg_write = cail_ioreg_write; 2010 } else { 2011 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n"); 2012 atom_card_info->ioreg_read = cail_reg_read; 2013 atom_card_info->ioreg_write = cail_reg_write; 2014 } 2015 atom_card_info->mc_read = cail_mc_read; 2016 atom_card_info->mc_write = cail_mc_write; 2017 atom_card_info->pll_read = cail_pll_read; 2018 atom_card_info->pll_write = cail_pll_write; 2019 2020 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios); 2021 if (!adev->mode_info.atom_context) { 2022 amdgpu_atombios_fini(adev); 2023 return -ENOMEM; 2024 } 2025 2026 mutex_init(&adev->mode_info.atom_context->mutex); 2027 if (adev->is_atom_fw) { 2028 amdgpu_atomfirmware_scratch_regs_init(adev); 2029 amdgpu_atomfirmware_allocate_fb_scratch(adev); 2030 ret = amdgpu_atomfirmware_get_mem_train_info(adev); 2031 if (ret) { 2032 DRM_ERROR("Failed to get mem train fb location.\n"); 2033 return ret; 2034 } 2035 } else { 2036 amdgpu_atombios_scratch_regs_init(adev); 2037 amdgpu_atombios_allocate_fb_scratch(adev); 2038 } 2039 2040 ret = device_create_file(adev->dev, &dev_attr_vbios_version); 2041 if (ret) { 2042 DRM_ERROR("Failed to create device file for VBIOS version\n"); 2043 return ret; 2044 } 2045 2046 return 0; 2047 } 2048 2049
Indexes created Tue Sep 30 11:09:46 GMT 2025