amdgpu_cik.c revision 1.2
1 /* $NetBSD: amdgpu_cik.c,v 1.2 2018/08/27 14:23:31 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_cik.c,v 1.2 2018/08/27 14:23:31 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include "drmP.h" 33 #include "amdgpu.h" 34 #include "amdgpu_atombios.h" 35 #include "amdgpu_ih.h" 36 #include "amdgpu_uvd.h" 37 #include "amdgpu_vce.h" 38 #include "cikd.h" 39 #include "atom.h" 40 41 #include "cik.h" 42 #include "gmc_v7_0.h" 43 #include "cik_ih.h" 44 #include "dce_v8_0.h" 45 #include "gfx_v7_0.h" 46 #include "cik_sdma.h" 47 #include "uvd_v4_2.h" 48 #include "vce_v2_0.h" 49 #include "cik_dpm.h" 50 51 #include "uvd/uvd_4_2_d.h" 52 53 #include "smu/smu_7_0_1_d.h" 54 #include "smu/smu_7_0_1_sh_mask.h" 55 56 #include "dce/dce_8_0_d.h" 57 #include "dce/dce_8_0_sh_mask.h" 58 59 #include "bif/bif_4_1_d.h" 60 #include "bif/bif_4_1_sh_mask.h" 61 62 #include "gca/gfx_7_2_d.h" 63 #include "gca/gfx_7_2_enum.h" 64 #include "gca/gfx_7_2_sh_mask.h" 65 66 #include "gmc/gmc_7_1_d.h" 67 #include "gmc/gmc_7_1_sh_mask.h" 68 69 #include "oss/oss_2_0_d.h" 70 #include "oss/oss_2_0_sh_mask.h" 71 72 #include "amdgpu_amdkfd.h" 73 74 /* 75 * Indirect registers accessor 76 */ 77 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) 78 { 79 unsigned long flags; 80 u32 r; 81 82 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 83 WREG32(mmPCIE_INDEX, reg); 84 (void)RREG32(mmPCIE_INDEX); 85 r = RREG32(mmPCIE_DATA); 86 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 87 return r; 88 } 89 90 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 91 { 92 unsigned long flags; 93 94 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 95 WREG32(mmPCIE_INDEX, reg); 96 (void)RREG32(mmPCIE_INDEX); 97 WREG32(mmPCIE_DATA, v); 98 (void)RREG32(mmPCIE_DATA); 99 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 100 } 101 102 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) 103 { 104 unsigned long flags; 105 u32 r; 106 107 spin_lock_irqsave(&adev->smc_idx_lock, flags); 108 WREG32(mmSMC_IND_INDEX_0, (reg)); 109 r = RREG32(mmSMC_IND_DATA_0); 110 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 111 return r; 112 } 113 114 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 115 { 116 unsigned long flags; 117 118 spin_lock_irqsave(&adev->smc_idx_lock, flags); 119 WREG32(mmSMC_IND_INDEX_0, (reg)); 120 WREG32(mmSMC_IND_DATA_0, (v)); 121 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 122 } 123 124 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 125 { 126 unsigned long flags; 127 u32 r; 128 129 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 130 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 131 r = RREG32(mmUVD_CTX_DATA); 132 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 133 return r; 134 } 135 136 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 137 { 138 unsigned long flags; 139 140 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 141 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 142 WREG32(mmUVD_CTX_DATA, (v)); 143 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 144 } 145 146 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) 147 { 148 unsigned long flags; 149 u32 r; 150 151 spin_lock_irqsave(&adev->didt_idx_lock, flags); 152 WREG32(mmDIDT_IND_INDEX, (reg)); 153 r = RREG32(mmDIDT_IND_DATA); 154 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 155 return r; 156 } 157 158 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 159 { 160 unsigned long flags; 161 162 spin_lock_irqsave(&adev->didt_idx_lock, flags); 163 WREG32(mmDIDT_IND_INDEX, (reg)); 164 WREG32(mmDIDT_IND_DATA, (v)); 165 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 166 } 167 168 static const u32 bonaire_golden_spm_registers[] = 169 { 170 0xc200, 0xe0ffffff, 0xe0000000 171 }; 172 173 static const u32 bonaire_golden_common_registers[] = 174 { 175 0x31dc, 0xffffffff, 0x00000800, 176 0x31dd, 0xffffffff, 0x00000800, 177 0x31e6, 0xffffffff, 0x00007fbf, 178 0x31e7, 0xffffffff, 0x00007faf 179 }; 180 181 static const u32 bonaire_golden_registers[] = 182 { 183 0xcd5, 0x00000333, 0x00000333, 184 0xcd4, 0x000c0fc0, 0x00040200, 185 0x2684, 0x00010000, 0x00058208, 186 0xf000, 0xffff1fff, 0x00140000, 187 0xf080, 0xfdfc0fff, 0x00000100, 188 0xf08d, 0x40000000, 0x40000200, 189 0x260c, 0xffffffff, 0x00000000, 190 0x260d, 0xf00fffff, 0x00000400, 191 0x260e, 0x0002021c, 0x00020200, 192 0x31e, 0x00000080, 0x00000000, 193 0x16ec, 0x000000f0, 0x00000070, 194 0x16f0, 0xf0311fff, 0x80300000, 195 0x263e, 0x73773777, 0x12010001, 196 0xd43, 0x00810000, 0x408af000, 197 0x1c0c, 0x31000111, 0x00000011, 198 0xbd2, 0x73773777, 0x12010001, 199 0x883, 0x00007fb6, 0x0021a1b1, 200 0x884, 0x00007fb6, 0x002021b1, 201 0x860, 0x00007fb6, 0x00002191, 202 0x886, 0x00007fb6, 0x002121b1, 203 0x887, 0x00007fb6, 0x002021b1, 204 0x877, 0x00007fb6, 0x00002191, 205 0x878, 0x00007fb6, 0x00002191, 206 0xd8a, 0x0000003f, 0x0000000a, 207 0xd8b, 0x0000003f, 0x0000000a, 208 0xab9, 0x00073ffe, 0x000022a2, 209 0x903, 0x000007ff, 0x00000000, 210 0x2285, 0xf000003f, 0x00000007, 211 0x22fc, 0x00002001, 0x00000001, 212 0x22c9, 0xffffffff, 0x00ffffff, 213 0xc281, 0x0000ff0f, 0x00000000, 214 0xa293, 0x07ffffff, 0x06000000, 215 0x136, 0x00000fff, 0x00000100, 216 0xf9e, 0x00000001, 0x00000002, 217 0x2440, 0x03000000, 0x0362c688, 218 0x2300, 0x000000ff, 0x00000001, 219 0x390, 0x00001fff, 0x00001fff, 220 0x2418, 0x0000007f, 0x00000020, 221 0x2542, 0x00010000, 0x00010000, 222 0x2b05, 0x000003ff, 0x000000f3, 223 0x2b03, 0xffffffff, 0x00001032 224 }; 225 226 static const u32 bonaire_mgcg_cgcg_init[] = 227 { 228 0x3108, 0xffffffff, 0xfffffffc, 229 0xc200, 0xffffffff, 0xe0000000, 230 0xf0a8, 0xffffffff, 0x00000100, 231 0xf082, 0xffffffff, 0x00000100, 232 0xf0b0, 0xffffffff, 0xc0000100, 233 0xf0b2, 0xffffffff, 0xc0000100, 234 0xf0b1, 0xffffffff, 0xc0000100, 235 0x1579, 0xffffffff, 0x00600100, 236 0xf0a0, 0xffffffff, 0x00000100, 237 0xf085, 0xffffffff, 0x06000100, 238 0xf088, 0xffffffff, 0x00000100, 239 0xf086, 0xffffffff, 0x06000100, 240 0xf081, 0xffffffff, 0x00000100, 241 0xf0b8, 0xffffffff, 0x00000100, 242 0xf089, 0xffffffff, 0x00000100, 243 0xf080, 0xffffffff, 0x00000100, 244 0xf08c, 0xffffffff, 0x00000100, 245 0xf08d, 0xffffffff, 0x00000100, 246 0xf094, 0xffffffff, 0x00000100, 247 0xf095, 0xffffffff, 0x00000100, 248 0xf096, 0xffffffff, 0x00000100, 249 0xf097, 0xffffffff, 0x00000100, 250 0xf098, 0xffffffff, 0x00000100, 251 0xf09f, 0xffffffff, 0x00000100, 252 0xf09e, 0xffffffff, 0x00000100, 253 0xf084, 0xffffffff, 0x06000100, 254 0xf0a4, 0xffffffff, 0x00000100, 255 0xf09d, 0xffffffff, 0x00000100, 256 0xf0ad, 0xffffffff, 0x00000100, 257 0xf0ac, 0xffffffff, 0x00000100, 258 0xf09c, 0xffffffff, 0x00000100, 259 0xc200, 0xffffffff, 0xe0000000, 260 0xf008, 0xffffffff, 0x00010000, 261 0xf009, 0xffffffff, 0x00030002, 262 0xf00a, 0xffffffff, 0x00040007, 263 0xf00b, 0xffffffff, 0x00060005, 264 0xf00c, 0xffffffff, 0x00090008, 265 0xf00d, 0xffffffff, 0x00010000, 266 0xf00e, 0xffffffff, 0x00030002, 267 0xf00f, 0xffffffff, 0x00040007, 268 0xf010, 0xffffffff, 0x00060005, 269 0xf011, 0xffffffff, 0x00090008, 270 0xf012, 0xffffffff, 0x00010000, 271 0xf013, 0xffffffff, 0x00030002, 272 0xf014, 0xffffffff, 0x00040007, 273 0xf015, 0xffffffff, 0x00060005, 274 0xf016, 0xffffffff, 0x00090008, 275 0xf017, 0xffffffff, 0x00010000, 276 0xf018, 0xffffffff, 0x00030002, 277 0xf019, 0xffffffff, 0x00040007, 278 0xf01a, 0xffffffff, 0x00060005, 279 0xf01b, 0xffffffff, 0x00090008, 280 0xf01c, 0xffffffff, 0x00010000, 281 0xf01d, 0xffffffff, 0x00030002, 282 0xf01e, 0xffffffff, 0x00040007, 283 0xf01f, 0xffffffff, 0x00060005, 284 0xf020, 0xffffffff, 0x00090008, 285 0xf021, 0xffffffff, 0x00010000, 286 0xf022, 0xffffffff, 0x00030002, 287 0xf023, 0xffffffff, 0x00040007, 288 0xf024, 0xffffffff, 0x00060005, 289 0xf025, 0xffffffff, 0x00090008, 290 0xf026, 0xffffffff, 0x00010000, 291 0xf027, 0xffffffff, 0x00030002, 292 0xf028, 0xffffffff, 0x00040007, 293 0xf029, 0xffffffff, 0x00060005, 294 0xf02a, 0xffffffff, 0x00090008, 295 0xf000, 0xffffffff, 0x96e00200, 296 0x21c2, 0xffffffff, 0x00900100, 297 0x3109, 0xffffffff, 0x0020003f, 298 0xe, 0xffffffff, 0x0140001c, 299 0xf, 0x000f0000, 0x000f0000, 300 0x88, 0xffffffff, 0xc060000c, 301 0x89, 0xc0000fff, 0x00000100, 302 0x3e4, 0xffffffff, 0x00000100, 303 0x3e6, 0x00000101, 0x00000000, 304 0x82a, 0xffffffff, 0x00000104, 305 0x1579, 0xff000fff, 0x00000100, 306 0xc33, 0xc0000fff, 0x00000104, 307 0x3079, 0x00000001, 0x00000001, 308 0x3403, 0xff000ff0, 0x00000100, 309 0x3603, 0xff000ff0, 0x00000100 310 }; 311 312 static const u32 spectre_golden_spm_registers[] = 313 { 314 0xc200, 0xe0ffffff, 0xe0000000 315 }; 316 317 static const u32 spectre_golden_common_registers[] = 318 { 319 0x31dc, 0xffffffff, 0x00000800, 320 0x31dd, 0xffffffff, 0x00000800, 321 0x31e6, 0xffffffff, 0x00007fbf, 322 0x31e7, 0xffffffff, 0x00007faf 323 }; 324 325 static const u32 spectre_golden_registers[] = 326 { 327 0xf000, 0xffff1fff, 0x96940200, 328 0xf003, 0xffff0001, 0xff000000, 329 0xf080, 0xfffc0fff, 0x00000100, 330 0x1bb6, 0x00010101, 0x00010000, 331 0x260d, 0xf00fffff, 0x00000400, 332 0x260e, 0xfffffffc, 0x00020200, 333 0x16ec, 0x000000f0, 0x00000070, 334 0x16f0, 0xf0311fff, 0x80300000, 335 0x263e, 0x73773777, 0x12010001, 336 0x26df, 0x00ff0000, 0x00fc0000, 337 0xbd2, 0x73773777, 0x12010001, 338 0x2285, 0xf000003f, 0x00000007, 339 0x22c9, 0xffffffff, 0x00ffffff, 340 0xa0d4, 0x3f3f3fff, 0x00000082, 341 0xa0d5, 0x0000003f, 0x00000000, 342 0xf9e, 0x00000001, 0x00000002, 343 0x244f, 0xffff03df, 0x00000004, 344 0x31da, 0x00000008, 0x00000008, 345 0x2300, 0x000008ff, 0x00000800, 346 0x2542, 0x00010000, 0x00010000, 347 0x2b03, 0xffffffff, 0x54763210, 348 0x853e, 0x01ff01ff, 0x00000002, 349 0x8526, 0x007ff800, 0x00200000, 350 0x8057, 0xffffffff, 0x00000f40, 351 0xc24d, 0xffffffff, 0x00000001 352 }; 353 354 static const u32 spectre_mgcg_cgcg_init[] = 355 { 356 0x3108, 0xffffffff, 0xfffffffc, 357 0xc200, 0xffffffff, 0xe0000000, 358 0xf0a8, 0xffffffff, 0x00000100, 359 0xf082, 0xffffffff, 0x00000100, 360 0xf0b0, 0xffffffff, 0x00000100, 361 0xf0b2, 0xffffffff, 0x00000100, 362 0xf0b1, 0xffffffff, 0x00000100, 363 0x1579, 0xffffffff, 0x00600100, 364 0xf0a0, 0xffffffff, 0x00000100, 365 0xf085, 0xffffffff, 0x06000100, 366 0xf088, 0xffffffff, 0x00000100, 367 0xf086, 0xffffffff, 0x06000100, 368 0xf081, 0xffffffff, 0x00000100, 369 0xf0b8, 0xffffffff, 0x00000100, 370 0xf089, 0xffffffff, 0x00000100, 371 0xf080, 0xffffffff, 0x00000100, 372 0xf08c, 0xffffffff, 0x00000100, 373 0xf08d, 0xffffffff, 0x00000100, 374 0xf094, 0xffffffff, 0x00000100, 375 0xf095, 0xffffffff, 0x00000100, 376 0xf096, 0xffffffff, 0x00000100, 377 0xf097, 0xffffffff, 0x00000100, 378 0xf098, 0xffffffff, 0x00000100, 379 0xf09f, 0xffffffff, 0x00000100, 380 0xf09e, 0xffffffff, 0x00000100, 381 0xf084, 0xffffffff, 0x06000100, 382 0xf0a4, 0xffffffff, 0x00000100, 383 0xf09d, 0xffffffff, 0x00000100, 384 0xf0ad, 0xffffffff, 0x00000100, 385 0xf0ac, 0xffffffff, 0x00000100, 386 0xf09c, 0xffffffff, 0x00000100, 387 0xc200, 0xffffffff, 0xe0000000, 388 0xf008, 0xffffffff, 0x00010000, 389 0xf009, 0xffffffff, 0x00030002, 390 0xf00a, 0xffffffff, 0x00040007, 391 0xf00b, 0xffffffff, 0x00060005, 392 0xf00c, 0xffffffff, 0x00090008, 393 0xf00d, 0xffffffff, 0x00010000, 394 0xf00e, 0xffffffff, 0x00030002, 395 0xf00f, 0xffffffff, 0x00040007, 396 0xf010, 0xffffffff, 0x00060005, 397 0xf011, 0xffffffff, 0x00090008, 398 0xf012, 0xffffffff, 0x00010000, 399 0xf013, 0xffffffff, 0x00030002, 400 0xf014, 0xffffffff, 0x00040007, 401 0xf015, 0xffffffff, 0x00060005, 402 0xf016, 0xffffffff, 0x00090008, 403 0xf017, 0xffffffff, 0x00010000, 404 0xf018, 0xffffffff, 0x00030002, 405 0xf019, 0xffffffff, 0x00040007, 406 0xf01a, 0xffffffff, 0x00060005, 407 0xf01b, 0xffffffff, 0x00090008, 408 0xf01c, 0xffffffff, 0x00010000, 409 0xf01d, 0xffffffff, 0x00030002, 410 0xf01e, 0xffffffff, 0x00040007, 411 0xf01f, 0xffffffff, 0x00060005, 412 0xf020, 0xffffffff, 0x00090008, 413 0xf021, 0xffffffff, 0x00010000, 414 0xf022, 0xffffffff, 0x00030002, 415 0xf023, 0xffffffff, 0x00040007, 416 0xf024, 0xffffffff, 0x00060005, 417 0xf025, 0xffffffff, 0x00090008, 418 0xf026, 0xffffffff, 0x00010000, 419 0xf027, 0xffffffff, 0x00030002, 420 0xf028, 0xffffffff, 0x00040007, 421 0xf029, 0xffffffff, 0x00060005, 422 0xf02a, 0xffffffff, 0x00090008, 423 0xf02b, 0xffffffff, 0x00010000, 424 0xf02c, 0xffffffff, 0x00030002, 425 0xf02d, 0xffffffff, 0x00040007, 426 0xf02e, 0xffffffff, 0x00060005, 427 0xf02f, 0xffffffff, 0x00090008, 428 0xf000, 0xffffffff, 0x96e00200, 429 0x21c2, 0xffffffff, 0x00900100, 430 0x3109, 0xffffffff, 0x0020003f, 431 0xe, 0xffffffff, 0x0140001c, 432 0xf, 0x000f0000, 0x000f0000, 433 0x88, 0xffffffff, 0xc060000c, 434 0x89, 0xc0000fff, 0x00000100, 435 0x3e4, 0xffffffff, 0x00000100, 436 0x3e6, 0x00000101, 0x00000000, 437 0x82a, 0xffffffff, 0x00000104, 438 0x1579, 0xff000fff, 0x00000100, 439 0xc33, 0xc0000fff, 0x00000104, 440 0x3079, 0x00000001, 0x00000001, 441 0x3403, 0xff000ff0, 0x00000100, 442 0x3603, 0xff000ff0, 0x00000100 443 }; 444 445 static const u32 kalindi_golden_spm_registers[] = 446 { 447 0xc200, 0xe0ffffff, 0xe0000000 448 }; 449 450 static const u32 kalindi_golden_common_registers[] = 451 { 452 0x31dc, 0xffffffff, 0x00000800, 453 0x31dd, 0xffffffff, 0x00000800, 454 0x31e6, 0xffffffff, 0x00007fbf, 455 0x31e7, 0xffffffff, 0x00007faf 456 }; 457 458 static const u32 kalindi_golden_registers[] = 459 { 460 0xf000, 0xffffdfff, 0x6e944040, 461 0x1579, 0xff607fff, 0xfc000100, 462 0xf088, 0xff000fff, 0x00000100, 463 0xf089, 0xff000fff, 0x00000100, 464 0xf080, 0xfffc0fff, 0x00000100, 465 0x1bb6, 0x00010101, 0x00010000, 466 0x260c, 0xffffffff, 0x00000000, 467 0x260d, 0xf00fffff, 0x00000400, 468 0x16ec, 0x000000f0, 0x00000070, 469 0x16f0, 0xf0311fff, 0x80300000, 470 0x263e, 0x73773777, 0x12010001, 471 0x263f, 0xffffffff, 0x00000010, 472 0x26df, 0x00ff0000, 0x00fc0000, 473 0x200c, 0x00001f0f, 0x0000100a, 474 0xbd2, 0x73773777, 0x12010001, 475 0x902, 0x000fffff, 0x000c007f, 476 0x2285, 0xf000003f, 0x00000007, 477 0x22c9, 0x3fff3fff, 0x00ffcfff, 478 0xc281, 0x0000ff0f, 0x00000000, 479 0xa293, 0x07ffffff, 0x06000000, 480 0x136, 0x00000fff, 0x00000100, 481 0xf9e, 0x00000001, 0x00000002, 482 0x31da, 0x00000008, 0x00000008, 483 0x2300, 0x000000ff, 0x00000003, 484 0x853e, 0x01ff01ff, 0x00000002, 485 0x8526, 0x007ff800, 0x00200000, 486 0x8057, 0xffffffff, 0x00000f40, 487 0x2231, 0x001f3ae3, 0x00000082, 488 0x2235, 0x0000001f, 0x00000010, 489 0xc24d, 0xffffffff, 0x00000000 490 }; 491 492 static const u32 kalindi_mgcg_cgcg_init[] = 493 { 494 0x3108, 0xffffffff, 0xfffffffc, 495 0xc200, 0xffffffff, 0xe0000000, 496 0xf0a8, 0xffffffff, 0x00000100, 497 0xf082, 0xffffffff, 0x00000100, 498 0xf0b0, 0xffffffff, 0x00000100, 499 0xf0b2, 0xffffffff, 0x00000100, 500 0xf0b1, 0xffffffff, 0x00000100, 501 0x1579, 0xffffffff, 0x00600100, 502 0xf0a0, 0xffffffff, 0x00000100, 503 0xf085, 0xffffffff, 0x06000100, 504 0xf088, 0xffffffff, 0x00000100, 505 0xf086, 0xffffffff, 0x06000100, 506 0xf081, 0xffffffff, 0x00000100, 507 0xf0b8, 0xffffffff, 0x00000100, 508 0xf089, 0xffffffff, 0x00000100, 509 0xf080, 0xffffffff, 0x00000100, 510 0xf08c, 0xffffffff, 0x00000100, 511 0xf08d, 0xffffffff, 0x00000100, 512 0xf094, 0xffffffff, 0x00000100, 513 0xf095, 0xffffffff, 0x00000100, 514 0xf096, 0xffffffff, 0x00000100, 515 0xf097, 0xffffffff, 0x00000100, 516 0xf098, 0xffffffff, 0x00000100, 517 0xf09f, 0xffffffff, 0x00000100, 518 0xf09e, 0xffffffff, 0x00000100, 519 0xf084, 0xffffffff, 0x06000100, 520 0xf0a4, 0xffffffff, 0x00000100, 521 0xf09d, 0xffffffff, 0x00000100, 522 0xf0ad, 0xffffffff, 0x00000100, 523 0xf0ac, 0xffffffff, 0x00000100, 524 0xf09c, 0xffffffff, 0x00000100, 525 0xc200, 0xffffffff, 0xe0000000, 526 0xf008, 0xffffffff, 0x00010000, 527 0xf009, 0xffffffff, 0x00030002, 528 0xf00a, 0xffffffff, 0x00040007, 529 0xf00b, 0xffffffff, 0x00060005, 530 0xf00c, 0xffffffff, 0x00090008, 531 0xf00d, 0xffffffff, 0x00010000, 532 0xf00e, 0xffffffff, 0x00030002, 533 0xf00f, 0xffffffff, 0x00040007, 534 0xf010, 0xffffffff, 0x00060005, 535 0xf011, 0xffffffff, 0x00090008, 536 0xf000, 0xffffffff, 0x96e00200, 537 0x21c2, 0xffffffff, 0x00900100, 538 0x3109, 0xffffffff, 0x0020003f, 539 0xe, 0xffffffff, 0x0140001c, 540 0xf, 0x000f0000, 0x000f0000, 541 0x88, 0xffffffff, 0xc060000c, 542 0x89, 0xc0000fff, 0x00000100, 543 0x82a, 0xffffffff, 0x00000104, 544 0x1579, 0xff000fff, 0x00000100, 545 0xc33, 0xc0000fff, 0x00000104, 546 0x3079, 0x00000001, 0x00000001, 547 0x3403, 0xff000ff0, 0x00000100, 548 0x3603, 0xff000ff0, 0x00000100 549 }; 550 551 static const u32 hawaii_golden_spm_registers[] = 552 { 553 0xc200, 0xe0ffffff, 0xe0000000 554 }; 555 556 static const u32 hawaii_golden_common_registers[] = 557 { 558 0xc200, 0xffffffff, 0xe0000000, 559 0xa0d4, 0xffffffff, 0x3a00161a, 560 0xa0d5, 0xffffffff, 0x0000002e, 561 0x2684, 0xffffffff, 0x00018208, 562 0x263e, 0xffffffff, 0x12011003 563 }; 564 565 static const u32 hawaii_golden_registers[] = 566 { 567 0xcd5, 0x00000333, 0x00000333, 568 0x2684, 0x00010000, 0x00058208, 569 0x260c, 0xffffffff, 0x00000000, 570 0x260d, 0xf00fffff, 0x00000400, 571 0x260e, 0x0002021c, 0x00020200, 572 0x31e, 0x00000080, 0x00000000, 573 0x16ec, 0x000000f0, 0x00000070, 574 0x16f0, 0xf0311fff, 0x80300000, 575 0xd43, 0x00810000, 0x408af000, 576 0x1c0c, 0x31000111, 0x00000011, 577 0xbd2, 0x73773777, 0x12010001, 578 0x848, 0x0000007f, 0x0000001b, 579 0x877, 0x00007fb6, 0x00002191, 580 0xd8a, 0x0000003f, 0x0000000a, 581 0xd8b, 0x0000003f, 0x0000000a, 582 0xab9, 0x00073ffe, 0x000022a2, 583 0x903, 0x000007ff, 0x00000000, 584 0x22fc, 0x00002001, 0x00000001, 585 0x22c9, 0xffffffff, 0x00ffffff, 586 0xc281, 0x0000ff0f, 0x00000000, 587 0xa293, 0x07ffffff, 0x06000000, 588 0xf9e, 0x00000001, 0x00000002, 589 0x31da, 0x00000008, 0x00000008, 590 0x31dc, 0x00000f00, 0x00000800, 591 0x31dd, 0x00000f00, 0x00000800, 592 0x31e6, 0x00ffffff, 0x00ff7fbf, 593 0x31e7, 0x00ffffff, 0x00ff7faf, 594 0x2300, 0x000000ff, 0x00000800, 595 0x390, 0x00001fff, 0x00001fff, 596 0x2418, 0x0000007f, 0x00000020, 597 0x2542, 0x00010000, 0x00010000, 598 0x2b80, 0x00100000, 0x000ff07c, 599 0x2b05, 0x000003ff, 0x0000000f, 600 0x2b04, 0xffffffff, 0x7564fdec, 601 0x2b03, 0xffffffff, 0x3120b9a8, 602 0x2b02, 0x20000000, 0x0f9c0000 603 }; 604 605 static const u32 hawaii_mgcg_cgcg_init[] = 606 { 607 0x3108, 0xffffffff, 0xfffffffd, 608 0xc200, 0xffffffff, 0xe0000000, 609 0xf0a8, 0xffffffff, 0x00000100, 610 0xf082, 0xffffffff, 0x00000100, 611 0xf0b0, 0xffffffff, 0x00000100, 612 0xf0b2, 0xffffffff, 0x00000100, 613 0xf0b1, 0xffffffff, 0x00000100, 614 0x1579, 0xffffffff, 0x00200100, 615 0xf0a0, 0xffffffff, 0x00000100, 616 0xf085, 0xffffffff, 0x06000100, 617 0xf088, 0xffffffff, 0x00000100, 618 0xf086, 0xffffffff, 0x06000100, 619 0xf081, 0xffffffff, 0x00000100, 620 0xf0b8, 0xffffffff, 0x00000100, 621 0xf089, 0xffffffff, 0x00000100, 622 0xf080, 0xffffffff, 0x00000100, 623 0xf08c, 0xffffffff, 0x00000100, 624 0xf08d, 0xffffffff, 0x00000100, 625 0xf094, 0xffffffff, 0x00000100, 626 0xf095, 0xffffffff, 0x00000100, 627 0xf096, 0xffffffff, 0x00000100, 628 0xf097, 0xffffffff, 0x00000100, 629 0xf098, 0xffffffff, 0x00000100, 630 0xf09f, 0xffffffff, 0x00000100, 631 0xf09e, 0xffffffff, 0x00000100, 632 0xf084, 0xffffffff, 0x06000100, 633 0xf0a4, 0xffffffff, 0x00000100, 634 0xf09d, 0xffffffff, 0x00000100, 635 0xf0ad, 0xffffffff, 0x00000100, 636 0xf0ac, 0xffffffff, 0x00000100, 637 0xf09c, 0xffffffff, 0x00000100, 638 0xc200, 0xffffffff, 0xe0000000, 639 0xf008, 0xffffffff, 0x00010000, 640 0xf009, 0xffffffff, 0x00030002, 641 0xf00a, 0xffffffff, 0x00040007, 642 0xf00b, 0xffffffff, 0x00060005, 643 0xf00c, 0xffffffff, 0x00090008, 644 0xf00d, 0xffffffff, 0x00010000, 645 0xf00e, 0xffffffff, 0x00030002, 646 0xf00f, 0xffffffff, 0x00040007, 647 0xf010, 0xffffffff, 0x00060005, 648 0xf011, 0xffffffff, 0x00090008, 649 0xf012, 0xffffffff, 0x00010000, 650 0xf013, 0xffffffff, 0x00030002, 651 0xf014, 0xffffffff, 0x00040007, 652 0xf015, 0xffffffff, 0x00060005, 653 0xf016, 0xffffffff, 0x00090008, 654 0xf017, 0xffffffff, 0x00010000, 655 0xf018, 0xffffffff, 0x00030002, 656 0xf019, 0xffffffff, 0x00040007, 657 0xf01a, 0xffffffff, 0x00060005, 658 0xf01b, 0xffffffff, 0x00090008, 659 0xf01c, 0xffffffff, 0x00010000, 660 0xf01d, 0xffffffff, 0x00030002, 661 0xf01e, 0xffffffff, 0x00040007, 662 0xf01f, 0xffffffff, 0x00060005, 663 0xf020, 0xffffffff, 0x00090008, 664 0xf021, 0xffffffff, 0x00010000, 665 0xf022, 0xffffffff, 0x00030002, 666 0xf023, 0xffffffff, 0x00040007, 667 0xf024, 0xffffffff, 0x00060005, 668 0xf025, 0xffffffff, 0x00090008, 669 0xf026, 0xffffffff, 0x00010000, 670 0xf027, 0xffffffff, 0x00030002, 671 0xf028, 0xffffffff, 0x00040007, 672 0xf029, 0xffffffff, 0x00060005, 673 0xf02a, 0xffffffff, 0x00090008, 674 0xf02b, 0xffffffff, 0x00010000, 675 0xf02c, 0xffffffff, 0x00030002, 676 0xf02d, 0xffffffff, 0x00040007, 677 0xf02e, 0xffffffff, 0x00060005, 678 0xf02f, 0xffffffff, 0x00090008, 679 0xf030, 0xffffffff, 0x00010000, 680 0xf031, 0xffffffff, 0x00030002, 681 0xf032, 0xffffffff, 0x00040007, 682 0xf033, 0xffffffff, 0x00060005, 683 0xf034, 0xffffffff, 0x00090008, 684 0xf035, 0xffffffff, 0x00010000, 685 0xf036, 0xffffffff, 0x00030002, 686 0xf037, 0xffffffff, 0x00040007, 687 0xf038, 0xffffffff, 0x00060005, 688 0xf039, 0xffffffff, 0x00090008, 689 0xf03a, 0xffffffff, 0x00010000, 690 0xf03b, 0xffffffff, 0x00030002, 691 0xf03c, 0xffffffff, 0x00040007, 692 0xf03d, 0xffffffff, 0x00060005, 693 0xf03e, 0xffffffff, 0x00090008, 694 0x30c6, 0xffffffff, 0x00020200, 695 0xcd4, 0xffffffff, 0x00000200, 696 0x570, 0xffffffff, 0x00000400, 697 0x157a, 0xffffffff, 0x00000000, 698 0xbd4, 0xffffffff, 0x00000902, 699 0xf000, 0xffffffff, 0x96940200, 700 0x21c2, 0xffffffff, 0x00900100, 701 0x3109, 0xffffffff, 0x0020003f, 702 0xe, 0xffffffff, 0x0140001c, 703 0xf, 0x000f0000, 0x000f0000, 704 0x88, 0xffffffff, 0xc060000c, 705 0x89, 0xc0000fff, 0x00000100, 706 0x3e4, 0xffffffff, 0x00000100, 707 0x3e6, 0x00000101, 0x00000000, 708 0x82a, 0xffffffff, 0x00000104, 709 0x1579, 0xff000fff, 0x00000100, 710 0xc33, 0xc0000fff, 0x00000104, 711 0x3079, 0x00000001, 0x00000001, 712 0x3403, 0xff000ff0, 0x00000100, 713 0x3603, 0xff000ff0, 0x00000100 714 }; 715 716 static const u32 godavari_golden_registers[] = 717 { 718 0x1579, 0xff607fff, 0xfc000100, 719 0x1bb6, 0x00010101, 0x00010000, 720 0x260c, 0xffffffff, 0x00000000, 721 0x260c0, 0xf00fffff, 0x00000400, 722 0x184c, 0xffffffff, 0x00010000, 723 0x16ec, 0x000000f0, 0x00000070, 724 0x16f0, 0xf0311fff, 0x80300000, 725 0x263e, 0x73773777, 0x12010001, 726 0x263f, 0xffffffff, 0x00000010, 727 0x200c, 0x00001f0f, 0x0000100a, 728 0xbd2, 0x73773777, 0x12010001, 729 0x902, 0x000fffff, 0x000c007f, 730 0x2285, 0xf000003f, 0x00000007, 731 0x22c9, 0xffffffff, 0x00ff0fff, 732 0xc281, 0x0000ff0f, 0x00000000, 733 0xa293, 0x07ffffff, 0x06000000, 734 0x136, 0x00000fff, 0x00000100, 735 0x3405, 0x00010000, 0x00810001, 736 0x3605, 0x00010000, 0x00810001, 737 0xf9e, 0x00000001, 0x00000002, 738 0x31da, 0x00000008, 0x00000008, 739 0x31dc, 0x00000f00, 0x00000800, 740 0x31dd, 0x00000f00, 0x00000800, 741 0x31e6, 0x00ffffff, 0x00ff7fbf, 742 0x31e7, 0x00ffffff, 0x00ff7faf, 743 0x2300, 0x000000ff, 0x00000001, 744 0x853e, 0x01ff01ff, 0x00000002, 745 0x8526, 0x007ff800, 0x00200000, 746 0x8057, 0xffffffff, 0x00000f40, 747 0x2231, 0x001f3ae3, 0x00000082, 748 0x2235, 0x0000001f, 0x00000010, 749 0xc24d, 0xffffffff, 0x00000000 750 }; 751 752 static void cik_init_golden_registers(struct amdgpu_device *adev) 753 { 754 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 755 mutex_lock(&adev->grbm_idx_mutex); 756 757 switch (adev->asic_type) { 758 case CHIP_BONAIRE: 759 amdgpu_program_register_sequence(adev, 760 bonaire_mgcg_cgcg_init, 761 (const u32)ARRAY_SIZE(bonaire_mgcg_cgcg_init)); 762 amdgpu_program_register_sequence(adev, 763 bonaire_golden_registers, 764 (const u32)ARRAY_SIZE(bonaire_golden_registers)); 765 amdgpu_program_register_sequence(adev, 766 bonaire_golden_common_registers, 767 (const u32)ARRAY_SIZE(bonaire_golden_common_registers)); 768 amdgpu_program_register_sequence(adev, 769 bonaire_golden_spm_registers, 770 (const u32)ARRAY_SIZE(bonaire_golden_spm_registers)); 771 break; 772 case CHIP_KABINI: 773 amdgpu_program_register_sequence(adev, 774 kalindi_mgcg_cgcg_init, 775 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 776 amdgpu_program_register_sequence(adev, 777 kalindi_golden_registers, 778 (const u32)ARRAY_SIZE(kalindi_golden_registers)); 779 amdgpu_program_register_sequence(adev, 780 kalindi_golden_common_registers, 781 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 782 amdgpu_program_register_sequence(adev, 783 kalindi_golden_spm_registers, 784 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 785 break; 786 case CHIP_MULLINS: 787 amdgpu_program_register_sequence(adev, 788 kalindi_mgcg_cgcg_init, 789 (const u32)ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 790 amdgpu_program_register_sequence(adev, 791 godavari_golden_registers, 792 (const u32)ARRAY_SIZE(godavari_golden_registers)); 793 amdgpu_program_register_sequence(adev, 794 kalindi_golden_common_registers, 795 (const u32)ARRAY_SIZE(kalindi_golden_common_registers)); 796 amdgpu_program_register_sequence(adev, 797 kalindi_golden_spm_registers, 798 (const u32)ARRAY_SIZE(kalindi_golden_spm_registers)); 799 break; 800 case CHIP_KAVERI: 801 amdgpu_program_register_sequence(adev, 802 spectre_mgcg_cgcg_init, 803 (const u32)ARRAY_SIZE(spectre_mgcg_cgcg_init)); 804 amdgpu_program_register_sequence(adev, 805 spectre_golden_registers, 806 (const u32)ARRAY_SIZE(spectre_golden_registers)); 807 amdgpu_program_register_sequence(adev, 808 spectre_golden_common_registers, 809 (const u32)ARRAY_SIZE(spectre_golden_common_registers)); 810 amdgpu_program_register_sequence(adev, 811 spectre_golden_spm_registers, 812 (const u32)ARRAY_SIZE(spectre_golden_spm_registers)); 813 break; 814 case CHIP_HAWAII: 815 amdgpu_program_register_sequence(adev, 816 hawaii_mgcg_cgcg_init, 817 (const u32)ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 818 amdgpu_program_register_sequence(adev, 819 hawaii_golden_registers, 820 (const u32)ARRAY_SIZE(hawaii_golden_registers)); 821 amdgpu_program_register_sequence(adev, 822 hawaii_golden_common_registers, 823 (const u32)ARRAY_SIZE(hawaii_golden_common_registers)); 824 amdgpu_program_register_sequence(adev, 825 hawaii_golden_spm_registers, 826 (const u32)ARRAY_SIZE(hawaii_golden_spm_registers)); 827 break; 828 default: 829 break; 830 } 831 mutex_unlock(&adev->grbm_idx_mutex); 832 } 833 834 /** 835 * cik_get_xclk - get the xclk 836 * 837 * @adev: amdgpu_device pointer 838 * 839 * Returns the reference clock used by the gfx engine 840 * (CIK). 841 */ 842 static u32 cik_get_xclk(struct amdgpu_device *adev) 843 { 844 u32 reference_clock = adev->clock.spll.reference_freq; 845 846 if (adev->flags & AMD_IS_APU) { 847 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) 848 return reference_clock / 2; 849 } else { 850 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 851 return reference_clock / 4; 852 } 853 return reference_clock; 854 } 855 856 /** 857 * cik_srbm_select - select specific register instances 858 * 859 * @adev: amdgpu_device pointer 860 * @me: selected ME (micro engine) 861 * @pipe: pipe 862 * @queue: queue 863 * @vmid: VMID 864 * 865 * Switches the currently active registers instances. Some 866 * registers are instanced per VMID, others are instanced per 867 * me/pipe/queue combination. 868 */ 869 void cik_srbm_select(struct amdgpu_device *adev, 870 u32 me, u32 pipe, u32 queue, u32 vmid) 871 { 872 u32 srbm_gfx_cntl = 873 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)| 874 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)| 875 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)| 876 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK)); 877 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 878 } 879 880 static void cik_vga_set_state(struct amdgpu_device *adev, bool state) 881 { 882 uint32_t tmp; 883 884 tmp = RREG32(mmCONFIG_CNTL); 885 if (state == false) 886 tmp |= CONFIG_CNTL__VGA_DIS_MASK; 887 else 888 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK; 889 WREG32(mmCONFIG_CNTL, tmp); 890 } 891 892 static bool cik_read_disabled_bios(struct amdgpu_device *adev) 893 { 894 u32 bus_cntl; 895 u32 d1vga_control = 0; 896 u32 d2vga_control = 0; 897 u32 vga_render_control = 0; 898 u32 rom_cntl; 899 bool r; 900 901 bus_cntl = RREG32(mmBUS_CNTL); 902 if (adev->mode_info.num_crtc) { 903 d1vga_control = RREG32(mmD1VGA_CONTROL); 904 d2vga_control = RREG32(mmD2VGA_CONTROL); 905 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 906 } 907 rom_cntl = RREG32_SMC(ixROM_CNTL); 908 909 /* enable the rom */ 910 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 911 if (adev->mode_info.num_crtc) { 912 /* Disable VGA mode */ 913 WREG32(mmD1VGA_CONTROL, 914 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 915 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 916 WREG32(mmD2VGA_CONTROL, 917 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 918 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 919 WREG32(mmVGA_RENDER_CONTROL, 920 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 921 } 922 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 923 924 r = amdgpu_read_bios(adev); 925 926 /* restore regs */ 927 WREG32(mmBUS_CNTL, bus_cntl); 928 if (adev->mode_info.num_crtc) { 929 WREG32(mmD1VGA_CONTROL, d1vga_control); 930 WREG32(mmD2VGA_CONTROL, d2vga_control); 931 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 932 } 933 WREG32_SMC(ixROM_CNTL, rom_cntl); 934 return r; 935 } 936 937 static struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { 938 {mmGRBM_STATUS, false}, 939 {mmGB_ADDR_CONFIG, false}, 940 {mmMC_ARB_RAMCFG, false}, 941 {mmGB_TILE_MODE0, false}, 942 {mmGB_TILE_MODE1, false}, 943 {mmGB_TILE_MODE2, false}, 944 {mmGB_TILE_MODE3, false}, 945 {mmGB_TILE_MODE4, false}, 946 {mmGB_TILE_MODE5, false}, 947 {mmGB_TILE_MODE6, false}, 948 {mmGB_TILE_MODE7, false}, 949 {mmGB_TILE_MODE8, false}, 950 {mmGB_TILE_MODE9, false}, 951 {mmGB_TILE_MODE10, false}, 952 {mmGB_TILE_MODE11, false}, 953 {mmGB_TILE_MODE12, false}, 954 {mmGB_TILE_MODE13, false}, 955 {mmGB_TILE_MODE14, false}, 956 {mmGB_TILE_MODE15, false}, 957 {mmGB_TILE_MODE16, false}, 958 {mmGB_TILE_MODE17, false}, 959 {mmGB_TILE_MODE18, false}, 960 {mmGB_TILE_MODE19, false}, 961 {mmGB_TILE_MODE20, false}, 962 {mmGB_TILE_MODE21, false}, 963 {mmGB_TILE_MODE22, false}, 964 {mmGB_TILE_MODE23, false}, 965 {mmGB_TILE_MODE24, false}, 966 {mmGB_TILE_MODE25, false}, 967 {mmGB_TILE_MODE26, false}, 968 {mmGB_TILE_MODE27, false}, 969 {mmGB_TILE_MODE28, false}, 970 {mmGB_TILE_MODE29, false}, 971 {mmGB_TILE_MODE30, false}, 972 {mmGB_TILE_MODE31, false}, 973 {mmGB_MACROTILE_MODE0, false}, 974 {mmGB_MACROTILE_MODE1, false}, 975 {mmGB_MACROTILE_MODE2, false}, 976 {mmGB_MACROTILE_MODE3, false}, 977 {mmGB_MACROTILE_MODE4, false}, 978 {mmGB_MACROTILE_MODE5, false}, 979 {mmGB_MACROTILE_MODE6, false}, 980 {mmGB_MACROTILE_MODE7, false}, 981 {mmGB_MACROTILE_MODE8, false}, 982 {mmGB_MACROTILE_MODE9, false}, 983 {mmGB_MACROTILE_MODE10, false}, 984 {mmGB_MACROTILE_MODE11, false}, 985 {mmGB_MACROTILE_MODE12, false}, 986 {mmGB_MACROTILE_MODE13, false}, 987 {mmGB_MACROTILE_MODE14, false}, 988 {mmGB_MACROTILE_MODE15, false}, 989 {mmCC_RB_BACKEND_DISABLE, false, true}, 990 {mmGC_USER_RB_BACKEND_DISABLE, false, true}, 991 {mmGB_BACKEND_MAP, false, false}, 992 {mmPA_SC_RASTER_CONFIG, false, true}, 993 {mmPA_SC_RASTER_CONFIG_1, false, true}, 994 }; 995 996 static uint32_t cik_read_indexed_register(struct amdgpu_device *adev, 997 u32 se_num, u32 sh_num, 998 u32 reg_offset) 999 { 1000 uint32_t val; 1001 1002 mutex_lock(&adev->grbm_idx_mutex); 1003 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1004 gfx_v7_0_select_se_sh(adev, se_num, sh_num); 1005 1006 val = RREG32(reg_offset); 1007 1008 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1009 gfx_v7_0_select_se_sh(adev, 0xffffffff, 0xffffffff); 1010 mutex_unlock(&adev->grbm_idx_mutex); 1011 return val; 1012 } 1013 1014 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, 1015 u32 sh_num, u32 reg_offset, u32 *value) 1016 { 1017 uint32_t i; 1018 1019 *value = 0; 1020 for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) { 1021 if (reg_offset != cik_allowed_read_registers[i].reg_offset) 1022 continue; 1023 1024 if (!cik_allowed_read_registers[i].untouched) 1025 *value = cik_allowed_read_registers[i].grbm_indexed ? 1026 cik_read_indexed_register(adev, se_num, 1027 sh_num, reg_offset) : 1028 RREG32(reg_offset); 1029 return 0; 1030 } 1031 return -EINVAL; 1032 } 1033 1034 static void cik_print_gpu_status_regs(struct amdgpu_device *adev) 1035 { 1036 dev_info(adev->dev, " GRBM_STATUS=0x%08X\n", 1037 RREG32(mmGRBM_STATUS)); 1038 dev_info(adev->dev, " GRBM_STATUS2=0x%08X\n", 1039 RREG32(mmGRBM_STATUS2)); 1040 dev_info(adev->dev, " GRBM_STATUS_SE0=0x%08X\n", 1041 RREG32(mmGRBM_STATUS_SE0)); 1042 dev_info(adev->dev, " GRBM_STATUS_SE1=0x%08X\n", 1043 RREG32(mmGRBM_STATUS_SE1)); 1044 dev_info(adev->dev, " GRBM_STATUS_SE2=0x%08X\n", 1045 RREG32(mmGRBM_STATUS_SE2)); 1046 dev_info(adev->dev, " GRBM_STATUS_SE3=0x%08X\n", 1047 RREG32(mmGRBM_STATUS_SE3)); 1048 dev_info(adev->dev, " SRBM_STATUS=0x%08X\n", 1049 RREG32(mmSRBM_STATUS)); 1050 dev_info(adev->dev, " SRBM_STATUS2=0x%08X\n", 1051 RREG32(mmSRBM_STATUS2)); 1052 dev_info(adev->dev, " SDMA0_STATUS_REG = 0x%08X\n", 1053 RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET)); 1054 dev_info(adev->dev, " SDMA1_STATUS_REG = 0x%08X\n", 1055 RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET)); 1056 dev_info(adev->dev, " CP_STAT = 0x%08x\n", RREG32(mmCP_STAT)); 1057 dev_info(adev->dev, " CP_STALLED_STAT1 = 0x%08x\n", 1058 RREG32(mmCP_STALLED_STAT1)); 1059 dev_info(adev->dev, " CP_STALLED_STAT2 = 0x%08x\n", 1060 RREG32(mmCP_STALLED_STAT2)); 1061 dev_info(adev->dev, " CP_STALLED_STAT3 = 0x%08x\n", 1062 RREG32(mmCP_STALLED_STAT3)); 1063 dev_info(adev->dev, " CP_CPF_BUSY_STAT = 0x%08x\n", 1064 RREG32(mmCP_CPF_BUSY_STAT)); 1065 dev_info(adev->dev, " CP_CPF_STALLED_STAT1 = 0x%08x\n", 1066 RREG32(mmCP_CPF_STALLED_STAT1)); 1067 dev_info(adev->dev, " CP_CPF_STATUS = 0x%08x\n", RREG32(mmCP_CPF_STATUS)); 1068 dev_info(adev->dev, " CP_CPC_BUSY_STAT = 0x%08x\n", RREG32(mmCP_CPC_BUSY_STAT)); 1069 dev_info(adev->dev, " CP_CPC_STALLED_STAT1 = 0x%08x\n", 1070 RREG32(mmCP_CPC_STALLED_STAT1)); 1071 dev_info(adev->dev, " CP_CPC_STATUS = 0x%08x\n", RREG32(mmCP_CPC_STATUS)); 1072 } 1073 1074 /** 1075 * cik_gpu_check_soft_reset - check which blocks are busy 1076 * 1077 * @adev: amdgpu_device pointer 1078 * 1079 * Check which blocks are busy and return the relevant reset 1080 * mask to be used by cik_gpu_soft_reset(). 1081 * Returns a mask of the blocks to be reset. 1082 */ 1083 u32 amdgpu_cik_gpu_check_soft_reset(struct amdgpu_device *adev) 1084 { 1085 u32 reset_mask = 0; 1086 u32 tmp; 1087 1088 /* GRBM_STATUS */ 1089 tmp = RREG32(mmGRBM_STATUS); 1090 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK | 1091 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK | 1092 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK | 1093 GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK | 1094 GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK | 1095 GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) 1096 reset_mask |= AMDGPU_RESET_GFX; 1097 1098 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) 1099 reset_mask |= AMDGPU_RESET_CP; 1100 1101 /* GRBM_STATUS2 */ 1102 tmp = RREG32(mmGRBM_STATUS2); 1103 if (tmp & GRBM_STATUS2__RLC_BUSY_MASK) 1104 reset_mask |= AMDGPU_RESET_RLC; 1105 1106 /* SDMA0_STATUS_REG */ 1107 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET); 1108 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1109 reset_mask |= AMDGPU_RESET_DMA; 1110 1111 /* SDMA1_STATUS_REG */ 1112 tmp = RREG32(mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET); 1113 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK)) 1114 reset_mask |= AMDGPU_RESET_DMA1; 1115 1116 /* SRBM_STATUS2 */ 1117 tmp = RREG32(mmSRBM_STATUS2); 1118 if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) 1119 reset_mask |= AMDGPU_RESET_DMA; 1120 1121 if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) 1122 reset_mask |= AMDGPU_RESET_DMA1; 1123 1124 /* SRBM_STATUS */ 1125 tmp = RREG32(mmSRBM_STATUS); 1126 1127 if (tmp & SRBM_STATUS__IH_BUSY_MASK) 1128 reset_mask |= AMDGPU_RESET_IH; 1129 1130 if (tmp & SRBM_STATUS__SEM_BUSY_MASK) 1131 reset_mask |= AMDGPU_RESET_SEM; 1132 1133 if (tmp & SRBM_STATUS__GRBM_RQ_PENDING_MASK) 1134 reset_mask |= AMDGPU_RESET_GRBM; 1135 1136 if (tmp & SRBM_STATUS__VMC_BUSY_MASK) 1137 reset_mask |= AMDGPU_RESET_VMC; 1138 1139 if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | 1140 SRBM_STATUS__MCC_BUSY_MASK | SRBM_STATUS__MCD_BUSY_MASK)) 1141 reset_mask |= AMDGPU_RESET_MC; 1142 1143 if (amdgpu_display_is_display_hung(adev)) 1144 reset_mask |= AMDGPU_RESET_DISPLAY; 1145 1146 /* Skip MC reset as it's mostly likely not hung, just busy */ 1147 if (reset_mask & AMDGPU_RESET_MC) { 1148 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask); 1149 reset_mask &= ~AMDGPU_RESET_MC; 1150 } 1151 1152 return reset_mask; 1153 } 1154 1155 /** 1156 * cik_gpu_soft_reset - soft reset GPU 1157 * 1158 * @adev: amdgpu_device pointer 1159 * @reset_mask: mask of which blocks to reset 1160 * 1161 * Soft reset the blocks specified in @reset_mask. 1162 */ 1163 static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) 1164 { 1165 struct amdgpu_mode_mc_save save; 1166 u32 grbm_soft_reset = 0, srbm_soft_reset = 0; 1167 u32 tmp; 1168 1169 if (reset_mask == 0) 1170 return; 1171 1172 dev_info(adev->dev, "GPU softreset: 0x%08X\n", reset_mask); 1173 1174 cik_print_gpu_status_regs(adev); 1175 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n", 1176 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_ADDR)); 1177 dev_info(adev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n", 1178 RREG32(mmVM_CONTEXT1_PROTECTION_FAULT_STATUS)); 1179 1180 /* disable CG/PG */ 1181 1182 /* stop the rlc */ 1183 gfx_v7_0_rlc_stop(adev); 1184 1185 /* Disable GFX parsing/prefetching */ 1186 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1187 1188 /* Disable MEC parsing/prefetching */ 1189 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1190 1191 if (reset_mask & AMDGPU_RESET_DMA) { 1192 /* sdma0 */ 1193 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1194 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1195 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1196 } 1197 if (reset_mask & AMDGPU_RESET_DMA1) { 1198 /* sdma1 */ 1199 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1200 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1201 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1202 } 1203 1204 gmc_v7_0_mc_stop(adev, &save); 1205 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1206 dev_warn(adev->dev, "Wait for MC idle timedout !\n"); 1207 } 1208 1209 if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) 1210 grbm_soft_reset = GRBM_SOFT_RESET__SOFT_RESET_CP_MASK | 1211 GRBM_SOFT_RESET__SOFT_RESET_GFX_MASK; 1212 1213 if (reset_mask & AMDGPU_RESET_CP) { 1214 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_CP_MASK; 1215 1216 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1217 } 1218 1219 if (reset_mask & AMDGPU_RESET_DMA) 1220 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK; 1221 1222 if (reset_mask & AMDGPU_RESET_DMA1) 1223 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK; 1224 1225 if (reset_mask & AMDGPU_RESET_DISPLAY) 1226 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; 1227 1228 if (reset_mask & AMDGPU_RESET_RLC) 1229 grbm_soft_reset |= GRBM_SOFT_RESET__SOFT_RESET_RLC_MASK; 1230 1231 if (reset_mask & AMDGPU_RESET_SEM) 1232 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SEM_MASK; 1233 1234 if (reset_mask & AMDGPU_RESET_IH) 1235 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_IH_MASK; 1236 1237 if (reset_mask & AMDGPU_RESET_GRBM) 1238 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_GRBM_MASK; 1239 1240 if (reset_mask & AMDGPU_RESET_VMC) 1241 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; 1242 1243 if (!(adev->flags & AMD_IS_APU)) { 1244 if (reset_mask & AMDGPU_RESET_MC) 1245 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; 1246 } 1247 1248 if (grbm_soft_reset) { 1249 tmp = RREG32(mmGRBM_SOFT_RESET); 1250 tmp |= grbm_soft_reset; 1251 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp); 1252 WREG32(mmGRBM_SOFT_RESET, tmp); 1253 tmp = RREG32(mmGRBM_SOFT_RESET); 1254 1255 udelay(50); 1256 1257 tmp &= ~grbm_soft_reset; 1258 WREG32(mmGRBM_SOFT_RESET, tmp); 1259 tmp = RREG32(mmGRBM_SOFT_RESET); 1260 } 1261 1262 if (srbm_soft_reset) { 1263 tmp = RREG32(mmSRBM_SOFT_RESET); 1264 tmp |= srbm_soft_reset; 1265 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp); 1266 WREG32(mmSRBM_SOFT_RESET, tmp); 1267 tmp = RREG32(mmSRBM_SOFT_RESET); 1268 1269 udelay(50); 1270 1271 tmp &= ~srbm_soft_reset; 1272 WREG32(mmSRBM_SOFT_RESET, tmp); 1273 tmp = RREG32(mmSRBM_SOFT_RESET); 1274 } 1275 1276 /* Wait a little for things to settle down */ 1277 udelay(50); 1278 1279 gmc_v7_0_mc_resume(adev, &save); 1280 udelay(50); 1281 1282 cik_print_gpu_status_regs(adev); 1283 } 1284 1285 struct kv_reset_save_regs { 1286 u32 gmcon_reng_execute; 1287 u32 gmcon_misc; 1288 u32 gmcon_misc3; 1289 }; 1290 1291 static void kv_save_regs_for_reset(struct amdgpu_device *adev, 1292 struct kv_reset_save_regs *save) 1293 { 1294 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); 1295 save->gmcon_misc = RREG32(mmGMCON_MISC); 1296 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); 1297 1298 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & 1299 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK); 1300 WREG32(mmGMCON_MISC, save->gmcon_misc & 1301 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK | 1302 GMCON_MISC__STCTRL_STUTTER_EN_MASK)); 1303 } 1304 1305 static void kv_restore_regs_for_reset(struct amdgpu_device *adev, 1306 struct kv_reset_save_regs *save) 1307 { 1308 int i; 1309 1310 WREG32(mmGMCON_PGFSM_WRITE, 0); 1311 WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); 1312 1313 for (i = 0; i < 5; i++) 1314 WREG32(mmGMCON_PGFSM_WRITE, 0); 1315 1316 WREG32(mmGMCON_PGFSM_WRITE, 0); 1317 WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); 1318 1319 for (i = 0; i < 5; i++) 1320 WREG32(mmGMCON_PGFSM_WRITE, 0); 1321 1322 WREG32(mmGMCON_PGFSM_WRITE, 0x210000); 1323 WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); 1324 1325 for (i = 0; i < 5; i++) 1326 WREG32(mmGMCON_PGFSM_WRITE, 0); 1327 1328 WREG32(mmGMCON_PGFSM_WRITE, 0x21003); 1329 WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); 1330 1331 for (i = 0; i < 5; i++) 1332 WREG32(mmGMCON_PGFSM_WRITE, 0); 1333 1334 WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); 1335 WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); 1336 1337 for (i = 0; i < 5; i++) 1338 WREG32(mmGMCON_PGFSM_WRITE, 0); 1339 1340 WREG32(mmGMCON_PGFSM_WRITE, 0); 1341 WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); 1342 1343 for (i = 0; i < 5; i++) 1344 WREG32(mmGMCON_PGFSM_WRITE, 0); 1345 1346 WREG32(mmGMCON_PGFSM_WRITE, 0x420000); 1347 WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); 1348 1349 for (i = 0; i < 5; i++) 1350 WREG32(mmGMCON_PGFSM_WRITE, 0); 1351 1352 WREG32(mmGMCON_PGFSM_WRITE, 0x120202); 1353 WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); 1354 1355 for (i = 0; i < 5; i++) 1356 WREG32(mmGMCON_PGFSM_WRITE, 0); 1357 1358 WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); 1359 WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); 1360 1361 for (i = 0; i < 5; i++) 1362 WREG32(mmGMCON_PGFSM_WRITE, 0); 1363 1364 WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); 1365 WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); 1366 1367 for (i = 0; i < 5; i++) 1368 WREG32(mmGMCON_PGFSM_WRITE, 0); 1369 1370 WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); 1371 WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); 1372 1373 WREG32(mmGMCON_MISC3, save->gmcon_misc3); 1374 WREG32(mmGMCON_MISC, save->gmcon_misc); 1375 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); 1376 } 1377 1378 static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) 1379 { 1380 struct amdgpu_mode_mc_save save; 1381 struct kv_reset_save_regs kv_save = { 0 }; 1382 u32 tmp, i; 1383 1384 dev_info(adev->dev, "GPU pci config reset\n"); 1385 1386 /* disable dpm? */ 1387 1388 /* disable cg/pg */ 1389 1390 /* Disable GFX parsing/prefetching */ 1391 WREG32(mmCP_ME_CNTL, CP_ME_CNTL__ME_HALT_MASK | 1392 CP_ME_CNTL__PFP_HALT_MASK | CP_ME_CNTL__CE_HALT_MASK); 1393 1394 /* Disable MEC parsing/prefetching */ 1395 WREG32(mmCP_MEC_CNTL, 1396 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); 1397 1398 /* sdma0 */ 1399 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET); 1400 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1401 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp); 1402 /* sdma1 */ 1403 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET); 1404 tmp |= SDMA0_F32_CNTL__HALT_MASK; 1405 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp); 1406 /* XXX other engines? */ 1407 1408 /* halt the rlc, disable cp internal ints */ 1409 gfx_v7_0_rlc_stop(adev); 1410 1411 udelay(50); 1412 1413 /* disable mem access */ 1414 gmc_v7_0_mc_stop(adev, &save); 1415 if (amdgpu_asic_wait_for_mc_idle(adev)) { 1416 dev_warn(adev->dev, "Wait for MC idle timed out !\n"); 1417 } 1418 1419 if (adev->flags & AMD_IS_APU) 1420 kv_save_regs_for_reset(adev, &kv_save); 1421 1422 /* disable BM */ 1423 pci_clear_master(adev->pdev); 1424 /* reset */ 1425 amdgpu_pci_config_reset(adev); 1426 1427 udelay(100); 1428 1429 /* wait for asic to come out of reset */ 1430 for (i = 0; i < adev->usec_timeout; i++) { 1431 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) 1432 break; 1433 udelay(1); 1434 } 1435 1436 /* does asic init need to be run first??? */ 1437 if (adev->flags & AMD_IS_APU) 1438 kv_restore_regs_for_reset(adev, &kv_save); 1439 } 1440 1441 static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung) 1442 { 1443 u32 tmp = RREG32(mmBIOS_SCRATCH_3); 1444 1445 if (hung) 1446 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1447 else 1448 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG; 1449 1450 WREG32(mmBIOS_SCRATCH_3, tmp); 1451 } 1452 1453 /** 1454 * cik_asic_reset - soft reset GPU 1455 * 1456 * @adev: amdgpu_device pointer 1457 * 1458 * Look up which blocks are hung and attempt 1459 * to reset them. 1460 * Returns 0 for success. 1461 */ 1462 static int cik_asic_reset(struct amdgpu_device *adev) 1463 { 1464 u32 reset_mask; 1465 1466 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1467 1468 if (reset_mask) 1469 cik_set_bios_scratch_engine_hung(adev, true); 1470 1471 /* try soft reset */ 1472 cik_gpu_soft_reset(adev, reset_mask); 1473 1474 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1475 1476 /* try pci config reset */ 1477 if (reset_mask && amdgpu_hard_reset) 1478 cik_gpu_pci_config_reset(adev); 1479 1480 reset_mask = amdgpu_cik_gpu_check_soft_reset(adev); 1481 1482 if (!reset_mask) 1483 cik_set_bios_scratch_engine_hung(adev, false); 1484 1485 return 0; 1486 } 1487 1488 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 1489 u32 cntl_reg, u32 status_reg) 1490 { 1491 int r, i; 1492 struct atom_clock_dividers dividers; 1493 uint32_t tmp; 1494 1495 r = amdgpu_atombios_get_clock_dividers(adev, 1496 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1497 clock, false, ÷rs); 1498 if (r) 1499 return r; 1500 1501 tmp = RREG32_SMC(cntl_reg); 1502 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 1503 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 1504 tmp |= dividers.post_divider; 1505 WREG32_SMC(cntl_reg, tmp); 1506 1507 for (i = 0; i < 100; i++) { 1508 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1509 break; 1510 mdelay(10); 1511 } 1512 if (i == 100) 1513 return -ETIMEDOUT; 1514 1515 return 0; 1516 } 1517 1518 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1519 { 1520 int r = 0; 1521 1522 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1523 if (r) 1524 return r; 1525 1526 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1527 return r; 1528 } 1529 1530 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1531 { 1532 int r, i; 1533 struct atom_clock_dividers dividers; 1534 u32 tmp; 1535 1536 r = amdgpu_atombios_get_clock_dividers(adev, 1537 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1538 ecclk, false, ÷rs); 1539 if (r) 1540 return r; 1541 1542 for (i = 0; i < 100; i++) { 1543 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1544 break; 1545 mdelay(10); 1546 } 1547 if (i == 100) 1548 return -ETIMEDOUT; 1549 1550 tmp = RREG32_SMC(ixCG_ECLK_CNTL); 1551 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | 1552 CG_ECLK_CNTL__ECLK_DIVIDER_MASK); 1553 tmp |= dividers.post_divider; 1554 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 1555 1556 for (i = 0; i < 100; i++) { 1557 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1558 break; 1559 mdelay(10); 1560 } 1561 if (i == 100) 1562 return -ETIMEDOUT; 1563 1564 return 0; 1565 } 1566 1567 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1568 { 1569 #ifndef __NetBSD__ /* XXX amdgpu pcie */ 1570 struct pci_dev *root = adev->pdev->bus->self; 1571 int bridge_pos, gpu_pos; 1572 u32 speed_cntl, mask, current_data_rate; 1573 int ret, i; 1574 u16 tmp16; 1575 1576 if (pci_is_root_bus(adev->pdev->bus)) 1577 return; 1578 1579 if (amdgpu_pcie_gen2 == 0) 1580 return; 1581 1582 if (adev->flags & AMD_IS_APU) 1583 return; 1584 1585 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); 1586 if (ret != 0) 1587 return; 1588 1589 if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) 1590 return; 1591 1592 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1593 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> 1594 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 1595 if (mask & DRM_PCIE_SPEED_80) { 1596 if (current_data_rate == 2) { 1597 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1598 return; 1599 } 1600 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1601 } else if (mask & DRM_PCIE_SPEED_50) { 1602 if (current_data_rate == 1) { 1603 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1604 return; 1605 } 1606 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1607 } 1608 1609 bridge_pos = pci_pcie_cap(root); 1610 if (!bridge_pos) 1611 return; 1612 1613 gpu_pos = pci_pcie_cap(adev->pdev); 1614 if (!gpu_pos) 1615 return; 1616 1617 if (mask & DRM_PCIE_SPEED_80) { 1618 /* re-try equalization if gen3 is not already enabled */ 1619 if (current_data_rate != 2) { 1620 u16 bridge_cfg, gpu_cfg; 1621 u16 bridge_cfg2, gpu_cfg2; 1622 u32 max_lw, current_lw, tmp; 1623 1624 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1625 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1626 1627 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1628 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1629 1630 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1631 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1632 1633 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1634 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> 1635 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; 1636 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) 1637 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; 1638 1639 if (current_lw < max_lw) { 1640 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1641 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { 1642 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | 1643 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); 1644 tmp |= (max_lw << 1645 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); 1646 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | 1647 PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | 1648 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; 1649 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); 1650 } 1651 } 1652 1653 for (i = 0; i < 10; i++) { 1654 /* check status */ 1655 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_DEVSTA, &tmp16); 1656 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1657 break; 1658 1659 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &bridge_cfg); 1660 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &gpu_cfg); 1661 1662 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &bridge_cfg2); 1663 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &gpu_cfg2); 1664 1665 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1666 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1667 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1668 1669 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1670 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; 1671 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1672 1673 mdelay(100); 1674 1675 /* linkctl */ 1676 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL, &tmp16); 1677 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1678 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1679 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL, tmp16); 1680 1681 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, &tmp16); 1682 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1683 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1684 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16); 1685 1686 /* linkctl2 */ 1687 pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16); 1688 tmp16 &= ~((1 << 4) | (7 << 9)); 1689 tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 9))); 1690 pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16); 1691 1692 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1693 tmp16 &= ~((1 << 4) | (7 << 9)); 1694 tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 9))); 1695 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1696 1697 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1698 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1699 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1700 } 1701 } 1702 } 1703 1704 /* set the link speed */ 1705 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | 1706 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; 1707 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1708 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1709 1710 pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); 1711 tmp16 &= ~0xf; 1712 if (mask & DRM_PCIE_SPEED_80) 1713 tmp16 |= 3; /* gen3 */ 1714 else if (mask & DRM_PCIE_SPEED_50) 1715 tmp16 |= 2; /* gen2 */ 1716 else 1717 tmp16 |= 1; /* gen1 */ 1718 pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16); 1719 1720 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1721 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; 1722 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1723 1724 for (i = 0; i < adev->usec_timeout; i++) { 1725 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1726 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) 1727 break; 1728 udelay(1); 1729 } 1730 #endif 1731 } 1732 1733 static void cik_program_aspm(struct amdgpu_device *adev) 1734 { 1735 u32 data, orig; 1736 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1737 bool disable_clkreq = false; 1738 1739 if (amdgpu_aspm == 0) 1740 return; 1741 1742 /* XXX double check APUs */ 1743 if (adev->flags & AMD_IS_APU) 1744 return; 1745 1746 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1747 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1748 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | 1749 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1750 if (orig != data) 1751 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1752 1753 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1754 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1755 if (orig != data) 1756 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1757 1758 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1759 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1760 if (orig != data) 1761 WREG32_PCIE(ixPCIE_P_CNTL, data); 1762 1763 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1764 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | 1765 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 1766 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1767 if (!disable_l0s) 1768 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); 1769 1770 if (!disable_l1) { 1771 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); 1772 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1773 if (orig != data) 1774 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1775 1776 if (!disable_plloff_in_l1) { 1777 bool clk_req_support; 1778 1779 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0); 1780 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1781 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1782 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1783 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1784 if (orig != data) 1785 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data); 1786 1787 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1); 1788 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1789 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1790 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1791 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1792 if (orig != data) 1793 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data); 1794 1795 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0); 1796 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1797 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1798 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1799 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1800 if (orig != data) 1801 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data); 1802 1803 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1); 1804 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1805 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1806 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1807 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1808 if (orig != data) 1809 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data); 1810 1811 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1812 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1813 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); 1814 if (orig != data) 1815 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1816 1817 if (!disable_clkreq) { 1818 #ifdef __NetBSD__ /* XXX amdgpu pcie */ 1819 clk_req_support = false; 1820 #else 1821 struct pci_dev *root = adev->pdev->bus->self; 1822 u32 lnkcap; 1823 1824 clk_req_support = false; 1825 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 1826 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 1827 clk_req_support = true; 1828 #endif 1829 } else { 1830 clk_req_support = false; 1831 } 1832 1833 if (clk_req_support) { 1834 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1835 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 1836 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1837 if (orig != data) 1838 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1839 1840 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1841 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | 1842 THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1843 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1844 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1845 if (orig != data) 1846 WREG32_SMC(ixTHM_CLK_CNTL, data); 1847 1848 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1849 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1850 MISC_CLK_CTRL__ZCLK_SEL_MASK); 1851 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1852 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1853 if (orig != data) 1854 WREG32_SMC(ixMISC_CLK_CTRL, data); 1855 1856 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1857 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; 1858 if (orig != data) 1859 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1860 1861 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1862 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; 1863 if (orig != data) 1864 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); 1865 1866 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1867 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1868 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1869 if (orig != data) 1870 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1871 } 1872 } 1873 } else { 1874 if (orig != data) 1875 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1876 } 1877 1878 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 1879 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1880 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1881 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1882 if (orig != data) 1883 WREG32_PCIE(ixPCIE_CNTL2, data); 1884 1885 if (!disable_l0s) { 1886 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1887 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == 1888 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { 1889 data = RREG32_PCIE(ixPCIE_LC_STATUS1); 1890 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && 1891 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { 1892 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1893 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1894 if (orig != data) 1895 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1896 } 1897 } 1898 } 1899 } 1900 1901 static uint32_t cik_get_rev_id(struct amdgpu_device *adev) 1902 { 1903 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1904 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1905 } 1906 1907 static const struct amdgpu_ip_block_version bonaire_ip_blocks[] = 1908 { 1909 /* ORDER MATTERS! */ 1910 { 1911 .type = AMD_IP_BLOCK_TYPE_COMMON, 1912 .major = 1, 1913 .minor = 0, 1914 .rev = 0, 1915 .funcs = &cik_common_ip_funcs, 1916 }, 1917 { 1918 .type = AMD_IP_BLOCK_TYPE_GMC, 1919 .major = 7, 1920 .minor = 0, 1921 .rev = 0, 1922 .funcs = &gmc_v7_0_ip_funcs, 1923 }, 1924 { 1925 .type = AMD_IP_BLOCK_TYPE_IH, 1926 .major = 2, 1927 .minor = 0, 1928 .rev = 0, 1929 .funcs = &cik_ih_ip_funcs, 1930 }, 1931 { 1932 .type = AMD_IP_BLOCK_TYPE_SMC, 1933 .major = 7, 1934 .minor = 0, 1935 .rev = 0, 1936 .funcs = &ci_dpm_ip_funcs, 1937 }, 1938 { 1939 .type = AMD_IP_BLOCK_TYPE_DCE, 1940 .major = 8, 1941 .minor = 2, 1942 .rev = 0, 1943 .funcs = &dce_v8_0_ip_funcs, 1944 }, 1945 { 1946 .type = AMD_IP_BLOCK_TYPE_GFX, 1947 .major = 7, 1948 .minor = 2, 1949 .rev = 0, 1950 .funcs = &gfx_v7_0_ip_funcs, 1951 }, 1952 { 1953 .type = AMD_IP_BLOCK_TYPE_SDMA, 1954 .major = 2, 1955 .minor = 0, 1956 .rev = 0, 1957 .funcs = &cik_sdma_ip_funcs, 1958 }, 1959 { 1960 .type = AMD_IP_BLOCK_TYPE_UVD, 1961 .major = 4, 1962 .minor = 2, 1963 .rev = 0, 1964 .funcs = &uvd_v4_2_ip_funcs, 1965 }, 1966 { 1967 .type = AMD_IP_BLOCK_TYPE_VCE, 1968 .major = 2, 1969 .minor = 0, 1970 .rev = 0, 1971 .funcs = &vce_v2_0_ip_funcs, 1972 }, 1973 }; 1974 1975 static const struct amdgpu_ip_block_version hawaii_ip_blocks[] = 1976 { 1977 /* ORDER MATTERS! */ 1978 { 1979 .type = AMD_IP_BLOCK_TYPE_COMMON, 1980 .major = 1, 1981 .minor = 0, 1982 .rev = 0, 1983 .funcs = &cik_common_ip_funcs, 1984 }, 1985 { 1986 .type = AMD_IP_BLOCK_TYPE_GMC, 1987 .major = 7, 1988 .minor = 0, 1989 .rev = 0, 1990 .funcs = &gmc_v7_0_ip_funcs, 1991 }, 1992 { 1993 .type = AMD_IP_BLOCK_TYPE_IH, 1994 .major = 2, 1995 .minor = 0, 1996 .rev = 0, 1997 .funcs = &cik_ih_ip_funcs, 1998 }, 1999 { 2000 .type = AMD_IP_BLOCK_TYPE_SMC, 2001 .major = 7, 2002 .minor = 0, 2003 .rev = 0, 2004 .funcs = &ci_dpm_ip_funcs, 2005 }, 2006 { 2007 .type = AMD_IP_BLOCK_TYPE_DCE, 2008 .major = 8, 2009 .minor = 5, 2010 .rev = 0, 2011 .funcs = &dce_v8_0_ip_funcs, 2012 }, 2013 { 2014 .type = AMD_IP_BLOCK_TYPE_GFX, 2015 .major = 7, 2016 .minor = 3, 2017 .rev = 0, 2018 .funcs = &gfx_v7_0_ip_funcs, 2019 }, 2020 { 2021 .type = AMD_IP_BLOCK_TYPE_SDMA, 2022 .major = 2, 2023 .minor = 0, 2024 .rev = 0, 2025 .funcs = &cik_sdma_ip_funcs, 2026 }, 2027 { 2028 .type = AMD_IP_BLOCK_TYPE_UVD, 2029 .major = 4, 2030 .minor = 2, 2031 .rev = 0, 2032 .funcs = &uvd_v4_2_ip_funcs, 2033 }, 2034 { 2035 .type = AMD_IP_BLOCK_TYPE_VCE, 2036 .major = 2, 2037 .minor = 0, 2038 .rev = 0, 2039 .funcs = &vce_v2_0_ip_funcs, 2040 }, 2041 }; 2042 2043 static const struct amdgpu_ip_block_version kabini_ip_blocks[] = 2044 { 2045 /* ORDER MATTERS! */ 2046 { 2047 .type = AMD_IP_BLOCK_TYPE_COMMON, 2048 .major = 1, 2049 .minor = 0, 2050 .rev = 0, 2051 .funcs = &cik_common_ip_funcs, 2052 }, 2053 { 2054 .type = AMD_IP_BLOCK_TYPE_GMC, 2055 .major = 7, 2056 .minor = 0, 2057 .rev = 0, 2058 .funcs = &gmc_v7_0_ip_funcs, 2059 }, 2060 { 2061 .type = AMD_IP_BLOCK_TYPE_IH, 2062 .major = 2, 2063 .minor = 0, 2064 .rev = 0, 2065 .funcs = &cik_ih_ip_funcs, 2066 }, 2067 { 2068 .type = AMD_IP_BLOCK_TYPE_SMC, 2069 .major = 7, 2070 .minor = 0, 2071 .rev = 0, 2072 .funcs = &kv_dpm_ip_funcs, 2073 }, 2074 { 2075 .type = AMD_IP_BLOCK_TYPE_DCE, 2076 .major = 8, 2077 .minor = 3, 2078 .rev = 0, 2079 .funcs = &dce_v8_0_ip_funcs, 2080 }, 2081 { 2082 .type = AMD_IP_BLOCK_TYPE_GFX, 2083 .major = 7, 2084 .minor = 2, 2085 .rev = 0, 2086 .funcs = &gfx_v7_0_ip_funcs, 2087 }, 2088 { 2089 .type = AMD_IP_BLOCK_TYPE_SDMA, 2090 .major = 2, 2091 .minor = 0, 2092 .rev = 0, 2093 .funcs = &cik_sdma_ip_funcs, 2094 }, 2095 { 2096 .type = AMD_IP_BLOCK_TYPE_UVD, 2097 .major = 4, 2098 .minor = 2, 2099 .rev = 0, 2100 .funcs = &uvd_v4_2_ip_funcs, 2101 }, 2102 { 2103 .type = AMD_IP_BLOCK_TYPE_VCE, 2104 .major = 2, 2105 .minor = 0, 2106 .rev = 0, 2107 .funcs = &vce_v2_0_ip_funcs, 2108 }, 2109 }; 2110 2111 static const struct amdgpu_ip_block_version mullins_ip_blocks[] = 2112 { 2113 /* ORDER MATTERS! */ 2114 { 2115 .type = AMD_IP_BLOCK_TYPE_COMMON, 2116 .major = 1, 2117 .minor = 0, 2118 .rev = 0, 2119 .funcs = &cik_common_ip_funcs, 2120 }, 2121 { 2122 .type = AMD_IP_BLOCK_TYPE_GMC, 2123 .major = 7, 2124 .minor = 0, 2125 .rev = 0, 2126 .funcs = &gmc_v7_0_ip_funcs, 2127 }, 2128 { 2129 .type = AMD_IP_BLOCK_TYPE_IH, 2130 .major = 2, 2131 .minor = 0, 2132 .rev = 0, 2133 .funcs = &cik_ih_ip_funcs, 2134 }, 2135 { 2136 .type = AMD_IP_BLOCK_TYPE_SMC, 2137 .major = 7, 2138 .minor = 0, 2139 .rev = 0, 2140 .funcs = &kv_dpm_ip_funcs, 2141 }, 2142 { 2143 .type = AMD_IP_BLOCK_TYPE_DCE, 2144 .major = 8, 2145 .minor = 3, 2146 .rev = 0, 2147 .funcs = &dce_v8_0_ip_funcs, 2148 }, 2149 { 2150 .type = AMD_IP_BLOCK_TYPE_GFX, 2151 .major = 7, 2152 .minor = 2, 2153 .rev = 0, 2154 .funcs = &gfx_v7_0_ip_funcs, 2155 }, 2156 { 2157 .type = AMD_IP_BLOCK_TYPE_SDMA, 2158 .major = 2, 2159 .minor = 0, 2160 .rev = 0, 2161 .funcs = &cik_sdma_ip_funcs, 2162 }, 2163 { 2164 .type = AMD_IP_BLOCK_TYPE_UVD, 2165 .major = 4, 2166 .minor = 2, 2167 .rev = 0, 2168 .funcs = &uvd_v4_2_ip_funcs, 2169 }, 2170 { 2171 .type = AMD_IP_BLOCK_TYPE_VCE, 2172 .major = 2, 2173 .minor = 0, 2174 .rev = 0, 2175 .funcs = &vce_v2_0_ip_funcs, 2176 }, 2177 }; 2178 2179 static const struct amdgpu_ip_block_version kaveri_ip_blocks[] = 2180 { 2181 /* ORDER MATTERS! */ 2182 { 2183 .type = AMD_IP_BLOCK_TYPE_COMMON, 2184 .major = 1, 2185 .minor = 0, 2186 .rev = 0, 2187 .funcs = &cik_common_ip_funcs, 2188 }, 2189 { 2190 .type = AMD_IP_BLOCK_TYPE_GMC, 2191 .major = 7, 2192 .minor = 0, 2193 .rev = 0, 2194 .funcs = &gmc_v7_0_ip_funcs, 2195 }, 2196 { 2197 .type = AMD_IP_BLOCK_TYPE_IH, 2198 .major = 2, 2199 .minor = 0, 2200 .rev = 0, 2201 .funcs = &cik_ih_ip_funcs, 2202 }, 2203 { 2204 .type = AMD_IP_BLOCK_TYPE_SMC, 2205 .major = 7, 2206 .minor = 0, 2207 .rev = 0, 2208 .funcs = &kv_dpm_ip_funcs, 2209 }, 2210 { 2211 .type = AMD_IP_BLOCK_TYPE_DCE, 2212 .major = 8, 2213 .minor = 1, 2214 .rev = 0, 2215 .funcs = &dce_v8_0_ip_funcs, 2216 }, 2217 { 2218 .type = AMD_IP_BLOCK_TYPE_GFX, 2219 .major = 7, 2220 .minor = 1, 2221 .rev = 0, 2222 .funcs = &gfx_v7_0_ip_funcs, 2223 }, 2224 { 2225 .type = AMD_IP_BLOCK_TYPE_SDMA, 2226 .major = 2, 2227 .minor = 0, 2228 .rev = 0, 2229 .funcs = &cik_sdma_ip_funcs, 2230 }, 2231 { 2232 .type = AMD_IP_BLOCK_TYPE_UVD, 2233 .major = 4, 2234 .minor = 2, 2235 .rev = 0, 2236 .funcs = &uvd_v4_2_ip_funcs, 2237 }, 2238 { 2239 .type = AMD_IP_BLOCK_TYPE_VCE, 2240 .major = 2, 2241 .minor = 0, 2242 .rev = 0, 2243 .funcs = &vce_v2_0_ip_funcs, 2244 }, 2245 }; 2246 2247 int cik_set_ip_blocks(struct amdgpu_device *adev) 2248 { 2249 switch (adev->asic_type) { 2250 case CHIP_BONAIRE: 2251 adev->ip_blocks = bonaire_ip_blocks; 2252 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks); 2253 break; 2254 case CHIP_HAWAII: 2255 adev->ip_blocks = hawaii_ip_blocks; 2256 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks); 2257 break; 2258 case CHIP_KAVERI: 2259 adev->ip_blocks = kaveri_ip_blocks; 2260 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks); 2261 break; 2262 case CHIP_KABINI: 2263 adev->ip_blocks = kabini_ip_blocks; 2264 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks); 2265 break; 2266 case CHIP_MULLINS: 2267 adev->ip_blocks = mullins_ip_blocks; 2268 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks); 2269 break; 2270 default: 2271 /* FIXME: not supported yet */ 2272 return -EINVAL; 2273 } 2274 2275 return 0; 2276 } 2277 2278 static const struct amdgpu_asic_funcs cik_asic_funcs = 2279 { 2280 .read_disabled_bios = &cik_read_disabled_bios, 2281 .read_register = &cik_read_register, 2282 .reset = &cik_asic_reset, 2283 .set_vga_state = &cik_vga_set_state, 2284 .get_xclk = &cik_get_xclk, 2285 .set_uvd_clocks = &cik_set_uvd_clocks, 2286 .set_vce_clocks = &cik_set_vce_clocks, 2287 .get_cu_info = &gfx_v7_0_get_cu_info, 2288 /* these should be moved to their own ip modules */ 2289 .get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter, 2290 .wait_for_mc_idle = &gmc_v7_0_mc_wait_for_idle, 2291 }; 2292 2293 static int cik_common_early_init(void *handle) 2294 { 2295 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2296 2297 adev->smc_rreg = &cik_smc_rreg; 2298 adev->smc_wreg = &cik_smc_wreg; 2299 adev->pcie_rreg = &cik_pcie_rreg; 2300 adev->pcie_wreg = &cik_pcie_wreg; 2301 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; 2302 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; 2303 adev->didt_rreg = &cik_didt_rreg; 2304 adev->didt_wreg = &cik_didt_wreg; 2305 2306 adev->asic_funcs = &cik_asic_funcs; 2307 2308 adev->has_uvd = true; 2309 2310 adev->rev_id = cik_get_rev_id(adev); 2311 adev->external_rev_id = 0xFF; 2312 switch (adev->asic_type) { 2313 case CHIP_BONAIRE: 2314 adev->cg_flags = 2315 AMDGPU_CG_SUPPORT_GFX_MGCG | 2316 AMDGPU_CG_SUPPORT_GFX_MGLS | 2317 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2318 AMDGPU_CG_SUPPORT_GFX_CGLS | 2319 AMDGPU_CG_SUPPORT_GFX_CGTS | 2320 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2321 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2322 AMDGPU_CG_SUPPORT_MC_LS | 2323 AMDGPU_CG_SUPPORT_MC_MGCG | 2324 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2325 AMDGPU_CG_SUPPORT_SDMA_LS | 2326 AMDGPU_CG_SUPPORT_BIF_LS | 2327 AMDGPU_CG_SUPPORT_VCE_MGCG | 2328 AMDGPU_CG_SUPPORT_UVD_MGCG | 2329 AMDGPU_CG_SUPPORT_HDP_LS | 2330 AMDGPU_CG_SUPPORT_HDP_MGCG; 2331 adev->pg_flags = 0; 2332 adev->external_rev_id = adev->rev_id + 0x14; 2333 break; 2334 case CHIP_HAWAII: 2335 adev->cg_flags = 2336 AMDGPU_CG_SUPPORT_GFX_MGCG | 2337 AMDGPU_CG_SUPPORT_GFX_MGLS | 2338 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2339 AMDGPU_CG_SUPPORT_GFX_CGLS | 2340 AMDGPU_CG_SUPPORT_GFX_CGTS | 2341 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2342 AMDGPU_CG_SUPPORT_MC_LS | 2343 AMDGPU_CG_SUPPORT_MC_MGCG | 2344 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2345 AMDGPU_CG_SUPPORT_SDMA_LS | 2346 AMDGPU_CG_SUPPORT_BIF_LS | 2347 AMDGPU_CG_SUPPORT_VCE_MGCG | 2348 AMDGPU_CG_SUPPORT_UVD_MGCG | 2349 AMDGPU_CG_SUPPORT_HDP_LS | 2350 AMDGPU_CG_SUPPORT_HDP_MGCG; 2351 adev->pg_flags = 0; 2352 adev->external_rev_id = 0x28; 2353 break; 2354 case CHIP_KAVERI: 2355 adev->cg_flags = 2356 AMDGPU_CG_SUPPORT_GFX_MGCG | 2357 AMDGPU_CG_SUPPORT_GFX_MGLS | 2358 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2359 AMDGPU_CG_SUPPORT_GFX_CGLS | 2360 AMDGPU_CG_SUPPORT_GFX_CGTS | 2361 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2362 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2363 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2364 AMDGPU_CG_SUPPORT_SDMA_LS | 2365 AMDGPU_CG_SUPPORT_BIF_LS | 2366 AMDGPU_CG_SUPPORT_VCE_MGCG | 2367 AMDGPU_CG_SUPPORT_UVD_MGCG | 2368 AMDGPU_CG_SUPPORT_HDP_LS | 2369 AMDGPU_CG_SUPPORT_HDP_MGCG; 2370 adev->pg_flags = 2371 /*AMDGPU_PG_SUPPORT_GFX_PG | 2372 AMDGPU_PG_SUPPORT_GFX_SMG | 2373 AMDGPU_PG_SUPPORT_GFX_DMG |*/ 2374 AMDGPU_PG_SUPPORT_UVD | 2375 /*AMDGPU_PG_SUPPORT_VCE | 2376 AMDGPU_PG_SUPPORT_CP | 2377 AMDGPU_PG_SUPPORT_GDS | 2378 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2379 AMDGPU_PG_SUPPORT_ACP | 2380 AMDGPU_PG_SUPPORT_SAMU |*/ 2381 0; 2382 if (adev->pdev->device == 0x1312 || 2383 adev->pdev->device == 0x1316 || 2384 adev->pdev->device == 0x1317) 2385 adev->external_rev_id = 0x41; 2386 else 2387 adev->external_rev_id = 0x1; 2388 break; 2389 case CHIP_KABINI: 2390 case CHIP_MULLINS: 2391 adev->cg_flags = 2392 AMDGPU_CG_SUPPORT_GFX_MGCG | 2393 AMDGPU_CG_SUPPORT_GFX_MGLS | 2394 /*AMDGPU_CG_SUPPORT_GFX_CGCG |*/ 2395 AMDGPU_CG_SUPPORT_GFX_CGLS | 2396 AMDGPU_CG_SUPPORT_GFX_CGTS | 2397 AMDGPU_CG_SUPPORT_GFX_CGTS_LS | 2398 AMDGPU_CG_SUPPORT_GFX_CP_LS | 2399 AMDGPU_CG_SUPPORT_SDMA_MGCG | 2400 AMDGPU_CG_SUPPORT_SDMA_LS | 2401 AMDGPU_CG_SUPPORT_BIF_LS | 2402 AMDGPU_CG_SUPPORT_VCE_MGCG | 2403 AMDGPU_CG_SUPPORT_UVD_MGCG | 2404 AMDGPU_CG_SUPPORT_HDP_LS | 2405 AMDGPU_CG_SUPPORT_HDP_MGCG; 2406 adev->pg_flags = 2407 /*AMDGPU_PG_SUPPORT_GFX_PG | 2408 AMDGPU_PG_SUPPORT_GFX_SMG | */ 2409 AMDGPU_PG_SUPPORT_UVD | 2410 /*AMDGPU_PG_SUPPORT_VCE | 2411 AMDGPU_PG_SUPPORT_CP | 2412 AMDGPU_PG_SUPPORT_GDS | 2413 AMDGPU_PG_SUPPORT_RLC_SMU_HS | 2414 AMDGPU_PG_SUPPORT_SAMU |*/ 2415 0; 2416 if (adev->asic_type == CHIP_KABINI) { 2417 if (adev->rev_id == 0) 2418 adev->external_rev_id = 0x81; 2419 else if (adev->rev_id == 1) 2420 adev->external_rev_id = 0x82; 2421 else if (adev->rev_id == 2) 2422 adev->external_rev_id = 0x85; 2423 } else 2424 adev->external_rev_id = adev->rev_id + 0xa1; 2425 break; 2426 default: 2427 /* FIXME: not supported yet */ 2428 return -EINVAL; 2429 } 2430 2431 return 0; 2432 } 2433 2434 static int cik_common_sw_init(void *handle) 2435 { 2436 return 0; 2437 } 2438 2439 static int cik_common_sw_fini(void *handle) 2440 { 2441 return 0; 2442 } 2443 2444 static int cik_common_hw_init(void *handle) 2445 { 2446 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2447 2448 /* move the golden regs per IP block */ 2449 cik_init_golden_registers(adev); 2450 /* enable pcie gen2/3 link */ 2451 cik_pcie_gen3_enable(adev); 2452 /* enable aspm */ 2453 cik_program_aspm(adev); 2454 2455 return 0; 2456 } 2457 2458 static int cik_common_hw_fini(void *handle) 2459 { 2460 return 0; 2461 } 2462 2463 static int cik_common_suspend(void *handle) 2464 { 2465 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2466 2467 amdgpu_amdkfd_suspend(adev); 2468 2469 return cik_common_hw_fini(adev); 2470 } 2471 2472 static int cik_common_resume(void *handle) 2473 { 2474 int r; 2475 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2476 2477 r = cik_common_hw_init(adev); 2478 if (r) 2479 return r; 2480 2481 return amdgpu_amdkfd_resume(adev); 2482 } 2483 2484 static bool cik_common_is_idle(void *handle) 2485 { 2486 return true; 2487 } 2488 2489 static int cik_common_wait_for_idle(void *handle) 2490 { 2491 return 0; 2492 } 2493 2494 static void cik_common_print_status(void *handle) 2495 { 2496 2497 } 2498 2499 static int cik_common_soft_reset(void *handle) 2500 { 2501 /* XXX hard reset?? */ 2502 return 0; 2503 } 2504 2505 static int cik_common_set_clockgating_state(void *handle, 2506 enum amd_clockgating_state state) 2507 { 2508 return 0; 2509 } 2510 2511 static int cik_common_set_powergating_state(void *handle, 2512 enum amd_powergating_state state) 2513 { 2514 return 0; 2515 } 2516 2517 const struct amd_ip_funcs cik_common_ip_funcs = { 2518 .early_init = cik_common_early_init, 2519 .late_init = NULL, 2520 .sw_init = cik_common_sw_init, 2521 .sw_fini = cik_common_sw_fini, 2522 .hw_init = cik_common_hw_init, 2523 .hw_fini = cik_common_hw_fini, 2524 .suspend = cik_common_suspend, 2525 .resume = cik_common_resume, 2526 .is_idle = cik_common_is_idle, 2527 .wait_for_idle = cik_common_wait_for_idle, 2528 .soft_reset = cik_common_soft_reset, 2529 .print_status = cik_common_print_status, 2530 .set_clockgating_state = cik_common_set_clockgating_state, 2531 .set_powergating_state = cik_common_set_powergating_state, 2532 }; 2533
Indexes created Mon Sep 29 18:09:42 GMT 2025