amdgpu_cik.c revision 1.4
1 /* $NetBSD: amdgpu_cik.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_cik.c,v 1.4 2021/12/18 23:44:58 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <linux/pci.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_atombios.h" 36 #include "amdgpu_ih.h" 37 #include "amdgpu_uvd.h" 38 #include "amdgpu_vce.h" 39 #include "cikd.h" 40 #include "atom.h" 41 #include "amd_pcie.h" 42 43 #include "cik.h" 44 #include "gmc_v7_0.h" 45 #include "cik_ih.h" 46 #include "dce_v8_0.h" 47 #include "gfx_v7_0.h" 48 #include "cik_sdma.h" 49 #include "uvd_v4_2.h" 50 #include "vce_v2_0.h" 51 #include "cik_dpm.h" 52 53 #include "uvd/uvd_4_2_d.h" 54 55 #include "smu/smu_7_0_1_d.h" 56 #include "smu/smu_7_0_1_sh_mask.h" 57 58 #include "dce/dce_8_0_d.h" 59 #include "dce/dce_8_0_sh_mask.h" 60 61 #include "bif/bif_4_1_d.h" 62 #include "bif/bif_4_1_sh_mask.h" 63 64 #include "gca/gfx_7_2_d.h" 65 #include "gca/gfx_7_2_enum.h" 66 #include "gca/gfx_7_2_sh_mask.h" 67 68 #include "gmc/gmc_7_1_d.h" 69 #include "gmc/gmc_7_1_sh_mask.h" 70 71 #include "oss/oss_2_0_d.h" 72 #include "oss/oss_2_0_sh_mask.h" 73 74 #include "amdgpu_dm.h" 75 #include "amdgpu_amdkfd.h" 76 #include "dce_virtual.h" 77 78 /* 79 * Indirect registers accessor 80 */ 81 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg) 82 { 83 unsigned long flags; 84 u32 r; 85 86 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 87 WREG32(mmPCIE_INDEX, reg); 88 (void)RREG32(mmPCIE_INDEX); 89 r = RREG32(mmPCIE_DATA); 90 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 91 return r; 92 } 93 94 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 95 { 96 unsigned long flags; 97 98 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 99 WREG32(mmPCIE_INDEX, reg); 100 (void)RREG32(mmPCIE_INDEX); 101 WREG32(mmPCIE_DATA, v); 102 (void)RREG32(mmPCIE_DATA); 103 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 104 } 105 106 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg) 107 { 108 unsigned long flags; 109 u32 r; 110 111 spin_lock_irqsave(&adev->smc_idx_lock, flags); 112 WREG32(mmSMC_IND_INDEX_0, (reg)); 113 r = RREG32(mmSMC_IND_DATA_0); 114 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 115 return r; 116 } 117 118 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 119 { 120 unsigned long flags; 121 122 spin_lock_irqsave(&adev->smc_idx_lock, flags); 123 WREG32(mmSMC_IND_INDEX_0, (reg)); 124 WREG32(mmSMC_IND_DATA_0, (v)); 125 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 126 } 127 128 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg) 129 { 130 unsigned long flags; 131 u32 r; 132 133 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 134 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 135 r = RREG32(mmUVD_CTX_DATA); 136 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 137 return r; 138 } 139 140 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 141 { 142 unsigned long flags; 143 144 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags); 145 WREG32(mmUVD_CTX_INDEX, ((reg) & 0x1ff)); 146 WREG32(mmUVD_CTX_DATA, (v)); 147 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags); 148 } 149 150 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg) 151 { 152 unsigned long flags; 153 u32 r; 154 155 spin_lock_irqsave(&adev->didt_idx_lock, flags); 156 WREG32(mmDIDT_IND_INDEX, (reg)); 157 r = RREG32(mmDIDT_IND_DATA); 158 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 159 return r; 160 } 161 162 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 163 { 164 unsigned long flags; 165 166 spin_lock_irqsave(&adev->didt_idx_lock, flags); 167 WREG32(mmDIDT_IND_INDEX, (reg)); 168 WREG32(mmDIDT_IND_DATA, (v)); 169 spin_unlock_irqrestore(&adev->didt_idx_lock, flags); 170 } 171 172 static const u32 bonaire_golden_spm_registers[] = 173 { 174 0xc200, 0xe0ffffff, 0xe0000000 175 }; 176 177 static const u32 bonaire_golden_common_registers[] = 178 { 179 0x31dc, 0xffffffff, 0x00000800, 180 0x31dd, 0xffffffff, 0x00000800, 181 0x31e6, 0xffffffff, 0x00007fbf, 182 0x31e7, 0xffffffff, 0x00007faf 183 }; 184 185 static const u32 bonaire_golden_registers[] = 186 { 187 0xcd5, 0x00000333, 0x00000333, 188 0xcd4, 0x000c0fc0, 0x00040200, 189 0x2684, 0x00010000, 0x00058208, 190 0xf000, 0xffff1fff, 0x00140000, 191 0xf080, 0xfdfc0fff, 0x00000100, 192 0xf08d, 0x40000000, 0x40000200, 193 0x260c, 0xffffffff, 0x00000000, 194 0x260d, 0xf00fffff, 0x00000400, 195 0x260e, 0x0002021c, 0x00020200, 196 0x31e, 0x00000080, 0x00000000, 197 0x16ec, 0x000000f0, 0x00000070, 198 0x16f0, 0xf0311fff, 0x80300000, 199 0x263e, 0x73773777, 0x12010001, 200 0xd43, 0x00810000, 0x408af000, 201 0x1c0c, 0x31000111, 0x00000011, 202 0xbd2, 0x73773777, 0x12010001, 203 0x883, 0x00007fb6, 0x0021a1b1, 204 0x884, 0x00007fb6, 0x002021b1, 205 0x860, 0x00007fb6, 0x00002191, 206 0x886, 0x00007fb6, 0x002121b1, 207 0x887, 0x00007fb6, 0x002021b1, 208 0x877, 0x00007fb6, 0x00002191, 209 0x878, 0x00007fb6, 0x00002191, 210 0xd8a, 0x0000003f, 0x0000000a, 211 0xd8b, 0x0000003f, 0x0000000a, 212 0xab9, 0x00073ffe, 0x000022a2, 213 0x903, 0x000007ff, 0x00000000, 214 0x2285, 0xf000003f, 0x00000007, 215 0x22fc, 0x00002001, 0x00000001, 216 0x22c9, 0xffffffff, 0x00ffffff, 217 0xc281, 0x0000ff0f, 0x00000000, 218 0xa293, 0x07ffffff, 0x06000000, 219 0x136, 0x00000fff, 0x00000100, 220 0xf9e, 0x00000001, 0x00000002, 221 0x2440, 0x03000000, 0x0362c688, 222 0x2300, 0x000000ff, 0x00000001, 223 0x390, 0x00001fff, 0x00001fff, 224 0x2418, 0x0000007f, 0x00000020, 225 0x2542, 0x00010000, 0x00010000, 226 0x2b05, 0x000003ff, 0x000000f3, 227 0x2b03, 0xffffffff, 0x00001032 228 }; 229 230 static const u32 bonaire_mgcg_cgcg_init[] = 231 { 232 0x3108, 0xffffffff, 0xfffffffc, 233 0xc200, 0xffffffff, 0xe0000000, 234 0xf0a8, 0xffffffff, 0x00000100, 235 0xf082, 0xffffffff, 0x00000100, 236 0xf0b0, 0xffffffff, 0xc0000100, 237 0xf0b2, 0xffffffff, 0xc0000100, 238 0xf0b1, 0xffffffff, 0xc0000100, 239 0x1579, 0xffffffff, 0x00600100, 240 0xf0a0, 0xffffffff, 0x00000100, 241 0xf085, 0xffffffff, 0x06000100, 242 0xf088, 0xffffffff, 0x00000100, 243 0xf086, 0xffffffff, 0x06000100, 244 0xf081, 0xffffffff, 0x00000100, 245 0xf0b8, 0xffffffff, 0x00000100, 246 0xf089, 0xffffffff, 0x00000100, 247 0xf080, 0xffffffff, 0x00000100, 248 0xf08c, 0xffffffff, 0x00000100, 249 0xf08d, 0xffffffff, 0x00000100, 250 0xf094, 0xffffffff, 0x00000100, 251 0xf095, 0xffffffff, 0x00000100, 252 0xf096, 0xffffffff, 0x00000100, 253 0xf097, 0xffffffff, 0x00000100, 254 0xf098, 0xffffffff, 0x00000100, 255 0xf09f, 0xffffffff, 0x00000100, 256 0xf09e, 0xffffffff, 0x00000100, 257 0xf084, 0xffffffff, 0x06000100, 258 0xf0a4, 0xffffffff, 0x00000100, 259 0xf09d, 0xffffffff, 0x00000100, 260 0xf0ad, 0xffffffff, 0x00000100, 261 0xf0ac, 0xffffffff, 0x00000100, 262 0xf09c, 0xffffffff, 0x00000100, 263 0xc200, 0xffffffff, 0xe0000000, 264 0xf008, 0xffffffff, 0x00010000, 265 0xf009, 0xffffffff, 0x00030002, 266 0xf00a, 0xffffffff, 0x00040007, 267 0xf00b, 0xffffffff, 0x00060005, 268 0xf00c, 0xffffffff, 0x00090008, 269 0xf00d, 0xffffffff, 0x00010000, 270 0xf00e, 0xffffffff, 0x00030002, 271 0xf00f, 0xffffffff, 0x00040007, 272 0xf010, 0xffffffff, 0x00060005, 273 0xf011, 0xffffffff, 0x00090008, 274 0xf012, 0xffffffff, 0x00010000, 275 0xf013, 0xffffffff, 0x00030002, 276 0xf014, 0xffffffff, 0x00040007, 277 0xf015, 0xffffffff, 0x00060005, 278 0xf016, 0xffffffff, 0x00090008, 279 0xf017, 0xffffffff, 0x00010000, 280 0xf018, 0xffffffff, 0x00030002, 281 0xf019, 0xffffffff, 0x00040007, 282 0xf01a, 0xffffffff, 0x00060005, 283 0xf01b, 0xffffffff, 0x00090008, 284 0xf01c, 0xffffffff, 0x00010000, 285 0xf01d, 0xffffffff, 0x00030002, 286 0xf01e, 0xffffffff, 0x00040007, 287 0xf01f, 0xffffffff, 0x00060005, 288 0xf020, 0xffffffff, 0x00090008, 289 0xf021, 0xffffffff, 0x00010000, 290 0xf022, 0xffffffff, 0x00030002, 291 0xf023, 0xffffffff, 0x00040007, 292 0xf024, 0xffffffff, 0x00060005, 293 0xf025, 0xffffffff, 0x00090008, 294 0xf026, 0xffffffff, 0x00010000, 295 0xf027, 0xffffffff, 0x00030002, 296 0xf028, 0xffffffff, 0x00040007, 297 0xf029, 0xffffffff, 0x00060005, 298 0xf02a, 0xffffffff, 0x00090008, 299 0xf000, 0xffffffff, 0x96e00200, 300 0x21c2, 0xffffffff, 0x00900100, 301 0x3109, 0xffffffff, 0x0020003f, 302 0xe, 0xffffffff, 0x0140001c, 303 0xf, 0x000f0000, 0x000f0000, 304 0x88, 0xffffffff, 0xc060000c, 305 0x89, 0xc0000fff, 0x00000100, 306 0x3e4, 0xffffffff, 0x00000100, 307 0x3e6, 0x00000101, 0x00000000, 308 0x82a, 0xffffffff, 0x00000104, 309 0x1579, 0xff000fff, 0x00000100, 310 0xc33, 0xc0000fff, 0x00000104, 311 0x3079, 0x00000001, 0x00000001, 312 0x3403, 0xff000ff0, 0x00000100, 313 0x3603, 0xff000ff0, 0x00000100 314 }; 315 316 static const u32 spectre_golden_spm_registers[] = 317 { 318 0xc200, 0xe0ffffff, 0xe0000000 319 }; 320 321 static const u32 spectre_golden_common_registers[] = 322 { 323 0x31dc, 0xffffffff, 0x00000800, 324 0x31dd, 0xffffffff, 0x00000800, 325 0x31e6, 0xffffffff, 0x00007fbf, 326 0x31e7, 0xffffffff, 0x00007faf 327 }; 328 329 static const u32 spectre_golden_registers[] = 330 { 331 0xf000, 0xffff1fff, 0x96940200, 332 0xf003, 0xffff0001, 0xff000000, 333 0xf080, 0xfffc0fff, 0x00000100, 334 0x1bb6, 0x00010101, 0x00010000, 335 0x260d, 0xf00fffff, 0x00000400, 336 0x260e, 0xfffffffc, 0x00020200, 337 0x16ec, 0x000000f0, 0x00000070, 338 0x16f0, 0xf0311fff, 0x80300000, 339 0x263e, 0x73773777, 0x12010001, 340 0x26df, 0x00ff0000, 0x00fc0000, 341 0xbd2, 0x73773777, 0x12010001, 342 0x2285, 0xf000003f, 0x00000007, 343 0x22c9, 0xffffffff, 0x00ffffff, 344 0xa0d4, 0x3f3f3fff, 0x00000082, 345 0xa0d5, 0x0000003f, 0x00000000, 346 0xf9e, 0x00000001, 0x00000002, 347 0x244f, 0xffff03df, 0x00000004, 348 0x31da, 0x00000008, 0x00000008, 349 0x2300, 0x000008ff, 0x00000800, 350 0x2542, 0x00010000, 0x00010000, 351 0x2b03, 0xffffffff, 0x54763210, 352 0x853e, 0x01ff01ff, 0x00000002, 353 0x8526, 0x007ff800, 0x00200000, 354 0x8057, 0xffffffff, 0x00000f40, 355 0xc24d, 0xffffffff, 0x00000001 356 }; 357 358 static const u32 spectre_mgcg_cgcg_init[] = 359 { 360 0x3108, 0xffffffff, 0xfffffffc, 361 0xc200, 0xffffffff, 0xe0000000, 362 0xf0a8, 0xffffffff, 0x00000100, 363 0xf082, 0xffffffff, 0x00000100, 364 0xf0b0, 0xffffffff, 0x00000100, 365 0xf0b2, 0xffffffff, 0x00000100, 366 0xf0b1, 0xffffffff, 0x00000100, 367 0x1579, 0xffffffff, 0x00600100, 368 0xf0a0, 0xffffffff, 0x00000100, 369 0xf085, 0xffffffff, 0x06000100, 370 0xf088, 0xffffffff, 0x00000100, 371 0xf086, 0xffffffff, 0x06000100, 372 0xf081, 0xffffffff, 0x00000100, 373 0xf0b8, 0xffffffff, 0x00000100, 374 0xf089, 0xffffffff, 0x00000100, 375 0xf080, 0xffffffff, 0x00000100, 376 0xf08c, 0xffffffff, 0x00000100, 377 0xf08d, 0xffffffff, 0x00000100, 378 0xf094, 0xffffffff, 0x00000100, 379 0xf095, 0xffffffff, 0x00000100, 380 0xf096, 0xffffffff, 0x00000100, 381 0xf097, 0xffffffff, 0x00000100, 382 0xf098, 0xffffffff, 0x00000100, 383 0xf09f, 0xffffffff, 0x00000100, 384 0xf09e, 0xffffffff, 0x00000100, 385 0xf084, 0xffffffff, 0x06000100, 386 0xf0a4, 0xffffffff, 0x00000100, 387 0xf09d, 0xffffffff, 0x00000100, 388 0xf0ad, 0xffffffff, 0x00000100, 389 0xf0ac, 0xffffffff, 0x00000100, 390 0xf09c, 0xffffffff, 0x00000100, 391 0xc200, 0xffffffff, 0xe0000000, 392 0xf008, 0xffffffff, 0x00010000, 393 0xf009, 0xffffffff, 0x00030002, 394 0xf00a, 0xffffffff, 0x00040007, 395 0xf00b, 0xffffffff, 0x00060005, 396 0xf00c, 0xffffffff, 0x00090008, 397 0xf00d, 0xffffffff, 0x00010000, 398 0xf00e, 0xffffffff, 0x00030002, 399 0xf00f, 0xffffffff, 0x00040007, 400 0xf010, 0xffffffff, 0x00060005, 401 0xf011, 0xffffffff, 0x00090008, 402 0xf012, 0xffffffff, 0x00010000, 403 0xf013, 0xffffffff, 0x00030002, 404 0xf014, 0xffffffff, 0x00040007, 405 0xf015, 0xffffffff, 0x00060005, 406 0xf016, 0xffffffff, 0x00090008, 407 0xf017, 0xffffffff, 0x00010000, 408 0xf018, 0xffffffff, 0x00030002, 409 0xf019, 0xffffffff, 0x00040007, 410 0xf01a, 0xffffffff, 0x00060005, 411 0xf01b, 0xffffffff, 0x00090008, 412 0xf01c, 0xffffffff, 0x00010000, 413 0xf01d, 0xffffffff, 0x00030002, 414 0xf01e, 0xffffffff, 0x00040007, 415 0xf01f, 0xffffffff, 0x00060005, 416 0xf020, 0xffffffff, 0x00090008, 417 0xf021, 0xffffffff, 0x00010000, 418 0xf022, 0xffffffff, 0x00030002, 419 0xf023, 0xffffffff, 0x00040007, 420 0xf024, 0xffffffff, 0x00060005, 421 0xf025, 0xffffffff, 0x00090008, 422 0xf026, 0xffffffff, 0x00010000, 423 0xf027, 0xffffffff, 0x00030002, 424 0xf028, 0xffffffff, 0x00040007, 425 0xf029, 0xffffffff, 0x00060005, 426 0xf02a, 0xffffffff, 0x00090008, 427 0xf02b, 0xffffffff, 0x00010000, 428 0xf02c, 0xffffffff, 0x00030002, 429 0xf02d, 0xffffffff, 0x00040007, 430 0xf02e, 0xffffffff, 0x00060005, 431 0xf02f, 0xffffffff, 0x00090008, 432 0xf000, 0xffffffff, 0x96e00200, 433 0x21c2, 0xffffffff, 0x00900100, 434 0x3109, 0xffffffff, 0x0020003f, 435 0xe, 0xffffffff, 0x0140001c, 436 0xf, 0x000f0000, 0x000f0000, 437 0x88, 0xffffffff, 0xc060000c, 438 0x89, 0xc0000fff, 0x00000100, 439 0x3e4, 0xffffffff, 0x00000100, 440 0x3e6, 0x00000101, 0x00000000, 441 0x82a, 0xffffffff, 0x00000104, 442 0x1579, 0xff000fff, 0x00000100, 443 0xc33, 0xc0000fff, 0x00000104, 444 0x3079, 0x00000001, 0x00000001, 445 0x3403, 0xff000ff0, 0x00000100, 446 0x3603, 0xff000ff0, 0x00000100 447 }; 448 449 static const u32 kalindi_golden_spm_registers[] = 450 { 451 0xc200, 0xe0ffffff, 0xe0000000 452 }; 453 454 static const u32 kalindi_golden_common_registers[] = 455 { 456 0x31dc, 0xffffffff, 0x00000800, 457 0x31dd, 0xffffffff, 0x00000800, 458 0x31e6, 0xffffffff, 0x00007fbf, 459 0x31e7, 0xffffffff, 0x00007faf 460 }; 461 462 static const u32 kalindi_golden_registers[] = 463 { 464 0xf000, 0xffffdfff, 0x6e944040, 465 0x1579, 0xff607fff, 0xfc000100, 466 0xf088, 0xff000fff, 0x00000100, 467 0xf089, 0xff000fff, 0x00000100, 468 0xf080, 0xfffc0fff, 0x00000100, 469 0x1bb6, 0x00010101, 0x00010000, 470 0x260c, 0xffffffff, 0x00000000, 471 0x260d, 0xf00fffff, 0x00000400, 472 0x16ec, 0x000000f0, 0x00000070, 473 0x16f0, 0xf0311fff, 0x80300000, 474 0x263e, 0x73773777, 0x12010001, 475 0x263f, 0xffffffff, 0x00000010, 476 0x26df, 0x00ff0000, 0x00fc0000, 477 0x200c, 0x00001f0f, 0x0000100a, 478 0xbd2, 0x73773777, 0x12010001, 479 0x902, 0x000fffff, 0x000c007f, 480 0x2285, 0xf000003f, 0x00000007, 481 0x22c9, 0x3fff3fff, 0x00ffcfff, 482 0xc281, 0x0000ff0f, 0x00000000, 483 0xa293, 0x07ffffff, 0x06000000, 484 0x136, 0x00000fff, 0x00000100, 485 0xf9e, 0x00000001, 0x00000002, 486 0x31da, 0x00000008, 0x00000008, 487 0x2300, 0x000000ff, 0x00000003, 488 0x853e, 0x01ff01ff, 0x00000002, 489 0x8526, 0x007ff800, 0x00200000, 490 0x8057, 0xffffffff, 0x00000f40, 491 0x2231, 0x001f3ae3, 0x00000082, 492 0x2235, 0x0000001f, 0x00000010, 493 0xc24d, 0xffffffff, 0x00000000 494 }; 495 496 static const u32 kalindi_mgcg_cgcg_init[] = 497 { 498 0x3108, 0xffffffff, 0xfffffffc, 499 0xc200, 0xffffffff, 0xe0000000, 500 0xf0a8, 0xffffffff, 0x00000100, 501 0xf082, 0xffffffff, 0x00000100, 502 0xf0b0, 0xffffffff, 0x00000100, 503 0xf0b2, 0xffffffff, 0x00000100, 504 0xf0b1, 0xffffffff, 0x00000100, 505 0x1579, 0xffffffff, 0x00600100, 506 0xf0a0, 0xffffffff, 0x00000100, 507 0xf085, 0xffffffff, 0x06000100, 508 0xf088, 0xffffffff, 0x00000100, 509 0xf086, 0xffffffff, 0x06000100, 510 0xf081, 0xffffffff, 0x00000100, 511 0xf0b8, 0xffffffff, 0x00000100, 512 0xf089, 0xffffffff, 0x00000100, 513 0xf080, 0xffffffff, 0x00000100, 514 0xf08c, 0xffffffff, 0x00000100, 515 0xf08d, 0xffffffff, 0x00000100, 516 0xf094, 0xffffffff, 0x00000100, 517 0xf095, 0xffffffff, 0x00000100, 518 0xf096, 0xffffffff, 0x00000100, 519 0xf097, 0xffffffff, 0x00000100, 520 0xf098, 0xffffffff, 0x00000100, 521 0xf09f, 0xffffffff, 0x00000100, 522 0xf09e, 0xffffffff, 0x00000100, 523 0xf084, 0xffffffff, 0x06000100, 524 0xf0a4, 0xffffffff, 0x00000100, 525 0xf09d, 0xffffffff, 0x00000100, 526 0xf0ad, 0xffffffff, 0x00000100, 527 0xf0ac, 0xffffffff, 0x00000100, 528 0xf09c, 0xffffffff, 0x00000100, 529 0xc200, 0xffffffff, 0xe0000000, 530 0xf008, 0xffffffff, 0x00010000, 531 0xf009, 0xffffffff, 0x00030002, 532 0xf00a, 0xffffffff, 0x00040007, 533 0xf00b, 0xffffffff, 0x00060005, 534 0xf00c, 0xffffffff, 0x00090008, 535 0xf00d, 0xffffffff, 0x00010000, 536 0xf00e, 0xffffffff, 0x00030002, 537 0xf00f, 0xffffffff, 0x00040007, 538 0xf010, 0xffffffff, 0x00060005, 539 0xf011, 0xffffffff, 0x00090008, 540 0xf000, 0xffffffff, 0x96e00200, 541 0x21c2, 0xffffffff, 0x00900100, 542 0x3109, 0xffffffff, 0x0020003f, 543 0xe, 0xffffffff, 0x0140001c, 544 0xf, 0x000f0000, 0x000f0000, 545 0x88, 0xffffffff, 0xc060000c, 546 0x89, 0xc0000fff, 0x00000100, 547 0x82a, 0xffffffff, 0x00000104, 548 0x1579, 0xff000fff, 0x00000100, 549 0xc33, 0xc0000fff, 0x00000104, 550 0x3079, 0x00000001, 0x00000001, 551 0x3403, 0xff000ff0, 0x00000100, 552 0x3603, 0xff000ff0, 0x00000100 553 }; 554 555 static const u32 hawaii_golden_spm_registers[] = 556 { 557 0xc200, 0xe0ffffff, 0xe0000000 558 }; 559 560 static const u32 hawaii_golden_common_registers[] = 561 { 562 0xc200, 0xffffffff, 0xe0000000, 563 0xa0d4, 0xffffffff, 0x3a00161a, 564 0xa0d5, 0xffffffff, 0x0000002e, 565 0x2684, 0xffffffff, 0x00018208, 566 0x263e, 0xffffffff, 0x12011003 567 }; 568 569 static const u32 hawaii_golden_registers[] = 570 { 571 0xcd5, 0x00000333, 0x00000333, 572 0x2684, 0x00010000, 0x00058208, 573 0x260c, 0xffffffff, 0x00000000, 574 0x260d, 0xf00fffff, 0x00000400, 575 0x260e, 0x0002021c, 0x00020200, 576 0x31e, 0x00000080, 0x00000000, 577 0x16ec, 0x000000f0, 0x00000070, 578 0x16f0, 0xf0311fff, 0x80300000, 579 0xd43, 0x00810000, 0x408af000, 580 0x1c0c, 0x31000111, 0x00000011, 581 0xbd2, 0x73773777, 0x12010001, 582 0x848, 0x0000007f, 0x0000001b, 583 0x877, 0x00007fb6, 0x00002191, 584 0xd8a, 0x0000003f, 0x0000000a, 585 0xd8b, 0x0000003f, 0x0000000a, 586 0xab9, 0x00073ffe, 0x000022a2, 587 0x903, 0x000007ff, 0x00000000, 588 0x22fc, 0x00002001, 0x00000001, 589 0x22c9, 0xffffffff, 0x00ffffff, 590 0xc281, 0x0000ff0f, 0x00000000, 591 0xa293, 0x07ffffff, 0x06000000, 592 0xf9e, 0x00000001, 0x00000002, 593 0x31da, 0x00000008, 0x00000008, 594 0x31dc, 0x00000f00, 0x00000800, 595 0x31dd, 0x00000f00, 0x00000800, 596 0x31e6, 0x00ffffff, 0x00ff7fbf, 597 0x31e7, 0x00ffffff, 0x00ff7faf, 598 0x2300, 0x000000ff, 0x00000800, 599 0x390, 0x00001fff, 0x00001fff, 600 0x2418, 0x0000007f, 0x00000020, 601 0x2542, 0x00010000, 0x00010000, 602 0x2b80, 0x00100000, 0x000ff07c, 603 0x2b05, 0x000003ff, 0x0000000f, 604 0x2b04, 0xffffffff, 0x7564fdec, 605 0x2b03, 0xffffffff, 0x3120b9a8, 606 0x2b02, 0x20000000, 0x0f9c0000 607 }; 608 609 static const u32 hawaii_mgcg_cgcg_init[] = 610 { 611 0x3108, 0xffffffff, 0xfffffffd, 612 0xc200, 0xffffffff, 0xe0000000, 613 0xf0a8, 0xffffffff, 0x00000100, 614 0xf082, 0xffffffff, 0x00000100, 615 0xf0b0, 0xffffffff, 0x00000100, 616 0xf0b2, 0xffffffff, 0x00000100, 617 0xf0b1, 0xffffffff, 0x00000100, 618 0x1579, 0xffffffff, 0x00200100, 619 0xf0a0, 0xffffffff, 0x00000100, 620 0xf085, 0xffffffff, 0x06000100, 621 0xf088, 0xffffffff, 0x00000100, 622 0xf086, 0xffffffff, 0x06000100, 623 0xf081, 0xffffffff, 0x00000100, 624 0xf0b8, 0xffffffff, 0x00000100, 625 0xf089, 0xffffffff, 0x00000100, 626 0xf080, 0xffffffff, 0x00000100, 627 0xf08c, 0xffffffff, 0x00000100, 628 0xf08d, 0xffffffff, 0x00000100, 629 0xf094, 0xffffffff, 0x00000100, 630 0xf095, 0xffffffff, 0x00000100, 631 0xf096, 0xffffffff, 0x00000100, 632 0xf097, 0xffffffff, 0x00000100, 633 0xf098, 0xffffffff, 0x00000100, 634 0xf09f, 0xffffffff, 0x00000100, 635 0xf09e, 0xffffffff, 0x00000100, 636 0xf084, 0xffffffff, 0x06000100, 637 0xf0a4, 0xffffffff, 0x00000100, 638 0xf09d, 0xffffffff, 0x00000100, 639 0xf0ad, 0xffffffff, 0x00000100, 640 0xf0ac, 0xffffffff, 0x00000100, 641 0xf09c, 0xffffffff, 0x00000100, 642 0xc200, 0xffffffff, 0xe0000000, 643 0xf008, 0xffffffff, 0x00010000, 644 0xf009, 0xffffffff, 0x00030002, 645 0xf00a, 0xffffffff, 0x00040007, 646 0xf00b, 0xffffffff, 0x00060005, 647 0xf00c, 0xffffffff, 0x00090008, 648 0xf00d, 0xffffffff, 0x00010000, 649 0xf00e, 0xffffffff, 0x00030002, 650 0xf00f, 0xffffffff, 0x00040007, 651 0xf010, 0xffffffff, 0x00060005, 652 0xf011, 0xffffffff, 0x00090008, 653 0xf012, 0xffffffff, 0x00010000, 654 0xf013, 0xffffffff, 0x00030002, 655 0xf014, 0xffffffff, 0x00040007, 656 0xf015, 0xffffffff, 0x00060005, 657 0xf016, 0xffffffff, 0x00090008, 658 0xf017, 0xffffffff, 0x00010000, 659 0xf018, 0xffffffff, 0x00030002, 660 0xf019, 0xffffffff, 0x00040007, 661 0xf01a, 0xffffffff, 0x00060005, 662 0xf01b, 0xffffffff, 0x00090008, 663 0xf01c, 0xffffffff, 0x00010000, 664 0xf01d, 0xffffffff, 0x00030002, 665 0xf01e, 0xffffffff, 0x00040007, 666 0xf01f, 0xffffffff, 0x00060005, 667 0xf020, 0xffffffff, 0x00090008, 668 0xf021, 0xffffffff, 0x00010000, 669 0xf022, 0xffffffff, 0x00030002, 670 0xf023, 0xffffffff, 0x00040007, 671 0xf024, 0xffffffff, 0x00060005, 672 0xf025, 0xffffffff, 0x00090008, 673 0xf026, 0xffffffff, 0x00010000, 674 0xf027, 0xffffffff, 0x00030002, 675 0xf028, 0xffffffff, 0x00040007, 676 0xf029, 0xffffffff, 0x00060005, 677 0xf02a, 0xffffffff, 0x00090008, 678 0xf02b, 0xffffffff, 0x00010000, 679 0xf02c, 0xffffffff, 0x00030002, 680 0xf02d, 0xffffffff, 0x00040007, 681 0xf02e, 0xffffffff, 0x00060005, 682 0xf02f, 0xffffffff, 0x00090008, 683 0xf030, 0xffffffff, 0x00010000, 684 0xf031, 0xffffffff, 0x00030002, 685 0xf032, 0xffffffff, 0x00040007, 686 0xf033, 0xffffffff, 0x00060005, 687 0xf034, 0xffffffff, 0x00090008, 688 0xf035, 0xffffffff, 0x00010000, 689 0xf036, 0xffffffff, 0x00030002, 690 0xf037, 0xffffffff, 0x00040007, 691 0xf038, 0xffffffff, 0x00060005, 692 0xf039, 0xffffffff, 0x00090008, 693 0xf03a, 0xffffffff, 0x00010000, 694 0xf03b, 0xffffffff, 0x00030002, 695 0xf03c, 0xffffffff, 0x00040007, 696 0xf03d, 0xffffffff, 0x00060005, 697 0xf03e, 0xffffffff, 0x00090008, 698 0x30c6, 0xffffffff, 0x00020200, 699 0xcd4, 0xffffffff, 0x00000200, 700 0x570, 0xffffffff, 0x00000400, 701 0x157a, 0xffffffff, 0x00000000, 702 0xbd4, 0xffffffff, 0x00000902, 703 0xf000, 0xffffffff, 0x96940200, 704 0x21c2, 0xffffffff, 0x00900100, 705 0x3109, 0xffffffff, 0x0020003f, 706 0xe, 0xffffffff, 0x0140001c, 707 0xf, 0x000f0000, 0x000f0000, 708 0x88, 0xffffffff, 0xc060000c, 709 0x89, 0xc0000fff, 0x00000100, 710 0x3e4, 0xffffffff, 0x00000100, 711 0x3e6, 0x00000101, 0x00000000, 712 0x82a, 0xffffffff, 0x00000104, 713 0x1579, 0xff000fff, 0x00000100, 714 0xc33, 0xc0000fff, 0x00000104, 715 0x3079, 0x00000001, 0x00000001, 716 0x3403, 0xff000ff0, 0x00000100, 717 0x3603, 0xff000ff0, 0x00000100 718 }; 719 720 static const u32 godavari_golden_registers[] = 721 { 722 0x1579, 0xff607fff, 0xfc000100, 723 0x1bb6, 0x00010101, 0x00010000, 724 0x260c, 0xffffffff, 0x00000000, 725 0x260c0, 0xf00fffff, 0x00000400, 726 0x184c, 0xffffffff, 0x00010000, 727 0x16ec, 0x000000f0, 0x00000070, 728 0x16f0, 0xf0311fff, 0x80300000, 729 0x263e, 0x73773777, 0x12010001, 730 0x263f, 0xffffffff, 0x00000010, 731 0x200c, 0x00001f0f, 0x0000100a, 732 0xbd2, 0x73773777, 0x12010001, 733 0x902, 0x000fffff, 0x000c007f, 734 0x2285, 0xf000003f, 0x00000007, 735 0x22c9, 0xffffffff, 0x00ff0fff, 736 0xc281, 0x0000ff0f, 0x00000000, 737 0xa293, 0x07ffffff, 0x06000000, 738 0x136, 0x00000fff, 0x00000100, 739 0x3405, 0x00010000, 0x00810001, 740 0x3605, 0x00010000, 0x00810001, 741 0xf9e, 0x00000001, 0x00000002, 742 0x31da, 0x00000008, 0x00000008, 743 0x31dc, 0x00000f00, 0x00000800, 744 0x31dd, 0x00000f00, 0x00000800, 745 0x31e6, 0x00ffffff, 0x00ff7fbf, 746 0x31e7, 0x00ffffff, 0x00ff7faf, 747 0x2300, 0x000000ff, 0x00000001, 748 0x853e, 0x01ff01ff, 0x00000002, 749 0x8526, 0x007ff800, 0x00200000, 750 0x8057, 0xffffffff, 0x00000f40, 751 0x2231, 0x001f3ae3, 0x00000082, 752 0x2235, 0x0000001f, 0x00000010, 753 0xc24d, 0xffffffff, 0x00000000 754 }; 755 756 static void cik_init_golden_registers(struct amdgpu_device *adev) 757 { 758 /* Some of the registers might be dependent on GRBM_GFX_INDEX */ 759 mutex_lock(&adev->grbm_idx_mutex); 760 761 switch (adev->asic_type) { 762 case CHIP_BONAIRE: 763 amdgpu_device_program_register_sequence(adev, 764 bonaire_mgcg_cgcg_init, 765 ARRAY_SIZE(bonaire_mgcg_cgcg_init)); 766 amdgpu_device_program_register_sequence(adev, 767 bonaire_golden_registers, 768 ARRAY_SIZE(bonaire_golden_registers)); 769 amdgpu_device_program_register_sequence(adev, 770 bonaire_golden_common_registers, 771 ARRAY_SIZE(bonaire_golden_common_registers)); 772 amdgpu_device_program_register_sequence(adev, 773 bonaire_golden_spm_registers, 774 ARRAY_SIZE(bonaire_golden_spm_registers)); 775 break; 776 case CHIP_KABINI: 777 amdgpu_device_program_register_sequence(adev, 778 kalindi_mgcg_cgcg_init, 779 ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 780 amdgpu_device_program_register_sequence(adev, 781 kalindi_golden_registers, 782 ARRAY_SIZE(kalindi_golden_registers)); 783 amdgpu_device_program_register_sequence(adev, 784 kalindi_golden_common_registers, 785 ARRAY_SIZE(kalindi_golden_common_registers)); 786 amdgpu_device_program_register_sequence(adev, 787 kalindi_golden_spm_registers, 788 ARRAY_SIZE(kalindi_golden_spm_registers)); 789 break; 790 case CHIP_MULLINS: 791 amdgpu_device_program_register_sequence(adev, 792 kalindi_mgcg_cgcg_init, 793 ARRAY_SIZE(kalindi_mgcg_cgcg_init)); 794 amdgpu_device_program_register_sequence(adev, 795 godavari_golden_registers, 796 ARRAY_SIZE(godavari_golden_registers)); 797 amdgpu_device_program_register_sequence(adev, 798 kalindi_golden_common_registers, 799 ARRAY_SIZE(kalindi_golden_common_registers)); 800 amdgpu_device_program_register_sequence(adev, 801 kalindi_golden_spm_registers, 802 ARRAY_SIZE(kalindi_golden_spm_registers)); 803 break; 804 case CHIP_KAVERI: 805 amdgpu_device_program_register_sequence(adev, 806 spectre_mgcg_cgcg_init, 807 ARRAY_SIZE(spectre_mgcg_cgcg_init)); 808 amdgpu_device_program_register_sequence(adev, 809 spectre_golden_registers, 810 ARRAY_SIZE(spectre_golden_registers)); 811 amdgpu_device_program_register_sequence(adev, 812 spectre_golden_common_registers, 813 ARRAY_SIZE(spectre_golden_common_registers)); 814 amdgpu_device_program_register_sequence(adev, 815 spectre_golden_spm_registers, 816 ARRAY_SIZE(spectre_golden_spm_registers)); 817 break; 818 case CHIP_HAWAII: 819 amdgpu_device_program_register_sequence(adev, 820 hawaii_mgcg_cgcg_init, 821 ARRAY_SIZE(hawaii_mgcg_cgcg_init)); 822 amdgpu_device_program_register_sequence(adev, 823 hawaii_golden_registers, 824 ARRAY_SIZE(hawaii_golden_registers)); 825 amdgpu_device_program_register_sequence(adev, 826 hawaii_golden_common_registers, 827 ARRAY_SIZE(hawaii_golden_common_registers)); 828 amdgpu_device_program_register_sequence(adev, 829 hawaii_golden_spm_registers, 830 ARRAY_SIZE(hawaii_golden_spm_registers)); 831 break; 832 default: 833 break; 834 } 835 mutex_unlock(&adev->grbm_idx_mutex); 836 } 837 838 /** 839 * cik_get_xclk - get the xclk 840 * 841 * @adev: amdgpu_device pointer 842 * 843 * Returns the reference clock used by the gfx engine 844 * (CIK). 845 */ 846 static u32 cik_get_xclk(struct amdgpu_device *adev) 847 { 848 u32 reference_clock = adev->clock.spll.reference_freq; 849 850 if (adev->flags & AMD_IS_APU) { 851 if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) 852 return reference_clock / 2; 853 } else { 854 if (RREG32_SMC(ixCG_CLKPIN_CNTL) & CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK) 855 return reference_clock / 4; 856 } 857 return reference_clock; 858 } 859 860 /** 861 * cik_srbm_select - select specific register instances 862 * 863 * @adev: amdgpu_device pointer 864 * @me: selected ME (micro engine) 865 * @pipe: pipe 866 * @queue: queue 867 * @vmid: VMID 868 * 869 * Switches the currently active registers instances. Some 870 * registers are instanced per VMID, others are instanced per 871 * me/pipe/queue combination. 872 */ 873 void cik_srbm_select(struct amdgpu_device *adev, 874 u32 me, u32 pipe, u32 queue, u32 vmid) 875 { 876 u32 srbm_gfx_cntl = 877 (((pipe << SRBM_GFX_CNTL__PIPEID__SHIFT) & SRBM_GFX_CNTL__PIPEID_MASK)| 878 ((me << SRBM_GFX_CNTL__MEID__SHIFT) & SRBM_GFX_CNTL__MEID_MASK)| 879 ((vmid << SRBM_GFX_CNTL__VMID__SHIFT) & SRBM_GFX_CNTL__VMID_MASK)| 880 ((queue << SRBM_GFX_CNTL__QUEUEID__SHIFT) & SRBM_GFX_CNTL__QUEUEID_MASK)); 881 WREG32(mmSRBM_GFX_CNTL, srbm_gfx_cntl); 882 } 883 884 static void cik_vga_set_state(struct amdgpu_device *adev, bool state) 885 { 886 uint32_t tmp; 887 888 tmp = RREG32(mmCONFIG_CNTL); 889 if (!state) 890 tmp |= CONFIG_CNTL__VGA_DIS_MASK; 891 else 892 tmp &= ~CONFIG_CNTL__VGA_DIS_MASK; 893 WREG32(mmCONFIG_CNTL, tmp); 894 } 895 896 static bool cik_read_disabled_bios(struct amdgpu_device *adev) 897 { 898 u32 bus_cntl; 899 u32 d1vga_control = 0; 900 u32 d2vga_control = 0; 901 u32 vga_render_control = 0; 902 u32 rom_cntl; 903 bool r; 904 905 bus_cntl = RREG32(mmBUS_CNTL); 906 if (adev->mode_info.num_crtc) { 907 d1vga_control = RREG32(mmD1VGA_CONTROL); 908 d2vga_control = RREG32(mmD2VGA_CONTROL); 909 vga_render_control = RREG32(mmVGA_RENDER_CONTROL); 910 } 911 rom_cntl = RREG32_SMC(ixROM_CNTL); 912 913 /* enable the rom */ 914 WREG32(mmBUS_CNTL, (bus_cntl & ~BUS_CNTL__BIOS_ROM_DIS_MASK)); 915 if (adev->mode_info.num_crtc) { 916 /* Disable VGA mode */ 917 WREG32(mmD1VGA_CONTROL, 918 (d1vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 919 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 920 WREG32(mmD2VGA_CONTROL, 921 (d2vga_control & ~(D1VGA_CONTROL__D1VGA_MODE_ENABLE_MASK | 922 D1VGA_CONTROL__D1VGA_TIMING_SELECT_MASK))); 923 WREG32(mmVGA_RENDER_CONTROL, 924 (vga_render_control & ~VGA_RENDER_CONTROL__VGA_VSTATUS_CNTL_MASK)); 925 } 926 WREG32_SMC(ixROM_CNTL, rom_cntl | ROM_CNTL__SCK_OVERWRITE_MASK); 927 928 r = amdgpu_read_bios(adev); 929 930 /* restore regs */ 931 WREG32(mmBUS_CNTL, bus_cntl); 932 if (adev->mode_info.num_crtc) { 933 WREG32(mmD1VGA_CONTROL, d1vga_control); 934 WREG32(mmD2VGA_CONTROL, d2vga_control); 935 WREG32(mmVGA_RENDER_CONTROL, vga_render_control); 936 } 937 WREG32_SMC(ixROM_CNTL, rom_cntl); 938 return r; 939 } 940 941 static bool cik_read_bios_from_rom(struct amdgpu_device *adev, 942 u8 *bios, u32 length_bytes) 943 { 944 u32 *dw_ptr; 945 unsigned long flags; 946 u32 i, length_dw; 947 948 if (bios == NULL) 949 return false; 950 if (length_bytes == 0) 951 return false; 952 /* APU vbios image is part of sbios image */ 953 if (adev->flags & AMD_IS_APU) 954 return false; 955 956 dw_ptr = (u32 *)bios; 957 length_dw = ALIGN(length_bytes, 4) / 4; 958 /* take the smc lock since we are using the smc index */ 959 spin_lock_irqsave(&adev->smc_idx_lock, flags); 960 /* set rom index to 0 */ 961 WREG32(mmSMC_IND_INDEX_0, ixROM_INDEX); 962 WREG32(mmSMC_IND_DATA_0, 0); 963 /* set index to data for continous read */ 964 WREG32(mmSMC_IND_INDEX_0, ixROM_DATA); 965 for (i = 0; i < length_dw; i++) 966 dw_ptr[i] = RREG32(mmSMC_IND_DATA_0); 967 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 968 969 return true; 970 } 971 972 static const struct amdgpu_allowed_register_entry cik_allowed_read_registers[] = { 973 {mmGRBM_STATUS}, 974 {mmGRBM_STATUS2}, 975 {mmGRBM_STATUS_SE0}, 976 {mmGRBM_STATUS_SE1}, 977 {mmGRBM_STATUS_SE2}, 978 {mmGRBM_STATUS_SE3}, 979 {mmSRBM_STATUS}, 980 {mmSRBM_STATUS2}, 981 {mmSDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET}, 982 {mmSDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET}, 983 {mmCP_STAT}, 984 {mmCP_STALLED_STAT1}, 985 {mmCP_STALLED_STAT2}, 986 {mmCP_STALLED_STAT3}, 987 {mmCP_CPF_BUSY_STAT}, 988 {mmCP_CPF_STALLED_STAT1}, 989 {mmCP_CPF_STATUS}, 990 {mmCP_CPC_BUSY_STAT}, 991 {mmCP_CPC_STALLED_STAT1}, 992 {mmCP_CPC_STATUS}, 993 {mmGB_ADDR_CONFIG}, 994 {mmMC_ARB_RAMCFG}, 995 {mmGB_TILE_MODE0}, 996 {mmGB_TILE_MODE1}, 997 {mmGB_TILE_MODE2}, 998 {mmGB_TILE_MODE3}, 999 {mmGB_TILE_MODE4}, 1000 {mmGB_TILE_MODE5}, 1001 {mmGB_TILE_MODE6}, 1002 {mmGB_TILE_MODE7}, 1003 {mmGB_TILE_MODE8}, 1004 {mmGB_TILE_MODE9}, 1005 {mmGB_TILE_MODE10}, 1006 {mmGB_TILE_MODE11}, 1007 {mmGB_TILE_MODE12}, 1008 {mmGB_TILE_MODE13}, 1009 {mmGB_TILE_MODE14}, 1010 {mmGB_TILE_MODE15}, 1011 {mmGB_TILE_MODE16}, 1012 {mmGB_TILE_MODE17}, 1013 {mmGB_TILE_MODE18}, 1014 {mmGB_TILE_MODE19}, 1015 {mmGB_TILE_MODE20}, 1016 {mmGB_TILE_MODE21}, 1017 {mmGB_TILE_MODE22}, 1018 {mmGB_TILE_MODE23}, 1019 {mmGB_TILE_MODE24}, 1020 {mmGB_TILE_MODE25}, 1021 {mmGB_TILE_MODE26}, 1022 {mmGB_TILE_MODE27}, 1023 {mmGB_TILE_MODE28}, 1024 {mmGB_TILE_MODE29}, 1025 {mmGB_TILE_MODE30}, 1026 {mmGB_TILE_MODE31}, 1027 {mmGB_MACROTILE_MODE0}, 1028 {mmGB_MACROTILE_MODE1}, 1029 {mmGB_MACROTILE_MODE2}, 1030 {mmGB_MACROTILE_MODE3}, 1031 {mmGB_MACROTILE_MODE4}, 1032 {mmGB_MACROTILE_MODE5}, 1033 {mmGB_MACROTILE_MODE6}, 1034 {mmGB_MACROTILE_MODE7}, 1035 {mmGB_MACROTILE_MODE8}, 1036 {mmGB_MACROTILE_MODE9}, 1037 {mmGB_MACROTILE_MODE10}, 1038 {mmGB_MACROTILE_MODE11}, 1039 {mmGB_MACROTILE_MODE12}, 1040 {mmGB_MACROTILE_MODE13}, 1041 {mmGB_MACROTILE_MODE14}, 1042 {mmGB_MACROTILE_MODE15}, 1043 {mmCC_RB_BACKEND_DISABLE, true}, 1044 {mmGC_USER_RB_BACKEND_DISABLE, true}, 1045 {mmGB_BACKEND_MAP, false}, 1046 {mmPA_SC_RASTER_CONFIG, true}, 1047 {mmPA_SC_RASTER_CONFIG_1, true}, 1048 }; 1049 1050 1051 static uint32_t cik_get_register_value(struct amdgpu_device *adev, 1052 bool indexed, u32 se_num, 1053 u32 sh_num, u32 reg_offset) 1054 { 1055 if (indexed) { 1056 uint32_t val; 1057 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 1058 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1059 1060 switch (reg_offset) { 1061 case mmCC_RB_BACKEND_DISABLE: 1062 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 1063 case mmGC_USER_RB_BACKEND_DISABLE: 1064 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 1065 case mmPA_SC_RASTER_CONFIG: 1066 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 1067 case mmPA_SC_RASTER_CONFIG_1: 1068 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1; 1069 } 1070 1071 mutex_lock(&adev->grbm_idx_mutex); 1072 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1073 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1074 1075 val = RREG32(reg_offset); 1076 1077 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1078 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1079 mutex_unlock(&adev->grbm_idx_mutex); 1080 return val; 1081 } else { 1082 unsigned idx; 1083 1084 switch (reg_offset) { 1085 case mmGB_ADDR_CONFIG: 1086 return adev->gfx.config.gb_addr_config; 1087 case mmMC_ARB_RAMCFG: 1088 return adev->gfx.config.mc_arb_ramcfg; 1089 case mmGB_TILE_MODE0: 1090 case mmGB_TILE_MODE1: 1091 case mmGB_TILE_MODE2: 1092 case mmGB_TILE_MODE3: 1093 case mmGB_TILE_MODE4: 1094 case mmGB_TILE_MODE5: 1095 case mmGB_TILE_MODE6: 1096 case mmGB_TILE_MODE7: 1097 case mmGB_TILE_MODE8: 1098 case mmGB_TILE_MODE9: 1099 case mmGB_TILE_MODE10: 1100 case mmGB_TILE_MODE11: 1101 case mmGB_TILE_MODE12: 1102 case mmGB_TILE_MODE13: 1103 case mmGB_TILE_MODE14: 1104 case mmGB_TILE_MODE15: 1105 case mmGB_TILE_MODE16: 1106 case mmGB_TILE_MODE17: 1107 case mmGB_TILE_MODE18: 1108 case mmGB_TILE_MODE19: 1109 case mmGB_TILE_MODE20: 1110 case mmGB_TILE_MODE21: 1111 case mmGB_TILE_MODE22: 1112 case mmGB_TILE_MODE23: 1113 case mmGB_TILE_MODE24: 1114 case mmGB_TILE_MODE25: 1115 case mmGB_TILE_MODE26: 1116 case mmGB_TILE_MODE27: 1117 case mmGB_TILE_MODE28: 1118 case mmGB_TILE_MODE29: 1119 case mmGB_TILE_MODE30: 1120 case mmGB_TILE_MODE31: 1121 idx = (reg_offset - mmGB_TILE_MODE0); 1122 return adev->gfx.config.tile_mode_array[idx]; 1123 case mmGB_MACROTILE_MODE0: 1124 case mmGB_MACROTILE_MODE1: 1125 case mmGB_MACROTILE_MODE2: 1126 case mmGB_MACROTILE_MODE3: 1127 case mmGB_MACROTILE_MODE4: 1128 case mmGB_MACROTILE_MODE5: 1129 case mmGB_MACROTILE_MODE6: 1130 case mmGB_MACROTILE_MODE7: 1131 case mmGB_MACROTILE_MODE8: 1132 case mmGB_MACROTILE_MODE9: 1133 case mmGB_MACROTILE_MODE10: 1134 case mmGB_MACROTILE_MODE11: 1135 case mmGB_MACROTILE_MODE12: 1136 case mmGB_MACROTILE_MODE13: 1137 case mmGB_MACROTILE_MODE14: 1138 case mmGB_MACROTILE_MODE15: 1139 idx = (reg_offset - mmGB_MACROTILE_MODE0); 1140 return adev->gfx.config.macrotile_mode_array[idx]; 1141 default: 1142 return RREG32(reg_offset); 1143 } 1144 } 1145 } 1146 1147 static int cik_read_register(struct amdgpu_device *adev, u32 se_num, 1148 u32 sh_num, u32 reg_offset, u32 *value) 1149 { 1150 uint32_t i; 1151 1152 *value = 0; 1153 for (i = 0; i < ARRAY_SIZE(cik_allowed_read_registers); i++) { 1154 bool indexed = cik_allowed_read_registers[i].grbm_indexed; 1155 1156 if (reg_offset != cik_allowed_read_registers[i].reg_offset) 1157 continue; 1158 1159 *value = cik_get_register_value(adev, indexed, se_num, sh_num, 1160 reg_offset); 1161 return 0; 1162 } 1163 return -EINVAL; 1164 } 1165 1166 struct kv_reset_save_regs { 1167 u32 gmcon_reng_execute; 1168 u32 gmcon_misc; 1169 u32 gmcon_misc3; 1170 }; 1171 1172 static void kv_save_regs_for_reset(struct amdgpu_device *adev, 1173 struct kv_reset_save_regs *save) 1174 { 1175 save->gmcon_reng_execute = RREG32(mmGMCON_RENG_EXECUTE); 1176 save->gmcon_misc = RREG32(mmGMCON_MISC); 1177 save->gmcon_misc3 = RREG32(mmGMCON_MISC3); 1178 1179 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute & 1180 ~GMCON_RENG_EXECUTE__RENG_EXECUTE_ON_PWR_UP_MASK); 1181 WREG32(mmGMCON_MISC, save->gmcon_misc & 1182 ~(GMCON_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK | 1183 GMCON_MISC__STCTRL_STUTTER_EN_MASK)); 1184 } 1185 1186 static void kv_restore_regs_for_reset(struct amdgpu_device *adev, 1187 struct kv_reset_save_regs *save) 1188 { 1189 int i; 1190 1191 WREG32(mmGMCON_PGFSM_WRITE, 0); 1192 WREG32(mmGMCON_PGFSM_CONFIG, 0x200010ff); 1193 1194 for (i = 0; i < 5; i++) 1195 WREG32(mmGMCON_PGFSM_WRITE, 0); 1196 1197 WREG32(mmGMCON_PGFSM_WRITE, 0); 1198 WREG32(mmGMCON_PGFSM_CONFIG, 0x300010ff); 1199 1200 for (i = 0; i < 5; i++) 1201 WREG32(mmGMCON_PGFSM_WRITE, 0); 1202 1203 WREG32(mmGMCON_PGFSM_WRITE, 0x210000); 1204 WREG32(mmGMCON_PGFSM_CONFIG, 0xa00010ff); 1205 1206 for (i = 0; i < 5; i++) 1207 WREG32(mmGMCON_PGFSM_WRITE, 0); 1208 1209 WREG32(mmGMCON_PGFSM_WRITE, 0x21003); 1210 WREG32(mmGMCON_PGFSM_CONFIG, 0xb00010ff); 1211 1212 for (i = 0; i < 5; i++) 1213 WREG32(mmGMCON_PGFSM_WRITE, 0); 1214 1215 WREG32(mmGMCON_PGFSM_WRITE, 0x2b00); 1216 WREG32(mmGMCON_PGFSM_CONFIG, 0xc00010ff); 1217 1218 for (i = 0; i < 5; i++) 1219 WREG32(mmGMCON_PGFSM_WRITE, 0); 1220 1221 WREG32(mmGMCON_PGFSM_WRITE, 0); 1222 WREG32(mmGMCON_PGFSM_CONFIG, 0xd00010ff); 1223 1224 for (i = 0; i < 5; i++) 1225 WREG32(mmGMCON_PGFSM_WRITE, 0); 1226 1227 WREG32(mmGMCON_PGFSM_WRITE, 0x420000); 1228 WREG32(mmGMCON_PGFSM_CONFIG, 0x100010ff); 1229 1230 for (i = 0; i < 5; i++) 1231 WREG32(mmGMCON_PGFSM_WRITE, 0); 1232 1233 WREG32(mmGMCON_PGFSM_WRITE, 0x120202); 1234 WREG32(mmGMCON_PGFSM_CONFIG, 0x500010ff); 1235 1236 for (i = 0; i < 5; i++) 1237 WREG32(mmGMCON_PGFSM_WRITE, 0); 1238 1239 WREG32(mmGMCON_PGFSM_WRITE, 0x3e3e36); 1240 WREG32(mmGMCON_PGFSM_CONFIG, 0x600010ff); 1241 1242 for (i = 0; i < 5; i++) 1243 WREG32(mmGMCON_PGFSM_WRITE, 0); 1244 1245 WREG32(mmGMCON_PGFSM_WRITE, 0x373f3e); 1246 WREG32(mmGMCON_PGFSM_CONFIG, 0x700010ff); 1247 1248 for (i = 0; i < 5; i++) 1249 WREG32(mmGMCON_PGFSM_WRITE, 0); 1250 1251 WREG32(mmGMCON_PGFSM_WRITE, 0x3e1332); 1252 WREG32(mmGMCON_PGFSM_CONFIG, 0xe00010ff); 1253 1254 WREG32(mmGMCON_MISC3, save->gmcon_misc3); 1255 WREG32(mmGMCON_MISC, save->gmcon_misc); 1256 WREG32(mmGMCON_RENG_EXECUTE, save->gmcon_reng_execute); 1257 } 1258 1259 static int cik_gpu_pci_config_reset(struct amdgpu_device *adev) 1260 { 1261 struct kv_reset_save_regs kv_save = { 0 }; 1262 u32 i; 1263 int r = -EINVAL; 1264 1265 dev_info(adev->dev, "GPU pci config reset\n"); 1266 1267 if (adev->flags & AMD_IS_APU) 1268 kv_save_regs_for_reset(adev, &kv_save); 1269 1270 /* disable BM */ 1271 pci_clear_master(adev->pdev); 1272 /* reset */ 1273 amdgpu_device_pci_config_reset(adev); 1274 1275 udelay(100); 1276 1277 /* wait for asic to come out of reset */ 1278 for (i = 0; i < adev->usec_timeout; i++) { 1279 if (RREG32(mmCONFIG_MEMSIZE) != 0xffffffff) { 1280 /* enable BM */ 1281 pci_set_master(adev->pdev); 1282 adev->has_hw_reset = true; 1283 r = 0; 1284 break; 1285 } 1286 udelay(1); 1287 } 1288 1289 /* does asic init need to be run first??? */ 1290 if (adev->flags & AMD_IS_APU) 1291 kv_restore_regs_for_reset(adev, &kv_save); 1292 1293 return r; 1294 } 1295 1296 /** 1297 * cik_asic_pci_config_reset - soft reset GPU 1298 * 1299 * @adev: amdgpu_device pointer 1300 * 1301 * Use PCI Config method to reset the GPU. 1302 * 1303 * Returns 0 for success. 1304 */ 1305 static int cik_asic_pci_config_reset(struct amdgpu_device *adev) 1306 { 1307 int r; 1308 1309 amdgpu_atombios_scratch_regs_engine_hung(adev, true); 1310 1311 r = cik_gpu_pci_config_reset(adev); 1312 1313 amdgpu_atombios_scratch_regs_engine_hung(adev, false); 1314 1315 return r; 1316 } 1317 1318 static bool cik_asic_supports_baco(struct amdgpu_device *adev) 1319 { 1320 switch (adev->asic_type) { 1321 case CHIP_BONAIRE: 1322 case CHIP_HAWAII: 1323 return amdgpu_dpm_is_baco_supported(adev); 1324 default: 1325 return false; 1326 } 1327 } 1328 1329 static enum amd_reset_method 1330 cik_asic_reset_method(struct amdgpu_device *adev) 1331 { 1332 bool baco_reset; 1333 1334 switch (adev->asic_type) { 1335 case CHIP_BONAIRE: 1336 case CHIP_HAWAII: 1337 /* disable baco reset until it works */ 1338 /* smu7_asic_get_baco_capability(adev, &baco_reset); */ 1339 baco_reset = false; 1340 break; 1341 default: 1342 baco_reset = false; 1343 break; 1344 } 1345 1346 if (baco_reset) 1347 return AMD_RESET_METHOD_BACO; 1348 else 1349 return AMD_RESET_METHOD_LEGACY; 1350 } 1351 1352 /** 1353 * cik_asic_reset - soft reset GPU 1354 * 1355 * @adev: amdgpu_device pointer 1356 * 1357 * Look up which blocks are hung and attempt 1358 * to reset them. 1359 * Returns 0 for success. 1360 */ 1361 static int cik_asic_reset(struct amdgpu_device *adev) 1362 { 1363 int r; 1364 1365 if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) { 1366 if (!adev->in_suspend) 1367 amdgpu_inc_vram_lost(adev); 1368 r = amdgpu_dpm_baco_reset(adev); 1369 } else { 1370 r = cik_asic_pci_config_reset(adev); 1371 } 1372 1373 return r; 1374 } 1375 1376 static u32 cik_get_config_memsize(struct amdgpu_device *adev) 1377 { 1378 return RREG32(mmCONFIG_MEMSIZE); 1379 } 1380 1381 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock, 1382 u32 cntl_reg, u32 status_reg) 1383 { 1384 int r, i; 1385 struct atom_clock_dividers dividers; 1386 uint32_t tmp; 1387 1388 r = amdgpu_atombios_get_clock_dividers(adev, 1389 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1390 clock, false, ÷rs); 1391 if (r) 1392 return r; 1393 1394 tmp = RREG32_SMC(cntl_reg); 1395 tmp &= ~(CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK | 1396 CG_DCLK_CNTL__DCLK_DIVIDER_MASK); 1397 tmp |= dividers.post_divider; 1398 WREG32_SMC(cntl_reg, tmp); 1399 1400 for (i = 0; i < 100; i++) { 1401 if (RREG32_SMC(status_reg) & CG_DCLK_STATUS__DCLK_STATUS_MASK) 1402 break; 1403 mdelay(10); 1404 } 1405 if (i == 100) 1406 return -ETIMEDOUT; 1407 1408 return 0; 1409 } 1410 1411 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1412 { 1413 int r = 0; 1414 1415 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS); 1416 if (r) 1417 return r; 1418 1419 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS); 1420 return r; 1421 } 1422 1423 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk) 1424 { 1425 int r, i; 1426 struct atom_clock_dividers dividers; 1427 u32 tmp; 1428 1429 r = amdgpu_atombios_get_clock_dividers(adev, 1430 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, 1431 ecclk, false, ÷rs); 1432 if (r) 1433 return r; 1434 1435 for (i = 0; i < 100; i++) { 1436 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1437 break; 1438 mdelay(10); 1439 } 1440 if (i == 100) 1441 return -ETIMEDOUT; 1442 1443 tmp = RREG32_SMC(ixCG_ECLK_CNTL); 1444 tmp &= ~(CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK | 1445 CG_ECLK_CNTL__ECLK_DIVIDER_MASK); 1446 tmp |= dividers.post_divider; 1447 WREG32_SMC(ixCG_ECLK_CNTL, tmp); 1448 1449 for (i = 0; i < 100; i++) { 1450 if (RREG32_SMC(ixCG_ECLK_STATUS) & CG_ECLK_STATUS__ECLK_STATUS_MASK) 1451 break; 1452 mdelay(10); 1453 } 1454 if (i == 100) 1455 return -ETIMEDOUT; 1456 1457 return 0; 1458 } 1459 1460 static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 1461 { 1462 #ifndef __NetBSD__ /* XXX amdgpu pcie */ 1463 struct pci_dev *root = adev->pdev->bus->self; 1464 u32 speed_cntl, current_data_rate; 1465 int i; 1466 u16 tmp16; 1467 1468 if (pci_is_root_bus(adev->pdev->bus)) 1469 return; 1470 1471 if (amdgpu_pcie_gen2 == 0) 1472 return; 1473 1474 if (adev->flags & AMD_IS_APU) 1475 return; 1476 1477 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1478 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 1479 return; 1480 1481 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1482 current_data_rate = (speed_cntl & PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK) >> 1483 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT; 1484 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1485 if (current_data_rate == 2) { 1486 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1487 return; 1488 } 1489 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1490 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { 1491 if (current_data_rate == 1) { 1492 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1493 return; 1494 } 1495 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1496 } 1497 1498 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1499 return; 1500 1501 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1502 /* re-try equalization if gen3 is not already enabled */ 1503 if (current_data_rate != 2) { 1504 u16 bridge_cfg, gpu_cfg; 1505 u16 bridge_cfg2, gpu_cfg2; 1506 u32 max_lw, current_lw, tmp; 1507 1508 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1509 &bridge_cfg); 1510 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1511 &gpu_cfg); 1512 1513 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1514 pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1515 1516 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1517 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1518 tmp16); 1519 1520 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); 1521 max_lw = (tmp & PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH_MASK) >> 1522 PCIE_LC_STATUS1__LC_DETECTED_LINK_WIDTH__SHIFT; 1523 current_lw = (tmp & PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH_MASK) 1524 >> PCIE_LC_STATUS1__LC_OPERATING_LINK_WIDTH__SHIFT; 1525 1526 if (current_lw < max_lw) { 1527 tmp = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1528 if (tmp & PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATION_SUPPORT_MASK) { 1529 tmp &= ~(PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_MASK | 1530 PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_DIS_MASK); 1531 tmp |= (max_lw << 1532 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH__SHIFT); 1533 tmp |= PCIE_LC_LINK_WIDTH_CNTL__LC_UPCONFIGURE_SUPPORT_MASK | 1534 PCIE_LC_LINK_WIDTH_CNTL__LC_RENEGOTIATE_EN_MASK | 1535 PCIE_LC_LINK_WIDTH_CNTL__LC_RECONFIG_NOW_MASK; 1536 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, tmp); 1537 } 1538 } 1539 1540 for (i = 0; i < 10; i++) { 1541 /* check status */ 1542 pcie_capability_read_word(adev->pdev, 1543 PCI_EXP_DEVSTA, 1544 &tmp16); 1545 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1546 break; 1547 1548 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1549 &bridge_cfg); 1550 pcie_capability_read_word(adev->pdev, 1551 PCI_EXP_LNKCTL, 1552 &gpu_cfg); 1553 1554 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1555 &bridge_cfg2); 1556 pcie_capability_read_word(adev->pdev, 1557 PCI_EXP_LNKCTL2, 1558 &gpu_cfg2); 1559 1560 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1561 tmp |= PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1562 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1563 1564 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1565 tmp |= PCIE_LC_CNTL4__LC_REDO_EQ_MASK; 1566 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1567 1568 msleep(100); 1569 1570 /* linkctl */ 1571 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1572 &tmp16); 1573 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1574 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1575 pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1576 tmp16); 1577 1578 pcie_capability_read_word(adev->pdev, 1579 PCI_EXP_LNKCTL, 1580 &tmp16); 1581 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1582 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1583 pcie_capability_write_word(adev->pdev, 1584 PCI_EXP_LNKCTL, 1585 tmp16); 1586 1587 /* linkctl2 */ 1588 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1589 &tmp16); 1590 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1591 PCI_EXP_LNKCTL2_TX_MARGIN); 1592 tmp16 |= (bridge_cfg2 & 1593 (PCI_EXP_LNKCTL2_ENTER_COMP | 1594 PCI_EXP_LNKCTL2_TX_MARGIN)); 1595 pcie_capability_write_word(root, 1596 PCI_EXP_LNKCTL2, 1597 tmp16); 1598 1599 pcie_capability_read_word(adev->pdev, 1600 PCI_EXP_LNKCTL2, 1601 &tmp16); 1602 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1603 PCI_EXP_LNKCTL2_TX_MARGIN); 1604 tmp16 |= (gpu_cfg2 & 1605 (PCI_EXP_LNKCTL2_ENTER_COMP | 1606 PCI_EXP_LNKCTL2_TX_MARGIN)); 1607 pcie_capability_write_word(adev->pdev, 1608 PCI_EXP_LNKCTL2, 1609 tmp16); 1610 1611 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); 1612 tmp &= ~PCIE_LC_CNTL4__LC_SET_QUIESCE_MASK; 1613 WREG32_PCIE(ixPCIE_LC_CNTL4, tmp); 1614 } 1615 } 1616 } 1617 1618 /* set the link speed */ 1619 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_FORCE_EN_SW_SPEED_CHANGE_MASK | 1620 PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_HW_SPEED_CHANGE_MASK; 1621 speed_cntl &= ~PCIE_LC_SPEED_CNTL__LC_FORCE_DIS_SW_SPEED_CHANGE_MASK; 1622 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1623 1624 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1625 tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1626 1627 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1628 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1629 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1630 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1631 else 1632 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1633 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1634 1635 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1636 speed_cntl |= PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK; 1637 WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl); 1638 1639 for (i = 0; i < adev->usec_timeout; i++) { 1640 speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL); 1641 if ((speed_cntl & PCIE_LC_SPEED_CNTL__LC_INITIATE_LINK_SPEED_CHANGE_MASK) == 0) 1642 break; 1643 udelay(1); 1644 } 1645 #endif 1646 } 1647 1648 static void cik_program_aspm(struct amdgpu_device *adev) 1649 { 1650 u32 data, orig; 1651 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1652 bool disable_clkreq = false; 1653 1654 if (amdgpu_aspm == 0) 1655 return; 1656 1657 if (pci_is_root_bus(adev->pdev->bus)) 1658 return; 1659 1660 /* XXX double check APUs */ 1661 if (adev->flags & AMD_IS_APU) 1662 return; 1663 1664 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1665 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK; 1666 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) | 1667 PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK; 1668 if (orig != data) 1669 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data); 1670 1671 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); 1672 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK; 1673 if (orig != data) 1674 WREG32_PCIE(ixPCIE_LC_CNTL3, data); 1675 1676 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); 1677 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK; 1678 if (orig != data) 1679 WREG32_PCIE(ixPCIE_P_CNTL, data); 1680 1681 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1682 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK | 1683 PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK); 1684 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1685 if (!disable_l0s) 1686 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT); 1687 1688 if (!disable_l1) { 1689 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT); 1690 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; 1691 if (orig != data) 1692 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1693 1694 if (!disable_plloff_in_l1) { 1695 bool clk_req_support; 1696 1697 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0); 1698 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1699 PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1700 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1701 (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1702 if (orig != data) 1703 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data); 1704 1705 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1); 1706 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1707 PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1708 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1709 (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1710 if (orig != data) 1711 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data); 1712 1713 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0); 1714 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK | 1715 PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0_MASK); 1716 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) | 1717 (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_TXS2_0__SHIFT); 1718 if (orig != data) 1719 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data); 1720 1721 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1); 1722 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK | 1723 PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1_MASK); 1724 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) | 1725 (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_TXS2_1__SHIFT); 1726 if (orig != data) 1727 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data); 1728 1729 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL); 1730 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK; 1731 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT); 1732 if (orig != data) 1733 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data); 1734 1735 if (!disable_clkreq) { 1736 #ifdef __NetBSD__ /* XXX amdgpu pcie */ 1737 clk_req_support = false; 1738 #else 1739 struct pci_dev *root = adev->pdev->bus->self; 1740 u32 lnkcap; 1741 1742 clk_req_support = false; 1743 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 1744 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 1745 clk_req_support = true; 1746 #endif 1747 } else { 1748 clk_req_support = false; 1749 } 1750 1751 if (clk_req_support) { 1752 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2); 1753 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK | 1754 PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK; 1755 if (orig != data) 1756 WREG32_PCIE(ixPCIE_LC_CNTL2, data); 1757 1758 orig = data = RREG32_SMC(ixTHM_CLK_CNTL); 1759 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | 1760 THM_CLK_CNTL__TMON_CLK_SEL_MASK); 1761 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) | 1762 (1 << THM_CLK_CNTL__TMON_CLK_SEL__SHIFT); 1763 if (orig != data) 1764 WREG32_SMC(ixTHM_CLK_CNTL, data); 1765 1766 orig = data = RREG32_SMC(ixMISC_CLK_CTRL); 1767 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK | 1768 MISC_CLK_CTRL__ZCLK_SEL_MASK); 1769 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) | 1770 (1 << MISC_CLK_CTRL__ZCLK_SEL__SHIFT); 1771 if (orig != data) 1772 WREG32_SMC(ixMISC_CLK_CTRL, data); 1773 1774 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL); 1775 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK; 1776 if (orig != data) 1777 WREG32_SMC(ixCG_CLKPIN_CNTL, data); 1778 1779 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2); 1780 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK; 1781 if (orig != data) 1782 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data); 1783 1784 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL); 1785 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK; 1786 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT); 1787 if (orig != data) 1788 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data); 1789 } 1790 } 1791 } else { 1792 if (orig != data) 1793 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1794 } 1795 1796 orig = data = RREG32_PCIE(ixPCIE_CNTL2); 1797 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | 1798 PCIE_CNTL2__MST_MEM_LS_EN_MASK | 1799 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK; 1800 if (orig != data) 1801 WREG32_PCIE(ixPCIE_CNTL2, data); 1802 1803 if (!disable_l0s) { 1804 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); 1805 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == 1806 PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) { 1807 data = RREG32_PCIE(ixPCIE_LC_STATUS1); 1808 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) && 1809 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) { 1810 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); 1811 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; 1812 if (orig != data) 1813 WREG32_PCIE(ixPCIE_LC_CNTL, data); 1814 } 1815 } 1816 } 1817 } 1818 1819 static uint32_t cik_get_rev_id(struct amdgpu_device *adev) 1820 { 1821 return (RREG32(mmCC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1822 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1823 } 1824 1825 static void cik_detect_hw_virtualization(struct amdgpu_device *adev) 1826 { 1827 if (is_virtual_machine()) /* passthrough mode */ 1828 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 1829 } 1830 1831 static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1832 { 1833 if (!ring || !ring->funcs->emit_wreg) { 1834 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1835 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1836 } else { 1837 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1838 } 1839 } 1840 1841 static void cik_invalidate_hdp(struct amdgpu_device *adev, 1842 struct amdgpu_ring *ring) 1843 { 1844 if (!ring || !ring->funcs->emit_wreg) { 1845 WREG32(mmHDP_DEBUG0, 1); 1846 RREG32(mmHDP_DEBUG0); 1847 } else { 1848 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1849 } 1850 } 1851 1852 static bool cik_need_full_reset(struct amdgpu_device *adev) 1853 { 1854 /* change this when we support soft reset */ 1855 return true; 1856 } 1857 1858 static void cik_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1859 uint64_t *count1) 1860 { 1861 uint32_t perfctr = 0; 1862 uint64_t cnt0_of, cnt1_of; 1863 int tmp; 1864 1865 /* This reports 0 on APUs, so return to avoid writing/reading registers 1866 * that may or may not be different from their GPU counterparts 1867 */ 1868 if (adev->flags & AMD_IS_APU) 1869 return; 1870 1871 /* Set the 2 events that we wish to watch, defined above */ 1872 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1873 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1874 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1875 1876 /* Write to enable desired perf counters */ 1877 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1878 /* Zero out and enable the perf counters 1879 * Write 0x5: 1880 * Bit 0 = Start all counters(1) 1881 * Bit 2 = Global counter reset enable(1) 1882 */ 1883 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1884 1885 msleep(1000); 1886 1887 /* Load the shadow and disable the perf counters 1888 * Write 0x2: 1889 * Bit 0 = Stop counters(0) 1890 * Bit 1 = Load the shadow counters(1) 1891 */ 1892 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1893 1894 /* Read register values to get any >32bit overflow */ 1895 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1896 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1897 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1898 1899 /* Get the values and add the overflow */ 1900 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1901 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1902 } 1903 1904 static bool cik_need_reset_on_init(struct amdgpu_device *adev) 1905 { 1906 u32 clock_cntl, pc; 1907 1908 if (adev->flags & AMD_IS_APU) 1909 return false; 1910 1911 /* check if the SMC is already running */ 1912 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); 1913 pc = RREG32_SMC(ixSMC_PC_C); 1914 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && 1915 (0x20100 <= pc)) 1916 return true; 1917 1918 return false; 1919 } 1920 1921 static uint64_t cik_get_pcie_replay_count(struct amdgpu_device *adev) 1922 { 1923 uint64_t nak_r, nak_g; 1924 1925 /* Get the number of NAKs received and generated */ 1926 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1927 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1928 1929 /* Add the total number of NAKs, i.e the number of replays */ 1930 return (nak_r + nak_g); 1931 } 1932 1933 static const struct amdgpu_asic_funcs cik_asic_funcs = 1934 { 1935 .read_disabled_bios = &cik_read_disabled_bios, 1936 .read_bios_from_rom = &cik_read_bios_from_rom, 1937 .read_register = &cik_read_register, 1938 .reset = &cik_asic_reset, 1939 .reset_method = &cik_asic_reset_method, 1940 .set_vga_state = &cik_vga_set_state, 1941 .get_xclk = &cik_get_xclk, 1942 .set_uvd_clocks = &cik_set_uvd_clocks, 1943 .set_vce_clocks = &cik_set_vce_clocks, 1944 .get_config_memsize = &cik_get_config_memsize, 1945 .flush_hdp = &cik_flush_hdp, 1946 .invalidate_hdp = &cik_invalidate_hdp, 1947 .need_full_reset = &cik_need_full_reset, 1948 .init_doorbell_index = &legacy_doorbell_index_init, 1949 .get_pcie_usage = &cik_get_pcie_usage, 1950 .need_reset_on_init = &cik_need_reset_on_init, 1951 .get_pcie_replay_count = &cik_get_pcie_replay_count, 1952 .supports_baco = &cik_asic_supports_baco, 1953 }; 1954 1955 static int cik_common_early_init(void *handle) 1956 { 1957 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1958 1959 adev->smc_rreg = &cik_smc_rreg; 1960 adev->smc_wreg = &cik_smc_wreg; 1961 adev->pcie_rreg = &cik_pcie_rreg; 1962 adev->pcie_wreg = &cik_pcie_wreg; 1963 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg; 1964 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg; 1965 adev->didt_rreg = &cik_didt_rreg; 1966 adev->didt_wreg = &cik_didt_wreg; 1967 1968 adev->asic_funcs = &cik_asic_funcs; 1969 1970 adev->rev_id = cik_get_rev_id(adev); 1971 adev->external_rev_id = 0xFF; 1972 switch (adev->asic_type) { 1973 case CHIP_BONAIRE: 1974 adev->cg_flags = 1975 AMD_CG_SUPPORT_GFX_MGCG | 1976 AMD_CG_SUPPORT_GFX_MGLS | 1977 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1978 AMD_CG_SUPPORT_GFX_CGLS | 1979 AMD_CG_SUPPORT_GFX_CGTS | 1980 AMD_CG_SUPPORT_GFX_CGTS_LS | 1981 AMD_CG_SUPPORT_GFX_CP_LS | 1982 AMD_CG_SUPPORT_MC_LS | 1983 AMD_CG_SUPPORT_MC_MGCG | 1984 AMD_CG_SUPPORT_SDMA_MGCG | 1985 AMD_CG_SUPPORT_SDMA_LS | 1986 AMD_CG_SUPPORT_BIF_LS | 1987 AMD_CG_SUPPORT_VCE_MGCG | 1988 AMD_CG_SUPPORT_UVD_MGCG | 1989 AMD_CG_SUPPORT_HDP_LS | 1990 AMD_CG_SUPPORT_HDP_MGCG; 1991 adev->pg_flags = 0; 1992 adev->external_rev_id = adev->rev_id + 0x14; 1993 break; 1994 case CHIP_HAWAII: 1995 adev->cg_flags = 1996 AMD_CG_SUPPORT_GFX_MGCG | 1997 AMD_CG_SUPPORT_GFX_MGLS | 1998 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1999 AMD_CG_SUPPORT_GFX_CGLS | 2000 AMD_CG_SUPPORT_GFX_CGTS | 2001 AMD_CG_SUPPORT_GFX_CP_LS | 2002 AMD_CG_SUPPORT_MC_LS | 2003 AMD_CG_SUPPORT_MC_MGCG | 2004 AMD_CG_SUPPORT_SDMA_MGCG | 2005 AMD_CG_SUPPORT_SDMA_LS | 2006 AMD_CG_SUPPORT_BIF_LS | 2007 AMD_CG_SUPPORT_VCE_MGCG | 2008 AMD_CG_SUPPORT_UVD_MGCG | 2009 AMD_CG_SUPPORT_HDP_LS | 2010 AMD_CG_SUPPORT_HDP_MGCG; 2011 adev->pg_flags = 0; 2012 adev->external_rev_id = 0x28; 2013 break; 2014 case CHIP_KAVERI: 2015 adev->cg_flags = 2016 AMD_CG_SUPPORT_GFX_MGCG | 2017 AMD_CG_SUPPORT_GFX_MGLS | 2018 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2019 AMD_CG_SUPPORT_GFX_CGLS | 2020 AMD_CG_SUPPORT_GFX_CGTS | 2021 AMD_CG_SUPPORT_GFX_CGTS_LS | 2022 AMD_CG_SUPPORT_GFX_CP_LS | 2023 AMD_CG_SUPPORT_SDMA_MGCG | 2024 AMD_CG_SUPPORT_SDMA_LS | 2025 AMD_CG_SUPPORT_BIF_LS | 2026 AMD_CG_SUPPORT_VCE_MGCG | 2027 AMD_CG_SUPPORT_UVD_MGCG | 2028 AMD_CG_SUPPORT_HDP_LS | 2029 AMD_CG_SUPPORT_HDP_MGCG; 2030 adev->pg_flags = 2031 /*AMD_PG_SUPPORT_GFX_PG | 2032 AMD_PG_SUPPORT_GFX_SMG | 2033 AMD_PG_SUPPORT_GFX_DMG |*/ 2034 AMD_PG_SUPPORT_UVD | 2035 AMD_PG_SUPPORT_VCE | 2036 /* AMD_PG_SUPPORT_CP | 2037 AMD_PG_SUPPORT_GDS | 2038 AMD_PG_SUPPORT_RLC_SMU_HS | 2039 AMD_PG_SUPPORT_ACP | 2040 AMD_PG_SUPPORT_SAMU |*/ 2041 0; 2042 if (adev->pdev->device == 0x1312 || 2043 adev->pdev->device == 0x1316 || 2044 adev->pdev->device == 0x1317) 2045 adev->external_rev_id = 0x41; 2046 else 2047 adev->external_rev_id = 0x1; 2048 break; 2049 case CHIP_KABINI: 2050 case CHIP_MULLINS: 2051 adev->cg_flags = 2052 AMD_CG_SUPPORT_GFX_MGCG | 2053 AMD_CG_SUPPORT_GFX_MGLS | 2054 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 2055 AMD_CG_SUPPORT_GFX_CGLS | 2056 AMD_CG_SUPPORT_GFX_CGTS | 2057 AMD_CG_SUPPORT_GFX_CGTS_LS | 2058 AMD_CG_SUPPORT_GFX_CP_LS | 2059 AMD_CG_SUPPORT_SDMA_MGCG | 2060 AMD_CG_SUPPORT_SDMA_LS | 2061 AMD_CG_SUPPORT_BIF_LS | 2062 AMD_CG_SUPPORT_VCE_MGCG | 2063 AMD_CG_SUPPORT_UVD_MGCG | 2064 AMD_CG_SUPPORT_HDP_LS | 2065 AMD_CG_SUPPORT_HDP_MGCG; 2066 adev->pg_flags = 2067 /*AMD_PG_SUPPORT_GFX_PG | 2068 AMD_PG_SUPPORT_GFX_SMG | */ 2069 AMD_PG_SUPPORT_UVD | 2070 /*AMD_PG_SUPPORT_VCE | 2071 AMD_PG_SUPPORT_CP | 2072 AMD_PG_SUPPORT_GDS | 2073 AMD_PG_SUPPORT_RLC_SMU_HS | 2074 AMD_PG_SUPPORT_SAMU |*/ 2075 0; 2076 if (adev->asic_type == CHIP_KABINI) { 2077 if (adev->rev_id == 0) 2078 adev->external_rev_id = 0x81; 2079 else if (adev->rev_id == 1) 2080 adev->external_rev_id = 0x82; 2081 else if (adev->rev_id == 2) 2082 adev->external_rev_id = 0x85; 2083 } else 2084 adev->external_rev_id = adev->rev_id + 0xa1; 2085 break; 2086 default: 2087 /* FIXME: not supported yet */ 2088 return -EINVAL; 2089 } 2090 2091 return 0; 2092 } 2093 2094 static int cik_common_sw_init(void *handle) 2095 { 2096 return 0; 2097 } 2098 2099 static int cik_common_sw_fini(void *handle) 2100 { 2101 return 0; 2102 } 2103 2104 static int cik_common_hw_init(void *handle) 2105 { 2106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2107 2108 /* move the golden regs per IP block */ 2109 cik_init_golden_registers(adev); 2110 /* enable pcie gen2/3 link */ 2111 cik_pcie_gen3_enable(adev); 2112 /* enable aspm */ 2113 cik_program_aspm(adev); 2114 2115 return 0; 2116 } 2117 2118 static int cik_common_hw_fini(void *handle) 2119 { 2120 return 0; 2121 } 2122 2123 static int cik_common_suspend(void *handle) 2124 { 2125 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2126 2127 return cik_common_hw_fini(adev); 2128 } 2129 2130 static int cik_common_resume(void *handle) 2131 { 2132 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2133 2134 return cik_common_hw_init(adev); 2135 } 2136 2137 static bool cik_common_is_idle(void *handle) 2138 { 2139 return true; 2140 } 2141 2142 static int cik_common_wait_for_idle(void *handle) 2143 { 2144 return 0; 2145 } 2146 2147 static int cik_common_soft_reset(void *handle) 2148 { 2149 /* XXX hard reset?? */ 2150 return 0; 2151 } 2152 2153 static int cik_common_set_clockgating_state(void *handle, 2154 enum amd_clockgating_state state) 2155 { 2156 return 0; 2157 } 2158 2159 static int cik_common_set_powergating_state(void *handle, 2160 enum amd_powergating_state state) 2161 { 2162 return 0; 2163 } 2164 2165 static const struct amd_ip_funcs cik_common_ip_funcs = { 2166 .name = "cik_common", 2167 .early_init = cik_common_early_init, 2168 .late_init = NULL, 2169 .sw_init = cik_common_sw_init, 2170 .sw_fini = cik_common_sw_fini, 2171 .hw_init = cik_common_hw_init, 2172 .hw_fini = cik_common_hw_fini, 2173 .suspend = cik_common_suspend, 2174 .resume = cik_common_resume, 2175 .is_idle = cik_common_is_idle, 2176 .wait_for_idle = cik_common_wait_for_idle, 2177 .soft_reset = cik_common_soft_reset, 2178 .set_clockgating_state = cik_common_set_clockgating_state, 2179 .set_powergating_state = cik_common_set_powergating_state, 2180 }; 2181 2182 static const struct amdgpu_ip_block_version cik_common_ip_block = 2183 { 2184 .type = AMD_IP_BLOCK_TYPE_COMMON, 2185 .major = 1, 2186 .minor = 0, 2187 .rev = 0, 2188 .funcs = &cik_common_ip_funcs, 2189 }; 2190 2191 int cik_set_ip_blocks(struct amdgpu_device *adev) 2192 { 2193 cik_detect_hw_virtualization(adev); 2194 2195 switch (adev->asic_type) { 2196 case CHIP_BONAIRE: 2197 amdgpu_device_ip_block_add(adev, &cik_common_ip_block); 2198 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); 2199 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); 2200 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); 2201 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); 2202 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2203 if (adev->enable_virtual_display) 2204 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2205 #if defined(CONFIG_DRM_AMD_DC) 2206 else if (amdgpu_device_has_dc_support(adev)) 2207 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2208 #endif 2209 else 2210 amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block); 2211 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); 2212 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); 2213 break; 2214 case CHIP_HAWAII: 2215 amdgpu_device_ip_block_add(adev, &cik_common_ip_block); 2216 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); 2217 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); 2218 amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block); 2219 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); 2220 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2221 if (adev->enable_virtual_display) 2222 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2223 #if defined(CONFIG_DRM_AMD_DC) 2224 else if (amdgpu_device_has_dc_support(adev)) 2225 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2226 #endif 2227 else 2228 amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block); 2229 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); 2230 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); 2231 break; 2232 case CHIP_KAVERI: 2233 amdgpu_device_ip_block_add(adev, &cik_common_ip_block); 2234 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); 2235 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); 2236 amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block); 2237 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); 2238 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block); 2239 if (adev->enable_virtual_display) 2240 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2241 #if defined(CONFIG_DRM_AMD_DC) 2242 else if (amdgpu_device_has_dc_support(adev)) 2243 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2244 #endif 2245 else 2246 amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block); 2247 2248 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); 2249 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); 2250 break; 2251 case CHIP_KABINI: 2252 case CHIP_MULLINS: 2253 amdgpu_device_ip_block_add(adev, &cik_common_ip_block); 2254 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block); 2255 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block); 2256 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block); 2257 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block); 2258 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block); 2259 if (adev->enable_virtual_display) 2260 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2261 #if defined(CONFIG_DRM_AMD_DC) 2262 else if (amdgpu_device_has_dc_support(adev)) 2263 amdgpu_device_ip_block_add(adev, &dm_ip_block); 2264 #endif 2265 else 2266 amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block); 2267 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block); 2268 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block); 2269 break; 2270 default: 2271 /* FIXME: not supported yet */ 2272 return -EINVAL; 2273 } 2274 return 0; 2275 } 2276
Indexes created Mon Sep 29 21:09:56 GMT 2025