amdgpu_display.c revision 1.1
1 /* $NetBSD: amdgpu_display.c,v 1.1 2018/08/27 01:34:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_display.c,v 1.1 2018/08/27 01:34:43 riastradh Exp $"); 30 31 #include <drm/drmP.h> 32 #include <drm/amdgpu_drm.h> 33 #include "amdgpu.h" 34 #include "amdgpu_i2c.h" 35 #include "atom.h" 36 #include "amdgpu_connectors.h" 37 #include <asm/div64.h> 38 39 #include <linux/pm_runtime.h> 40 #include <drm/drm_crtc_helper.h> 41 #include <drm/drm_edid.h> 42 43 static void amdgpu_flip_wait_fence(struct amdgpu_device *adev, 44 struct fence **f) 45 { 46 struct amdgpu_fence *fence; 47 long r; 48 49 if (*f == NULL) 50 return; 51 52 fence = to_amdgpu_fence(*f); 53 if (fence) { 54 r = fence_wait(&fence->base, false); 55 if (r == -EDEADLK) 56 r = amdgpu_gpu_reset(adev); 57 } else 58 r = fence_wait(*f, false); 59 60 if (r) 61 DRM_ERROR("failed to wait on page flip fence (%ld)!\n", r); 62 63 /* We continue with the page flip even if we failed to wait on 64 * the fence, otherwise the DRM core and userspace will be 65 * confused about which BO the CRTC is scanning out 66 */ 67 fence_put(*f); 68 *f = NULL; 69 } 70 71 static void amdgpu_flip_work_func(struct work_struct *__work) 72 { 73 struct amdgpu_flip_work *work = 74 container_of(__work, struct amdgpu_flip_work, flip_work); 75 struct amdgpu_device *adev = work->adev; 76 struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; 77 78 struct drm_crtc *crtc = &amdgpuCrtc->base; 79 unsigned long flags; 80 unsigned i, repcnt = 4; 81 int vpos, hpos, stat, min_udelay = 0; 82 struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; 83 84 amdgpu_flip_wait_fence(adev, &work->excl); 85 for (i = 0; i < work->shared_count; ++i) 86 amdgpu_flip_wait_fence(adev, &work->shared[i]); 87 88 /* We borrow the event spin lock for protecting flip_status */ 89 spin_lock_irqsave(&crtc->dev->event_lock, flags); 90 91 /* If this happens to execute within the "virtually extended" vblank 92 * interval before the start of the real vblank interval then it needs 93 * to delay programming the mmio flip until the real vblank is entered. 94 * This prevents completing a flip too early due to the way we fudge 95 * our vblank counter and vblank timestamps in order to work around the 96 * problem that the hw fires vblank interrupts before actual start of 97 * vblank (when line buffer refilling is done for a frame). It 98 * complements the fudging logic in amdgpu_get_crtc_scanoutpos() for 99 * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. 100 * 101 * In practice this won't execute very often unless on very fast 102 * machines because the time window for this to happen is very small. 103 */ 104 while (amdgpuCrtc->enabled && --repcnt) { 105 /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank 106 * start in hpos, and to the "fudged earlier" vblank start in 107 * vpos. 108 */ 109 stat = amdgpu_get_crtc_scanoutpos(adev->ddev, work->crtc_id, 110 GET_DISTANCE_TO_VBLANKSTART, 111 &vpos, &hpos, NULL, NULL, 112 &crtc->hwmode); 113 114 if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 115 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || 116 !(vpos >= 0 && hpos <= 0)) 117 break; 118 119 /* Sleep at least until estimated real start of hw vblank */ 120 min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); 121 if (min_udelay > vblank->framedur_ns / 2000) { 122 /* Don't wait ridiculously long - something is wrong */ 123 repcnt = 0; 124 break; 125 } 126 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 127 usleep_range(min_udelay, 2 * min_udelay); 128 spin_lock_irqsave(&crtc->dev->event_lock, flags); 129 }; 130 131 if (!repcnt) 132 DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " 133 "framedur %d, linedur %d, stat %d, vpos %d, " 134 "hpos %d\n", work->crtc_id, min_udelay, 135 vblank->framedur_ns / 1000, 136 vblank->linedur_ns / 1000, stat, vpos, hpos); 137 138 /* do the flip (mmio) */ 139 adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base); 140 /* set the flip status */ 141 amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; 142 143 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 144 } 145 146 /* 147 * Handle unpin events outside the interrupt handler proper. 148 */ 149 static void amdgpu_unpin_work_func(struct work_struct *__work) 150 { 151 struct amdgpu_flip_work *work = 152 container_of(__work, struct amdgpu_flip_work, unpin_work); 153 int r; 154 155 /* unpin of the old buffer */ 156 r = amdgpu_bo_reserve(work->old_rbo, false); 157 if (likely(r == 0)) { 158 r = amdgpu_bo_unpin(work->old_rbo); 159 if (unlikely(r != 0)) { 160 DRM_ERROR("failed to unpin buffer after flip\n"); 161 } 162 amdgpu_bo_unreserve(work->old_rbo); 163 } else 164 DRM_ERROR("failed to reserve buffer after flip\n"); 165 166 amdgpu_bo_unref(&work->old_rbo); 167 kfree(work->shared); 168 kfree(work); 169 } 170 171 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 172 struct drm_framebuffer *fb, 173 struct drm_pending_vblank_event *event, 174 uint32_t page_flip_flags) 175 { 176 struct drm_device *dev = crtc->dev; 177 struct amdgpu_device *adev = dev->dev_private; 178 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 179 struct amdgpu_framebuffer *old_amdgpu_fb; 180 struct amdgpu_framebuffer *new_amdgpu_fb; 181 struct drm_gem_object *obj; 182 struct amdgpu_flip_work *work; 183 struct amdgpu_bo *new_rbo; 184 unsigned long flags; 185 u64 tiling_flags; 186 u64 base; 187 int i, r; 188 189 work = kzalloc(sizeof *work, GFP_KERNEL); 190 if (work == NULL) 191 return -ENOMEM; 192 193 INIT_WORK(&work->flip_work, amdgpu_flip_work_func); 194 INIT_WORK(&work->unpin_work, amdgpu_unpin_work_func); 195 196 work->event = event; 197 work->adev = adev; 198 work->crtc_id = amdgpu_crtc->crtc_id; 199 200 /* schedule unpin of the old buffer */ 201 old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); 202 obj = old_amdgpu_fb->obj; 203 204 /* take a reference to the old object */ 205 work->old_rbo = gem_to_amdgpu_bo(obj); 206 amdgpu_bo_ref(work->old_rbo); 207 208 new_amdgpu_fb = to_amdgpu_framebuffer(fb); 209 obj = new_amdgpu_fb->obj; 210 new_rbo = gem_to_amdgpu_bo(obj); 211 212 /* pin the new buffer */ 213 r = amdgpu_bo_reserve(new_rbo, false); 214 if (unlikely(r != 0)) { 215 DRM_ERROR("failed to reserve new rbo buffer before flip\n"); 216 goto cleanup; 217 } 218 219 r = amdgpu_bo_pin_restricted(new_rbo, AMDGPU_GEM_DOMAIN_VRAM, 0, 0, &base); 220 if (unlikely(r != 0)) { 221 amdgpu_bo_unreserve(new_rbo); 222 r = -EINVAL; 223 DRM_ERROR("failed to pin new rbo buffer before flip\n"); 224 goto cleanup; 225 } 226 227 r = reservation_object_get_fences_rcu(new_rbo->tbo.resv, &work->excl, 228 &work->shared_count, 229 &work->shared); 230 if (unlikely(r != 0)) { 231 amdgpu_bo_unreserve(new_rbo); 232 DRM_ERROR("failed to get fences for buffer\n"); 233 goto cleanup; 234 } 235 236 amdgpu_bo_get_tiling_flags(new_rbo, &tiling_flags); 237 amdgpu_bo_unreserve(new_rbo); 238 239 work->base = base; 240 241 r = drm_vblank_get(crtc->dev, amdgpu_crtc->crtc_id); 242 if (r) { 243 DRM_ERROR("failed to get vblank before flip\n"); 244 goto pflip_cleanup; 245 } 246 247 /* we borrow the event spin lock for protecting flip_wrok */ 248 spin_lock_irqsave(&crtc->dev->event_lock, flags); 249 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { 250 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 251 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 252 r = -EBUSY; 253 goto vblank_cleanup; 254 } 255 256 amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; 257 amdgpu_crtc->pflip_works = work; 258 259 /* update crtc fb */ 260 crtc->primary->fb = fb; 261 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 262 queue_work(amdgpu_crtc->pflip_queue, &work->flip_work); 263 return 0; 264 265 vblank_cleanup: 266 drm_vblank_put(crtc->dev, amdgpu_crtc->crtc_id); 267 268 pflip_cleanup: 269 if (unlikely(amdgpu_bo_reserve(new_rbo, false) != 0)) { 270 DRM_ERROR("failed to reserve new rbo in error path\n"); 271 goto cleanup; 272 } 273 if (unlikely(amdgpu_bo_unpin(new_rbo) != 0)) { 274 DRM_ERROR("failed to unpin new rbo in error path\n"); 275 } 276 amdgpu_bo_unreserve(new_rbo); 277 278 cleanup: 279 amdgpu_bo_unref(&work->old_rbo); 280 fence_put(work->excl); 281 for (i = 0; i < work->shared_count; ++i) 282 fence_put(work->shared[i]); 283 kfree(work->shared); 284 kfree(work); 285 286 return r; 287 } 288 289 int amdgpu_crtc_set_config(struct drm_mode_set *set) 290 { 291 struct drm_device *dev; 292 struct amdgpu_device *adev; 293 struct drm_crtc *crtc; 294 bool active = false; 295 int ret; 296 297 if (!set || !set->crtc) 298 return -EINVAL; 299 300 dev = set->crtc->dev; 301 302 ret = pm_runtime_get_sync(dev->dev); 303 if (ret < 0) 304 return ret; 305 306 ret = drm_crtc_helper_set_config(set); 307 308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) 309 if (crtc->enabled) 310 active = true; 311 312 pm_runtime_mark_last_busy(dev->dev); 313 314 adev = dev->dev_private; 315 /* if we have active crtcs and we don't have a power ref, 316 take the current one */ 317 if (active && !adev->have_disp_power_ref) { 318 adev->have_disp_power_ref = true; 319 return ret; 320 } 321 /* if we have no active crtcs, then drop the power ref 322 we got before */ 323 if (!active && adev->have_disp_power_ref) { 324 pm_runtime_put_autosuspend(dev->dev); 325 adev->have_disp_power_ref = false; 326 } 327 328 /* drop the power reference we got coming in here */ 329 pm_runtime_put_autosuspend(dev->dev); 330 return ret; 331 } 332 333 static const char *encoder_names[38] = { 334 "NONE", 335 "INTERNAL_LVDS", 336 "INTERNAL_TMDS1", 337 "INTERNAL_TMDS2", 338 "INTERNAL_DAC1", 339 "INTERNAL_DAC2", 340 "INTERNAL_SDVOA", 341 "INTERNAL_SDVOB", 342 "SI170B", 343 "CH7303", 344 "CH7301", 345 "INTERNAL_DVO1", 346 "EXTERNAL_SDVOA", 347 "EXTERNAL_SDVOB", 348 "TITFP513", 349 "INTERNAL_LVTM1", 350 "VT1623", 351 "HDMI_SI1930", 352 "HDMI_INTERNAL", 353 "INTERNAL_KLDSCP_TMDS1", 354 "INTERNAL_KLDSCP_DVO1", 355 "INTERNAL_KLDSCP_DAC1", 356 "INTERNAL_KLDSCP_DAC2", 357 "SI178", 358 "MVPU_FPGA", 359 "INTERNAL_DDI", 360 "VT1625", 361 "HDMI_SI1932", 362 "DP_AN9801", 363 "DP_DP501", 364 "INTERNAL_UNIPHY", 365 "INTERNAL_KLDSCP_LVTMA", 366 "INTERNAL_UNIPHY1", 367 "INTERNAL_UNIPHY2", 368 "NUTMEG", 369 "TRAVIS", 370 "INTERNAL_VCE", 371 "INTERNAL_UNIPHY3", 372 }; 373 374 static const char *hpd_names[6] = { 375 "HPD1", 376 "HPD2", 377 "HPD3", 378 "HPD4", 379 "HPD5", 380 "HPD6", 381 }; 382 383 void amdgpu_print_display_setup(struct drm_device *dev) 384 { 385 struct drm_connector *connector; 386 struct amdgpu_connector *amdgpu_connector; 387 struct drm_encoder *encoder; 388 struct amdgpu_encoder *amdgpu_encoder; 389 uint32_t devices; 390 int i = 0; 391 392 DRM_INFO("AMDGPU Display Connectors\n"); 393 list_for_each_entry(connector, &dev->mode_config.connector_list, head) { 394 amdgpu_connector = to_amdgpu_connector(connector); 395 DRM_INFO("Connector %d:\n", i); 396 DRM_INFO(" %s\n", connector->name); 397 if (amdgpu_connector->hpd.hpd != AMDGPU_HPD_NONE) 398 DRM_INFO(" %s\n", hpd_names[amdgpu_connector->hpd.hpd]); 399 if (amdgpu_connector->ddc_bus) { 400 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", 401 amdgpu_connector->ddc_bus->rec.mask_clk_reg, 402 amdgpu_connector->ddc_bus->rec.mask_data_reg, 403 amdgpu_connector->ddc_bus->rec.a_clk_reg, 404 amdgpu_connector->ddc_bus->rec.a_data_reg, 405 amdgpu_connector->ddc_bus->rec.en_clk_reg, 406 amdgpu_connector->ddc_bus->rec.en_data_reg, 407 amdgpu_connector->ddc_bus->rec.y_clk_reg, 408 amdgpu_connector->ddc_bus->rec.y_data_reg); 409 if (amdgpu_connector->router.ddc_valid) 410 DRM_INFO(" DDC Router 0x%x/0x%x\n", 411 amdgpu_connector->router.ddc_mux_control_pin, 412 amdgpu_connector->router.ddc_mux_state); 413 if (amdgpu_connector->router.cd_valid) 414 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n", 415 amdgpu_connector->router.cd_mux_control_pin, 416 amdgpu_connector->router.cd_mux_state); 417 } else { 418 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA || 419 connector->connector_type == DRM_MODE_CONNECTOR_DVII || 420 connector->connector_type == DRM_MODE_CONNECTOR_DVID || 421 connector->connector_type == DRM_MODE_CONNECTOR_DVIA || 422 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA || 423 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB) 424 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati (at) lists.x.org\n"); 425 } 426 DRM_INFO(" Encoders:\n"); 427 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 428 amdgpu_encoder = to_amdgpu_encoder(encoder); 429 devices = amdgpu_encoder->devices & amdgpu_connector->devices; 430 if (devices) { 431 if (devices & ATOM_DEVICE_CRT1_SUPPORT) 432 DRM_INFO(" CRT1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 433 if (devices & ATOM_DEVICE_CRT2_SUPPORT) 434 DRM_INFO(" CRT2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 435 if (devices & ATOM_DEVICE_LCD1_SUPPORT) 436 DRM_INFO(" LCD1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 437 if (devices & ATOM_DEVICE_DFP1_SUPPORT) 438 DRM_INFO(" DFP1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 439 if (devices & ATOM_DEVICE_DFP2_SUPPORT) 440 DRM_INFO(" DFP2: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 441 if (devices & ATOM_DEVICE_DFP3_SUPPORT) 442 DRM_INFO(" DFP3: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 443 if (devices & ATOM_DEVICE_DFP4_SUPPORT) 444 DRM_INFO(" DFP4: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 445 if (devices & ATOM_DEVICE_DFP5_SUPPORT) 446 DRM_INFO(" DFP5: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 447 if (devices & ATOM_DEVICE_DFP6_SUPPORT) 448 DRM_INFO(" DFP6: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 449 if (devices & ATOM_DEVICE_TV1_SUPPORT) 450 DRM_INFO(" TV1: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 451 if (devices & ATOM_DEVICE_CV_SUPPORT) 452 DRM_INFO(" CV: %s\n", encoder_names[amdgpu_encoder->encoder_id]); 453 } 454 } 455 i++; 456 } 457 } 458 459 /** 460 * amdgpu_ddc_probe 461 * 462 */ 463 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, 464 bool use_aux) 465 { 466 u8 out = 0x0; 467 u8 buf[8]; 468 int ret; 469 struct i2c_msg msgs[] = { 470 { 471 .addr = DDC_ADDR, 472 .flags = 0, 473 .len = 1, 474 .buf = &out, 475 }, 476 { 477 .addr = DDC_ADDR, 478 .flags = I2C_M_RD, 479 .len = 8, 480 .buf = buf, 481 } 482 }; 483 484 /* on hw with routers, select right port */ 485 if (amdgpu_connector->router.ddc_valid) 486 amdgpu_i2c_router_select_ddc_port(amdgpu_connector); 487 488 if (use_aux) { 489 ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); 490 } else { 491 ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); 492 } 493 494 if (ret != 2) 495 /* Couldn't find an accessible DDC on this connector */ 496 return false; 497 /* Probe also for valid EDID header 498 * EDID header starts with: 499 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 500 * Only the first 6 bytes must be valid as 501 * drm_edid_block_valid() can fix the last 2 bytes */ 502 if (drm_edid_header_is_valid(buf) < 6) { 503 /* Couldn't find an accessible EDID on this 504 * connector */ 505 return false; 506 } 507 return true; 508 } 509 510 static void amdgpu_user_framebuffer_destroy(struct drm_framebuffer *fb) 511 { 512 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 513 514 if (amdgpu_fb->obj) { 515 drm_gem_object_unreference_unlocked(amdgpu_fb->obj); 516 } 517 drm_framebuffer_cleanup(fb); 518 kfree(amdgpu_fb); 519 } 520 521 static int amdgpu_user_framebuffer_create_handle(struct drm_framebuffer *fb, 522 struct drm_file *file_priv, 523 unsigned int *handle) 524 { 525 struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); 526 527 return drm_gem_handle_create(file_priv, amdgpu_fb->obj, handle); 528 } 529 530 static const struct drm_framebuffer_funcs amdgpu_fb_funcs = { 531 .destroy = amdgpu_user_framebuffer_destroy, 532 .create_handle = amdgpu_user_framebuffer_create_handle, 533 }; 534 535 int 536 amdgpu_framebuffer_init(struct drm_device *dev, 537 struct amdgpu_framebuffer *rfb, 538 struct drm_mode_fb_cmd2 *mode_cmd, 539 struct drm_gem_object *obj) 540 { 541 int ret; 542 rfb->obj = obj; 543 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd); 544 ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); 545 if (ret) { 546 rfb->obj = NULL; 547 return ret; 548 } 549 return 0; 550 } 551 552 static struct drm_framebuffer * 553 amdgpu_user_framebuffer_create(struct drm_device *dev, 554 struct drm_file *file_priv, 555 struct drm_mode_fb_cmd2 *mode_cmd) 556 { 557 struct drm_gem_object *obj; 558 struct amdgpu_framebuffer *amdgpu_fb; 559 int ret; 560 561 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handles[0]); 562 if (obj == NULL) { 563 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, " 564 "can't create framebuffer\n", mode_cmd->handles[0]); 565 return ERR_PTR(-ENOENT); 566 } 567 568 /* Handle is imported dma-buf, so cannot be migrated to VRAM for scanout */ 569 if (obj->import_attach) { 570 DRM_DEBUG_KMS("Cannot create framebuffer from imported dma_buf\n"); 571 return ERR_PTR(-EINVAL); 572 } 573 574 amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); 575 if (amdgpu_fb == NULL) { 576 drm_gem_object_unreference_unlocked(obj); 577 return ERR_PTR(-ENOMEM); 578 } 579 580 ret = amdgpu_framebuffer_init(dev, amdgpu_fb, mode_cmd, obj); 581 if (ret) { 582 kfree(amdgpu_fb); 583 drm_gem_object_unreference_unlocked(obj); 584 return ERR_PTR(ret); 585 } 586 587 return &amdgpu_fb->base; 588 } 589 590 static void amdgpu_output_poll_changed(struct drm_device *dev) 591 { 592 struct amdgpu_device *adev = dev->dev_private; 593 amdgpu_fb_output_poll_changed(adev); 594 } 595 596 const struct drm_mode_config_funcs amdgpu_mode_funcs = { 597 .fb_create = amdgpu_user_framebuffer_create, 598 .output_poll_changed = amdgpu_output_poll_changed 599 }; 600 601 static struct drm_prop_enum_list amdgpu_underscan_enum_list[] = 602 { { UNDERSCAN_OFF, "off" }, 603 { UNDERSCAN_ON, "on" }, 604 { UNDERSCAN_AUTO, "auto" }, 605 }; 606 607 static struct drm_prop_enum_list amdgpu_audio_enum_list[] = 608 { { AMDGPU_AUDIO_DISABLE, "off" }, 609 { AMDGPU_AUDIO_ENABLE, "on" }, 610 { AMDGPU_AUDIO_AUTO, "auto" }, 611 }; 612 613 /* XXX support different dither options? spatial, temporal, both, etc. */ 614 static struct drm_prop_enum_list amdgpu_dither_enum_list[] = 615 { { AMDGPU_FMT_DITHER_DISABLE, "off" }, 616 { AMDGPU_FMT_DITHER_ENABLE, "on" }, 617 }; 618 619 int amdgpu_modeset_create_props(struct amdgpu_device *adev) 620 { 621 int sz; 622 623 if (adev->is_atom_bios) { 624 adev->mode_info.coherent_mode_property = 625 drm_property_create_range(adev->ddev, 0 , "coherent", 0, 1); 626 if (!adev->mode_info.coherent_mode_property) 627 return -ENOMEM; 628 } 629 630 adev->mode_info.load_detect_property = 631 drm_property_create_range(adev->ddev, 0, "load detection", 0, 1); 632 if (!adev->mode_info.load_detect_property) 633 return -ENOMEM; 634 635 drm_mode_create_scaling_mode_property(adev->ddev); 636 637 sz = ARRAY_SIZE(amdgpu_underscan_enum_list); 638 adev->mode_info.underscan_property = 639 drm_property_create_enum(adev->ddev, 0, 640 "underscan", 641 amdgpu_underscan_enum_list, sz); 642 643 adev->mode_info.underscan_hborder_property = 644 drm_property_create_range(adev->ddev, 0, 645 "underscan hborder", 0, 128); 646 if (!adev->mode_info.underscan_hborder_property) 647 return -ENOMEM; 648 649 adev->mode_info.underscan_vborder_property = 650 drm_property_create_range(adev->ddev, 0, 651 "underscan vborder", 0, 128); 652 if (!adev->mode_info.underscan_vborder_property) 653 return -ENOMEM; 654 655 sz = ARRAY_SIZE(amdgpu_audio_enum_list); 656 adev->mode_info.audio_property = 657 drm_property_create_enum(adev->ddev, 0, 658 "audio", 659 amdgpu_audio_enum_list, sz); 660 661 sz = ARRAY_SIZE(amdgpu_dither_enum_list); 662 adev->mode_info.dither_property = 663 drm_property_create_enum(adev->ddev, 0, 664 "dither", 665 amdgpu_dither_enum_list, sz); 666 667 return 0; 668 } 669 670 void amdgpu_update_display_priority(struct amdgpu_device *adev) 671 { 672 /* adjustment options for the display watermarks */ 673 if ((amdgpu_disp_priority == 0) || (amdgpu_disp_priority > 2)) 674 adev->mode_info.disp_priority = 0; 675 else 676 adev->mode_info.disp_priority = amdgpu_disp_priority; 677 678 } 679 680 static bool is_hdtv_mode(const struct drm_display_mode *mode) 681 { 682 /* try and guess if this is a tv or a monitor */ 683 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */ 684 (mode->vdisplay == 576) || /* 576p */ 685 (mode->vdisplay == 720) || /* 720p */ 686 (mode->vdisplay == 1080)) /* 1080p */ 687 return true; 688 else 689 return false; 690 } 691 692 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 693 const struct drm_display_mode *mode, 694 struct drm_display_mode *adjusted_mode) 695 { 696 struct drm_device *dev = crtc->dev; 697 struct drm_encoder *encoder; 698 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 699 struct amdgpu_encoder *amdgpu_encoder; 700 struct drm_connector *connector; 701 struct amdgpu_connector *amdgpu_connector; 702 u32 src_v = 1, dst_v = 1; 703 u32 src_h = 1, dst_h = 1; 704 705 amdgpu_crtc->h_border = 0; 706 amdgpu_crtc->v_border = 0; 707 708 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 709 if (encoder->crtc != crtc) 710 continue; 711 amdgpu_encoder = to_amdgpu_encoder(encoder); 712 connector = amdgpu_get_connector_for_encoder(encoder); 713 amdgpu_connector = to_amdgpu_connector(connector); 714 715 /* set scaling */ 716 if (amdgpu_encoder->rmx_type == RMX_OFF) 717 amdgpu_crtc->rmx_type = RMX_OFF; 718 else if (mode->hdisplay < amdgpu_encoder->native_mode.hdisplay || 719 mode->vdisplay < amdgpu_encoder->native_mode.vdisplay) 720 amdgpu_crtc->rmx_type = amdgpu_encoder->rmx_type; 721 else 722 amdgpu_crtc->rmx_type = RMX_OFF; 723 /* copy native mode */ 724 memcpy(&amdgpu_crtc->native_mode, 725 &amdgpu_encoder->native_mode, 726 sizeof(struct drm_display_mode)); 727 src_v = crtc->mode.vdisplay; 728 dst_v = amdgpu_crtc->native_mode.vdisplay; 729 src_h = crtc->mode.hdisplay; 730 dst_h = amdgpu_crtc->native_mode.hdisplay; 731 732 /* fix up for overscan on hdmi */ 733 if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && 734 ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || 735 ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && 736 drm_detect_hdmi_monitor(amdgpu_connector_edid(connector)) && 737 is_hdtv_mode(mode)))) { 738 if (amdgpu_encoder->underscan_hborder != 0) 739 amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; 740 else 741 amdgpu_crtc->h_border = (mode->hdisplay >> 5) + 16; 742 if (amdgpu_encoder->underscan_vborder != 0) 743 amdgpu_crtc->v_border = amdgpu_encoder->underscan_vborder; 744 else 745 amdgpu_crtc->v_border = (mode->vdisplay >> 5) + 16; 746 amdgpu_crtc->rmx_type = RMX_FULL; 747 src_v = crtc->mode.vdisplay; 748 dst_v = crtc->mode.vdisplay - (amdgpu_crtc->v_border * 2); 749 src_h = crtc->mode.hdisplay; 750 dst_h = crtc->mode.hdisplay - (amdgpu_crtc->h_border * 2); 751 } 752 } 753 if (amdgpu_crtc->rmx_type != RMX_OFF) { 754 fixed20_12 a, b; 755 a.full = dfixed_const(src_v); 756 b.full = dfixed_const(dst_v); 757 amdgpu_crtc->vsc.full = dfixed_div(a, b); 758 a.full = dfixed_const(src_h); 759 b.full = dfixed_const(dst_h); 760 amdgpu_crtc->hsc.full = dfixed_div(a, b); 761 } else { 762 amdgpu_crtc->vsc.full = dfixed_const(1); 763 amdgpu_crtc->hsc.full = dfixed_const(1); 764 } 765 return true; 766 } 767 768 /* 769 * Retrieve current video scanout position of crtc on a given gpu, and 770 * an optional accurate timestamp of when query happened. 771 * 772 * \param dev Device to query. 773 * \param pipe Crtc to query. 774 * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). 775 * For driver internal use only also supports these flags: 776 * 777 * USE_REAL_VBLANKSTART to use the real start of vblank instead 778 * of a fudged earlier start of vblank. 779 * 780 * GET_DISTANCE_TO_VBLANKSTART to return distance to the 781 * fudged earlier start of vblank in *vpos and the distance 782 * to true start of vblank in *hpos. 783 * 784 * \param *vpos Location where vertical scanout position should be stored. 785 * \param *hpos Location where horizontal scanout position should go. 786 * \param *stime Target location for timestamp taken immediately before 787 * scanout position query. Can be NULL to skip timestamp. 788 * \param *etime Target location for timestamp taken immediately after 789 * scanout position query. Can be NULL to skip timestamp. 790 * 791 * Returns vpos as a positive number while in active scanout area. 792 * Returns vpos as a negative number inside vblank, counting the number 793 * of scanlines to go until end of vblank, e.g., -1 means "one scanline 794 * until start of active scanout / end of vblank." 795 * 796 * \return Flags, or'ed together as follows: 797 * 798 * DRM_SCANOUTPOS_VALID = Query successful. 799 * DRM_SCANOUTPOS_INVBL = Inside vblank. 800 * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of 801 * this flag means that returned position may be offset by a constant but 802 * unknown small number of scanlines wrt. real scanout position. 803 * 804 */ 805 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 806 unsigned int flags, int *vpos, int *hpos, 807 ktime_t *stime, ktime_t *etime, 808 const struct drm_display_mode *mode) 809 { 810 u32 vbl = 0, position = 0; 811 int vbl_start, vbl_end, vtotal, ret = 0; 812 bool in_vbl = true; 813 814 struct amdgpu_device *adev = dev->dev_private; 815 816 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 817 818 /* Get optional system timestamp before query. */ 819 if (stime) 820 *stime = ktime_get(); 821 822 if (amdgpu_display_page_flip_get_scanoutpos(adev, pipe, &vbl, &position) == 0) 823 ret |= DRM_SCANOUTPOS_VALID; 824 825 /* Get optional system timestamp after query. */ 826 if (etime) 827 *etime = ktime_get(); 828 829 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 830 831 /* Decode into vertical and horizontal scanout position. */ 832 *vpos = position & 0x1fff; 833 *hpos = (position >> 16) & 0x1fff; 834 835 /* Valid vblank area boundaries from gpu retrieved? */ 836 if (vbl > 0) { 837 /* Yes: Decode. */ 838 ret |= DRM_SCANOUTPOS_ACCURATE; 839 vbl_start = vbl & 0x1fff; 840 vbl_end = (vbl >> 16) & 0x1fff; 841 } 842 else { 843 /* No: Fake something reasonable which gives at least ok results. */ 844 vbl_start = mode->crtc_vdisplay; 845 vbl_end = 0; 846 } 847 848 /* Called from driver internal vblank counter query code? */ 849 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 850 /* Caller wants distance from real vbl_start in *hpos */ 851 *hpos = *vpos - vbl_start; 852 } 853 854 /* Fudge vblank to start a few scanlines earlier to handle the 855 * problem that vblank irqs fire a few scanlines before start 856 * of vblank. Some driver internal callers need the true vblank 857 * start to be used and signal this via the USE_REAL_VBLANKSTART flag. 858 * 859 * The cause of the "early" vblank irq is that the irq is triggered 860 * by the line buffer logic when the line buffer read position enters 861 * the vblank, whereas our crtc scanout position naturally lags the 862 * line buffer read position. 863 */ 864 if (!(flags & USE_REAL_VBLANKSTART)) 865 vbl_start -= adev->mode_info.crtcs[pipe]->lb_vblank_lead_lines; 866 867 /* Test scanout position against vblank region. */ 868 if ((*vpos < vbl_start) && (*vpos >= vbl_end)) 869 in_vbl = false; 870 871 /* In vblank? */ 872 if (in_vbl) 873 ret |= DRM_SCANOUTPOS_IN_VBLANK; 874 875 /* Called from driver internal vblank counter query code? */ 876 if (flags & GET_DISTANCE_TO_VBLANKSTART) { 877 /* Caller wants distance from fudged earlier vbl_start */ 878 *vpos -= vbl_start; 879 return ret; 880 } 881 882 /* Check if inside vblank area and apply corrective offsets: 883 * vpos will then be >=0 in video scanout area, but negative 884 * within vblank area, counting down the number of lines until 885 * start of scanout. 886 */ 887 888 /* Inside "upper part" of vblank area? Apply corrective offset if so: */ 889 if (in_vbl && (*vpos >= vbl_start)) { 890 vtotal = mode->crtc_vtotal; 891 *vpos = *vpos - vtotal; 892 } 893 894 /* Correct for shifted end of vbl at vbl_end. */ 895 *vpos = *vpos - vbl_end; 896 897 return ret; 898 } 899 900 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc) 901 { 902 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) 903 return AMDGPU_CRTC_IRQ_NONE; 904 905 switch (crtc) { 906 case 0: 907 return AMDGPU_CRTC_IRQ_VBLANK1; 908 case 1: 909 return AMDGPU_CRTC_IRQ_VBLANK2; 910 case 2: 911 return AMDGPU_CRTC_IRQ_VBLANK3; 912 case 3: 913 return AMDGPU_CRTC_IRQ_VBLANK4; 914 case 4: 915 return AMDGPU_CRTC_IRQ_VBLANK5; 916 case 5: 917 return AMDGPU_CRTC_IRQ_VBLANK6; 918 default: 919 return AMDGPU_CRTC_IRQ_NONE; 920 } 921 } 922
Indexes created Mon Sep 29 13:09:55 GMT 2025