amdgpu_drv.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_drv.c,v 1.1.1.2 2021/12/18 20:11:06 riastradh Exp $ */ 2 3 /* 4 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_drv.c,v 1.1.1.2 2021/12/18 20:11:06 riastradh Exp $"); 29 30 #include <drm/amdgpu_drm.h> 31 #include <drm/drm_drv.h> 32 #include <drm/drm_gem.h> 33 #include <drm/drm_vblank.h> 34 #include "amdgpu_drv.h" 35 36 #include <drm/drm_pciids.h> 37 #include <linux/console.h> 38 #include <linux/module.h> 39 #include <linux/pci.h> 40 #include <linux/pm_runtime.h> 41 #include <linux/vga_switcheroo.h> 42 #include <drm/drm_probe_helper.h> 43 #include <linux/mmu_notifier.h> 44 45 #include "amdgpu.h" 46 #include "amdgpu_irq.h" 47 #include "amdgpu_dma_buf.h" 48 49 #include "amdgpu_amdkfd.h" 50 51 #include "amdgpu_ras.h" 52 53 /* 54 * KMS wrapper. 55 * - 3.0.0 - initial driver 56 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 57 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same 58 * at the end of IBs. 59 * - 3.3.0 - Add VM support for UVD on supported hardware. 60 * - 3.4.0 - Add AMDGPU_INFO_NUM_EVICTIONS. 61 * - 3.5.0 - Add support for new UVD_NO_OP register. 62 * - 3.6.0 - kmd involves use CONTEXT_CONTROL in ring buffer. 63 * - 3.7.0 - Add support for VCE clock list packet 64 * - 3.8.0 - Add support raster config init in the kernel 65 * - 3.9.0 - Add support for memory query info about VRAM and GTT. 66 * - 3.10.0 - Add support for new fences ioctl, new gem ioctl flags 67 * - 3.11.0 - Add support for sensor query info (clocks, temp, etc). 68 * - 3.12.0 - Add query for double offchip LDS buffers 69 * - 3.13.0 - Add PRT support 70 * - 3.14.0 - Fix race in amdgpu_ctx_get_fence() and note new functionality 71 * - 3.15.0 - Export more gpu info for gfx9 72 * - 3.16.0 - Add reserved vmid support 73 * - 3.17.0 - Add AMDGPU_NUM_VRAM_CPU_PAGE_FAULTS. 74 * - 3.18.0 - Export gpu always on cu bitmap 75 * - 3.19.0 - Add support for UVD MJPEG decode 76 * - 3.20.0 - Add support for local BOs 77 * - 3.21.0 - Add DRM_AMDGPU_FENCE_TO_HANDLE ioctl 78 * - 3.22.0 - Add DRM_AMDGPU_SCHED ioctl 79 * - 3.23.0 - Add query for VRAM lost counter 80 * - 3.24.0 - Add high priority compute support for gfx9 81 * - 3.25.0 - Add support for sensor query info (stable pstate sclk/mclk). 82 * - 3.26.0 - GFX9: Process AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE. 83 * - 3.27.0 - Add new chunk to to AMDGPU_CS to enable BO_LIST creation. 84 * - 3.28.0 - Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 85 * - 3.29.0 - Add AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID 86 * - 3.30.0 - Add AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE. 87 * - 3.31.0 - Add support for per-flip tiling attribute changes with DC 88 * - 3.32.0 - Add syncobj timeline support to AMDGPU_CS. 89 * - 3.33.0 - Fixes for GDS ENOMEM failures in AMDGPU_CS. 90 * - 3.34.0 - Non-DC can flip correctly between buffers with different pitches 91 * - 3.35.0 - Add drm_amdgpu_info_device::tcc_disabled_mask 92 * - 3.36.0 - Allow reading more status registers on si/cik 93 */ 94 #define KMS_DRIVER_MAJOR 3 95 #define KMS_DRIVER_MINOR 36 96 #define KMS_DRIVER_PATCHLEVEL 0 97 98 int amdgpu_vram_limit = 0; 99 int amdgpu_vis_vram_limit = 0; 100 int amdgpu_gart_size = -1; /* auto */ 101 int amdgpu_gtt_size = -1; /* auto */ 102 int amdgpu_moverate = -1; /* auto */ 103 int amdgpu_benchmarking = 0; 104 int amdgpu_testing = 0; 105 int amdgpu_audio = -1; 106 int amdgpu_disp_priority = 0; 107 int amdgpu_hw_i2c = 0; 108 int amdgpu_pcie_gen2 = -1; 109 int amdgpu_msi = -1; 110 char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH]; 111 int amdgpu_dpm = -1; 112 int amdgpu_fw_load_type = -1; 113 int amdgpu_aspm = -1; 114 int amdgpu_runtime_pm = -1; 115 uint amdgpu_ip_block_mask = 0xffffffff; 116 int amdgpu_bapm = -1; 117 int amdgpu_deep_color = 0; 118 int amdgpu_vm_size = -1; 119 int amdgpu_vm_fragment_size = -1; 120 int amdgpu_vm_block_size = -1; 121 int amdgpu_vm_fault_stop = 0; 122 int amdgpu_vm_debug = 0; 123 int amdgpu_vm_update_mode = -1; 124 int amdgpu_exp_hw_support = 0; 125 int amdgpu_dc = -1; 126 int amdgpu_sched_jobs = 32; 127 int amdgpu_sched_hw_submission = 2; 128 uint amdgpu_pcie_gen_cap = 0; 129 uint amdgpu_pcie_lane_cap = 0; 130 uint amdgpu_cg_mask = 0xffffffff; 131 uint amdgpu_pg_mask = 0xffffffff; 132 uint amdgpu_sdma_phase_quantum = 32; 133 char *amdgpu_disable_cu = NULL; 134 char *amdgpu_virtual_display = NULL; 135 /* OverDrive(bit 14) disabled by default*/ 136 uint amdgpu_pp_feature_mask = 0xffffbfff; 137 uint amdgpu_force_long_training = 0; 138 int amdgpu_job_hang_limit = 0; 139 int amdgpu_lbpw = -1; 140 int amdgpu_compute_multipipe = -1; 141 int amdgpu_gpu_recovery = -1; /* auto */ 142 int amdgpu_emu_mode = 0; 143 uint amdgpu_smu_memory_pool_size = 0; 144 /* FBC (bit 0) disabled by default*/ 145 uint amdgpu_dc_feature_mask = 0; 146 int amdgpu_async_gfx_ring = 1; 147 int amdgpu_mcbp = 0; 148 int amdgpu_discovery = -1; 149 int amdgpu_mes = 0; 150 int amdgpu_noretry; 151 int amdgpu_force_asic_type = -1; 152 153 struct amdgpu_mgpu_info mgpu_info = { 154 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), 155 }; 156 int amdgpu_ras_enable = -1; 157 uint amdgpu_ras_mask = 0xffffffff; 158 159 /** 160 * DOC: vramlimit (int) 161 * Restrict the total amount of VRAM in MiB for testing. The default is 0 (Use full VRAM). 162 */ 163 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 164 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 165 166 /** 167 * DOC: vis_vramlimit (int) 168 * Restrict the amount of CPU visible VRAM in MiB for testing. The default is 0 (Use full CPU visible VRAM). 169 */ 170 MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes"); 171 module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444); 172 173 /** 174 * DOC: gartsize (uint) 175 * Restrict the size of GART in Mib (32, 64, etc.) for testing. The default is -1 (The size depends on asic). 176 */ 177 MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)"); 178 module_param_named(gartsize, amdgpu_gart_size, uint, 0600); 179 180 /** 181 * DOC: gttsize (int) 182 * Restrict the size of GTT domain in MiB for testing. The default is -1 (It's VRAM size if 3GB < VRAM < 3/4 RAM, 183 * otherwise 3/4 RAM size). 184 */ 185 MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)"); 186 module_param_named(gttsize, amdgpu_gtt_size, int, 0600); 187 188 /** 189 * DOC: moverate (int) 190 * Set maximum buffer migration rate in MB/s. The default is -1 (8 MB/s). 191 */ 192 MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)"); 193 module_param_named(moverate, amdgpu_moverate, int, 0600); 194 195 /** 196 * DOC: benchmark (int) 197 * Run benchmarks. The default is 0 (Skip benchmarks). 198 */ 199 MODULE_PARM_DESC(benchmark, "Run benchmark"); 200 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 201 202 /** 203 * DOC: test (int) 204 * Test BO GTT->VRAM and VRAM->GTT GPU copies. The default is 0 (Skip test, only set 1 to run test). 205 */ 206 MODULE_PARM_DESC(test, "Run tests"); 207 module_param_named(test, amdgpu_testing, int, 0444); 208 209 /** 210 * DOC: audio (int) 211 * Set HDMI/DPAudio. Only affects non-DC display handling. The default is -1 (Enabled), set 0 to disabled it. 212 */ 213 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 214 module_param_named(audio, amdgpu_audio, int, 0444); 215 216 /** 217 * DOC: disp_priority (int) 218 * Set display Priority (1 = normal, 2 = high). Only affects non-DC display handling. The default is 0 (auto). 219 */ 220 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 221 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 222 223 /** 224 * DOC: hw_i2c (int) 225 * To enable hw i2c engine. Only affects non-DC display handling. The default is 0 (Disabled). 226 */ 227 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 228 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 229 230 /** 231 * DOC: pcie_gen2 (int) 232 * To disable PCIE Gen2/3 mode (0 = disable, 1 = enable). The default is -1 (auto, enabled). 233 */ 234 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 235 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 236 237 /** 238 * DOC: msi (int) 239 * To disable Message Signaled Interrupts (MSI) functionality (1 = enable, 0 = disable). The default is -1 (auto, enabled). 240 */ 241 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 242 module_param_named(msi, amdgpu_msi, int, 0444); 243 244 /** 245 * DOC: lockup_timeout (string) 246 * Set GPU scheduler timeout value in ms. 247 * 248 * The format can be [Non-Compute] or [GFX,Compute,SDMA,Video]. That is there can be one or 249 * multiple values specified. 0 and negative values are invalidated. They will be adjusted 250 * to the default timeout. 251 * 252 * - With one value specified, the setting will apply to all non-compute jobs. 253 * - With multiple values specified, the first one will be for GFX. 254 * The second one is for Compute. The third and fourth ones are 255 * for SDMA and Video. 256 * 257 * By default(with no lockup_timeout settings), the timeout for all non-compute(GFX, SDMA and Video) 258 * jobs is 10000. And there is no timeout enforced on compute jobs. 259 */ 260 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and infinity timeout for compute jobs; " 261 "for passthrough or sriov, 10000 for all jobs." 262 " 0: keep default value. negative: infinity timeout), " 263 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; " 264 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video]."); 265 module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444); 266 267 /** 268 * DOC: dpm (int) 269 * Override for dynamic power management setting 270 * (0 = disable, 1 = enable, 2 = enable sw smu driver for vega20) 271 * The default is -1 (auto). 272 */ 273 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 274 module_param_named(dpm, amdgpu_dpm, int, 0444); 275 276 /** 277 * DOC: fw_load_type (int) 278 * Set different firmware loading type for debugging (0 = direct, 1 = SMU, 2 = PSP). The default is -1 (auto). 279 */ 280 MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)"); 281 module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444); 282 283 /** 284 * DOC: aspm (int) 285 * To disable ASPM (1 = enable, 0 = disable). The default is -1 (auto, enabled). 286 */ 287 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 288 module_param_named(aspm, amdgpu_aspm, int, 0444); 289 290 /** 291 * DOC: runpm (int) 292 * Override for runtime power management control for dGPUs in PX/HG laptops. The amdgpu driver can dynamically power down 293 * the dGPU on PX/HG laptops when it is idle. The default is -1 (auto enable). Setting the value to 0 disables this functionality. 294 */ 295 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 296 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 297 298 /** 299 * DOC: ip_block_mask (uint) 300 * Override what IP blocks are enabled on the GPU. Each GPU is a collection of IP blocks (gfx, display, video, etc.). 301 * Use this parameter to disable specific blocks. Note that the IP blocks do not have a fixed index. Some asics may not have 302 * some IPs or may include multiple instances of an IP so the ordering various from asic to asic. See the driver output in 303 * the kernel log for the list of IPs on the asic. The default is 0xffffffff (enable all blocks on a device). 304 */ 305 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 306 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 307 308 /** 309 * DOC: bapm (int) 310 * Bidirectional Application Power Management (BAPM) used to dynamically share TDP between CPU and GPU. Set value 0 to disable it. 311 * The default -1 (auto, enabled) 312 */ 313 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 314 module_param_named(bapm, amdgpu_bapm, int, 0444); 315 316 /** 317 * DOC: deep_color (int) 318 * Set 1 to enable Deep Color support. Only affects non-DC display handling. The default is 0 (disabled). 319 */ 320 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 321 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 322 323 /** 324 * DOC: vm_size (int) 325 * Override the size of the GPU's per client virtual address space in GiB. The default is -1 (automatic for each asic). 326 */ 327 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 328 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 329 330 /** 331 * DOC: vm_fragment_size (int) 332 * Override VM fragment size in bits (4, 5, etc. 4 = 64K, 9 = 2M). The default is -1 (automatic for each asic). 333 */ 334 MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)"); 335 module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444); 336 337 /** 338 * DOC: vm_block_size (int) 339 * Override VM page table size in bits (default depending on vm_size and hw setup). The default is -1 (automatic for each asic). 340 */ 341 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 342 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 343 344 /** 345 * DOC: vm_fault_stop (int) 346 * Stop on VM fault for debugging (0 = never, 1 = print first, 2 = always). The default is 0 (No stop). 347 */ 348 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 349 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 350 351 /** 352 * DOC: vm_debug (int) 353 * Debug VM handling (0 = disabled, 1 = enabled). The default is 0 (Disabled). 354 */ 355 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 356 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 357 358 /** 359 * DOC: vm_update_mode (int) 360 * Override VM update mode. VM updated by using CPU (0 = never, 1 = Graphics only, 2 = Compute only, 3 = Both). The default 361 * is -1 (Only in large BAR(LB) systems Compute VM tables will be updated by CPU, otherwise 0, never). 362 */ 363 MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both"); 364 module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444); 365 366 /** 367 * DOC: exp_hw_support (int) 368 * Enable experimental hw support (1 = enable). The default is 0 (disabled). 369 */ 370 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 371 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 372 373 /** 374 * DOC: dc (int) 375 * Disable/Enable Display Core driver for debugging (1 = enable, 0 = disable). The default is -1 (automatic for each asic). 376 */ 377 MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))"); 378 module_param_named(dc, amdgpu_dc, int, 0444); 379 380 /** 381 * DOC: sched_jobs (int) 382 * Override the max number of jobs supported in the sw queue. The default is 32. 383 */ 384 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)"); 385 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 386 387 /** 388 * DOC: sched_hw_submission (int) 389 * Override the max number of HW submissions. The default is 2. 390 */ 391 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 392 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 393 394 /** 395 * DOC: ppfeaturemask (uint) 396 * Override power features enabled. See enum PP_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 397 * The default is the current set of stable power features. 398 */ 399 MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); 400 module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, uint, 0444); 401 402 /** 403 * DOC: forcelongtraining (uint) 404 * Force long memory training in resume. 405 * The default is zero, indicates short training in resume. 406 */ 407 MODULE_PARM_DESC(forcelongtraining, "force memory long training"); 408 module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444); 409 410 /** 411 * DOC: pcie_gen_cap (uint) 412 * Override PCIE gen speed capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 413 * The default is 0 (automatic for each asic). 414 */ 415 MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))"); 416 module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444); 417 418 /** 419 * DOC: pcie_lane_cap (uint) 420 * Override PCIE lanes capabilities. See the CAIL flags in drivers/gpu/drm/amd/include/amd_pcie.h. 421 * The default is 0 (automatic for each asic). 422 */ 423 MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))"); 424 module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444); 425 426 /** 427 * DOC: cg_mask (uint) 428 * Override Clockgating features enabled on GPU (0 = disable clock gating). See the AMD_CG_SUPPORT flags in 429 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 430 */ 431 MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)"); 432 module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444); 433 434 /** 435 * DOC: pg_mask (uint) 436 * Override Powergating features enabled on GPU (0 = disable power gating). See the AMD_PG_SUPPORT flags in 437 * drivers/gpu/drm/amd/include/amd_shared.h. The default is 0xffffffff (all enabled). 438 */ 439 MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)"); 440 module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444); 441 442 /** 443 * DOC: sdma_phase_quantum (uint) 444 * Override SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change). The default is 32. 445 */ 446 MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))"); 447 module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444); 448 449 /** 450 * DOC: disable_cu (charp) 451 * Set to disable CUs (It's set like se.sh.cu,...). The default is NULL. 452 */ 453 MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)"); 454 module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444); 455 456 /** 457 * DOC: virtual_display (charp) 458 * Set to enable virtual display feature. This feature provides a virtual display hardware on headless boards 459 * or in virtualized environments. It will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x. It's the pci address of 460 * the device, plus the number of crtcs to expose. E.g., 0000:26:00.0,4 would enable 4 virtual crtcs on the pci 461 * device at 26:00.0. The default is NULL. 462 */ 463 MODULE_PARM_DESC(virtual_display, 464 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)"); 465 module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444); 466 467 /** 468 * DOC: job_hang_limit (int) 469 * Set how much time allow a job hang and not drop it. The default is 0. 470 */ 471 MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)"); 472 module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444); 473 474 /** 475 * DOC: lbpw (int) 476 * Override Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable). The default is -1 (auto, enabled). 477 */ 478 MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)"); 479 module_param_named(lbpw, amdgpu_lbpw, int, 0444); 480 481 MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)"); 482 module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444); 483 484 /** 485 * DOC: gpu_recovery (int) 486 * Set to enable GPU recovery mechanism (1 = enable, 0 = disable). The default is -1 (auto, disabled except SRIOV). 487 */ 488 MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (1 = enable, 0 = disable, -1 = auto)"); 489 module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444); 490 491 /** 492 * DOC: emu_mode (int) 493 * Set value 1 to enable emulation mode. This is only needed when running on an emulator. The default is 0 (disabled). 494 */ 495 MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)"); 496 module_param_named(emu_mode, amdgpu_emu_mode, int, 0444); 497 498 /** 499 * DOC: ras_enable (int) 500 * Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default)) 501 */ 502 MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))"); 503 module_param_named(ras_enable, amdgpu_ras_enable, int, 0444); 504 505 /** 506 * DOC: ras_mask (uint) 507 * Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1 508 * See the flags in drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h 509 */ 510 MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1"); 511 module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444); 512 513 /** 514 * DOC: si_support (int) 515 * Set SI support driver. This parameter works after set config CONFIG_DRM_AMDGPU_SI. For SI asic, when radeon driver is enabled, 516 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 517 * otherwise using amdgpu driver. 518 */ 519 #ifdef CONFIG_DRM_AMDGPU_SI 520 521 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 522 int amdgpu_si_support = 0; 523 MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); 524 #else 525 int amdgpu_si_support = 1; 526 MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); 527 #endif 528 529 module_param_named(si_support, amdgpu_si_support, int, 0444); 530 #endif 531 532 /** 533 * DOC: cik_support (int) 534 * Set CIK support driver. This parameter works after set config CONFIG_DRM_AMDGPU_CIK. For CIK asic, when radeon driver is enabled, 535 * set value 0 to use radeon driver, while set value 1 to use amdgpu driver. The default is using radeon driver when it available, 536 * otherwise using amdgpu driver. 537 */ 538 #ifdef CONFIG_DRM_AMDGPU_CIK 539 540 #if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE) 541 int amdgpu_cik_support = 0; 542 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); 543 #else 544 int amdgpu_cik_support = 1; 545 MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); 546 #endif 547 548 module_param_named(cik_support, amdgpu_cik_support, int, 0444); 549 #endif 550 551 /** 552 * DOC: smu_memory_pool_size (uint) 553 * It is used to reserve gtt for smu debug usage, setting value 0 to disable it. The actual size is value * 256MiB. 554 * E.g. 0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte. The default is 0 (disabled). 555 */ 556 MODULE_PARM_DESC(smu_memory_pool_size, 557 "reserve gtt for smu debug usage, 0 = disable," 558 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte"); 559 module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444); 560 561 /** 562 * DOC: async_gfx_ring (int) 563 * It is used to enable gfx rings that could be configured with different prioritites or equal priorities 564 */ 565 MODULE_PARM_DESC(async_gfx_ring, 566 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))"); 567 module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444); 568 569 /** 570 * DOC: mcbp (int) 571 * It is used to enable mid command buffer preemption. (0 = disabled (default), 1 = enabled) 572 */ 573 MODULE_PARM_DESC(mcbp, 574 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)"); 575 module_param_named(mcbp, amdgpu_mcbp, int, 0444); 576 577 /** 578 * DOC: discovery (int) 579 * Allow driver to discover hardware IP information from IP Discovery table at the top of VRAM. 580 * (-1 = auto (default), 0 = disabled, 1 = enabled) 581 */ 582 MODULE_PARM_DESC(discovery, 583 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM"); 584 module_param_named(discovery, amdgpu_discovery, int, 0444); 585 586 /** 587 * DOC: mes (int) 588 * Enable Micro Engine Scheduler. This is a new hw scheduling engine for gfx, sdma, and compute. 589 * (0 = disabled (default), 1 = enabled) 590 */ 591 MODULE_PARM_DESC(mes, 592 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)"); 593 module_param_named(mes, amdgpu_mes, int, 0444); 594 595 MODULE_PARM_DESC(noretry, 596 "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); 597 module_param_named(noretry, amdgpu_noretry, int, 0644); 598 599 /** 600 * DOC: force_asic_type (int) 601 * A non negative value used to specify the asic type for all supported GPUs. 602 */ 603 MODULE_PARM_DESC(force_asic_type, 604 "A non negative value used to specify the asic type for all supported GPUs"); 605 module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444); 606 607 608 609 #ifdef CONFIG_HSA_AMD 610 /** 611 * DOC: sched_policy (int) 612 * Set scheduling policy. Default is HWS(hardware scheduling) with over-subscription. 613 * Setting 1 disables over-subscription. Setting 2 disables HWS and statically 614 * assigns queues to HQDs. 615 */ 616 int sched_policy = KFD_SCHED_POLICY_HWS; 617 module_param(sched_policy, int, 0444); 618 MODULE_PARM_DESC(sched_policy, 619 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)"); 620 621 /** 622 * DOC: hws_max_conc_proc (int) 623 * Maximum number of processes that HWS can schedule concurrently. The maximum is the 624 * number of VMIDs assigned to the HWS, which is also the default. 625 */ 626 int hws_max_conc_proc = 8; 627 module_param(hws_max_conc_proc, int, 0444); 628 MODULE_PARM_DESC(hws_max_conc_proc, 629 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))"); 630 631 /** 632 * DOC: cwsr_enable (int) 633 * CWSR(compute wave store and resume) allows the GPU to preempt shader execution in 634 * the middle of a compute wave. Default is 1 to enable this feature. Setting 0 635 * disables it. 636 */ 637 int cwsr_enable = 1; 638 module_param(cwsr_enable, int, 0444); 639 MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))"); 640 641 /** 642 * DOC: max_num_of_queues_per_device (int) 643 * Maximum number of queues per device. Valid setting is between 1 and 4096. Default 644 * is 4096. 645 */ 646 int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT; 647 module_param(max_num_of_queues_per_device, int, 0444); 648 MODULE_PARM_DESC(max_num_of_queues_per_device, 649 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)"); 650 651 /** 652 * DOC: send_sigterm (int) 653 * Send sigterm to HSA process on unhandled exceptions. Default is not to send sigterm 654 * but just print errors on dmesg. Setting 1 enables sending sigterm. 655 */ 656 int send_sigterm; 657 module_param(send_sigterm, int, 0444); 658 MODULE_PARM_DESC(send_sigterm, 659 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)"); 660 661 /** 662 * DOC: debug_largebar (int) 663 * Set debug_largebar as 1 to enable simulating large-bar capability on non-large bar 664 * system. This limits the VRAM size reported to ROCm applications to the visible 665 * size, usually 256MB. 666 * Default value is 0, diabled. 667 */ 668 int debug_largebar; 669 module_param(debug_largebar, int, 0444); 670 MODULE_PARM_DESC(debug_largebar, 671 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)"); 672 673 /** 674 * DOC: ignore_crat (int) 675 * Ignore CRAT table during KFD initialization. By default, KFD uses the ACPI CRAT 676 * table to get information about AMD APUs. This option can serve as a workaround on 677 * systems with a broken CRAT table. 678 */ 679 int ignore_crat; 680 module_param(ignore_crat, int, 0444); 681 MODULE_PARM_DESC(ignore_crat, 682 "Ignore CRAT table during KFD initialization (0 = use CRAT (default), 1 = ignore CRAT)"); 683 684 /** 685 * DOC: halt_if_hws_hang (int) 686 * Halt if HWS hang is detected. Default value, 0, disables the halt on hang. 687 * Setting 1 enables halt on hang. 688 */ 689 int halt_if_hws_hang; 690 module_param(halt_if_hws_hang, int, 0644); 691 MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)"); 692 693 /** 694 * DOC: hws_gws_support(bool) 695 * Whether HWS support gws barriers. Default value: false (not supported) 696 * This will be replaced with a MEC firmware version check once firmware 697 * is ready 698 */ 699 bool hws_gws_support; 700 module_param(hws_gws_support, bool, 0444); 701 MODULE_PARM_DESC(hws_gws_support, "MEC FW support gws barriers (false = not supported (Default), true = supported)"); 702 703 /** 704 * DOC: queue_preemption_timeout_ms (int) 705 * queue preemption timeout in ms (1 = Minimum, 9000 = default) 706 */ 707 int queue_preemption_timeout_ms = 9000; 708 module_param(queue_preemption_timeout_ms, int, 0644); 709 MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)"); 710 #endif 711 712 /** 713 * DOC: dcfeaturemask (uint) 714 * Override display features enabled. See enum DC_FEATURE_MASK in drivers/gpu/drm/amd/include/amd_shared.h. 715 * The default is the current set of stable display features. 716 */ 717 MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))"); 718 module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444); 719 720 /** 721 * DOC: abmlevel (uint) 722 * Override the default ABM (Adaptive Backlight Management) level used for DC 723 * enabled hardware. Requires DMCU to be supported and loaded. 724 * Valid levels are 0-4. A value of 0 indicates that ABM should be disabled by 725 * default. Values 1-4 control the maximum allowable brightness reduction via 726 * the ABM algorithm, with 1 being the least reduction and 4 being the most 727 * reduction. 728 * 729 * Defaults to 0, or disabled. Userspace can still override this level later 730 * after boot. 731 */ 732 uint amdgpu_dm_abm_level = 0; 733 MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) "); 734 module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444); 735 736 static const struct pci_device_id pciidlist[] = { 737 #ifdef CONFIG_DRM_AMDGPU_SI 738 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 739 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 740 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 741 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 742 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 743 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 744 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 745 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 746 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 747 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 748 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 749 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 750 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI}, 751 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 752 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 753 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY}, 754 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 755 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 756 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 757 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 758 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 759 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 760 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 761 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 762 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN}, 763 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 764 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 765 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 766 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 767 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 768 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 769 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 770 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 771 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 772 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 773 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 774 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 775 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 776 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 777 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 778 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY}, 779 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND}, 780 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 781 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 782 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 783 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 784 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 785 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 786 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 787 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 788 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 789 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 790 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 791 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 792 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 793 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 794 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 795 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 796 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY}, 797 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 798 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 799 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 800 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 801 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 802 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 803 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE}, 804 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 805 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 806 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 807 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 808 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 809 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY}, 810 #endif 811 #ifdef CONFIG_DRM_AMDGPU_CIK 812 /* Kaveri */ 813 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 814 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 815 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 816 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 817 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 818 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 819 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 820 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 821 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 822 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 823 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 824 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 825 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 826 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 827 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 828 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 829 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 830 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 831 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 832 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 833 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 834 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 835 /* Bonaire */ 836 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 837 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 838 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 839 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 840 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 841 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 842 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 843 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 844 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 845 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 846 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 847 /* Hawaii */ 848 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 849 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 850 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 851 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 852 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 853 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 854 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 855 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 856 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 857 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 858 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 859 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 860 /* Kabini */ 861 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 862 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 863 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 864 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 865 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 866 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 867 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 868 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 869 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 870 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 871 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 872 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 873 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 874 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 875 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 876 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 877 /* mullins */ 878 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 879 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 880 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 881 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 882 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 883 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 884 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 885 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 886 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 887 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 888 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 889 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 890 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 891 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 892 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 893 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 894 #endif 895 /* topaz */ 896 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 897 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 898 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 899 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 900 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 901 /* tonga */ 902 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 903 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 904 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 905 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 906 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 907 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 908 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 909 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 910 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 911 /* fiji */ 912 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 913 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 914 /* carrizo */ 915 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 916 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 917 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 918 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 919 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 920 /* stoney */ 921 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 922 /* Polaris11 */ 923 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 924 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 925 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 926 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 927 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 928 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 929 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 930 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 931 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, 932 /* Polaris10 */ 933 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 934 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 935 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 936 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 937 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 938 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 939 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 940 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 941 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 942 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 943 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 944 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 945 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, 946 /* Polaris12 */ 947 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 948 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 949 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 950 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 951 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 952 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 953 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 954 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12}, 955 /* VEGAM */ 956 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 957 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 958 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM}, 959 /* Vega 10 */ 960 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 961 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 962 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 963 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 964 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 965 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 966 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 967 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 968 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 969 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 970 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 971 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 972 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 973 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 974 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10}, 975 /* Vega 12 */ 976 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 977 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 978 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 979 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 980 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12}, 981 /* Vega 20 */ 982 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 983 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 984 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 985 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 986 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 987 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 988 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20}, 989 /* Raven */ 990 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 991 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU}, 992 /* Arcturus */ 993 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 994 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 995 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 996 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS|AMD_EXP_HW_SUPPORT}, 997 /* Navi10 */ 998 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 999 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1000 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1001 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1002 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1003 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1004 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10}, 1005 /* Navi14 */ 1006 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1007 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1008 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1009 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14}, 1010 1011 /* Renoir */ 1012 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU}, 1013 1014 /* Navi12 */ 1015 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1016 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12|AMD_EXP_HW_SUPPORT}, 1017 1018 {0, 0, 0} 1019 }; 1020 1021 MODULE_DEVICE_TABLE(pci, pciidlist); 1022 1023 static struct drm_driver kms_driver; 1024 1025 static int amdgpu_pci_probe(struct pci_dev *pdev, 1026 const struct pci_device_id *ent) 1027 { 1028 struct drm_device *dev; 1029 unsigned long flags = ent->driver_data; 1030 int ret, retry = 0; 1031 bool supports_atomic = false; 1032 1033 if (!amdgpu_virtual_display && 1034 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) 1035 supports_atomic = true; 1036 1037 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 1038 DRM_INFO("This hardware requires experimental hardware support.\n" 1039 "See modparam exp_hw_support\n"); 1040 return -ENODEV; 1041 } 1042 1043 #ifdef CONFIG_DRM_AMDGPU_SI 1044 if (!amdgpu_si_support) { 1045 switch (flags & AMD_ASIC_MASK) { 1046 case CHIP_TAHITI: 1047 case CHIP_PITCAIRN: 1048 case CHIP_VERDE: 1049 case CHIP_OLAND: 1050 case CHIP_HAINAN: 1051 dev_info(&pdev->dev, 1052 "SI support provided by radeon.\n"); 1053 dev_info(&pdev->dev, 1054 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n" 1055 ); 1056 return -ENODEV; 1057 } 1058 } 1059 #endif 1060 #ifdef CONFIG_DRM_AMDGPU_CIK 1061 if (!amdgpu_cik_support) { 1062 switch (flags & AMD_ASIC_MASK) { 1063 case CHIP_KAVERI: 1064 case CHIP_BONAIRE: 1065 case CHIP_HAWAII: 1066 case CHIP_KABINI: 1067 case CHIP_MULLINS: 1068 dev_info(&pdev->dev, 1069 "CIK support provided by radeon.\n"); 1070 dev_info(&pdev->dev, 1071 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n" 1072 ); 1073 return -ENODEV; 1074 } 1075 } 1076 #endif 1077 1078 /* Get rid of things like offb */ 1079 ret = drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); 1080 if (ret) 1081 return ret; 1082 1083 dev = drm_dev_alloc(&kms_driver, &pdev->dev); 1084 if (IS_ERR(dev)) 1085 return PTR_ERR(dev); 1086 1087 if (!supports_atomic) 1088 dev->driver_features &= ~DRIVER_ATOMIC; 1089 1090 ret = pci_enable_device(pdev); 1091 if (ret) 1092 goto err_free; 1093 1094 dev->pdev = pdev; 1095 1096 pci_set_drvdata(pdev, dev); 1097 1098 retry_init: 1099 ret = drm_dev_register(dev, ent->driver_data); 1100 if (ret == -EAGAIN && ++retry <= 3) { 1101 DRM_INFO("retry init %d\n", retry); 1102 /* Don't request EX mode too frequently which is attacking */ 1103 msleep(5000); 1104 goto retry_init; 1105 } else if (ret) 1106 goto err_pci; 1107 1108 return 0; 1109 1110 err_pci: 1111 pci_disable_device(pdev); 1112 err_free: 1113 drm_dev_put(dev); 1114 return ret; 1115 } 1116 1117 static void 1118 amdgpu_pci_remove(struct pci_dev *pdev) 1119 { 1120 struct drm_device *dev = pci_get_drvdata(pdev); 1121 1122 #ifdef MODULE 1123 if (THIS_MODULE->state != MODULE_STATE_GOING) 1124 #endif 1125 DRM_ERROR("Hotplug removal is not supported\n"); 1126 drm_dev_unplug(dev); 1127 drm_dev_put(dev); 1128 pci_disable_device(pdev); 1129 pci_set_drvdata(pdev, NULL); 1130 } 1131 1132 static void 1133 amdgpu_pci_shutdown(struct pci_dev *pdev) 1134 { 1135 struct drm_device *dev = pci_get_drvdata(pdev); 1136 struct amdgpu_device *adev = dev->dev_private; 1137 1138 if (amdgpu_ras_intr_triggered()) 1139 return; 1140 1141 /* if we are running in a VM, make sure the device 1142 * torn down properly on reboot/shutdown. 1143 * unfortunately we can't detect certain 1144 * hypervisors so just do this all the time. 1145 */ 1146 adev->mp1_state = PP_MP1_STATE_UNLOAD; 1147 amdgpu_device_ip_suspend(adev); 1148 adev->mp1_state = PP_MP1_STATE_NONE; 1149 } 1150 1151 static int amdgpu_pmops_suspend(struct device *dev) 1152 { 1153 struct drm_device *drm_dev = dev_get_drvdata(dev); 1154 1155 return amdgpu_device_suspend(drm_dev, true); 1156 } 1157 1158 static int amdgpu_pmops_resume(struct device *dev) 1159 { 1160 struct drm_device *drm_dev = dev_get_drvdata(dev); 1161 1162 /* GPU comes up enabled by the bios on resume */ 1163 if (amdgpu_device_supports_boco(drm_dev) || 1164 amdgpu_device_supports_baco(drm_dev)) { 1165 pm_runtime_disable(dev); 1166 pm_runtime_set_active(dev); 1167 pm_runtime_enable(dev); 1168 } 1169 1170 return amdgpu_device_resume(drm_dev, true); 1171 } 1172 1173 static int amdgpu_pmops_freeze(struct device *dev) 1174 { 1175 struct drm_device *drm_dev = dev_get_drvdata(dev); 1176 struct amdgpu_device *adev = drm_dev->dev_private; 1177 int r; 1178 1179 r = amdgpu_device_suspend(drm_dev, true); 1180 if (r) 1181 return r; 1182 return amdgpu_asic_reset(adev); 1183 } 1184 1185 static int amdgpu_pmops_thaw(struct device *dev) 1186 { 1187 struct drm_device *drm_dev = dev_get_drvdata(dev); 1188 1189 return amdgpu_device_resume(drm_dev, true); 1190 } 1191 1192 static int amdgpu_pmops_poweroff(struct device *dev) 1193 { 1194 struct drm_device *drm_dev = dev_get_drvdata(dev); 1195 1196 return amdgpu_device_suspend(drm_dev, true); 1197 } 1198 1199 static int amdgpu_pmops_restore(struct device *dev) 1200 { 1201 struct drm_device *drm_dev = dev_get_drvdata(dev); 1202 1203 return amdgpu_device_resume(drm_dev, true); 1204 } 1205 1206 static int amdgpu_pmops_runtime_suspend(struct device *dev) 1207 { 1208 struct pci_dev *pdev = to_pci_dev(dev); 1209 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1210 struct amdgpu_device *adev = drm_dev->dev_private; 1211 int ret, i; 1212 1213 if (!adev->runpm) { 1214 pm_runtime_forbid(dev); 1215 return -EBUSY; 1216 } 1217 1218 /* wait for all rings to drain before suspending */ 1219 for (i = 0; i < AMDGPU_MAX_RINGS; i++) { 1220 struct amdgpu_ring *ring = adev->rings[i]; 1221 if (ring && ring->sched.ready) { 1222 ret = amdgpu_fence_wait_empty(ring); 1223 if (ret) 1224 return -EBUSY; 1225 } 1226 } 1227 1228 if (amdgpu_device_supports_boco(drm_dev)) 1229 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1230 drm_kms_helper_poll_disable(drm_dev); 1231 1232 ret = amdgpu_device_suspend(drm_dev, false); 1233 if (amdgpu_device_supports_boco(drm_dev)) { 1234 /* Only need to handle PCI state in the driver for ATPX 1235 * PCI core handles it for _PR3. 1236 */ 1237 if (amdgpu_is_atpx_hybrid()) { 1238 pci_ignore_hotplug(pdev); 1239 } else { 1240 pci_save_state(pdev); 1241 pci_disable_device(pdev); 1242 pci_ignore_hotplug(pdev); 1243 pci_set_power_state(pdev, PCI_D3cold); 1244 } 1245 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 1246 } else if (amdgpu_device_supports_baco(drm_dev)) { 1247 amdgpu_device_baco_enter(drm_dev); 1248 } 1249 1250 return 0; 1251 } 1252 1253 static int amdgpu_pmops_runtime_resume(struct device *dev) 1254 { 1255 struct pci_dev *pdev = to_pci_dev(dev); 1256 struct drm_device *drm_dev = pci_get_drvdata(pdev); 1257 struct amdgpu_device *adev = drm_dev->dev_private; 1258 int ret; 1259 1260 if (!adev->runpm) 1261 return -EINVAL; 1262 1263 if (amdgpu_device_supports_boco(drm_dev)) { 1264 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 1265 1266 /* Only need to handle PCI state in the driver for ATPX 1267 * PCI core handles it for _PR3. 1268 */ 1269 if (amdgpu_is_atpx_hybrid()) { 1270 pci_set_master(pdev); 1271 } else { 1272 pci_set_power_state(pdev, PCI_D0); 1273 pci_restore_state(pdev); 1274 ret = pci_enable_device(pdev); 1275 if (ret) 1276 return ret; 1277 pci_set_master(pdev); 1278 } 1279 } else if (amdgpu_device_supports_baco(drm_dev)) { 1280 amdgpu_device_baco_exit(drm_dev); 1281 } 1282 ret = amdgpu_device_resume(drm_dev, false); 1283 drm_kms_helper_poll_enable(drm_dev); 1284 if (amdgpu_device_supports_boco(drm_dev)) 1285 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 1286 return 0; 1287 } 1288 1289 static int amdgpu_pmops_runtime_idle(struct device *dev) 1290 { 1291 struct drm_device *drm_dev = dev_get_drvdata(dev); 1292 struct amdgpu_device *adev = drm_dev->dev_private; 1293 struct drm_crtc *crtc; 1294 1295 if (!adev->runpm) { 1296 pm_runtime_forbid(dev); 1297 return -EBUSY; 1298 } 1299 1300 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 1301 if (crtc->enabled) { 1302 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 1303 return -EBUSY; 1304 } 1305 } 1306 1307 pm_runtime_mark_last_busy(dev); 1308 pm_runtime_autosuspend(dev); 1309 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 1310 return 1; 1311 } 1312 1313 long amdgpu_drm_ioctl(struct file *filp, 1314 unsigned int cmd, unsigned long arg) 1315 { 1316 struct drm_file *file_priv = filp->private_data; 1317 struct drm_device *dev; 1318 long ret; 1319 dev = file_priv->minor->dev; 1320 ret = pm_runtime_get_sync(dev->dev); 1321 if (ret < 0) 1322 return ret; 1323 1324 ret = drm_ioctl(filp, cmd, arg); 1325 1326 pm_runtime_mark_last_busy(dev->dev); 1327 pm_runtime_put_autosuspend(dev->dev); 1328 return ret; 1329 } 1330 1331 static const struct dev_pm_ops amdgpu_pm_ops = { 1332 .suspend = amdgpu_pmops_suspend, 1333 .resume = amdgpu_pmops_resume, 1334 .freeze = amdgpu_pmops_freeze, 1335 .thaw = amdgpu_pmops_thaw, 1336 .poweroff = amdgpu_pmops_poweroff, 1337 .restore = amdgpu_pmops_restore, 1338 .runtime_suspend = amdgpu_pmops_runtime_suspend, 1339 .runtime_resume = amdgpu_pmops_runtime_resume, 1340 .runtime_idle = amdgpu_pmops_runtime_idle, 1341 }; 1342 1343 static int amdgpu_flush(struct file *f, fl_owner_t id) 1344 { 1345 struct drm_file *file_priv = f->private_data; 1346 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 1347 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY; 1348 1349 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout); 1350 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout); 1351 1352 return timeout >= 0 ? 0 : timeout; 1353 } 1354 1355 static const struct file_operations amdgpu_driver_kms_fops = { 1356 .owner = THIS_MODULE, 1357 .open = drm_open, 1358 .flush = amdgpu_flush, 1359 .release = drm_release, 1360 .unlocked_ioctl = amdgpu_drm_ioctl, 1361 .mmap = amdgpu_mmap, 1362 .poll = drm_poll, 1363 .read = drm_read, 1364 #ifdef CONFIG_COMPAT 1365 .compat_ioctl = amdgpu_kms_compat_ioctl, 1366 #endif 1367 }; 1368 1369 int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv) 1370 { 1371 struct drm_file *file; 1372 1373 if (!filp) 1374 return -EINVAL; 1375 1376 if (filp->f_op != &amdgpu_driver_kms_fops) { 1377 return -EINVAL; 1378 } 1379 1380 file = filp->private_data; 1381 *fpriv = file->driver_priv; 1382 return 0; 1383 } 1384 1385 static bool 1386 amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, 1387 bool in_vblank_irq, int *vpos, int *hpos, 1388 ktime_t *stime, ktime_t *etime, 1389 const struct drm_display_mode *mode) 1390 { 1391 return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, 1392 stime, etime, mode); 1393 } 1394 1395 static struct drm_driver kms_driver = { 1396 .driver_features = 1397 DRIVER_USE_AGP | DRIVER_ATOMIC | 1398 DRIVER_GEM | 1399 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1400 DRIVER_SYNCOBJ_TIMELINE, 1401 .load = amdgpu_driver_load_kms, 1402 .open = amdgpu_driver_open_kms, 1403 .postclose = amdgpu_driver_postclose_kms, 1404 .lastclose = amdgpu_driver_lastclose_kms, 1405 .unload = amdgpu_driver_unload_kms, 1406 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 1407 .enable_vblank = amdgpu_enable_vblank_kms, 1408 .disable_vblank = amdgpu_disable_vblank_kms, 1409 .get_vblank_timestamp = drm_calc_vbltimestamp_from_scanoutpos, 1410 .get_scanout_position = amdgpu_get_crtc_scanout_position, 1411 .irq_handler = amdgpu_irq_handler, 1412 .ioctls = amdgpu_ioctls_kms, 1413 .gem_free_object_unlocked = amdgpu_gem_object_free, 1414 .gem_open_object = amdgpu_gem_object_open, 1415 .gem_close_object = amdgpu_gem_object_close, 1416 .dumb_create = amdgpu_mode_dumb_create, 1417 .dumb_map_offset = amdgpu_mode_dumb_mmap, 1418 .fops = &amdgpu_driver_kms_fops, 1419 1420 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1421 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1422 .gem_prime_export = amdgpu_gem_prime_export, 1423 .gem_prime_import = amdgpu_gem_prime_import, 1424 .gem_prime_vmap = amdgpu_gem_prime_vmap, 1425 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 1426 .gem_prime_mmap = amdgpu_gem_prime_mmap, 1427 1428 .name = DRIVER_NAME, 1429 .desc = DRIVER_DESC, 1430 .date = DRIVER_DATE, 1431 .major = KMS_DRIVER_MAJOR, 1432 .minor = KMS_DRIVER_MINOR, 1433 .patchlevel = KMS_DRIVER_PATCHLEVEL, 1434 }; 1435 1436 static struct pci_driver amdgpu_kms_pci_driver = { 1437 .name = DRIVER_NAME, 1438 .id_table = pciidlist, 1439 .probe = amdgpu_pci_probe, 1440 .remove = amdgpu_pci_remove, 1441 .shutdown = amdgpu_pci_shutdown, 1442 .driver.pm = &amdgpu_pm_ops, 1443 }; 1444 1445 1446 1447 static int __init amdgpu_init(void) 1448 { 1449 int r; 1450 1451 if (vgacon_text_force()) { 1452 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 1453 return -EINVAL; 1454 } 1455 1456 r = amdgpu_sync_init(); 1457 if (r) 1458 goto error_sync; 1459 1460 r = amdgpu_fence_slab_init(); 1461 if (r) 1462 goto error_fence; 1463 1464 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 1465 kms_driver.num_ioctls = amdgpu_max_kms_ioctl; 1466 amdgpu_register_atpx_handler(); 1467 1468 /* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */ 1469 amdgpu_amdkfd_init(); 1470 1471 /* let modprobe override vga console setting */ 1472 return pci_register_driver(&amdgpu_kms_pci_driver); 1473 1474 error_fence: 1475 amdgpu_sync_fini(); 1476 1477 error_sync: 1478 return r; 1479 } 1480 1481 static void __exit amdgpu_exit(void) 1482 { 1483 amdgpu_amdkfd_fini(); 1484 pci_unregister_driver(&amdgpu_kms_pci_driver); 1485 amdgpu_unregister_atpx_handler(); 1486 amdgpu_sync_fini(); 1487 amdgpu_fence_slab_fini(); 1488 mmu_notifier_synchronize(); 1489 } 1490 1491 module_init(amdgpu_init); 1492 module_exit(amdgpu_exit); 1493 1494 MODULE_AUTHOR(DRIVER_AUTHOR); 1495 MODULE_DESCRIPTION(DRIVER_DESC); 1496 MODULE_LICENSE("GPL and additional rights"); 1497
Indexes created Mon Sep 29 21:09:56 GMT 2025