amdgpu_drv.c revision 1.5.2.2
1 /* $NetBSD: amdgpu_drv.c,v 1.5.2.2 2018/09/06 06:56:10 pgoyette Exp $ */ 2 3 /** 4 * \file amdgpu_drv.c 5 * AMD Amdgpu driver 6 * 7 * \author Gareth Hughes <gareth (at) valinux.com> 8 */ 9 10 /* 11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. 12 * All Rights Reserved. 13 * 14 * Permission is hereby granted, free of charge, to any person obtaining a 15 * copy of this software and associated documentation files (the "Software"), 16 * to deal in the Software without restriction, including without limitation 17 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 18 * and/or sell copies of the Software, and to permit persons to whom the 19 * Software is furnished to do so, subject to the following conditions: 20 * 21 * The above copyright notice and this permission notice (including the next 22 * paragraph) shall be included in all copies or substantial portions of the 23 * Software. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 31 * OTHER DEALINGS IN THE SOFTWARE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdgpu_drv.c,v 1.5.2.2 2018/09/06 06:56:10 pgoyette Exp $"); 36 37 #include <drm/drmP.h> 38 #include <drm/amdgpu_drm.h> 39 #include <drm/drm_gem.h> 40 #include "amdgpu_drv.h" 41 42 #include <drm/drm_pciids.h> 43 #include <linux/console.h> 44 #include <linux/module.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/vga_switcheroo.h> 47 #include "drm_crtc_helper.h" 48 49 #include "amdgpu.h" 50 #include "amdgpu_irq.h" 51 52 #include "amdgpu_amdkfd.h" 53 54 /* 55 * KMS wrapper. 56 * - 3.0.0 - initial driver 57 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP) 58 */ 59 #define KMS_DRIVER_MAJOR 3 60 #define KMS_DRIVER_MINOR 1 61 #define KMS_DRIVER_PATCHLEVEL 0 62 63 int amdgpu_vram_limit = 0; 64 int amdgpu_gart_size = -1; /* auto */ 65 int amdgpu_benchmarking = 0; 66 int amdgpu_testing = 0; 67 int amdgpu_audio = -1; 68 int amdgpu_disp_priority = 0; 69 int amdgpu_hw_i2c = 0; 70 int amdgpu_pcie_gen2 = -1; 71 int amdgpu_msi = -1; 72 int amdgpu_lockup_timeout = 0; 73 int amdgpu_dpm = -1; 74 int amdgpu_smc_load_fw = 1; 75 int amdgpu_aspm = -1; 76 int amdgpu_runtime_pm = -1; 77 int amdgpu_hard_reset = 0; 78 unsigned amdgpu_ip_block_mask = 0xffffffff; 79 int amdgpu_bapm = -1; 80 int amdgpu_deep_color = 0; 81 int amdgpu_vm_size = 64; 82 int amdgpu_vm_block_size = -1; 83 int amdgpu_vm_fault_stop = 0; 84 int amdgpu_vm_debug = 0; 85 int amdgpu_exp_hw_support = 0; 86 int amdgpu_enable_scheduler = 1; 87 int amdgpu_sched_jobs = 16; 88 int amdgpu_sched_hw_submission = 2; 89 int amdgpu_enable_semaphores = 0; 90 91 MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes"); 92 module_param_named(vramlimit, amdgpu_vram_limit, int, 0600); 93 94 MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)"); 95 module_param_named(gartsize, amdgpu_gart_size, int, 0600); 96 97 MODULE_PARM_DESC(benchmark, "Run benchmark"); 98 module_param_named(benchmark, amdgpu_benchmarking, int, 0444); 99 100 MODULE_PARM_DESC(test, "Run tests"); 101 module_param_named(test, amdgpu_testing, int, 0444); 102 103 MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)"); 104 module_param_named(audio, amdgpu_audio, int, 0444); 105 106 MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)"); 107 module_param_named(disp_priority, amdgpu_disp_priority, int, 0444); 108 109 MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)"); 110 module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444); 111 112 MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)"); 113 module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); 114 115 MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); 116 module_param_named(msi, amdgpu_msi, int, 0444); 117 118 MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 0 = disable)"); 119 module_param_named(lockup_timeout, amdgpu_lockup_timeout, int, 0444); 120 121 MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)"); 122 module_param_named(dpm, amdgpu_dpm, int, 0444); 123 124 MODULE_PARM_DESC(smc_load_fw, "SMC firmware loading(1 = enable, 0 = disable)"); 125 module_param_named(smc_load_fw, amdgpu_smc_load_fw, int, 0444); 126 127 MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)"); 128 module_param_named(aspm, amdgpu_aspm, int, 0444); 129 130 MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)"); 131 module_param_named(runpm, amdgpu_runtime_pm, int, 0444); 132 133 MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))"); 134 module_param_named(hard_reset, amdgpu_hard_reset, int, 0444); 135 136 MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))"); 137 module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444); 138 139 MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)"); 140 module_param_named(bapm, amdgpu_bapm, int, 0444); 141 142 MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))"); 143 module_param_named(deep_color, amdgpu_deep_color, int, 0444); 144 145 MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)"); 146 module_param_named(vm_size, amdgpu_vm_size, int, 0444); 147 148 MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)"); 149 module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444); 150 151 MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)"); 152 module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444); 153 154 MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)"); 155 module_param_named(vm_debug, amdgpu_vm_debug, int, 0644); 156 157 MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))"); 158 module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444); 159 160 MODULE_PARM_DESC(enable_scheduler, "enable SW GPU scheduler (1 = enable (default), 0 = disable)"); 161 module_param_named(enable_scheduler, amdgpu_enable_scheduler, int, 0444); 162 163 MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 16)"); 164 module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444); 165 166 MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)"); 167 module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); 168 169 MODULE_PARM_DESC(enable_semaphores, "Enable semaphores (1 = enable, 0 = disable (default))"); 170 module_param_named(enable_semaphores, amdgpu_enable_semaphores, int, 0644); 171 172 static struct pci_device_id pciidlist[] = { 173 #ifdef CONFIG_DRM_AMDGPU_CIK 174 /* Kaveri */ 175 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 176 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 177 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 178 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 179 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 180 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 181 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 182 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 183 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 184 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 185 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 186 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 187 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 188 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 189 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 190 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 191 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 192 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 193 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU}, 194 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 195 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 196 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU}, 197 /* Bonaire */ 198 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 199 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 200 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 201 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY}, 202 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 203 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 204 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 205 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 206 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 207 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 208 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE}, 209 /* Hawaii */ 210 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 211 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 212 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 213 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 214 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 215 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 216 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 217 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 218 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 219 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 220 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 221 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII}, 222 /* Kabini */ 223 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 224 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 225 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 226 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 227 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 228 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 229 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 230 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 231 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 232 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 233 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 234 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU}, 235 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 236 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 237 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 238 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU}, 239 /* mullins */ 240 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 241 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 242 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 243 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 244 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 245 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 246 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 247 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 248 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 249 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 250 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 251 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 252 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 253 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 254 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 255 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU}, 256 #endif 257 /* topaz */ 258 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 259 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 260 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 261 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 262 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ}, 263 /* tonga */ 264 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 265 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 266 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 267 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 268 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 269 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 270 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 271 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 272 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA}, 273 /* fiji */ 274 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI}, 275 /* carrizo */ 276 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 277 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 278 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 279 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 280 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, 281 /* stoney */ 282 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, 283 284 {0, 0, 0} 285 }; 286 287 MODULE_DEVICE_TABLE(pci, pciidlist); 288 289 static struct drm_driver kms_driver; 290 291 #if IS_ENABLED(CONFIG_FB) 292 static int amdgpu_kick_out_firmware_fb(struct pci_dev *pdev) 293 { 294 struct apertures_struct *ap; 295 bool primary = false; 296 297 ap = alloc_apertures(1); 298 if (!ap) 299 return -ENOMEM; 300 301 ap->ranges[0].base = pci_resource_start(pdev, 0); 302 ap->ranges[0].size = pci_resource_len(pdev, 0); 303 304 #ifdef CONFIG_X86 305 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; 306 #endif 307 remove_conflicting_framebuffers(ap, "amdgpudrmfb", primary); 308 kfree(ap); 309 310 return 0; 311 } 312 #endif 313 314 #ifndef __NetBSD__ 315 316 static int amdgpu_pci_probe(struct pci_dev *pdev, 317 const struct pci_device_id *ent) 318 { 319 unsigned long flags = ent->driver_data; 320 int ret; 321 322 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) { 323 DRM_INFO("This hardware requires experimental hardware support.\n" 324 "See modparam exp_hw_support\n"); 325 return -ENODEV; 326 } 327 328 /* Get rid of things like offb */ 329 ret = amdgpu_kick_out_firmware_fb(pdev); 330 if (ret) 331 return ret; 332 333 return drm_get_pci_dev(pdev, ent, &kms_driver); 334 } 335 336 static void 337 amdgpu_pci_remove(struct pci_dev *pdev) 338 { 339 struct drm_device *dev = pci_get_drvdata(pdev); 340 341 drm_put_dev(dev); 342 } 343 344 static int amdgpu_pmops_suspend(struct device *dev) 345 { 346 struct pci_dev *pdev = to_pci_dev(dev); 347 struct drm_device *drm_dev = pci_get_drvdata(pdev); 348 return amdgpu_suspend_kms(drm_dev, true, true); 349 } 350 351 static int amdgpu_pmops_resume(struct device *dev) 352 { 353 struct pci_dev *pdev = to_pci_dev(dev); 354 struct drm_device *drm_dev = pci_get_drvdata(pdev); 355 return amdgpu_resume_kms(drm_dev, true, true); 356 } 357 358 static int amdgpu_pmops_freeze(struct device *dev) 359 { 360 struct pci_dev *pdev = to_pci_dev(dev); 361 struct drm_device *drm_dev = pci_get_drvdata(pdev); 362 return amdgpu_suspend_kms(drm_dev, false, true); 363 } 364 365 static int amdgpu_pmops_thaw(struct device *dev) 366 { 367 struct pci_dev *pdev = to_pci_dev(dev); 368 struct drm_device *drm_dev = pci_get_drvdata(pdev); 369 return amdgpu_resume_kms(drm_dev, false, true); 370 } 371 372 static int amdgpu_pmops_runtime_suspend(struct device *dev) 373 { 374 struct pci_dev *pdev = to_pci_dev(dev); 375 struct drm_device *drm_dev = pci_get_drvdata(pdev); 376 int ret; 377 378 if (!amdgpu_device_is_px(drm_dev)) { 379 pm_runtime_forbid(dev); 380 return -EBUSY; 381 } 382 383 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 384 drm_kms_helper_poll_disable(drm_dev); 385 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF); 386 387 ret = amdgpu_suspend_kms(drm_dev, false, false); 388 pci_save_state(pdev); 389 pci_disable_device(pdev); 390 pci_ignore_hotplug(pdev); 391 pci_set_power_state(pdev, PCI_D3cold); 392 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF; 393 394 return 0; 395 } 396 397 static int amdgpu_pmops_runtime_resume(struct device *dev) 398 { 399 struct pci_dev *pdev = to_pci_dev(dev); 400 struct drm_device *drm_dev = pci_get_drvdata(pdev); 401 int ret; 402 403 if (!amdgpu_device_is_px(drm_dev)) 404 return -EINVAL; 405 406 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING; 407 408 pci_set_power_state(pdev, PCI_D0); 409 pci_restore_state(pdev); 410 ret = pci_enable_device(pdev); 411 if (ret) 412 return ret; 413 pci_set_master(pdev); 414 415 ret = amdgpu_resume_kms(drm_dev, false, false); 416 drm_kms_helper_poll_enable(drm_dev); 417 vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON); 418 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON; 419 return 0; 420 } 421 422 static int amdgpu_pmops_runtime_idle(struct device *dev) 423 { 424 struct pci_dev *pdev = to_pci_dev(dev); 425 struct drm_device *drm_dev = pci_get_drvdata(pdev); 426 struct drm_crtc *crtc; 427 428 if (!amdgpu_device_is_px(drm_dev)) { 429 pm_runtime_forbid(dev); 430 return -EBUSY; 431 } 432 433 list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) { 434 if (crtc->enabled) { 435 DRM_DEBUG_DRIVER("failing to power off - crtc active\n"); 436 return -EBUSY; 437 } 438 } 439 440 pm_runtime_mark_last_busy(dev); 441 pm_runtime_autosuspend(dev); 442 /* we don't want the main rpm_idle to call suspend - we want to autosuspend */ 443 return 1; 444 } 445 446 long amdgpu_drm_ioctl(struct file *filp, 447 unsigned int cmd, unsigned long arg) 448 { 449 struct drm_file *file_priv = filp->private_data; 450 struct drm_device *dev; 451 long ret; 452 dev = file_priv->minor->dev; 453 ret = pm_runtime_get_sync(dev->dev); 454 if (ret < 0) 455 return ret; 456 457 ret = drm_ioctl(filp, cmd, arg); 458 459 pm_runtime_mark_last_busy(dev->dev); 460 pm_runtime_put_autosuspend(dev->dev); 461 return ret; 462 } 463 464 static const struct dev_pm_ops amdgpu_pm_ops = { 465 .suspend = amdgpu_pmops_suspend, 466 .resume = amdgpu_pmops_resume, 467 .freeze = amdgpu_pmops_freeze, 468 .thaw = amdgpu_pmops_thaw, 469 .poweroff = amdgpu_pmops_freeze, 470 .restore = amdgpu_pmops_resume, 471 .runtime_suspend = amdgpu_pmops_runtime_suspend, 472 .runtime_resume = amdgpu_pmops_runtime_resume, 473 .runtime_idle = amdgpu_pmops_runtime_idle, 474 }; 475 476 static const struct file_operations amdgpu_driver_kms_fops = { 477 .owner = THIS_MODULE, 478 .open = drm_open, 479 .release = drm_release, 480 .unlocked_ioctl = amdgpu_drm_ioctl, 481 .mmap = amdgpu_mmap, 482 .poll = drm_poll, 483 .read = drm_read, 484 #ifdef CONFIG_COMPAT 485 .compat_ioctl = amdgpu_kms_compat_ioctl, 486 #endif 487 }; 488 489 #endif /* __NetBSD__ */ 490 491 #ifdef __NetBSD__ 492 /* XXX Kludge for the non-GEM GEM that amdgpu uses. */ 493 static const struct uvm_pagerops amdgpu_gem_uvm_ops; 494 #endif 495 496 static struct drm_driver kms_driver = { 497 .driver_features = 498 DRIVER_USE_AGP | 499 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | 500 DRIVER_PRIME | DRIVER_RENDER, 501 .dev_priv_size = 0, 502 .load = amdgpu_driver_load_kms, 503 .open = amdgpu_driver_open_kms, 504 .preclose = amdgpu_driver_preclose_kms, 505 .postclose = amdgpu_driver_postclose_kms, 506 .lastclose = amdgpu_driver_lastclose_kms, 507 .set_busid = drm_pci_set_busid, 508 .unload = amdgpu_driver_unload_kms, 509 .get_vblank_counter = amdgpu_get_vblank_counter_kms, 510 .enable_vblank = amdgpu_enable_vblank_kms, 511 .disable_vblank = amdgpu_disable_vblank_kms, 512 .get_vblank_timestamp = amdgpu_get_vblank_timestamp_kms, 513 .get_scanout_position = amdgpu_get_crtc_scanoutpos, 514 #if defined(CONFIG_DEBUG_FS) 515 .debugfs_init = amdgpu_debugfs_init, 516 .debugfs_cleanup = amdgpu_debugfs_cleanup, 517 #endif 518 .irq_preinstall = amdgpu_irq_preinstall, 519 .irq_postinstall = amdgpu_irq_postinstall, 520 .irq_uninstall = amdgpu_irq_uninstall, 521 .irq_handler = amdgpu_irq_handler, 522 #ifdef __NetBSD__ 523 .request_irq = drm_pci_request_irq, 524 .free_irq = drm_pci_free_irq, 525 #endif 526 .ioctls = amdgpu_ioctls_kms, 527 .gem_free_object = amdgpu_gem_object_free, 528 .gem_open_object = amdgpu_gem_object_open, 529 .gem_close_object = amdgpu_gem_object_close, 530 .dumb_create = amdgpu_mode_dumb_create, 531 .dumb_map_offset = amdgpu_mode_dumb_mmap, 532 .dumb_destroy = drm_gem_dumb_destroy, 533 #ifdef __NetBSD__ 534 .fops = NULL, 535 .mmap_object = &amdgpu_mmap_object, 536 .gem_uvm_ops = &amdgpu_gem_uvm_ops, 537 #else 538 .fops = &amdgpu_driver_kms_fops, 539 #endif 540 541 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 542 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 543 .gem_prime_export = amdgpu_gem_prime_export, 544 .gem_prime_import = drm_gem_prime_import, 545 .gem_prime_pin = amdgpu_gem_prime_pin, 546 .gem_prime_unpin = amdgpu_gem_prime_unpin, 547 .gem_prime_res_obj = amdgpu_gem_prime_res_obj, 548 .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, 549 .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, 550 .gem_prime_vmap = amdgpu_gem_prime_vmap, 551 .gem_prime_vunmap = amdgpu_gem_prime_vunmap, 552 553 .name = DRIVER_NAME, 554 .desc = DRIVER_DESC, 555 .date = DRIVER_DATE, 556 .major = KMS_DRIVER_MAJOR, 557 .minor = KMS_DRIVER_MINOR, 558 .patchlevel = KMS_DRIVER_PATCHLEVEL, 559 }; 560 561 #ifdef __NetBSD__ 562 563 struct drm_driver *const amdgpu_drm_driver = &kms_driver; 564 const struct pci_device_id *const amdgpu_device_ids = pciidlist; 565 const size_t amdgpu_n_device_ids = __arraycount(pciidlist); 566 567 #else /* __NetBSD__ */ 568 569 static struct drm_driver *driver; 570 static struct pci_driver *pdriver; 571 572 static struct pci_driver amdgpu_kms_pci_driver = { 573 .name = DRIVER_NAME, 574 .id_table = pciidlist, 575 .probe = amdgpu_pci_probe, 576 .remove = amdgpu_pci_remove, 577 .driver.pm = &amdgpu_pm_ops, 578 }; 579 580 static int __init amdgpu_init(void) 581 { 582 #ifdef CONFIG_VGA_CONSOLE 583 if (vgacon_text_force()) { 584 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n"); 585 return -EINVAL; 586 } 587 #endif 588 DRM_INFO("amdgpu kernel modesetting enabled.\n"); 589 driver = &kms_driver; 590 pdriver = &amdgpu_kms_pci_driver; 591 driver->driver_features |= DRIVER_MODESET; 592 driver->num_ioctls = amdgpu_max_kms_ioctl; 593 amdgpu_register_atpx_handler(); 594 595 amdgpu_amdkfd_init(); 596 597 /* let modprobe override vga console setting */ 598 return drm_pci_init(driver, pdriver); 599 } 600 601 static void __exit amdgpu_exit(void) 602 { 603 amdgpu_amdkfd_fini(); 604 drm_pci_exit(driver, pdriver); 605 amdgpu_unregister_atpx_handler(); 606 } 607 608 module_init(amdgpu_init); 609 module_exit(amdgpu_exit); 610 611 MODULE_AUTHOR(DRIVER_AUTHOR); 612 MODULE_DESCRIPTION(DRIVER_DESC); 613 MODULE_LICENSE("GPL and additional rights"); 614 615 #endif /* __NetBSD__ */ 616
Indexes created Mon Sep 29 18:09:42 GMT 2025