amdgpu_gart.h revision 1.1 1 /* $NetBSD: amdgpu_gart.h,v 1.1 2021/12/18 20:11:06 riastradh Exp $ */
2
3 /*
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25
26 #ifndef __AMDGPU_GART_H__
27 #define __AMDGPU_GART_H__
28
29 #include <linux/types.h>
30
31 /*
32 * GART structures, functions & helpers
33 */
34 struct amdgpu_device;
35 struct amdgpu_bo;
36
37 #define AMDGPU_GPU_PAGE_SIZE 4096
38 #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1)
39 #define AMDGPU_GPU_PAGE_SHIFT 12
40 #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK)
41
42 #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
43
44 struct amdgpu_gart {
45 struct amdgpu_bo *bo;
46 /* CPU kmapped address of gart table */
47 void *ptr;
48 unsigned num_gpu_pages;
49 unsigned num_cpu_pages;
50 unsigned table_size;
51 #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
52 struct page **pages;
53 #endif
54 bool ready;
55
56 /* Asic default pte flags */
57 uint64_t gart_pte_flags;
58 };
59
60 int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev);
61 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev);
62 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev);
63 void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev);
64 int amdgpu_gart_init(struct amdgpu_device *adev);
65 void amdgpu_gart_fini(struct amdgpu_device *adev);
66 int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
67 int pages);
68 int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
69 int pages, dma_addr_t *dma_addr, uint64_t flags,
70 void *dst);
71 int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
72 int pages, struct page **pagelist,
73 dma_addr_t *dma_addr, uint64_t flags);
74
75 #endif
76