amdgpu_gem.c revision 1.1.1.1
1 /* $NetBSD: amdgpu_gem.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: amdgpu_gem.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $"); 32 33 #include <linux/ktime.h> 34 #include <drm/drmP.h> 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu.h" 37 38 void amdgpu_gem_object_free(struct drm_gem_object *gobj) 39 { 40 struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); 41 42 if (robj) { 43 if (robj->gem_base.import_attach) 44 drm_prime_gem_destroy(&robj->gem_base, robj->tbo.sg); 45 amdgpu_mn_unregister(robj); 46 amdgpu_bo_unref(&robj); 47 } 48 } 49 50 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, 51 int alignment, u32 initial_domain, 52 u64 flags, bool kernel, 53 struct drm_gem_object **obj) 54 { 55 struct amdgpu_bo *robj; 56 unsigned long max_size; 57 int r; 58 59 *obj = NULL; 60 /* At least align on page size */ 61 if (alignment < PAGE_SIZE) { 62 alignment = PAGE_SIZE; 63 } 64 65 if (!(initial_domain & (AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA))) { 66 /* Maximum bo size is the unpinned gtt size since we use the gtt to 67 * handle vram to system pool migrations. 68 */ 69 max_size = adev->mc.gtt_size - adev->gart_pin_size; 70 if (size > max_size) { 71 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", 72 size >> 20, max_size >> 20); 73 return -ENOMEM; 74 } 75 } 76 retry: 77 r = amdgpu_bo_create(adev, size, alignment, kernel, initial_domain, 78 flags, NULL, NULL, &robj); 79 if (r) { 80 if (r != -ERESTARTSYS) { 81 if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) { 82 initial_domain |= AMDGPU_GEM_DOMAIN_GTT; 83 goto retry; 84 } 85 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 86 size, initial_domain, alignment, r); 87 } 88 return r; 89 } 90 *obj = &robj->gem_base; 91 robj->pid = task_pid_nr(current); 92 93 mutex_lock(&adev->gem.mutex); 94 list_add_tail(&robj->list, &adev->gem.objects); 95 mutex_unlock(&adev->gem.mutex); 96 97 return 0; 98 } 99 100 int amdgpu_gem_init(struct amdgpu_device *adev) 101 { 102 INIT_LIST_HEAD(&adev->gem.objects); 103 return 0; 104 } 105 106 void amdgpu_gem_fini(struct amdgpu_device *adev) 107 { 108 amdgpu_bo_force_delete(adev); 109 } 110 111 /* 112 * Call from drm_gem_handle_create which appear in both new and open ioctl 113 * case. 114 */ 115 int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) 116 { 117 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 118 struct amdgpu_device *adev = rbo->adev; 119 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 120 struct amdgpu_vm *vm = &fpriv->vm; 121 struct amdgpu_bo_va *bo_va; 122 int r; 123 r = amdgpu_bo_reserve(rbo, false); 124 if (r) 125 return r; 126 127 bo_va = amdgpu_vm_bo_find(vm, rbo); 128 if (!bo_va) { 129 bo_va = amdgpu_vm_bo_add(adev, vm, rbo); 130 } else { 131 ++bo_va->ref_count; 132 } 133 amdgpu_bo_unreserve(rbo); 134 return 0; 135 } 136 137 void amdgpu_gem_object_close(struct drm_gem_object *obj, 138 struct drm_file *file_priv) 139 { 140 struct amdgpu_bo *rbo = gem_to_amdgpu_bo(obj); 141 struct amdgpu_device *adev = rbo->adev; 142 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 143 struct amdgpu_vm *vm = &fpriv->vm; 144 struct amdgpu_bo_va *bo_va; 145 int r; 146 r = amdgpu_bo_reserve(rbo, true); 147 if (r) { 148 dev_err(adev->dev, "leaking bo va because " 149 "we fail to reserve bo (%d)\n", r); 150 return; 151 } 152 bo_va = amdgpu_vm_bo_find(vm, rbo); 153 if (bo_va) { 154 if (--bo_va->ref_count == 0) { 155 amdgpu_vm_bo_rmv(adev, bo_va); 156 } 157 } 158 amdgpu_bo_unreserve(rbo); 159 } 160 161 static int amdgpu_gem_handle_lockup(struct amdgpu_device *adev, int r) 162 { 163 if (r == -EDEADLK) { 164 r = amdgpu_gpu_reset(adev); 165 if (!r) 166 r = -EAGAIN; 167 } 168 return r; 169 } 170 171 /* 172 * GEM ioctls. 173 */ 174 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, 175 struct drm_file *filp) 176 { 177 struct amdgpu_device *adev = dev->dev_private; 178 union drm_amdgpu_gem_create *args = data; 179 uint64_t size = args->in.bo_size; 180 struct drm_gem_object *gobj; 181 uint32_t handle; 182 bool kernel = false; 183 int r; 184 185 /* create a gem object to contain this object in */ 186 if (args->in.domains & (AMDGPU_GEM_DOMAIN_GDS | 187 AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) { 188 kernel = true; 189 if (args->in.domains == AMDGPU_GEM_DOMAIN_GDS) 190 size = size << AMDGPU_GDS_SHIFT; 191 else if (args->in.domains == AMDGPU_GEM_DOMAIN_GWS) 192 size = size << AMDGPU_GWS_SHIFT; 193 else if (args->in.domains == AMDGPU_GEM_DOMAIN_OA) 194 size = size << AMDGPU_OA_SHIFT; 195 else { 196 r = -EINVAL; 197 goto error_unlock; 198 } 199 } 200 size = roundup(size, PAGE_SIZE); 201 202 r = amdgpu_gem_object_create(adev, size, args->in.alignment, 203 (u32)(0xffffffff & args->in.domains), 204 args->in.domain_flags, 205 kernel, &gobj); 206 if (r) 207 goto error_unlock; 208 209 r = drm_gem_handle_create(filp, gobj, &handle); 210 /* drop reference from allocate - handle holds it now */ 211 drm_gem_object_unreference_unlocked(gobj); 212 if (r) 213 goto error_unlock; 214 215 memset(args, 0, sizeof(*args)); 216 args->out.handle = handle; 217 return 0; 218 219 error_unlock: 220 r = amdgpu_gem_handle_lockup(adev, r); 221 return r; 222 } 223 224 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, 225 struct drm_file *filp) 226 { 227 struct amdgpu_device *adev = dev->dev_private; 228 struct drm_amdgpu_gem_userptr *args = data; 229 struct drm_gem_object *gobj; 230 struct amdgpu_bo *bo; 231 uint32_t handle; 232 int r; 233 234 if (offset_in_page(args->addr | args->size)) 235 return -EINVAL; 236 237 /* reject unknown flag values */ 238 if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | 239 AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | 240 AMDGPU_GEM_USERPTR_REGISTER)) 241 return -EINVAL; 242 243 if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && ( 244 !(args->flags & AMDGPU_GEM_USERPTR_ANONONLY) || 245 !(args->flags & AMDGPU_GEM_USERPTR_REGISTER))) { 246 247 /* if we want to write to it we must require anonymous 248 memory and install a MMU notifier */ 249 return -EACCES; 250 } 251 252 /* create a gem object to contain this object in */ 253 r = amdgpu_gem_object_create(adev, args->size, 0, 254 AMDGPU_GEM_DOMAIN_CPU, 0, 255 0, &gobj); 256 if (r) 257 goto handle_lockup; 258 259 bo = gem_to_amdgpu_bo(gobj); 260 r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags); 261 if (r) 262 goto release_object; 263 264 if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) { 265 r = amdgpu_mn_register(bo, args->addr); 266 if (r) 267 goto release_object; 268 } 269 270 if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) { 271 down_read(¤t->mm->mmap_sem); 272 r = amdgpu_bo_reserve(bo, true); 273 if (r) { 274 up_read(¤t->mm->mmap_sem); 275 goto release_object; 276 } 277 278 amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT); 279 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false); 280 amdgpu_bo_unreserve(bo); 281 up_read(¤t->mm->mmap_sem); 282 if (r) 283 goto release_object; 284 } 285 286 r = drm_gem_handle_create(filp, gobj, &handle); 287 /* drop reference from allocate - handle holds it now */ 288 drm_gem_object_unreference_unlocked(gobj); 289 if (r) 290 goto handle_lockup; 291 292 args->handle = handle; 293 return 0; 294 295 release_object: 296 drm_gem_object_unreference_unlocked(gobj); 297 298 handle_lockup: 299 r = amdgpu_gem_handle_lockup(adev, r); 300 301 return r; 302 } 303 304 int amdgpu_mode_dumb_mmap(struct drm_file *filp, 305 struct drm_device *dev, 306 uint32_t handle, uint64_t *offset_p) 307 { 308 struct drm_gem_object *gobj; 309 struct amdgpu_bo *robj; 310 311 gobj = drm_gem_object_lookup(dev, filp, handle); 312 if (gobj == NULL) { 313 return -ENOENT; 314 } 315 robj = gem_to_amdgpu_bo(gobj); 316 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm) || 317 (robj->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { 318 drm_gem_object_unreference_unlocked(gobj); 319 return -EPERM; 320 } 321 *offset_p = amdgpu_bo_mmap_offset(robj); 322 drm_gem_object_unreference_unlocked(gobj); 323 return 0; 324 } 325 326 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data, 327 struct drm_file *filp) 328 { 329 union drm_amdgpu_gem_mmap *args = data; 330 uint32_t handle = args->in.handle; 331 memset(args, 0, sizeof(*args)); 332 return amdgpu_mode_dumb_mmap(filp, dev, handle, &args->out.addr_ptr); 333 } 334 335 /** 336 * amdgpu_gem_timeout - calculate jiffies timeout from absolute value 337 * 338 * @timeout_ns: timeout in ns 339 * 340 * Calculate the timeout in jiffies from an absolute timeout in ns. 341 */ 342 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns) 343 { 344 unsigned long timeout_jiffies; 345 ktime_t timeout; 346 347 /* clamp timeout if it's to large */ 348 if (((int64_t)timeout_ns) < 0) 349 return MAX_SCHEDULE_TIMEOUT; 350 351 timeout = ktime_sub(ns_to_ktime(timeout_ns), ktime_get()); 352 if (ktime_to_ns(timeout) < 0) 353 return 0; 354 355 timeout_jiffies = nsecs_to_jiffies(ktime_to_ns(timeout)); 356 /* clamp timeout to avoid unsigned-> signed overflow */ 357 if (timeout_jiffies > MAX_SCHEDULE_TIMEOUT ) 358 return MAX_SCHEDULE_TIMEOUT - 1; 359 360 return timeout_jiffies; 361 } 362 363 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 364 struct drm_file *filp) 365 { 366 struct amdgpu_device *adev = dev->dev_private; 367 union drm_amdgpu_gem_wait_idle *args = data; 368 struct drm_gem_object *gobj; 369 struct amdgpu_bo *robj; 370 uint32_t handle = args->in.handle; 371 unsigned long timeout = amdgpu_gem_timeout(args->in.timeout); 372 int r = 0; 373 long ret; 374 375 gobj = drm_gem_object_lookup(dev, filp, handle); 376 if (gobj == NULL) { 377 return -ENOENT; 378 } 379 robj = gem_to_amdgpu_bo(gobj); 380 if (timeout == 0) 381 ret = reservation_object_test_signaled_rcu(robj->tbo.resv, true); 382 else 383 ret = reservation_object_wait_timeout_rcu(robj->tbo.resv, true, true, timeout); 384 385 /* ret == 0 means not signaled, 386 * ret > 0 means signaled 387 * ret < 0 means interrupted before timeout 388 */ 389 if (ret >= 0) { 390 memset(args, 0, sizeof(*args)); 391 args->out.status = (ret == 0); 392 } else 393 r = ret; 394 395 drm_gem_object_unreference_unlocked(gobj); 396 r = amdgpu_gem_handle_lockup(adev, r); 397 return r; 398 } 399 400 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, 401 struct drm_file *filp) 402 { 403 struct drm_amdgpu_gem_metadata *args = data; 404 struct drm_gem_object *gobj; 405 struct amdgpu_bo *robj; 406 int r = -1; 407 408 DRM_DEBUG("%d \n", args->handle); 409 gobj = drm_gem_object_lookup(dev, filp, args->handle); 410 if (gobj == NULL) 411 return -ENOENT; 412 robj = gem_to_amdgpu_bo(gobj); 413 414 r = amdgpu_bo_reserve(robj, false); 415 if (unlikely(r != 0)) 416 goto out; 417 418 if (args->op == AMDGPU_GEM_METADATA_OP_GET_METADATA) { 419 amdgpu_bo_get_tiling_flags(robj, &args->data.tiling_info); 420 r = amdgpu_bo_get_metadata(robj, args->data.data, 421 sizeof(args->data.data), 422 &args->data.data_size_bytes, 423 &args->data.flags); 424 } else if (args->op == AMDGPU_GEM_METADATA_OP_SET_METADATA) { 425 if (args->data.data_size_bytes > sizeof(args->data.data)) { 426 r = -EINVAL; 427 goto unreserve; 428 } 429 r = amdgpu_bo_set_tiling_flags(robj, args->data.tiling_info); 430 if (!r) 431 r = amdgpu_bo_set_metadata(robj, args->data.data, 432 args->data.data_size_bytes, 433 args->data.flags); 434 } 435 436 unreserve: 437 amdgpu_bo_unreserve(robj); 438 out: 439 drm_gem_object_unreference_unlocked(gobj); 440 return r; 441 } 442 443 /** 444 * amdgpu_gem_va_update_vm -update the bo_va in its VM 445 * 446 * @adev: amdgpu_device pointer 447 * @bo_va: bo_va to update 448 * 449 * Update the bo_va directly after setting it's address. Errors are not 450 * vital here, so they are not reported back to userspace. 451 */ 452 static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, 453 struct amdgpu_bo_va *bo_va, uint32_t operation) 454 { 455 struct ttm_validate_buffer tv, *entry; 456 struct amdgpu_bo_list_entry *vm_bos; 457 struct ww_acquire_ctx ticket; 458 struct list_head list, duplicates; 459 unsigned domain; 460 int r; 461 462 INIT_LIST_HEAD(&list); 463 INIT_LIST_HEAD(&duplicates); 464 465 tv.bo = &bo_va->bo->tbo; 466 tv.shared = true; 467 list_add(&tv.head, &list); 468 469 vm_bos = amdgpu_vm_get_bos(adev, bo_va->vm, &list); 470 if (!vm_bos) 471 return; 472 473 /* Provide duplicates to avoid -EALREADY */ 474 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 475 if (r) 476 goto error_free; 477 478 list_for_each_entry(entry, &list, head) { 479 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); 480 /* if anything is swapped out don't swap it in here, 481 just abort and wait for the next CS */ 482 if (domain == AMDGPU_GEM_DOMAIN_CPU) 483 goto error_unreserve; 484 } 485 list_for_each_entry(entry, &duplicates, head) { 486 domain = amdgpu_mem_type_to_domain(entry->bo->mem.mem_type); 487 /* if anything is swapped out don't swap it in here, 488 just abort and wait for the next CS */ 489 if (domain == AMDGPU_GEM_DOMAIN_CPU) 490 goto error_unreserve; 491 } 492 493 r = amdgpu_vm_update_page_directory(adev, bo_va->vm); 494 if (r) 495 goto error_unreserve; 496 497 r = amdgpu_vm_clear_freed(adev, bo_va->vm); 498 if (r) 499 goto error_unreserve; 500 501 if (operation == AMDGPU_VA_OP_MAP) 502 r = amdgpu_vm_bo_update(adev, bo_va, &bo_va->bo->tbo.mem); 503 504 error_unreserve: 505 ttm_eu_backoff_reservation(&ticket, &list); 506 507 error_free: 508 drm_free_large(vm_bos); 509 510 if (r && r != -ERESTARTSYS) 511 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 512 } 513 514 515 516 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, 517 struct drm_file *filp) 518 { 519 struct drm_amdgpu_gem_va *args = data; 520 struct drm_gem_object *gobj; 521 struct amdgpu_device *adev = dev->dev_private; 522 struct amdgpu_fpriv *fpriv = filp->driver_priv; 523 struct amdgpu_bo *rbo; 524 struct amdgpu_bo_va *bo_va; 525 struct ttm_validate_buffer tv, tv_pd; 526 struct ww_acquire_ctx ticket; 527 struct list_head list, duplicates; 528 uint32_t invalid_flags, va_flags = 0; 529 int r = 0; 530 531 if (!adev->vm_manager.enabled) 532 return -ENOTTY; 533 534 if (args->va_address < AMDGPU_VA_RESERVED_SIZE) { 535 dev_err(&dev->pdev->dev, 536 "va_address 0x%lX is in reserved area 0x%X\n", 537 (unsigned long)args->va_address, 538 AMDGPU_VA_RESERVED_SIZE); 539 return -EINVAL; 540 } 541 542 invalid_flags = ~(AMDGPU_VM_DELAY_UPDATE | AMDGPU_VM_PAGE_READABLE | 543 AMDGPU_VM_PAGE_WRITEABLE | AMDGPU_VM_PAGE_EXECUTABLE); 544 if ((args->flags & invalid_flags)) { 545 dev_err(&dev->pdev->dev, "invalid flags 0x%08X vs 0x%08X\n", 546 args->flags, invalid_flags); 547 return -EINVAL; 548 } 549 550 switch (args->operation) { 551 case AMDGPU_VA_OP_MAP: 552 case AMDGPU_VA_OP_UNMAP: 553 break; 554 default: 555 dev_err(&dev->pdev->dev, "unsupported operation %d\n", 556 args->operation); 557 return -EINVAL; 558 } 559 560 gobj = drm_gem_object_lookup(dev, filp, args->handle); 561 if (gobj == NULL) 562 return -ENOENT; 563 rbo = gem_to_amdgpu_bo(gobj); 564 INIT_LIST_HEAD(&list); 565 INIT_LIST_HEAD(&duplicates); 566 tv.bo = &rbo->tbo; 567 tv.shared = true; 568 list_add(&tv.head, &list); 569 570 if (args->operation == AMDGPU_VA_OP_MAP) { 571 tv_pd.bo = &fpriv->vm.page_directory->tbo; 572 tv_pd.shared = true; 573 list_add(&tv_pd.head, &list); 574 } 575 r = ttm_eu_reserve_buffers(&ticket, &list, true, &duplicates); 576 if (r) { 577 drm_gem_object_unreference_unlocked(gobj); 578 return r; 579 } 580 581 bo_va = amdgpu_vm_bo_find(&fpriv->vm, rbo); 582 if (!bo_va) { 583 ttm_eu_backoff_reservation(&ticket, &list); 584 drm_gem_object_unreference_unlocked(gobj); 585 return -ENOENT; 586 } 587 588 switch (args->operation) { 589 case AMDGPU_VA_OP_MAP: 590 if (args->flags & AMDGPU_VM_PAGE_READABLE) 591 va_flags |= AMDGPU_PTE_READABLE; 592 if (args->flags & AMDGPU_VM_PAGE_WRITEABLE) 593 va_flags |= AMDGPU_PTE_WRITEABLE; 594 if (args->flags & AMDGPU_VM_PAGE_EXECUTABLE) 595 va_flags |= AMDGPU_PTE_EXECUTABLE; 596 r = amdgpu_vm_bo_map(adev, bo_va, args->va_address, 597 args->offset_in_bo, args->map_size, 598 va_flags); 599 break; 600 case AMDGPU_VA_OP_UNMAP: 601 r = amdgpu_vm_bo_unmap(adev, bo_va, args->va_address); 602 break; 603 default: 604 break; 605 } 606 ttm_eu_backoff_reservation(&ticket, &list); 607 if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE)) 608 amdgpu_gem_va_update_vm(adev, bo_va, args->operation); 609 610 drm_gem_object_unreference_unlocked(gobj); 611 return r; 612 } 613 614 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, 615 struct drm_file *filp) 616 { 617 struct drm_amdgpu_gem_op *args = data; 618 struct drm_gem_object *gobj; 619 struct amdgpu_bo *robj; 620 int r; 621 622 gobj = drm_gem_object_lookup(dev, filp, args->handle); 623 if (gobj == NULL) { 624 return -ENOENT; 625 } 626 robj = gem_to_amdgpu_bo(gobj); 627 628 r = amdgpu_bo_reserve(robj, false); 629 if (unlikely(r)) 630 goto out; 631 632 switch (args->op) { 633 case AMDGPU_GEM_OP_GET_GEM_CREATE_INFO: { 634 struct drm_amdgpu_gem_create_in info; 635 void __user *out = (void __user *)(long)args->value; 636 637 info.bo_size = robj->gem_base.size; 638 info.alignment = robj->tbo.mem.page_alignment << PAGE_SHIFT; 639 info.domains = robj->initial_domain; 640 info.domain_flags = robj->flags; 641 amdgpu_bo_unreserve(robj); 642 if (copy_to_user(out, &info, sizeof(info))) 643 r = -EFAULT; 644 break; 645 } 646 case AMDGPU_GEM_OP_SET_PLACEMENT: 647 if (amdgpu_ttm_tt_has_userptr(robj->tbo.ttm)) { 648 r = -EPERM; 649 amdgpu_bo_unreserve(robj); 650 break; 651 } 652 robj->initial_domain = args->value & (AMDGPU_GEM_DOMAIN_VRAM | 653 AMDGPU_GEM_DOMAIN_GTT | 654 AMDGPU_GEM_DOMAIN_CPU); 655 amdgpu_bo_unreserve(robj); 656 break; 657 default: 658 amdgpu_bo_unreserve(robj); 659 r = -EINVAL; 660 } 661 662 out: 663 drm_gem_object_unreference_unlocked(gobj); 664 return r; 665 } 666 667 int amdgpu_mode_dumb_create(struct drm_file *file_priv, 668 struct drm_device *dev, 669 struct drm_mode_create_dumb *args) 670 { 671 struct amdgpu_device *adev = dev->dev_private; 672 struct drm_gem_object *gobj; 673 uint32_t handle; 674 int r; 675 676 args->pitch = amdgpu_align_pitch(adev, args->width, args->bpp, 0) * ((args->bpp + 1) / 8); 677 args->size = (u64)args->pitch * args->height; 678 args->size = ALIGN(args->size, PAGE_SIZE); 679 680 r = amdgpu_gem_object_create(adev, args->size, 0, 681 AMDGPU_GEM_DOMAIN_VRAM, 682 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED, 683 ttm_bo_type_device, 684 &gobj); 685 if (r) 686 return -ENOMEM; 687 688 r = drm_gem_handle_create(file_priv, gobj, &handle); 689 /* drop reference from allocate - handle holds it now */ 690 drm_gem_object_unreference_unlocked(gobj); 691 if (r) { 692 return r; 693 } 694 args->handle = handle; 695 return 0; 696 } 697 698 #if defined(CONFIG_DEBUG_FS) 699 static int amdgpu_debugfs_gem_info(struct seq_file *m, void *data) 700 { 701 struct drm_info_node *node = (struct drm_info_node *)m->private; 702 struct drm_device *dev = node->minor->dev; 703 struct amdgpu_device *adev = dev->dev_private; 704 struct amdgpu_bo *rbo; 705 unsigned i = 0; 706 707 mutex_lock(&adev->gem.mutex); 708 list_for_each_entry(rbo, &adev->gem.objects, list) { 709 unsigned domain; 710 const char *placement; 711 712 domain = amdgpu_mem_type_to_domain(rbo->tbo.mem.mem_type); 713 switch (domain) { 714 case AMDGPU_GEM_DOMAIN_VRAM: 715 placement = "VRAM"; 716 break; 717 case AMDGPU_GEM_DOMAIN_GTT: 718 placement = " GTT"; 719 break; 720 case AMDGPU_GEM_DOMAIN_CPU: 721 default: 722 placement = " CPU"; 723 break; 724 } 725 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", 726 i, amdgpu_bo_size(rbo) >> 10, amdgpu_bo_size(rbo) >> 20, 727 placement, (unsigned long)rbo->pid); 728 i++; 729 } 730 mutex_unlock(&adev->gem.mutex); 731 return 0; 732 } 733 734 static struct drm_info_list amdgpu_debugfs_gem_list[] = { 735 {"amdgpu_gem_info", &amdgpu_debugfs_gem_info, 0, NULL}, 736 }; 737 #endif 738 739 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev) 740 { 741 #if defined(CONFIG_DEBUG_FS) 742 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_gem_list, 1); 743 #endif 744 return 0; 745 } 746
Indexes created Wed Sep 24 05:09:52 GMT 2025