amdgpu_i2c.c revision 1.1.1.1
1 /* $NetBSD: amdgpu_i2c.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_i2c.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $"); 30 31 #include <linux/export.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_edid.h> 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu.h" 37 #include "amdgpu_i2c.h" 38 #include "amdgpu_atombios.h" 39 #include "atom.h" 40 #include "atombios_dp.h" 41 #include "atombios_i2c.h" 42 43 /* bit banging i2c */ 44 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) 45 { 46 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 47 struct amdgpu_device *adev = i2c->dev->dev_private; 48 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 49 uint32_t temp; 50 51 mutex_lock(&i2c->mutex); 52 53 /* switch the pads to ddc mode */ 54 if (rec->hw_capable) { 55 temp = RREG32(rec->mask_clk_reg); 56 temp &= ~(1 << 16); 57 WREG32(rec->mask_clk_reg, temp); 58 } 59 60 /* clear the output pin values */ 61 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 62 WREG32(rec->a_clk_reg, temp); 63 64 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 65 WREG32(rec->a_data_reg, temp); 66 67 /* set the pins to input */ 68 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 69 WREG32(rec->en_clk_reg, temp); 70 71 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 72 WREG32(rec->en_data_reg, temp); 73 74 /* mask the gpio pins for software use */ 75 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 76 WREG32(rec->mask_clk_reg, temp); 77 temp = RREG32(rec->mask_clk_reg); 78 79 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 80 WREG32(rec->mask_data_reg, temp); 81 temp = RREG32(rec->mask_data_reg); 82 83 return 0; 84 } 85 86 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) 87 { 88 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 89 struct amdgpu_device *adev = i2c->dev->dev_private; 90 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 91 uint32_t temp; 92 93 /* unmask the gpio pins for software use */ 94 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 95 WREG32(rec->mask_clk_reg, temp); 96 temp = RREG32(rec->mask_clk_reg); 97 98 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 99 WREG32(rec->mask_data_reg, temp); 100 temp = RREG32(rec->mask_data_reg); 101 102 mutex_unlock(&i2c->mutex); 103 } 104 105 static int amdgpu_i2c_get_clock(void *i2c_priv) 106 { 107 struct amdgpu_i2c_chan *i2c = i2c_priv; 108 struct amdgpu_device *adev = i2c->dev->dev_private; 109 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 110 uint32_t val; 111 112 /* read the value off the pin */ 113 val = RREG32(rec->y_clk_reg); 114 val &= rec->y_clk_mask; 115 116 return (val != 0); 117 } 118 119 120 static int amdgpu_i2c_get_data(void *i2c_priv) 121 { 122 struct amdgpu_i2c_chan *i2c = i2c_priv; 123 struct amdgpu_device *adev = i2c->dev->dev_private; 124 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 125 uint32_t val; 126 127 /* read the value off the pin */ 128 val = RREG32(rec->y_data_reg); 129 val &= rec->y_data_mask; 130 131 return (val != 0); 132 } 133 134 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) 135 { 136 struct amdgpu_i2c_chan *i2c = i2c_priv; 137 struct amdgpu_device *adev = i2c->dev->dev_private; 138 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 139 uint32_t val; 140 141 /* set pin direction */ 142 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 143 val |= clock ? 0 : rec->en_clk_mask; 144 WREG32(rec->en_clk_reg, val); 145 } 146 147 static void amdgpu_i2c_set_data(void *i2c_priv, int data) 148 { 149 struct amdgpu_i2c_chan *i2c = i2c_priv; 150 struct amdgpu_device *adev = i2c->dev->dev_private; 151 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 152 uint32_t val; 153 154 /* set pin direction */ 155 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 156 val |= data ? 0 : rec->en_data_mask; 157 WREG32(rec->en_data_reg, val); 158 } 159 160 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { 161 .master_xfer = amdgpu_atombios_i2c_xfer, 162 .functionality = amdgpu_atombios_i2c_func, 163 }; 164 165 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 166 struct amdgpu_i2c_bus_rec *rec, 167 const char *name) 168 { 169 struct amdgpu_i2c_chan *i2c; 170 int ret; 171 172 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 173 if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) 174 return NULL; 175 176 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); 177 if (i2c == NULL) 178 return NULL; 179 180 i2c->rec = *rec; 181 i2c->adapter.owner = THIS_MODULE; 182 i2c->adapter.class = I2C_CLASS_DDC; 183 i2c->adapter.dev.parent = &dev->pdev->dev; 184 i2c->dev = dev; 185 i2c_set_adapdata(&i2c->adapter, i2c); 186 mutex_init(&i2c->mutex); 187 if (rec->hw_capable && 188 amdgpu_hw_i2c) { 189 /* hw i2c using atom */ 190 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 191 "AMDGPU i2c hw bus %s", name); 192 i2c->adapter.algo = &amdgpu_atombios_i2c_algo; 193 ret = i2c_add_adapter(&i2c->adapter); 194 if (ret) { 195 DRM_ERROR("Failed to register hw i2c %s\n", name); 196 goto out_free; 197 } 198 } else { 199 /* set the amdgpu bit adapter */ 200 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 201 "AMDGPU i2c bit bus %s", name); 202 i2c->adapter.algo_data = &i2c->bit; 203 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; 204 i2c->bit.post_xfer = amdgpu_i2c_post_xfer; 205 i2c->bit.setsda = amdgpu_i2c_set_data; 206 i2c->bit.setscl = amdgpu_i2c_set_clock; 207 i2c->bit.getsda = amdgpu_i2c_get_data; 208 i2c->bit.getscl = amdgpu_i2c_get_clock; 209 i2c->bit.udelay = 10; 210 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 211 i2c->bit.data = i2c; 212 ret = i2c_bit_add_bus(&i2c->adapter); 213 if (ret) { 214 DRM_ERROR("Failed to register bit i2c %s\n", name); 215 goto out_free; 216 } 217 } 218 219 return i2c; 220 out_free: 221 kfree(i2c); 222 return NULL; 223 224 } 225 226 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) 227 { 228 if (!i2c) 229 return; 230 i2c_del_adapter(&i2c->adapter); 231 kfree(i2c); 232 } 233 234 /* Add the default buses */ 235 void amdgpu_i2c_init(struct amdgpu_device *adev) 236 { 237 if (amdgpu_hw_i2c) 238 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 239 240 if (adev->is_atom_bios) 241 amdgpu_atombios_i2c_init(adev); 242 } 243 244 /* remove all the buses */ 245 void amdgpu_i2c_fini(struct amdgpu_device *adev) 246 { 247 int i; 248 249 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 250 if (adev->i2c_bus[i]) { 251 amdgpu_i2c_destroy(adev->i2c_bus[i]); 252 adev->i2c_bus[i] = NULL; 253 } 254 } 255 } 256 257 /* Add additional buses */ 258 void amdgpu_i2c_add(struct amdgpu_device *adev, 259 struct amdgpu_i2c_bus_rec *rec, 260 const char *name) 261 { 262 struct drm_device *dev = adev->ddev; 263 int i; 264 265 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 266 if (!adev->i2c_bus[i]) { 267 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); 268 return; 269 } 270 } 271 } 272 273 /* looks up bus based on id */ 274 struct amdgpu_i2c_chan * 275 amdgpu_i2c_lookup(struct amdgpu_device *adev, 276 struct amdgpu_i2c_bus_rec *i2c_bus) 277 { 278 int i; 279 280 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 281 if (adev->i2c_bus[i] && 282 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 283 return adev->i2c_bus[i]; 284 } 285 } 286 return NULL; 287 } 288 289 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, 290 u8 slave_addr, 291 u8 addr, 292 u8 *val) 293 { 294 u8 out_buf[2]; 295 u8 in_buf[2]; 296 struct i2c_msg msgs[] = { 297 { 298 .addr = slave_addr, 299 .flags = 0, 300 .len = 1, 301 .buf = out_buf, 302 }, 303 { 304 .addr = slave_addr, 305 .flags = I2C_M_RD, 306 .len = 1, 307 .buf = in_buf, 308 } 309 }; 310 311 out_buf[0] = addr; 312 out_buf[1] = 0; 313 314 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 315 *val = in_buf[0]; 316 DRM_DEBUG("val = 0x%02x\n", *val); 317 } else { 318 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 319 addr, *val); 320 } 321 } 322 323 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, 324 u8 slave_addr, 325 u8 addr, 326 u8 val) 327 { 328 uint8_t out_buf[2]; 329 struct i2c_msg msg = { 330 .addr = slave_addr, 331 .flags = 0, 332 .len = 2, 333 .buf = out_buf, 334 }; 335 336 out_buf[0] = addr; 337 out_buf[1] = val; 338 339 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 340 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 341 addr, val); 342 } 343 344 /* ddc router switching */ 345 void 346 amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector) 347 { 348 u8 val; 349 350 if (!amdgpu_connector->router.ddc_valid) 351 return; 352 353 if (!amdgpu_connector->router_bus) 354 return; 355 356 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 357 amdgpu_connector->router.i2c_addr, 358 0x3, &val); 359 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 360 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 361 amdgpu_connector->router.i2c_addr, 362 0x3, val); 363 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 364 amdgpu_connector->router.i2c_addr, 365 0x1, &val); 366 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 367 val |= amdgpu_connector->router.ddc_mux_state; 368 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 369 amdgpu_connector->router.i2c_addr, 370 0x1, val); 371 } 372 373 /* clock/data router switching */ 374 void 375 amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector) 376 { 377 u8 val; 378 379 if (!amdgpu_connector->router.cd_valid) 380 return; 381 382 if (!amdgpu_connector->router_bus) 383 return; 384 385 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 386 amdgpu_connector->router.i2c_addr, 387 0x3, &val); 388 val &= ~amdgpu_connector->router.cd_mux_control_pin; 389 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 390 amdgpu_connector->router.i2c_addr, 391 0x3, val); 392 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 393 amdgpu_connector->router.i2c_addr, 394 0x1, &val); 395 val &= ~amdgpu_connector->router.cd_mux_control_pin; 396 val |= amdgpu_connector->router.cd_mux_state; 397 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 398 amdgpu_connector->router.i2c_addr, 399 0x1, val); 400 } 401
Indexes created Sun Sep 21 14:09:52 GMT 2025