amdgpu_i2c.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_i2c.c,v 1.1.1.2 2021/12/18 20:11:09 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: amdgpu_i2c.c,v 1.1.1.2 2021/12/18 20:11:09 riastradh Exp $"); 31 32 #include <linux/export.h> 33 #include <linux/pci.h> 34 35 #include <drm/drm_edid.h> 36 #include <drm/amdgpu_drm.h> 37 #include "amdgpu.h" 38 #include "amdgpu_i2c.h" 39 #include "amdgpu_atombios.h" 40 #include "atom.h" 41 #include "atombios_dp.h" 42 #include "atombios_i2c.h" 43 44 /* bit banging i2c */ 45 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) 46 { 47 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 48 struct amdgpu_device *adev = i2c->dev->dev_private; 49 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 50 uint32_t temp; 51 52 mutex_lock(&i2c->mutex); 53 54 /* switch the pads to ddc mode */ 55 if (rec->hw_capable) { 56 temp = RREG32(rec->mask_clk_reg); 57 temp &= ~(1 << 16); 58 WREG32(rec->mask_clk_reg, temp); 59 } 60 61 /* clear the output pin values */ 62 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 63 WREG32(rec->a_clk_reg, temp); 64 65 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 66 WREG32(rec->a_data_reg, temp); 67 68 /* set the pins to input */ 69 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 70 WREG32(rec->en_clk_reg, temp); 71 72 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 73 WREG32(rec->en_data_reg, temp); 74 75 /* mask the gpio pins for software use */ 76 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 77 WREG32(rec->mask_clk_reg, temp); 78 temp = RREG32(rec->mask_clk_reg); 79 80 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 81 WREG32(rec->mask_data_reg, temp); 82 temp = RREG32(rec->mask_data_reg); 83 84 return 0; 85 } 86 87 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) 88 { 89 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 90 struct amdgpu_device *adev = i2c->dev->dev_private; 91 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 92 uint32_t temp; 93 94 /* unmask the gpio pins for software use */ 95 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 96 WREG32(rec->mask_clk_reg, temp); 97 temp = RREG32(rec->mask_clk_reg); 98 99 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 100 WREG32(rec->mask_data_reg, temp); 101 temp = RREG32(rec->mask_data_reg); 102 103 mutex_unlock(&i2c->mutex); 104 } 105 106 static int amdgpu_i2c_get_clock(void *i2c_priv) 107 { 108 struct amdgpu_i2c_chan *i2c = i2c_priv; 109 struct amdgpu_device *adev = i2c->dev->dev_private; 110 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 111 uint32_t val; 112 113 /* read the value off the pin */ 114 val = RREG32(rec->y_clk_reg); 115 val &= rec->y_clk_mask; 116 117 return (val != 0); 118 } 119 120 121 static int amdgpu_i2c_get_data(void *i2c_priv) 122 { 123 struct amdgpu_i2c_chan *i2c = i2c_priv; 124 struct amdgpu_device *adev = i2c->dev->dev_private; 125 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 126 uint32_t val; 127 128 /* read the value off the pin */ 129 val = RREG32(rec->y_data_reg); 130 val &= rec->y_data_mask; 131 132 return (val != 0); 133 } 134 135 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) 136 { 137 struct amdgpu_i2c_chan *i2c = i2c_priv; 138 struct amdgpu_device *adev = i2c->dev->dev_private; 139 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 140 uint32_t val; 141 142 /* set pin direction */ 143 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 144 val |= clock ? 0 : rec->en_clk_mask; 145 WREG32(rec->en_clk_reg, val); 146 } 147 148 static void amdgpu_i2c_set_data(void *i2c_priv, int data) 149 { 150 struct amdgpu_i2c_chan *i2c = i2c_priv; 151 struct amdgpu_device *adev = i2c->dev->dev_private; 152 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 153 uint32_t val; 154 155 /* set pin direction */ 156 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 157 val |= data ? 0 : rec->en_data_mask; 158 WREG32(rec->en_data_reg, val); 159 } 160 161 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { 162 .master_xfer = amdgpu_atombios_i2c_xfer, 163 .functionality = amdgpu_atombios_i2c_func, 164 }; 165 166 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 167 const struct amdgpu_i2c_bus_rec *rec, 168 const char *name) 169 { 170 struct amdgpu_i2c_chan *i2c; 171 int ret; 172 173 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 174 if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) 175 return NULL; 176 177 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); 178 if (i2c == NULL) 179 return NULL; 180 181 i2c->rec = *rec; 182 i2c->adapter.owner = THIS_MODULE; 183 i2c->adapter.class = I2C_CLASS_DDC; 184 i2c->adapter.dev.parent = &dev->pdev->dev; 185 i2c->dev = dev; 186 i2c_set_adapdata(&i2c->adapter, i2c); 187 mutex_init(&i2c->mutex); 188 if (rec->hw_capable && 189 amdgpu_hw_i2c) { 190 /* hw i2c using atom */ 191 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 192 "AMDGPU i2c hw bus %s", name); 193 i2c->adapter.algo = &amdgpu_atombios_i2c_algo; 194 ret = i2c_add_adapter(&i2c->adapter); 195 if (ret) 196 goto out_free; 197 } else { 198 /* set the amdgpu bit adapter */ 199 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 200 "AMDGPU i2c bit bus %s", name); 201 i2c->adapter.algo_data = &i2c->bit; 202 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; 203 i2c->bit.post_xfer = amdgpu_i2c_post_xfer; 204 i2c->bit.setsda = amdgpu_i2c_set_data; 205 i2c->bit.setscl = amdgpu_i2c_set_clock; 206 i2c->bit.getsda = amdgpu_i2c_get_data; 207 i2c->bit.getscl = amdgpu_i2c_get_clock; 208 i2c->bit.udelay = 10; 209 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 210 i2c->bit.data = i2c; 211 ret = i2c_bit_add_bus(&i2c->adapter); 212 if (ret) { 213 DRM_ERROR("Failed to register bit i2c %s\n", name); 214 goto out_free; 215 } 216 } 217 218 return i2c; 219 out_free: 220 kfree(i2c); 221 return NULL; 222 223 } 224 225 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) 226 { 227 if (!i2c) 228 return; 229 WARN_ON(i2c->has_aux); 230 i2c_del_adapter(&i2c->adapter); 231 kfree(i2c); 232 } 233 234 /* Add the default buses */ 235 void amdgpu_i2c_init(struct amdgpu_device *adev) 236 { 237 if (amdgpu_hw_i2c) 238 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 239 240 amdgpu_atombios_i2c_init(adev); 241 } 242 243 /* remove all the buses */ 244 void amdgpu_i2c_fini(struct amdgpu_device *adev) 245 { 246 int i; 247 248 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 249 if (adev->i2c_bus[i]) { 250 amdgpu_i2c_destroy(adev->i2c_bus[i]); 251 adev->i2c_bus[i] = NULL; 252 } 253 } 254 } 255 256 /* Add additional buses */ 257 void amdgpu_i2c_add(struct amdgpu_device *adev, 258 const struct amdgpu_i2c_bus_rec *rec, 259 const char *name) 260 { 261 struct drm_device *dev = adev->ddev; 262 int i; 263 264 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 265 if (!adev->i2c_bus[i]) { 266 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); 267 return; 268 } 269 } 270 } 271 272 /* looks up bus based on id */ 273 struct amdgpu_i2c_chan * 274 amdgpu_i2c_lookup(struct amdgpu_device *adev, 275 const struct amdgpu_i2c_bus_rec *i2c_bus) 276 { 277 int i; 278 279 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 280 if (adev->i2c_bus[i] && 281 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 282 return adev->i2c_bus[i]; 283 } 284 } 285 return NULL; 286 } 287 288 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, 289 u8 slave_addr, 290 u8 addr, 291 u8 *val) 292 { 293 u8 out_buf[2]; 294 u8 in_buf[2]; 295 struct i2c_msg msgs[] = { 296 { 297 .addr = slave_addr, 298 .flags = 0, 299 .len = 1, 300 .buf = out_buf, 301 }, 302 { 303 .addr = slave_addr, 304 .flags = I2C_M_RD, 305 .len = 1, 306 .buf = in_buf, 307 } 308 }; 309 310 out_buf[0] = addr; 311 out_buf[1] = 0; 312 313 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 314 *val = in_buf[0]; 315 DRM_DEBUG("val = 0x%02x\n", *val); 316 } else { 317 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 318 addr, *val); 319 } 320 } 321 322 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, 323 u8 slave_addr, 324 u8 addr, 325 u8 val) 326 { 327 uint8_t out_buf[2]; 328 struct i2c_msg msg = { 329 .addr = slave_addr, 330 .flags = 0, 331 .len = 2, 332 .buf = out_buf, 333 }; 334 335 out_buf[0] = addr; 336 out_buf[1] = val; 337 338 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 339 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 340 addr, val); 341 } 342 343 /* ddc router switching */ 344 void 345 amdgpu_i2c_router_select_ddc_port(const struct amdgpu_connector *amdgpu_connector) 346 { 347 u8 val; 348 349 if (!amdgpu_connector->router.ddc_valid) 350 return; 351 352 if (!amdgpu_connector->router_bus) 353 return; 354 355 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 356 amdgpu_connector->router.i2c_addr, 357 0x3, &val); 358 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 359 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 360 amdgpu_connector->router.i2c_addr, 361 0x3, val); 362 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 363 amdgpu_connector->router.i2c_addr, 364 0x1, &val); 365 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 366 val |= amdgpu_connector->router.ddc_mux_state; 367 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 368 amdgpu_connector->router.i2c_addr, 369 0x1, val); 370 } 371 372 /* clock/data router switching */ 373 void 374 amdgpu_i2c_router_select_cd_port(const struct amdgpu_connector *amdgpu_connector) 375 { 376 u8 val; 377 378 if (!amdgpu_connector->router.cd_valid) 379 return; 380 381 if (!amdgpu_connector->router_bus) 382 return; 383 384 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 385 amdgpu_connector->router.i2c_addr, 386 0x3, &val); 387 val &= ~amdgpu_connector->router.cd_mux_control_pin; 388 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 389 amdgpu_connector->router.i2c_addr, 390 0x3, val); 391 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 392 amdgpu_connector->router.i2c_addr, 393 0x1, &val); 394 val &= ~amdgpu_connector->router.cd_mux_control_pin; 395 val |= amdgpu_connector->router.cd_mux_state; 396 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 397 amdgpu_connector->router.i2c_addr, 398 0x1, val); 399 } 400
Indexes created Sun Sep 21 14:09:52 GMT 2025