amdgpu_i2c.c revision 1.3.6.3
1 /* $NetBSD: amdgpu_i2c.c,v 1.3.6.3 2020/04/08 14:08:22 martin Exp $ */ 2 3 /* 4 * Copyright 2007-8 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: Dave Airlie 26 * Alex Deucher 27 */ 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_i2c.c,v 1.3.6.3 2020/04/08 14:08:22 martin Exp $"); 30 31 #include <linux/export.h> 32 33 #include <drm/drmP.h> 34 #include <drm/drm_edid.h> 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu.h" 37 #include "amdgpu_i2c.h" 38 #include "amdgpu_atombios.h" 39 #include "atom.h" 40 #include "atombios_dp.h" 41 #include "atombios_i2c.h" 42 43 #include <linux/nbsd-namespace.h> 44 45 /* bit banging i2c */ 46 static int amdgpu_i2c_pre_xfer(struct i2c_adapter *i2c_adap) 47 { 48 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 49 struct amdgpu_device *adev = i2c->dev->dev_private; 50 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 51 uint32_t temp; 52 53 mutex_lock(&i2c->mutex); 54 55 /* switch the pads to ddc mode */ 56 if (rec->hw_capable) { 57 temp = RREG32(rec->mask_clk_reg); 58 temp &= ~(1 << 16); 59 WREG32(rec->mask_clk_reg, temp); 60 } 61 62 /* clear the output pin values */ 63 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 64 WREG32(rec->a_clk_reg, temp); 65 66 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 67 WREG32(rec->a_data_reg, temp); 68 69 /* set the pins to input */ 70 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 71 WREG32(rec->en_clk_reg, temp); 72 73 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 74 WREG32(rec->en_data_reg, temp); 75 76 /* mask the gpio pins for software use */ 77 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 78 WREG32(rec->mask_clk_reg, temp); 79 temp = RREG32(rec->mask_clk_reg); 80 81 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 82 WREG32(rec->mask_data_reg, temp); 83 temp = RREG32(rec->mask_data_reg); 84 85 return 0; 86 } 87 88 static void amdgpu_i2c_post_xfer(struct i2c_adapter *i2c_adap) 89 { 90 struct amdgpu_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 91 struct amdgpu_device *adev = i2c->dev->dev_private; 92 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 93 uint32_t temp; 94 95 /* unmask the gpio pins for software use */ 96 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 97 WREG32(rec->mask_clk_reg, temp); 98 temp = RREG32(rec->mask_clk_reg); 99 100 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 101 WREG32(rec->mask_data_reg, temp); 102 temp = RREG32(rec->mask_data_reg); 103 104 mutex_unlock(&i2c->mutex); 105 } 106 107 static int amdgpu_i2c_get_clock(void *i2c_priv) 108 { 109 struct amdgpu_i2c_chan *i2c = i2c_priv; 110 struct amdgpu_device *adev = i2c->dev->dev_private; 111 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 112 uint32_t val; 113 114 /* read the value off the pin */ 115 val = RREG32(rec->y_clk_reg); 116 val &= rec->y_clk_mask; 117 118 return (val != 0); 119 } 120 121 122 static int amdgpu_i2c_get_data(void *i2c_priv) 123 { 124 struct amdgpu_i2c_chan *i2c = i2c_priv; 125 struct amdgpu_device *adev = i2c->dev->dev_private; 126 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 127 uint32_t val; 128 129 /* read the value off the pin */ 130 val = RREG32(rec->y_data_reg); 131 val &= rec->y_data_mask; 132 133 return (val != 0); 134 } 135 136 static void amdgpu_i2c_set_clock(void *i2c_priv, int clock) 137 { 138 struct amdgpu_i2c_chan *i2c = i2c_priv; 139 struct amdgpu_device *adev = i2c->dev->dev_private; 140 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 141 uint32_t val; 142 143 /* set pin direction */ 144 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 145 val |= clock ? 0 : rec->en_clk_mask; 146 WREG32(rec->en_clk_reg, val); 147 } 148 149 static void amdgpu_i2c_set_data(void *i2c_priv, int data) 150 { 151 struct amdgpu_i2c_chan *i2c = i2c_priv; 152 struct amdgpu_device *adev = i2c->dev->dev_private; 153 struct amdgpu_i2c_bus_rec *rec = &i2c->rec; 154 uint32_t val; 155 156 /* set pin direction */ 157 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 158 val |= data ? 0 : rec->en_data_mask; 159 WREG32(rec->en_data_reg, val); 160 } 161 162 static const struct i2c_algorithm amdgpu_atombios_i2c_algo = { 163 .master_xfer = amdgpu_atombios_i2c_xfer, 164 .functionality = amdgpu_atombios_i2c_func, 165 }; 166 167 struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, 168 struct amdgpu_i2c_bus_rec *rec, 169 const char *name) 170 { 171 struct amdgpu_i2c_chan *i2c; 172 int ret; 173 174 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 175 if (rec->mm_i2c && (amdgpu_hw_i2c == 0)) 176 return NULL; 177 178 i2c = kzalloc(sizeof(struct amdgpu_i2c_chan), GFP_KERNEL); 179 if (i2c == NULL) 180 return NULL; 181 182 i2c->rec = *rec; 183 i2c->adapter.owner = THIS_MODULE; 184 i2c->adapter.class = I2C_CLASS_DDC; 185 i2c->adapter.dev.parent = dev->dev; 186 i2c->dev = dev; 187 i2c_set_adapdata(&i2c->adapter, i2c); 188 mutex_init(&i2c->mutex); 189 if (rec->hw_capable && 190 amdgpu_hw_i2c) { 191 /* hw i2c using atom */ 192 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 193 "AMDGPU i2c hw bus %s", name); 194 i2c->adapter.algo = &amdgpu_atombios_i2c_algo; 195 ret = i2c_add_adapter(&i2c->adapter); 196 if (ret) { 197 DRM_ERROR("Failed to register hw i2c %s\n", name); 198 goto out_free; 199 } 200 } else { 201 /* set the amdgpu bit adapter */ 202 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 203 "AMDGPU i2c bit bus %s", name); 204 i2c->adapter.algo_data = &i2c->bit; 205 i2c->bit.pre_xfer = amdgpu_i2c_pre_xfer; 206 i2c->bit.post_xfer = amdgpu_i2c_post_xfer; 207 i2c->bit.setsda = amdgpu_i2c_set_data; 208 i2c->bit.setscl = amdgpu_i2c_set_clock; 209 i2c->bit.getsda = amdgpu_i2c_get_data; 210 i2c->bit.getscl = amdgpu_i2c_get_clock; 211 i2c->bit.udelay = 10; 212 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 213 i2c->bit.data = i2c; 214 ret = i2c_bit_add_bus(&i2c->adapter); 215 if (ret) { 216 DRM_ERROR("Failed to register bit i2c %s\n", name); 217 goto out_free; 218 } 219 } 220 221 return i2c; 222 out_free: 223 mutex_destroy(&i2c->mutex); 224 kfree(i2c); 225 return NULL; 226 227 } 228 229 void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) 230 { 231 if (!i2c) 232 return; 233 i2c_del_adapter(&i2c->adapter); 234 mutex_destroy(&i2c->mutex); 235 kfree(i2c); 236 } 237 238 /* Add the default buses */ 239 void amdgpu_i2c_init(struct amdgpu_device *adev) 240 { 241 if (amdgpu_hw_i2c) 242 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 243 244 if (adev->is_atom_bios) 245 amdgpu_atombios_i2c_init(adev); 246 } 247 248 /* remove all the buses */ 249 void amdgpu_i2c_fini(struct amdgpu_device *adev) 250 { 251 int i; 252 253 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 254 if (adev->i2c_bus[i]) { 255 amdgpu_i2c_destroy(adev->i2c_bus[i]); 256 adev->i2c_bus[i] = NULL; 257 } 258 } 259 } 260 261 /* Add additional buses */ 262 void amdgpu_i2c_add(struct amdgpu_device *adev, 263 struct amdgpu_i2c_bus_rec *rec, 264 const char *name) 265 { 266 struct drm_device *dev = adev->ddev; 267 int i; 268 269 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 270 if (!adev->i2c_bus[i]) { 271 adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); 272 return; 273 } 274 } 275 } 276 277 /* looks up bus based on id */ 278 struct amdgpu_i2c_chan * 279 amdgpu_i2c_lookup(struct amdgpu_device *adev, 280 struct amdgpu_i2c_bus_rec *i2c_bus) 281 { 282 int i; 283 284 for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { 285 if (adev->i2c_bus[i] && 286 (adev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 287 return adev->i2c_bus[i]; 288 } 289 } 290 return NULL; 291 } 292 293 static void amdgpu_i2c_get_byte(struct amdgpu_i2c_chan *i2c_bus, 294 u8 slave_addr, 295 u8 addr, 296 u8 *val) 297 { 298 u8 out_buf[2]; 299 u8 in_buf[2]; 300 struct i2c_msg msgs[] = { 301 { 302 .addr = slave_addr, 303 .flags = 0, 304 .len = 1, 305 .buf = out_buf, 306 }, 307 { 308 .addr = slave_addr, 309 .flags = I2C_M_RD, 310 .len = 1, 311 .buf = in_buf, 312 } 313 }; 314 315 out_buf[0] = addr; 316 out_buf[1] = 0; 317 318 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 319 *val = in_buf[0]; 320 DRM_DEBUG("val = 0x%02x\n", *val); 321 } else { 322 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 323 addr, *val); 324 } 325 } 326 327 static void amdgpu_i2c_put_byte(struct amdgpu_i2c_chan *i2c_bus, 328 u8 slave_addr, 329 u8 addr, 330 u8 val) 331 { 332 uint8_t out_buf[2]; 333 struct i2c_msg msg = { 334 .addr = slave_addr, 335 .flags = 0, 336 .len = 2, 337 .buf = out_buf, 338 }; 339 340 out_buf[0] = addr; 341 out_buf[1] = val; 342 343 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 344 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 345 addr, val); 346 } 347 348 /* ddc router switching */ 349 void 350 amdgpu_i2c_router_select_ddc_port(struct amdgpu_connector *amdgpu_connector) 351 { 352 u8 val; 353 354 if (!amdgpu_connector->router.ddc_valid) 355 return; 356 357 if (!amdgpu_connector->router_bus) 358 return; 359 360 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 361 amdgpu_connector->router.i2c_addr, 362 0x3, &val); 363 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 364 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 365 amdgpu_connector->router.i2c_addr, 366 0x3, val); 367 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 368 amdgpu_connector->router.i2c_addr, 369 0x1, &val); 370 val &= ~amdgpu_connector->router.ddc_mux_control_pin; 371 val |= amdgpu_connector->router.ddc_mux_state; 372 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 373 amdgpu_connector->router.i2c_addr, 374 0x1, val); 375 } 376 377 /* clock/data router switching */ 378 void 379 amdgpu_i2c_router_select_cd_port(struct amdgpu_connector *amdgpu_connector) 380 { 381 u8 val; 382 383 if (!amdgpu_connector->router.cd_valid) 384 return; 385 386 if (!amdgpu_connector->router_bus) 387 return; 388 389 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 390 amdgpu_connector->router.i2c_addr, 391 0x3, &val); 392 val &= ~amdgpu_connector->router.cd_mux_control_pin; 393 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 394 amdgpu_connector->router.i2c_addr, 395 0x3, val); 396 amdgpu_i2c_get_byte(amdgpu_connector->router_bus, 397 amdgpu_connector->router.i2c_addr, 398 0x1, &val); 399 val &= ~amdgpu_connector->router.cd_mux_control_pin; 400 val |= amdgpu_connector->router.cd_mux_state; 401 amdgpu_i2c_put_byte(amdgpu_connector->router_bus, 402 amdgpu_connector->router.i2c_addr, 403 0x1, val); 404 } 405
Indexes created Sun Sep 21 14:09:52 GMT 2025