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amdgpu_ih.c revision 1.1.1.1 
      1 /*	$NetBSD: amdgpu_ih.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2014 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $");
     28 
     29 #include <drm/drmP.h>
     30 #include "amdgpu.h"
     31 #include "amdgpu_ih.h"
     32 #include "amdgpu_amdkfd.h"
     33 
     34 /**
     35  * amdgpu_ih_ring_alloc - allocate memory for the IH ring
     36  *
     37  * @adev: amdgpu_device pointer
     38  *
     39  * Allocate a ring buffer for the interrupt controller.
     40  * Returns 0 for success, errors for failure.
     41  */
     42 static int amdgpu_ih_ring_alloc(struct amdgpu_device *adev)
     43 {
     44 	int r;
     45 
     46 	/* Allocate ring buffer */
     47 	if (adev->irq.ih.ring_obj == NULL) {
     48 		r = amdgpu_bo_create(adev, adev->irq.ih.ring_size,
     49 				     PAGE_SIZE, true,
     50 				     AMDGPU_GEM_DOMAIN_GTT, 0,
     51 				     NULL, NULL, &adev->irq.ih.ring_obj);
     52 		if (r) {
     53 			DRM_ERROR("amdgpu: failed to create ih ring buffer (%d).\n", r);
     54 			return r;
     55 		}
     56 		r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
     57 		if (unlikely(r != 0))
     58 			return r;
     59 		r = amdgpu_bo_pin(adev->irq.ih.ring_obj,
     60 				  AMDGPU_GEM_DOMAIN_GTT,
     61 				  &adev->irq.ih.gpu_addr);
     62 		if (r) {
     63 			amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
     64 			DRM_ERROR("amdgpu: failed to pin ih ring buffer (%d).\n", r);
     65 			return r;
     66 		}
     67 		r = amdgpu_bo_kmap(adev->irq.ih.ring_obj,
     68 				   (void **)&adev->irq.ih.ring);
     69 		amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
     70 		if (r) {
     71 			DRM_ERROR("amdgpu: failed to map ih ring buffer (%d).\n", r);
     72 			return r;
     73 		}
     74 	}
     75 	return 0;
     76 }
     77 
     78 /**
     79  * amdgpu_ih_ring_init - initialize the IH state
     80  *
     81  * @adev: amdgpu_device pointer
     82  *
     83  * Initializes the IH state and allocates a buffer
     84  * for the IH ring buffer.
     85  * Returns 0 for success, errors for failure.
     86  */
     87 int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
     88 			bool use_bus_addr)
     89 {
     90 	u32 rb_bufsz;
     91 	int r;
     92 
     93 	/* Align ring size */
     94 	rb_bufsz = order_base_2(ring_size / 4);
     95 	ring_size = (1 << rb_bufsz) * 4;
     96 	adev->irq.ih.ring_size = ring_size;
     97 	adev->irq.ih.ptr_mask = adev->irq.ih.ring_size - 1;
     98 	adev->irq.ih.rptr = 0;
     99 	adev->irq.ih.use_bus_addr = use_bus_addr;
    100 
    101 	if (adev->irq.ih.use_bus_addr) {
    102 		if (!adev->irq.ih.ring) {
    103 			/* add 8 bytes for the rptr/wptr shadows and
    104 			 * add them to the end of the ring allocation.
    105 			 */
    106 			adev->irq.ih.ring = pci_alloc_consistent(adev->pdev,
    107 								 adev->irq.ih.ring_size + 8,
    108 								 &adev->irq.ih.rb_dma_addr);
    109 			if (adev->irq.ih.ring == NULL)
    110 				return -ENOMEM;
    111 			memset((void *)adev->irq.ih.ring, 0, adev->irq.ih.ring_size + 8);
    112 			adev->irq.ih.wptr_offs = (adev->irq.ih.ring_size / 4) + 0;
    113 			adev->irq.ih.rptr_offs = (adev->irq.ih.ring_size / 4) + 1;
    114 		}
    115 		return 0;
    116 	} else {
    117 		r = amdgpu_wb_get(adev, &adev->irq.ih.wptr_offs);
    118 		if (r) {
    119 			dev_err(adev->dev, "(%d) ih wptr_offs wb alloc failed\n", r);
    120 			return r;
    121 		}
    122 
    123 		r = amdgpu_wb_get(adev, &adev->irq.ih.rptr_offs);
    124 		if (r) {
    125 			amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
    126 			dev_err(adev->dev, "(%d) ih rptr_offs wb alloc failed\n", r);
    127 			return r;
    128 		}
    129 
    130 		return amdgpu_ih_ring_alloc(adev);
    131 	}
    132 }
    133 
    134 /**
    135  * amdgpu_ih_ring_fini - tear down the IH state
    136  *
    137  * @adev: amdgpu_device pointer
    138  *
    139  * Tears down the IH state and frees buffer
    140  * used for the IH ring buffer.
    141  */
    142 void amdgpu_ih_ring_fini(struct amdgpu_device *adev)
    143 {
    144 	int r;
    145 
    146 	if (adev->irq.ih.use_bus_addr) {
    147 		if (adev->irq.ih.ring) {
    148 			/* add 8 bytes for the rptr/wptr shadows and
    149 			 * add them to the end of the ring allocation.
    150 			 */
    151 			pci_free_consistent(adev->pdev, adev->irq.ih.ring_size + 8,
    152 					    (void *)adev->irq.ih.ring,
    153 					    adev->irq.ih.rb_dma_addr);
    154 			adev->irq.ih.ring = NULL;
    155 		}
    156 	} else {
    157 		if (adev->irq.ih.ring_obj) {
    158 			r = amdgpu_bo_reserve(adev->irq.ih.ring_obj, false);
    159 			if (likely(r == 0)) {
    160 				amdgpu_bo_kunmap(adev->irq.ih.ring_obj);
    161 				amdgpu_bo_unpin(adev->irq.ih.ring_obj);
    162 				amdgpu_bo_unreserve(adev->irq.ih.ring_obj);
    163 			}
    164 			amdgpu_bo_unref(&adev->irq.ih.ring_obj);
    165 			adev->irq.ih.ring = NULL;
    166 			adev->irq.ih.ring_obj = NULL;
    167 		}
    168 		amdgpu_wb_free(adev, adev->irq.ih.wptr_offs);
    169 		amdgpu_wb_free(adev, adev->irq.ih.rptr_offs);
    170 	}
    171 }
    172 
    173 /**
    174  * amdgpu_ih_process - interrupt handler
    175  *
    176  * @adev: amdgpu_device pointer
    177  *
    178  * Interrupt hander (VI), walk the IH ring.
    179  * Returns irq process return code.
    180  */
    181 int amdgpu_ih_process(struct amdgpu_device *adev)
    182 {
    183 	struct amdgpu_iv_entry entry;
    184 	u32 wptr;
    185 
    186 	if (!adev->irq.ih.enabled || adev->shutdown)
    187 		return IRQ_NONE;
    188 
    189 	wptr = amdgpu_ih_get_wptr(adev);
    190 
    191 restart_ih:
    192 	/* is somebody else already processing irqs? */
    193 	if (atomic_xchg(&adev->irq.ih.lock, 1))
    194 		return IRQ_NONE;
    195 
    196 	DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, adev->irq.ih.rptr, wptr);
    197 
    198 	/* Order reading of wptr vs. reading of IH ring data */
    199 	rmb();
    200 
    201 	while (adev->irq.ih.rptr != wptr) {
    202 		u32 ring_index = adev->irq.ih.rptr >> 2;
    203 
    204 		/* Before dispatching irq to IP blocks, send it to amdkfd */
    205 		amdgpu_amdkfd_interrupt(adev,
    206 				(const void *) &adev->irq.ih.ring[ring_index]);
    207 
    208 		entry.iv_entry = (const uint32_t *)
    209 			&adev->irq.ih.ring[ring_index];
    210 		amdgpu_ih_decode_iv(adev, &entry);
    211 		adev->irq.ih.rptr &= adev->irq.ih.ptr_mask;
    212 
    213 		amdgpu_irq_dispatch(adev, &entry);
    214 	}
    215 	amdgpu_ih_set_rptr(adev);
    216 	atomic_set(&adev->irq.ih.lock, 0);
    217 
    218 	/* make sure wptr hasn't changed while processing */
    219 	wptr = amdgpu_ih_get_wptr(adev);
    220 	if (wptr != adev->irq.ih.rptr)
    221 		goto restart_ih;
    222 
    223 	return IRQ_HANDLED;
    224 }
    225