amdgpu_ih.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_ih.c,v 1.1.1.2 2021/12/18 20:11:09 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ih.c,v 1.1.1.2 2021/12/18 20:11:09 riastradh Exp $"); 28 29 #include <linux/dma-mapping.h> 30 31 #include "amdgpu.h" 32 #include "amdgpu_ih.h" 33 34 /** 35 * amdgpu_ih_ring_init - initialize the IH state 36 * 37 * @adev: amdgpu_device pointer 38 * @ih: ih ring to initialize 39 * @ring_size: ring size to allocate 40 * @use_bus_addr: true when we can use dma_alloc_coherent 41 * 42 * Initializes the IH state and allocates a buffer 43 * for the IH ring buffer. 44 * Returns 0 for success, errors for failure. 45 */ 46 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 47 unsigned ring_size, bool use_bus_addr) 48 { 49 u32 rb_bufsz; 50 int r; 51 52 /* Align ring size */ 53 rb_bufsz = order_base_2(ring_size / 4); 54 ring_size = (1 << rb_bufsz) * 4; 55 ih->ring_size = ring_size; 56 ih->ptr_mask = ih->ring_size - 1; 57 ih->rptr = 0; 58 ih->use_bus_addr = use_bus_addr; 59 60 if (use_bus_addr) { 61 dma_addr_t dma_addr; 62 63 if (ih->ring) 64 return 0; 65 66 /* add 8 bytes for the rptr/wptr shadows and 67 * add them to the end of the ring allocation. 68 */ 69 ih->ring = dma_alloc_coherent(adev->dev, ih->ring_size + 8, 70 &dma_addr, GFP_KERNEL); 71 if (ih->ring == NULL) 72 return -ENOMEM; 73 74 ih->gpu_addr = dma_addr; 75 ih->wptr_addr = dma_addr + ih->ring_size; 76 ih->wptr_cpu = &ih->ring[ih->ring_size / 4]; 77 ih->rptr_addr = dma_addr + ih->ring_size + 4; 78 ih->rptr_cpu = &ih->ring[(ih->ring_size / 4) + 1]; 79 } else { 80 unsigned wptr_offs, rptr_offs; 81 82 r = amdgpu_device_wb_get(adev, &wptr_offs); 83 if (r) 84 return r; 85 86 r = amdgpu_device_wb_get(adev, &rptr_offs); 87 if (r) { 88 amdgpu_device_wb_free(adev, wptr_offs); 89 return r; 90 } 91 92 r = amdgpu_bo_create_kernel(adev, ih->ring_size, PAGE_SIZE, 93 AMDGPU_GEM_DOMAIN_GTT, 94 &ih->ring_obj, &ih->gpu_addr, 95 (void **)&ih->ring); 96 if (r) { 97 amdgpu_device_wb_free(adev, rptr_offs); 98 amdgpu_device_wb_free(adev, wptr_offs); 99 return r; 100 } 101 102 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4; 103 ih->wptr_cpu = &adev->wb.wb[wptr_offs]; 104 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4; 105 ih->rptr_cpu = &adev->wb.wb[rptr_offs]; 106 } 107 return 0; 108 } 109 110 /** 111 * amdgpu_ih_ring_fini - tear down the IH state 112 * 113 * @adev: amdgpu_device pointer 114 * @ih: ih ring to tear down 115 * 116 * Tears down the IH state and frees buffer 117 * used for the IH ring buffer. 118 */ 119 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 120 { 121 if (ih->use_bus_addr) { 122 if (!ih->ring) 123 return; 124 125 /* add 8 bytes for the rptr/wptr shadows and 126 * add them to the end of the ring allocation. 127 */ 128 dma_free_coherent(adev->dev, ih->ring_size + 8, 129 (void *)ih->ring, ih->gpu_addr); 130 ih->ring = NULL; 131 } else { 132 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr, 133 (void **)&ih->ring); 134 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4); 135 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4); 136 } 137 } 138 139 /** 140 * amdgpu_ih_process - interrupt handler 141 * 142 * @adev: amdgpu_device pointer 143 * @ih: ih ring to process 144 * 145 * Interrupt hander (VI), walk the IH ring. 146 * Returns irq process return code. 147 */ 148 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih) 149 { 150 unsigned int count = AMDGPU_IH_MAX_NUM_IVS; 151 u32 wptr; 152 153 if (!ih->enabled || adev->shutdown) 154 return IRQ_NONE; 155 156 wptr = amdgpu_ih_get_wptr(adev, ih); 157 158 restart_ih: 159 /* is somebody else already processing irqs? */ 160 if (atomic_xchg(&ih->lock, 1)) 161 return IRQ_NONE; 162 163 DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); 164 165 /* Order reading of wptr vs. reading of IH ring data */ 166 rmb(); 167 168 while (ih->rptr != wptr && --count) { 169 amdgpu_irq_dispatch(adev, ih); 170 ih->rptr &= ih->ptr_mask; 171 } 172 173 amdgpu_ih_set_rptr(adev, ih); 174 atomic_set(&ih->lock, 0); 175 176 /* make sure wptr hasn't changed while processing */ 177 wptr = amdgpu_ih_get_wptr(adev, ih); 178 if (wptr != ih->rptr) 179 goto restart_ih; 180 181 return IRQ_HANDLED; 182 } 183 184
Indexes created Mon Sep 29 21:09:56 GMT 2025