amdgpu_kms.c revision 1.3.6.2
1 /* $NetBSD: amdgpu_kms.c,v 1.3.6.2 2019/06/10 22:07:58 christos Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: amdgpu_kms.c,v 1.3.6.2 2019/06/10 22:07:58 christos Exp $"); 32 33 #include <drm/drmP.h> 34 #include "amdgpu.h" 35 #include <drm/amdgpu_drm.h> 36 #include "amdgpu_uvd.h" 37 #include "amdgpu_vce.h" 38 39 #include <linux/vga_switcheroo.h> 40 #include <linux/slab.h> 41 #include <linux/pm_runtime.h> 42 #include "amdgpu_amdkfd.h" 43 44 #if defined(CONFIG_VGA_SWITCHEROO) 45 bool amdgpu_has_atpx(void); 46 #else 47 static inline bool amdgpu_has_atpx(void) { return false; } 48 #endif 49 50 /** 51 * amdgpu_driver_unload_kms - Main unload function for KMS. 52 * 53 * @dev: drm dev pointer 54 * 55 * This is the main unload function for KMS (all asics). 56 * Returns 0 on success. 57 */ 58 int amdgpu_driver_unload_kms(struct drm_device *dev) 59 { 60 struct amdgpu_device *adev = dev->dev_private; 61 62 if (adev == NULL) 63 return 0; 64 65 if (adev->rmmio_size == 0) 66 goto done_free; 67 68 pm_runtime_get_sync(dev->dev); 69 70 amdgpu_amdkfd_device_fini(adev); 71 72 amdgpu_acpi_fini(adev); 73 74 amdgpu_device_fini(adev); 75 76 done_free: 77 kfree(adev); 78 dev->dev_private = NULL; 79 return 0; 80 } 81 82 /** 83 * amdgpu_driver_load_kms - Main load function for KMS. 84 * 85 * @dev: drm dev pointer 86 * @flags: device flags 87 * 88 * This is the main load function for KMS (all asics). 89 * Returns 0 on success, error on failure. 90 */ 91 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags) 92 { 93 struct amdgpu_device *adev; 94 int r, acpi_status; 95 96 adev = kzalloc(sizeof(struct amdgpu_device), GFP_KERNEL); 97 if (adev == NULL) { 98 return -ENOMEM; 99 } 100 dev->dev_private = (void *)adev; 101 102 if ((amdgpu_runtime_pm != 0) && 103 amdgpu_has_atpx() && 104 ((flags & AMD_IS_APU) == 0)) 105 flags |= AMD_IS_PX; 106 107 /* amdgpu_device_init should report only fatal error 108 * like memory allocation failure or iomapping failure, 109 * or memory manager initialization failure, it must 110 * properly initialize the GPU MC controller and permit 111 * VRAM allocation 112 */ 113 r = amdgpu_device_init(adev, dev, dev->pdev, flags); 114 if (r) { 115 dev_err(pci_dev_dev(dev->pdev), "Fatal error during GPU init\n"); 116 goto out; 117 } 118 119 /* Call ACPI methods: require modeset init 120 * but failure is not fatal 121 */ 122 if (!r) { 123 acpi_status = amdgpu_acpi_init(adev); 124 if (acpi_status) 125 dev_dbg(pci_dev_dev(dev->pdev), 126 "Error during ACPI methods call\n"); 127 } 128 129 amdgpu_amdkfd_load_interface(adev); 130 amdgpu_amdkfd_device_probe(adev); 131 amdgpu_amdkfd_device_init(adev); 132 133 if (amdgpu_device_is_px(dev)) { 134 pm_runtime_use_autosuspend(dev->dev); 135 pm_runtime_set_autosuspend_delay(dev->dev, 5000); 136 pm_runtime_set_active(dev->dev); 137 pm_runtime_allow(dev->dev); 138 pm_runtime_mark_last_busy(dev->dev); 139 pm_runtime_put_autosuspend(dev->dev); 140 } 141 142 out: 143 if (r) 144 amdgpu_driver_unload_kms(dev); 145 146 147 return r; 148 } 149 150 /* 151 * Userspace get information ioctl 152 */ 153 /** 154 * amdgpu_info_ioctl - answer a device specific request. 155 * 156 * @adev: amdgpu device pointer 157 * @data: request object 158 * @filp: drm filp 159 * 160 * This function is used to pass device specific parameters to the userspace 161 * drivers. Examples include: pci device id, pipeline parms, tiling params, 162 * etc. (all asics). 163 * Returns 0 on success, -EINVAL on failure. 164 */ 165 static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) 166 { 167 struct amdgpu_device *adev = dev->dev_private; 168 struct drm_amdgpu_info *info = data; 169 struct amdgpu_mode_info *minfo = &adev->mode_info; 170 void __user *out = (void __user *)(long)info->return_pointer; 171 uint32_t size = info->return_size; 172 struct drm_crtc *crtc; 173 uint32_t ui32 = 0; 174 uint64_t ui64 = 0; 175 int i, found; 176 177 if (!info->return_size || !info->return_pointer) 178 return -EINVAL; 179 180 switch (info->query) { 181 case AMDGPU_INFO_ACCEL_WORKING: 182 ui32 = adev->accel_working; 183 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 184 case AMDGPU_INFO_CRTC_FROM_ID: 185 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) { 186 crtc = (struct drm_crtc *)minfo->crtcs[i]; 187 if (crtc && crtc->base.id == info->mode_crtc.id) { 188 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 189 ui32 = amdgpu_crtc->crtc_id; 190 found = 1; 191 break; 192 } 193 } 194 if (!found) { 195 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id); 196 return -EINVAL; 197 } 198 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; 199 case AMDGPU_INFO_HW_IP_INFO: { 200 struct drm_amdgpu_info_hw_ip ip = {}; 201 enum amd_ip_block_type type; 202 uint32_t ring_mask = 0; 203 uint32_t ib_start_alignment = 0; 204 uint32_t ib_size_alignment = 0; 205 206 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 207 return -EINVAL; 208 209 switch (info->query_hw_ip.type) { 210 case AMDGPU_HW_IP_GFX: 211 type = AMD_IP_BLOCK_TYPE_GFX; 212 for (i = 0; i < adev->gfx.num_gfx_rings; i++) 213 ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i); 214 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 215 ib_size_alignment = 8; 216 break; 217 case AMDGPU_HW_IP_COMPUTE: 218 type = AMD_IP_BLOCK_TYPE_GFX; 219 for (i = 0; i < adev->gfx.num_compute_rings; i++) 220 ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i); 221 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 222 ib_size_alignment = 8; 223 break; 224 case AMDGPU_HW_IP_DMA: 225 type = AMD_IP_BLOCK_TYPE_SDMA; 226 for (i = 0; i < adev->sdma.num_instances; i++) 227 ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i); 228 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 229 ib_size_alignment = 1; 230 break; 231 case AMDGPU_HW_IP_UVD: 232 type = AMD_IP_BLOCK_TYPE_UVD; 233 ring_mask = adev->uvd.ring.ready ? 1 : 0; 234 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 235 ib_size_alignment = 16; 236 break; 237 case AMDGPU_HW_IP_VCE: 238 type = AMD_IP_BLOCK_TYPE_VCE; 239 for (i = 0; i < AMDGPU_MAX_VCE_RINGS; i++) 240 ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i); 241 ib_start_alignment = AMDGPU_GPU_PAGE_SIZE; 242 ib_size_alignment = 8; 243 break; 244 default: 245 return -EINVAL; 246 } 247 248 for (i = 0; i < adev->num_ip_blocks; i++) { 249 if (adev->ip_blocks[i].type == type && 250 adev->ip_block_status[i].valid) { 251 ip.hw_ip_version_major = adev->ip_blocks[i].major; 252 ip.hw_ip_version_minor = adev->ip_blocks[i].minor; 253 ip.capabilities_flags = 0; 254 ip.available_rings = ring_mask; 255 ip.ib_start_alignment = ib_start_alignment; 256 ip.ib_size_alignment = ib_size_alignment; 257 break; 258 } 259 } 260 return copy_to_user(out, &ip, 261 min((size_t)size, sizeof(ip))) ? -EFAULT : 0; 262 } 263 case AMDGPU_INFO_HW_IP_COUNT: { 264 enum amd_ip_block_type type; 265 uint32_t count = 0; 266 267 switch (info->query_hw_ip.type) { 268 case AMDGPU_HW_IP_GFX: 269 type = AMD_IP_BLOCK_TYPE_GFX; 270 break; 271 case AMDGPU_HW_IP_COMPUTE: 272 type = AMD_IP_BLOCK_TYPE_GFX; 273 break; 274 case AMDGPU_HW_IP_DMA: 275 type = AMD_IP_BLOCK_TYPE_SDMA; 276 break; 277 case AMDGPU_HW_IP_UVD: 278 type = AMD_IP_BLOCK_TYPE_UVD; 279 break; 280 case AMDGPU_HW_IP_VCE: 281 type = AMD_IP_BLOCK_TYPE_VCE; 282 break; 283 default: 284 return -EINVAL; 285 } 286 287 for (i = 0; i < adev->num_ip_blocks; i++) 288 if (adev->ip_blocks[i].type == type && 289 adev->ip_block_status[i].valid && 290 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT) 291 count++; 292 293 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0; 294 } 295 case AMDGPU_INFO_TIMESTAMP: 296 ui64 = amdgpu_asic_get_gpu_clock_counter(adev); 297 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 298 case AMDGPU_INFO_FW_VERSION: { 299 struct drm_amdgpu_info_firmware fw_info; 300 301 /* We only support one instance of each IP block right now. */ 302 if (info->query_fw.ip_instance != 0) 303 return -EINVAL; 304 305 switch (info->query_fw.fw_type) { 306 case AMDGPU_INFO_FW_VCE: 307 fw_info.ver = adev->vce.fw_version; 308 fw_info.feature = adev->vce.fb_version; 309 break; 310 case AMDGPU_INFO_FW_UVD: 311 fw_info.ver = adev->uvd.fw_version; 312 fw_info.feature = 0; 313 break; 314 case AMDGPU_INFO_FW_GMC: 315 fw_info.ver = adev->mc.fw_version; 316 fw_info.feature = 0; 317 break; 318 case AMDGPU_INFO_FW_GFX_ME: 319 fw_info.ver = adev->gfx.me_fw_version; 320 fw_info.feature = adev->gfx.me_feature_version; 321 break; 322 case AMDGPU_INFO_FW_GFX_PFP: 323 fw_info.ver = adev->gfx.pfp_fw_version; 324 fw_info.feature = adev->gfx.pfp_feature_version; 325 break; 326 case AMDGPU_INFO_FW_GFX_CE: 327 fw_info.ver = adev->gfx.ce_fw_version; 328 fw_info.feature = adev->gfx.ce_feature_version; 329 break; 330 case AMDGPU_INFO_FW_GFX_RLC: 331 fw_info.ver = adev->gfx.rlc_fw_version; 332 fw_info.feature = adev->gfx.rlc_feature_version; 333 break; 334 case AMDGPU_INFO_FW_GFX_MEC: 335 if (info->query_fw.index == 0) { 336 fw_info.ver = adev->gfx.mec_fw_version; 337 fw_info.feature = adev->gfx.mec_feature_version; 338 } else if (info->query_fw.index == 1) { 339 fw_info.ver = adev->gfx.mec2_fw_version; 340 fw_info.feature = adev->gfx.mec2_feature_version; 341 } else 342 return -EINVAL; 343 break; 344 case AMDGPU_INFO_FW_SMC: 345 fw_info.ver = adev->pm.fw_version; 346 fw_info.feature = 0; 347 break; 348 case AMDGPU_INFO_FW_SDMA: 349 if (info->query_fw.index >= adev->sdma.num_instances) 350 return -EINVAL; 351 fw_info.ver = adev->sdma.instance[info->query_fw.index].fw_version; 352 fw_info.feature = adev->sdma.instance[info->query_fw.index].feature_version; 353 break; 354 default: 355 return -EINVAL; 356 } 357 return copy_to_user(out, &fw_info, 358 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0; 359 } 360 case AMDGPU_INFO_NUM_BYTES_MOVED: 361 ui64 = atomic64_read(&adev->num_bytes_moved); 362 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 363 case AMDGPU_INFO_VRAM_USAGE: 364 ui64 = atomic64_read(&adev->vram_usage); 365 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 366 case AMDGPU_INFO_VIS_VRAM_USAGE: 367 ui64 = atomic64_read(&adev->vram_vis_usage); 368 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 369 case AMDGPU_INFO_GTT_USAGE: 370 ui64 = atomic64_read(&adev->gtt_usage); 371 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0; 372 case AMDGPU_INFO_GDS_CONFIG: { 373 struct drm_amdgpu_info_gds gds_info; 374 375 memset(&gds_info, 0, sizeof(gds_info)); 376 gds_info.gds_gfx_partition_size = adev->gds.mem.gfx_partition_size >> AMDGPU_GDS_SHIFT; 377 gds_info.compute_partition_size = adev->gds.mem.cs_partition_size >> AMDGPU_GDS_SHIFT; 378 gds_info.gds_total_size = adev->gds.mem.total_size >> AMDGPU_GDS_SHIFT; 379 gds_info.gws_per_gfx_partition = adev->gds.gws.gfx_partition_size >> AMDGPU_GWS_SHIFT; 380 gds_info.gws_per_compute_partition = adev->gds.gws.cs_partition_size >> AMDGPU_GWS_SHIFT; 381 gds_info.oa_per_gfx_partition = adev->gds.oa.gfx_partition_size >> AMDGPU_OA_SHIFT; 382 gds_info.oa_per_compute_partition = adev->gds.oa.cs_partition_size >> AMDGPU_OA_SHIFT; 383 return copy_to_user(out, &gds_info, 384 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0; 385 } 386 case AMDGPU_INFO_VRAM_GTT: { 387 struct drm_amdgpu_info_vram_gtt vram_gtt; 388 389 vram_gtt.vram_size = adev->mc.real_vram_size; 390 vram_gtt.vram_cpu_accessible_size = adev->mc.visible_vram_size; 391 vram_gtt.vram_cpu_accessible_size -= adev->vram_pin_size; 392 vram_gtt.gtt_size = adev->mc.gtt_size; 393 vram_gtt.gtt_size -= adev->gart_pin_size; 394 return copy_to_user(out, &vram_gtt, 395 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0; 396 } 397 case AMDGPU_INFO_READ_MMR_REG: { 398 unsigned n, alloc_size; 399 uint32_t *regs; 400 unsigned se_num = (info->read_mmr_reg.instance >> 401 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) & 402 AMDGPU_INFO_MMR_SE_INDEX_MASK; 403 unsigned sh_num = (info->read_mmr_reg.instance >> 404 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) & 405 AMDGPU_INFO_MMR_SH_INDEX_MASK; 406 407 /* set full masks if the userspace set all bits 408 * in the bitfields */ 409 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) 410 se_num = 0xffffffff; 411 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) 412 sh_num = 0xffffffff; 413 414 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL); 415 if (!regs) 416 return -ENOMEM; 417 alloc_size = info->read_mmr_reg.count * sizeof(*regs); 418 419 for (i = 0; i < info->read_mmr_reg.count; i++) 420 if (amdgpu_asic_read_register(adev, se_num, sh_num, 421 info->read_mmr_reg.dword_offset + i, 422 ®s[i])) { 423 DRM_DEBUG_KMS("unallowed offset %#x\n", 424 info->read_mmr_reg.dword_offset + i); 425 kfree(regs); 426 return -EFAULT; 427 } 428 n = copy_to_user(out, regs, min(size, alloc_size)); 429 kfree(regs); 430 return n ? -EFAULT : 0; 431 } 432 case AMDGPU_INFO_DEV_INFO: { 433 struct drm_amdgpu_info_device dev_info = {}; 434 struct amdgpu_cu_info cu_info; 435 436 dev_info.device_id = dev->pdev->device; 437 dev_info.chip_rev = adev->rev_id; 438 dev_info.external_rev = adev->external_rev_id; 439 dev_info.pci_rev = dev->pdev->revision; 440 dev_info.family = adev->family; 441 dev_info.num_shader_engines = adev->gfx.config.max_shader_engines; 442 dev_info.num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; 443 /* return all clocks in KHz */ 444 dev_info.gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10; 445 if (adev->pm.dpm_enabled) { 446 dev_info.max_engine_clock = 447 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk * 10; 448 dev_info.max_memory_clock = 449 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk * 10; 450 } else { 451 dev_info.max_engine_clock = adev->pm.default_sclk * 10; 452 dev_info.max_memory_clock = adev->pm.default_mclk * 10; 453 } 454 dev_info.enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask; 455 dev_info.num_rb_pipes = adev->gfx.config.max_backends_per_se * 456 adev->gfx.config.max_shader_engines; 457 dev_info.num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts; 458 dev_info._pad = 0; 459 dev_info.ids_flags = 0; 460 if (adev->flags & AMD_IS_APU) 461 dev_info.ids_flags |= AMDGPU_IDS_FLAGS_FUSION; 462 dev_info.virtual_address_offset = AMDGPU_VA_RESERVED_SIZE; 463 dev_info.virtual_address_max = (uint64_t)adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; 464 dev_info.virtual_address_alignment = max((int)PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE); 465 dev_info.pte_fragment_size = (1 << AMDGPU_LOG2_PAGES_PER_FRAG) * 466 AMDGPU_GPU_PAGE_SIZE; 467 dev_info.gart_page_size = AMDGPU_GPU_PAGE_SIZE; 468 469 amdgpu_asic_get_cu_info(adev, &cu_info); 470 dev_info.cu_active_number = cu_info.number; 471 dev_info.cu_ao_mask = cu_info.ao_cu_mask; 472 dev_info.ce_ram_size = adev->gfx.ce_ram_size; 473 memcpy(&dev_info.cu_bitmap[0], &cu_info.bitmap[0], sizeof(cu_info.bitmap)); 474 dev_info.vram_type = adev->mc.vram_type; 475 dev_info.vram_bit_width = adev->mc.vram_width; 476 dev_info.vce_harvest_config = adev->vce.harvest_config; 477 478 return copy_to_user(out, &dev_info, 479 min((size_t)size, sizeof(dev_info))) ? -EFAULT : 0; 480 } 481 default: 482 DRM_DEBUG_KMS("Invalid request %d\n", info->query); 483 return -EINVAL; 484 } 485 return 0; 486 } 487 488 489 /* 490 * Outdated mess for old drm with Xorg being in charge (void function now). 491 */ 492 /** 493 * amdgpu_driver_lastclose_kms - drm callback for last close 494 * 495 * @dev: drm dev pointer 496 * 497 * Switch vga_switcheroo state after last close (all asics). 498 */ 499 void amdgpu_driver_lastclose_kms(struct drm_device *dev) 500 { 501 struct amdgpu_device *adev = dev->dev_private; 502 503 amdgpu_fbdev_restore_mode(adev); 504 #ifndef __NetBSD__ /* XXX radeon vga */ 505 vga_switcheroo_process_delayed_switch(); 506 #endif 507 } 508 509 /** 510 * amdgpu_driver_open_kms - drm callback for open 511 * 512 * @dev: drm dev pointer 513 * @file_priv: drm file 514 * 515 * On device open, init vm on cayman+ (all asics). 516 * Returns 0 on success, error on failure. 517 */ 518 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) 519 { 520 struct amdgpu_device *adev = dev->dev_private; 521 struct amdgpu_fpriv *fpriv; 522 int r; 523 524 file_priv->driver_priv = NULL; 525 526 r = pm_runtime_get_sync(dev->dev); 527 if (r < 0) 528 return r; 529 530 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 531 if (unlikely(!fpriv)) 532 return -ENOMEM; 533 534 r = amdgpu_vm_init(adev, &fpriv->vm); 535 if (r) 536 goto error_free; 537 538 #ifdef __NetBSD__ 539 linux_mutex_init(&fpriv->bo_list_lock); 540 #else 541 mutex_init(&fpriv->bo_list_lock); 542 #endif 543 idr_init(&fpriv->bo_list_handles); 544 545 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr); 546 547 file_priv->driver_priv = fpriv; 548 549 pm_runtime_mark_last_busy(dev->dev); 550 pm_runtime_put_autosuspend(dev->dev); 551 return 0; 552 553 error_free: 554 kfree(fpriv); 555 556 return r; 557 } 558 559 /** 560 * amdgpu_driver_postclose_kms - drm callback for post close 561 * 562 * @dev: drm dev pointer 563 * @file_priv: drm file 564 * 565 * On device post close, tear down vm on cayman+ (all asics). 566 */ 567 void amdgpu_driver_postclose_kms(struct drm_device *dev, 568 struct drm_file *file_priv) 569 { 570 struct amdgpu_device *adev = dev->dev_private; 571 struct amdgpu_fpriv *fpriv = file_priv->driver_priv; 572 struct amdgpu_bo_list *list; 573 int handle; 574 575 if (!fpriv) 576 return; 577 578 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr); 579 580 amdgpu_vm_fini(adev, &fpriv->vm); 581 582 idr_for_each_entry(&fpriv->bo_list_handles, list, handle) 583 amdgpu_bo_list_free(list); 584 585 idr_destroy(&fpriv->bo_list_handles); 586 #ifdef __NetBSD__ 587 linux_mutex_destroy(&fpriv->bo_list_lock); 588 #else 589 mutex_destroy(&fpriv->bo_list_lock); 590 #endif 591 592 kfree(fpriv); 593 file_priv->driver_priv = NULL; 594 } 595 596 /** 597 * amdgpu_driver_preclose_kms - drm callback for pre close 598 * 599 * @dev: drm dev pointer 600 * @file_priv: drm file 601 * 602 * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx 603 * (all asics). 604 */ 605 void amdgpu_driver_preclose_kms(struct drm_device *dev, 606 struct drm_file *file_priv) 607 { 608 struct amdgpu_device *adev = dev->dev_private; 609 610 amdgpu_uvd_free_handles(adev, file_priv); 611 amdgpu_vce_free_handles(adev, file_priv); 612 } 613 614 /* 615 * VBlank related functions. 616 */ 617 /** 618 * amdgpu_get_vblank_counter_kms - get frame count 619 * 620 * @dev: drm dev pointer 621 * @pipe: crtc to get the frame count from 622 * 623 * Gets the frame count on the requested crtc (all asics). 624 * Returns frame count on success, -EINVAL on failure. 625 */ 626 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe) 627 { 628 struct amdgpu_device *adev = dev->dev_private; 629 int vpos, hpos, stat; 630 u32 count; 631 632 if (pipe >= adev->mode_info.num_crtc) { 633 DRM_ERROR("Invalid crtc %u\n", pipe); 634 return -EINVAL; 635 } 636 637 /* The hw increments its frame counter at start of vsync, not at start 638 * of vblank, as is required by DRM core vblank counter handling. 639 * Cook the hw count here to make it appear to the caller as if it 640 * incremented at start of vblank. We measure distance to start of 641 * vblank in vpos. vpos therefore will be >= 0 between start of vblank 642 * and start of vsync, so vpos >= 0 means to bump the hw frame counter 643 * result by 1 to give the proper appearance to caller. 644 */ 645 if (adev->mode_info.crtcs[pipe]) { 646 /* Repeat readout if needed to provide stable result if 647 * we cross start of vsync during the queries. 648 */ 649 do { 650 count = amdgpu_display_vblank_get_counter(adev, pipe); 651 /* Ask amdgpu_get_crtc_scanoutpos to return vpos as 652 * distance to start of vblank, instead of regular 653 * vertical scanout pos. 654 */ 655 stat = amdgpu_get_crtc_scanoutpos( 656 dev, pipe, GET_DISTANCE_TO_VBLANKSTART, 657 &vpos, &hpos, NULL, NULL, 658 &adev->mode_info.crtcs[pipe]->base.hwmode); 659 } while (count != amdgpu_display_vblank_get_counter(adev, pipe)); 660 661 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != 662 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) { 663 DRM_DEBUG_VBL("Query failed! stat %d\n", stat); 664 } else { 665 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n", 666 pipe, vpos); 667 668 /* Bump counter if we are at >= leading edge of vblank, 669 * but before vsync where vpos would turn negative and 670 * the hw counter really increments. 671 */ 672 if (vpos >= 0) 673 count++; 674 } 675 } else { 676 /* Fallback to use value as is. */ 677 count = amdgpu_display_vblank_get_counter(adev, pipe); 678 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n"); 679 } 680 681 return count; 682 } 683 684 /** 685 * amdgpu_enable_vblank_kms - enable vblank interrupt 686 * 687 * @dev: drm dev pointer 688 * @pipe: crtc to enable vblank interrupt for 689 * 690 * Enable the interrupt on the requested crtc (all asics). 691 * Returns 0 on success, -EINVAL on failure. 692 */ 693 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe) 694 { 695 struct amdgpu_device *adev = dev->dev_private; 696 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 697 698 return amdgpu_irq_get(adev, &adev->crtc_irq, idx); 699 } 700 701 /** 702 * amdgpu_disable_vblank_kms - disable vblank interrupt 703 * 704 * @dev: drm dev pointer 705 * @pipe: crtc to disable vblank interrupt for 706 * 707 * Disable the interrupt on the requested crtc (all asics). 708 */ 709 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe) 710 { 711 struct amdgpu_device *adev = dev->dev_private; 712 int idx = amdgpu_crtc_idx_to_irq_type(adev, pipe); 713 714 amdgpu_irq_put(adev, &adev->crtc_irq, idx); 715 } 716 717 /** 718 * amdgpu_get_vblank_timestamp_kms - get vblank timestamp 719 * 720 * @dev: drm dev pointer 721 * @crtc: crtc to get the timestamp for 722 * @max_error: max error 723 * @vblank_time: time value 724 * @flags: flags passed to the driver 725 * 726 * Gets the timestamp on the requested crtc based on the 727 * scanout position. (all asics). 728 * Returns postive status flags on success, negative error on failure. 729 */ 730 int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, 731 int *max_error, 732 struct timeval *vblank_time, 733 unsigned flags) 734 { 735 struct drm_crtc *crtc; 736 struct amdgpu_device *adev = dev->dev_private; 737 738 if (pipe >= dev->num_crtcs) { 739 DRM_ERROR("Invalid crtc %u\n", pipe); 740 return -EINVAL; 741 } 742 743 /* Get associated drm_crtc: */ 744 crtc = &adev->mode_info.crtcs[pipe]->base; 745 746 /* Helper routine in DRM core does all the work: */ 747 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, 748 vblank_time, flags, 749 &crtc->hwmode); 750 } 751 752 const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { 753 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 754 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 755 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 756 /* KMS */ 757 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 758 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 759 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 760 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 761 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 762 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 763 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 764 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 765 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), 766 }; 767 int amdgpu_max_kms_ioctl = ARRAY_SIZE(amdgpu_ioctls_kms); 768
Indexes created Mon Sep 29 03:10:08 GMT 2025