amdgpu_mode.h revision 1.1.1.1
1 /* $NetBSD: amdgpu_mode.h,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 5 * VA Linux Systems Inc., Fremont, California. 6 * Copyright 2008 Red Hat Inc. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Original Authors: 27 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane 28 * 29 * Kernel port Author: Dave Airlie 30 */ 31 32 #ifndef AMDGPU_MODE_H 33 #define AMDGPU_MODE_H 34 35 #include <drm/drm_crtc.h> 36 #include <drm/drm_edid.h> 37 #include <drm/drm_dp_helper.h> 38 #include <drm/drm_fixed.h> 39 #include <drm/drm_crtc_helper.h> 40 #include <drm/drm_plane_helper.h> 41 #include <linux/i2c.h> 42 #include <linux/i2c-algo-bit.h> 43 44 struct amdgpu_bo; 45 struct amdgpu_device; 46 struct amdgpu_encoder; 47 struct amdgpu_router; 48 struct amdgpu_hpd; 49 50 #define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base) 51 #define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base) 52 #define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base) 53 #define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base) 54 55 #define AMDGPU_MAX_HPD_PINS 6 56 #define AMDGPU_MAX_CRTCS 6 57 #define AMDGPU_MAX_AFMT_BLOCKS 9 58 59 enum amdgpu_rmx_type { 60 RMX_OFF, 61 RMX_FULL, 62 RMX_CENTER, 63 RMX_ASPECT 64 }; 65 66 enum amdgpu_underscan_type { 67 UNDERSCAN_OFF, 68 UNDERSCAN_ON, 69 UNDERSCAN_AUTO, 70 }; 71 72 #define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50 73 #define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10 74 75 enum amdgpu_hpd_id { 76 AMDGPU_HPD_1 = 0, 77 AMDGPU_HPD_2, 78 AMDGPU_HPD_3, 79 AMDGPU_HPD_4, 80 AMDGPU_HPD_5, 81 AMDGPU_HPD_6, 82 AMDGPU_HPD_LAST, 83 AMDGPU_HPD_NONE = 0xff, 84 }; 85 86 enum amdgpu_crtc_irq { 87 AMDGPU_CRTC_IRQ_VBLANK1 = 0, 88 AMDGPU_CRTC_IRQ_VBLANK2, 89 AMDGPU_CRTC_IRQ_VBLANK3, 90 AMDGPU_CRTC_IRQ_VBLANK4, 91 AMDGPU_CRTC_IRQ_VBLANK5, 92 AMDGPU_CRTC_IRQ_VBLANK6, 93 AMDGPU_CRTC_IRQ_VLINE1, 94 AMDGPU_CRTC_IRQ_VLINE2, 95 AMDGPU_CRTC_IRQ_VLINE3, 96 AMDGPU_CRTC_IRQ_VLINE4, 97 AMDGPU_CRTC_IRQ_VLINE5, 98 AMDGPU_CRTC_IRQ_VLINE6, 99 AMDGPU_CRTC_IRQ_LAST, 100 AMDGPU_CRTC_IRQ_NONE = 0xff 101 }; 102 103 enum amdgpu_pageflip_irq { 104 AMDGPU_PAGEFLIP_IRQ_D1 = 0, 105 AMDGPU_PAGEFLIP_IRQ_D2, 106 AMDGPU_PAGEFLIP_IRQ_D3, 107 AMDGPU_PAGEFLIP_IRQ_D4, 108 AMDGPU_PAGEFLIP_IRQ_D5, 109 AMDGPU_PAGEFLIP_IRQ_D6, 110 AMDGPU_PAGEFLIP_IRQ_LAST, 111 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff 112 }; 113 114 enum amdgpu_flip_status { 115 AMDGPU_FLIP_NONE, 116 AMDGPU_FLIP_PENDING, 117 AMDGPU_FLIP_SUBMITTED 118 }; 119 120 #define AMDGPU_MAX_I2C_BUS 16 121 122 /* amdgpu gpio-based i2c 123 * 1. "mask" reg and bits 124 * grabs the gpio pins for software use 125 * 0=not held 1=held 126 * 2. "a" reg and bits 127 * output pin value 128 * 0=low 1=high 129 * 3. "en" reg and bits 130 * sets the pin direction 131 * 0=input 1=output 132 * 4. "y" reg and bits 133 * input pin value 134 * 0=low 1=high 135 */ 136 struct amdgpu_i2c_bus_rec { 137 bool valid; 138 /* id used by atom */ 139 uint8_t i2c_id; 140 /* id used by atom */ 141 enum amdgpu_hpd_id hpd; 142 /* can be used with hw i2c engine */ 143 bool hw_capable; 144 /* uses multi-media i2c engine */ 145 bool mm_i2c; 146 /* regs and bits */ 147 uint32_t mask_clk_reg; 148 uint32_t mask_data_reg; 149 uint32_t a_clk_reg; 150 uint32_t a_data_reg; 151 uint32_t en_clk_reg; 152 uint32_t en_data_reg; 153 uint32_t y_clk_reg; 154 uint32_t y_data_reg; 155 uint32_t mask_clk_mask; 156 uint32_t mask_data_mask; 157 uint32_t a_clk_mask; 158 uint32_t a_data_mask; 159 uint32_t en_clk_mask; 160 uint32_t en_data_mask; 161 uint32_t y_clk_mask; 162 uint32_t y_data_mask; 163 }; 164 165 #define AMDGPU_MAX_BIOS_CONNECTOR 16 166 167 /* pll flags */ 168 #define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0) 169 #define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1) 170 #define AMDGPU_PLL_USE_REF_DIV (1 << 2) 171 #define AMDGPU_PLL_LEGACY (1 << 3) 172 #define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4) 173 #define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5) 174 #define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6) 175 #define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7) 176 #define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8) 177 #define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9) 178 #define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10) 179 #define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11) 180 #define AMDGPU_PLL_USE_POST_DIV (1 << 12) 181 #define AMDGPU_PLL_IS_LCD (1 << 13) 182 #define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14) 183 184 struct amdgpu_pll { 185 /* reference frequency */ 186 uint32_t reference_freq; 187 188 /* fixed dividers */ 189 uint32_t reference_div; 190 uint32_t post_div; 191 192 /* pll in/out limits */ 193 uint32_t pll_in_min; 194 uint32_t pll_in_max; 195 uint32_t pll_out_min; 196 uint32_t pll_out_max; 197 uint32_t lcd_pll_out_min; 198 uint32_t lcd_pll_out_max; 199 uint32_t best_vco; 200 201 /* divider limits */ 202 uint32_t min_ref_div; 203 uint32_t max_ref_div; 204 uint32_t min_post_div; 205 uint32_t max_post_div; 206 uint32_t min_feedback_div; 207 uint32_t max_feedback_div; 208 uint32_t min_frac_feedback_div; 209 uint32_t max_frac_feedback_div; 210 211 /* flags for the current clock */ 212 uint32_t flags; 213 214 /* pll id */ 215 uint32_t id; 216 }; 217 218 struct amdgpu_i2c_chan { 219 struct i2c_adapter adapter; 220 struct drm_device *dev; 221 struct i2c_algo_bit_data bit; 222 struct amdgpu_i2c_bus_rec rec; 223 struct drm_dp_aux aux; 224 bool has_aux; 225 struct mutex mutex; 226 }; 227 228 struct amdgpu_fbdev; 229 230 struct amdgpu_afmt { 231 bool enabled; 232 int offset; 233 bool last_buffer_filled_status; 234 int id; 235 struct amdgpu_audio_pin *pin; 236 }; 237 238 /* 239 * Audio 240 */ 241 struct amdgpu_audio_pin { 242 int channels; 243 int rate; 244 int bits_per_sample; 245 u8 status_bits; 246 u8 category_code; 247 u32 offset; 248 bool connected; 249 u32 id; 250 }; 251 252 struct amdgpu_audio { 253 bool enabled; 254 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS]; 255 int num_pins; 256 }; 257 258 struct amdgpu_mode_mc_save { 259 u32 vga_render_control; 260 u32 vga_hdp_control; 261 bool crtc_enabled[AMDGPU_MAX_CRTCS]; 262 }; 263 264 struct amdgpu_display_funcs { 265 /* vga render */ 266 void (*set_vga_render_state)(struct amdgpu_device *adev, bool render); 267 /* display watermarks */ 268 void (*bandwidth_update)(struct amdgpu_device *adev); 269 /* get frame count */ 270 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc); 271 /* wait for vblank */ 272 void (*vblank_wait)(struct amdgpu_device *adev, int crtc); 273 /* is dce hung */ 274 bool (*is_display_hung)(struct amdgpu_device *adev); 275 /* set backlight level */ 276 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder, 277 u8 level); 278 /* get backlight level */ 279 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder); 280 /* hotplug detect */ 281 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd); 282 void (*hpd_set_polarity)(struct amdgpu_device *adev, 283 enum amdgpu_hpd_id hpd); 284 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev); 285 /* pageflipping */ 286 void (*page_flip)(struct amdgpu_device *adev, 287 int crtc_id, u64 crtc_base); 288 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc, 289 u32 *vbl, u32 *position); 290 /* display topology setup */ 291 void (*add_encoder)(struct amdgpu_device *adev, 292 uint32_t encoder_enum, 293 uint32_t supported_device, 294 u16 caps); 295 void (*add_connector)(struct amdgpu_device *adev, 296 uint32_t connector_id, 297 uint32_t supported_device, 298 int connector_type, 299 struct amdgpu_i2c_bus_rec *i2c_bus, 300 uint16_t connector_object_id, 301 struct amdgpu_hpd *hpd, 302 struct amdgpu_router *router); 303 void (*stop_mc_access)(struct amdgpu_device *adev, 304 struct amdgpu_mode_mc_save *save); 305 void (*resume_mc_access)(struct amdgpu_device *adev, 306 struct amdgpu_mode_mc_save *save); 307 }; 308 309 struct amdgpu_mode_info { 310 struct atom_context *atom_context; 311 struct card_info *atom_card_info; 312 bool mode_config_initialized; 313 struct amdgpu_crtc *crtcs[AMDGPU_MAX_CRTCS]; 314 struct amdgpu_afmt *afmt[AMDGPU_MAX_AFMT_BLOCKS]; 315 /* DVI-I properties */ 316 struct drm_property *coherent_mode_property; 317 /* DAC enable load detect */ 318 struct drm_property *load_detect_property; 319 /* underscan */ 320 struct drm_property *underscan_property; 321 struct drm_property *underscan_hborder_property; 322 struct drm_property *underscan_vborder_property; 323 /* audio */ 324 struct drm_property *audio_property; 325 /* FMT dithering */ 326 struct drm_property *dither_property; 327 /* hardcoded DFP edid from BIOS */ 328 struct edid *bios_hardcoded_edid; 329 int bios_hardcoded_edid_size; 330 331 /* pointer to fbdev info structure */ 332 struct amdgpu_fbdev *rfbdev; 333 /* firmware flags */ 334 u16 firmware_flags; 335 /* pointer to backlight encoder */ 336 struct amdgpu_encoder *bl_encoder; 337 struct amdgpu_audio audio; /* audio stuff */ 338 int num_crtc; /* number of crtcs */ 339 int num_hpd; /* number of hpd pins */ 340 int num_dig; /* number of dig blocks */ 341 int disp_priority; 342 const struct amdgpu_display_funcs *funcs; 343 }; 344 345 #define AMDGPU_MAX_BL_LEVEL 0xFF 346 347 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 348 349 struct amdgpu_backlight_privdata { 350 struct amdgpu_encoder *encoder; 351 uint8_t negative; 352 }; 353 354 #endif 355 356 struct amdgpu_atom_ss { 357 uint16_t percentage; 358 uint16_t percentage_divider; 359 uint8_t type; 360 uint16_t step; 361 uint8_t delay; 362 uint8_t range; 363 uint8_t refdiv; 364 /* asic_ss */ 365 uint16_t rate; 366 uint16_t amount; 367 }; 368 369 struct amdgpu_crtc { 370 struct drm_crtc base; 371 int crtc_id; 372 u16 lut_r[256], lut_g[256], lut_b[256]; 373 bool enabled; 374 bool can_tile; 375 uint32_t crtc_offset; 376 struct drm_gem_object *cursor_bo; 377 uint64_t cursor_addr; 378 int cursor_x; 379 int cursor_y; 380 int cursor_hot_x; 381 int cursor_hot_y; 382 int cursor_width; 383 int cursor_height; 384 int max_cursor_width; 385 int max_cursor_height; 386 enum amdgpu_rmx_type rmx_type; 387 u8 h_border; 388 u8 v_border; 389 fixed20_12 vsc; 390 fixed20_12 hsc; 391 struct drm_display_mode native_mode; 392 u32 pll_id; 393 /* page flipping */ 394 struct workqueue_struct *pflip_queue; 395 struct amdgpu_flip_work *pflip_works; 396 enum amdgpu_flip_status pflip_status; 397 int deferred_flip_completion; 398 /* pll sharing */ 399 struct amdgpu_atom_ss ss; 400 bool ss_enabled; 401 u32 adjusted_clock; 402 int bpc; 403 u32 pll_reference_div; 404 u32 pll_post_div; 405 u32 pll_flags; 406 struct drm_encoder *encoder; 407 struct drm_connector *connector; 408 /* for dpm */ 409 u32 line_time; 410 u32 wm_low; 411 u32 wm_high; 412 u32 lb_vblank_lead_lines; 413 struct drm_display_mode hw_mode; 414 }; 415 416 struct amdgpu_encoder_atom_dig { 417 bool linkb; 418 /* atom dig */ 419 bool coherent_mode; 420 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */ 421 /* atom lvds/edp */ 422 uint32_t lcd_misc; 423 uint16_t panel_pwr_delay; 424 uint32_t lcd_ss_id; 425 /* panel mode */ 426 struct drm_display_mode native_mode; 427 struct backlight_device *bl_dev; 428 int dpms_mode; 429 uint8_t backlight_level; 430 int panel_mode; 431 struct amdgpu_afmt *afmt; 432 }; 433 434 struct amdgpu_encoder { 435 struct drm_encoder base; 436 uint32_t encoder_enum; 437 uint32_t encoder_id; 438 uint32_t devices; 439 uint32_t active_device; 440 uint32_t flags; 441 uint32_t pixel_clock; 442 enum amdgpu_rmx_type rmx_type; 443 enum amdgpu_underscan_type underscan_type; 444 uint32_t underscan_hborder; 445 uint32_t underscan_vborder; 446 struct drm_display_mode native_mode; 447 void *enc_priv; 448 int audio_polling_active; 449 bool is_ext_encoder; 450 u16 caps; 451 }; 452 453 struct amdgpu_connector_atom_dig { 454 /* displayport */ 455 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 456 u8 dp_sink_type; 457 int dp_clock; 458 int dp_lane_count; 459 bool edp_on; 460 }; 461 462 struct amdgpu_gpio_rec { 463 bool valid; 464 u8 id; 465 u32 reg; 466 u32 mask; 467 u32 shift; 468 }; 469 470 struct amdgpu_hpd { 471 enum amdgpu_hpd_id hpd; 472 u8 plugged_state; 473 struct amdgpu_gpio_rec gpio; 474 }; 475 476 struct amdgpu_router { 477 u32 router_id; 478 struct amdgpu_i2c_bus_rec i2c_info; 479 u8 i2c_addr; 480 /* i2c mux */ 481 bool ddc_valid; 482 u8 ddc_mux_type; 483 u8 ddc_mux_control_pin; 484 u8 ddc_mux_state; 485 /* clock/data mux */ 486 bool cd_valid; 487 u8 cd_mux_type; 488 u8 cd_mux_control_pin; 489 u8 cd_mux_state; 490 }; 491 492 enum amdgpu_connector_audio { 493 AMDGPU_AUDIO_DISABLE = 0, 494 AMDGPU_AUDIO_ENABLE = 1, 495 AMDGPU_AUDIO_AUTO = 2 496 }; 497 498 enum amdgpu_connector_dither { 499 AMDGPU_FMT_DITHER_DISABLE = 0, 500 AMDGPU_FMT_DITHER_ENABLE = 1, 501 }; 502 503 struct amdgpu_connector { 504 struct drm_connector base; 505 uint32_t connector_id; 506 uint32_t devices; 507 struct amdgpu_i2c_chan *ddc_bus; 508 /* some systems have an hdmi and vga port with a shared ddc line */ 509 bool shared_ddc; 510 bool use_digital; 511 /* we need to mind the EDID between detect 512 and get modes due to analog/digital/tvencoder */ 513 struct edid *edid; 514 void *con_priv; 515 bool dac_load_detect; 516 bool detected_by_load; /* if the connection status was determined by load */ 517 uint16_t connector_object_id; 518 struct amdgpu_hpd hpd; 519 struct amdgpu_router router; 520 struct amdgpu_i2c_chan *router_bus; 521 enum amdgpu_connector_audio audio; 522 enum amdgpu_connector_dither dither; 523 unsigned pixelclock_for_modeset; 524 }; 525 526 struct amdgpu_framebuffer { 527 struct drm_framebuffer base; 528 struct drm_gem_object *obj; 529 }; 530 531 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \ 532 ((em) == ATOM_ENCODER_MODE_DP_MST)) 533 534 /* Driver internal use only flags of amdgpu_get_crtc_scanoutpos() */ 535 #define USE_REAL_VBLANKSTART (1 << 30) 536 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31) 537 538 void amdgpu_link_encoder_connector(struct drm_device *dev); 539 540 struct drm_connector * 541 amdgpu_get_connector_for_encoder(struct drm_encoder *encoder); 542 struct drm_connector * 543 amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder); 544 bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, 545 u32 pixel_clock); 546 547 u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder); 548 struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder); 549 550 bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux); 551 552 void amdgpu_encoder_set_active_device(struct drm_encoder *encoder); 553 554 int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe, 555 unsigned int flags, int *vpos, int *hpos, 556 ktime_t *stime, ktime_t *etime, 557 const struct drm_display_mode *mode); 558 559 int amdgpu_framebuffer_init(struct drm_device *dev, 560 struct amdgpu_framebuffer *rfb, 561 struct drm_mode_fb_cmd2 *mode_cmd, 562 struct drm_gem_object *obj); 563 564 int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); 565 566 void amdgpu_enc_destroy(struct drm_encoder *encoder); 567 void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj); 568 bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc, 569 const struct drm_display_mode *mode, 570 struct drm_display_mode *adjusted_mode); 571 void amdgpu_panel_mode_fixup(struct drm_encoder *encoder, 572 struct drm_display_mode *adjusted_mode); 573 int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc); 574 575 /* fbdev layer */ 576 int amdgpu_fbdev_init(struct amdgpu_device *adev); 577 void amdgpu_fbdev_fini(struct amdgpu_device *adev); 578 void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); 579 int amdgpu_fbdev_total_size(struct amdgpu_device *adev); 580 bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); 581 void amdgpu_fbdev_restore_mode(struct amdgpu_device *adev); 582 583 void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev); 584 585 586 int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); 587 588 /* amdgpu_display.c */ 589 void amdgpu_print_display_setup(struct drm_device *dev); 590 int amdgpu_modeset_create_props(struct amdgpu_device *adev); 591 int amdgpu_crtc_set_config(struct drm_mode_set *set); 592 int amdgpu_crtc_page_flip(struct drm_crtc *crtc, 593 struct drm_framebuffer *fb, 594 struct drm_pending_vblank_event *event, 595 uint32_t page_flip_flags); 596 extern const struct drm_mode_config_funcs amdgpu_mode_funcs; 597 598 #endif 599
Indexes created Mon Sep 29 21:09:56 GMT 2025