amdgpu_object.c revision 1.3.10.1
1 /* $NetBSD: amdgpu_object.c,v 1.3.10.1 2020/02/29 20:20:13 ad Exp $ */ 2 3 /* 4 * Copyright 2009 Jerome Glisse. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Jerome Glisse <glisse (at) freedesktop.org> 31 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 32 * Dave Airlie 33 */ 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: amdgpu_object.c,v 1.3.10.1 2020/02/29 20:20:13 ad Exp $"); 36 37 #include <linux/list.h> 38 #include <linux/slab.h> 39 #include <drm/drmP.h> 40 #include <drm/amdgpu_drm.h> 41 #include <drm/drm_cache.h> 42 #include "amdgpu.h" 43 #include "amdgpu_trace.h" 44 45 #include <linux/nbsd-namespace.h> 46 47 static u64 amdgpu_get_vis_part_size(struct amdgpu_device *adev, 48 struct ttm_mem_reg *mem) 49 { 50 u64 ret = 0; 51 if (mem->start << PAGE_SHIFT < adev->mc.visible_vram_size) { 52 ret = (u64)((mem->start << PAGE_SHIFT) + mem->size) > 53 adev->mc.visible_vram_size ? 54 adev->mc.visible_vram_size - (mem->start << PAGE_SHIFT) : 55 mem->size; 56 } 57 return ret; 58 } 59 60 static void amdgpu_update_memory_usage(struct amdgpu_device *adev, 61 struct ttm_mem_reg *old_mem, 62 struct ttm_mem_reg *new_mem) 63 { 64 u64 vis_size; 65 if (!adev) 66 return; 67 68 if (new_mem) { 69 switch (new_mem->mem_type) { 70 case TTM_PL_TT: 71 atomic64_add(new_mem->size, &adev->gtt_usage); 72 break; 73 case TTM_PL_VRAM: 74 atomic64_add(new_mem->size, &adev->vram_usage); 75 vis_size = amdgpu_get_vis_part_size(adev, new_mem); 76 atomic64_add(vis_size, &adev->vram_vis_usage); 77 break; 78 } 79 } 80 81 if (old_mem) { 82 switch (old_mem->mem_type) { 83 case TTM_PL_TT: 84 atomic64_sub(old_mem->size, &adev->gtt_usage); 85 break; 86 case TTM_PL_VRAM: 87 atomic64_sub(old_mem->size, &adev->vram_usage); 88 vis_size = amdgpu_get_vis_part_size(adev, old_mem); 89 atomic64_sub(vis_size, &adev->vram_vis_usage); 90 break; 91 } 92 } 93 } 94 95 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo) 96 { 97 struct amdgpu_bo *bo; 98 99 bo = container_of(tbo, struct amdgpu_bo, tbo); 100 101 amdgpu_update_memory_usage(bo->adev, &bo->tbo.mem, NULL); 102 103 mutex_lock(&bo->adev->gem.mutex); 104 list_del_init(&bo->list); 105 mutex_unlock(&bo->adev->gem.mutex); 106 drm_gem_object_release(&bo->gem_base); 107 amdgpu_bo_unref(&bo->parent); 108 kfree(bo->metadata); 109 kfree(bo); 110 } 111 112 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) 113 { 114 if (bo->destroy == &amdgpu_ttm_bo_destroy) 115 return true; 116 return false; 117 } 118 119 static void amdgpu_ttm_placement_init(struct amdgpu_device *adev, 120 struct ttm_placement *placement, 121 struct ttm_place *placements, 122 u32 domain, u64 flags) 123 { 124 u32 c = 0, i; 125 126 placement->placement = placements; 127 placement->busy_placement = placements; 128 129 if (domain & AMDGPU_GEM_DOMAIN_VRAM) { 130 if (flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS && 131 adev->mc.visible_vram_size < adev->mc.real_vram_size) { 132 placements[c].fpfn = 133 adev->mc.visible_vram_size >> PAGE_SHIFT; 134 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 135 TTM_PL_FLAG_VRAM | TTM_PL_FLAG_TOPDOWN; 136 } 137 placements[c].fpfn = 0; 138 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED | 139 TTM_PL_FLAG_VRAM; 140 if (!(flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) 141 placements[c - 1].flags |= TTM_PL_FLAG_TOPDOWN; 142 } 143 144 if (domain & AMDGPU_GEM_DOMAIN_GTT) { 145 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 146 placements[c].fpfn = 0; 147 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_TT | 148 TTM_PL_FLAG_UNCACHED; 149 } else { 150 placements[c].fpfn = 0; 151 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_TT; 152 } 153 } 154 155 if (domain & AMDGPU_GEM_DOMAIN_CPU) { 156 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { 157 placements[c].fpfn = 0; 158 placements[c++].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_SYSTEM | 159 TTM_PL_FLAG_UNCACHED; 160 } else { 161 placements[c].fpfn = 0; 162 placements[c++].flags = TTM_PL_FLAG_CACHED | TTM_PL_FLAG_SYSTEM; 163 } 164 } 165 166 if (domain & AMDGPU_GEM_DOMAIN_GDS) { 167 placements[c].fpfn = 0; 168 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 169 AMDGPU_PL_FLAG_GDS; 170 } 171 if (domain & AMDGPU_GEM_DOMAIN_GWS) { 172 placements[c].fpfn = 0; 173 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 174 AMDGPU_PL_FLAG_GWS; 175 } 176 if (domain & AMDGPU_GEM_DOMAIN_OA) { 177 placements[c].fpfn = 0; 178 placements[c++].flags = TTM_PL_FLAG_UNCACHED | 179 AMDGPU_PL_FLAG_OA; 180 } 181 182 if (!c) { 183 placements[c].fpfn = 0; 184 placements[c++].flags = TTM_PL_MASK_CACHING | 185 TTM_PL_FLAG_SYSTEM; 186 } 187 placement->num_placement = c; 188 placement->num_busy_placement = c; 189 190 for (i = 0; i < c; i++) { 191 if ((flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) && 192 (placements[i].flags & TTM_PL_FLAG_VRAM) && 193 !placements[i].fpfn) 194 placements[i].lpfn = 195 adev->mc.visible_vram_size >> PAGE_SHIFT; 196 else 197 placements[i].lpfn = 0; 198 } 199 } 200 201 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *rbo, u32 domain) 202 { 203 amdgpu_ttm_placement_init(rbo->adev, &rbo->placement, 204 rbo->placements, domain, rbo->flags); 205 } 206 207 static void amdgpu_fill_placement_to_bo(struct amdgpu_bo *bo, 208 struct ttm_placement *placement) 209 { 210 BUG_ON(placement->num_placement > (AMDGPU_GEM_DOMAIN_MAX + 1)); 211 212 memcpy(bo->placements, placement->placement, 213 placement->num_placement * sizeof(struct ttm_place)); 214 bo->placement.num_placement = placement->num_placement; 215 bo->placement.num_busy_placement = placement->num_busy_placement; 216 bo->placement.placement = bo->placements; 217 bo->placement.busy_placement = bo->placements; 218 } 219 220 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 221 unsigned long size, int byte_align, 222 bool kernel, u32 domain, u64 flags, 223 struct sg_table *sg, 224 struct ttm_placement *placement, 225 struct reservation_object *resv, 226 struct amdgpu_bo **bo_ptr) 227 { 228 struct amdgpu_bo *bo; 229 enum ttm_bo_type type; 230 unsigned long page_align; 231 size_t acc_size; 232 int r; 233 234 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 235 size = ALIGN(size, PAGE_SIZE); 236 237 if (kernel) { 238 type = ttm_bo_type_kernel; 239 } else if (sg) { 240 type = ttm_bo_type_sg; 241 } else { 242 type = ttm_bo_type_device; 243 } 244 *bo_ptr = NULL; 245 246 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size, 247 sizeof(struct amdgpu_bo)); 248 249 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL); 250 if (bo == NULL) 251 return -ENOMEM; 252 r = drm_gem_object_init(adev->ddev, &bo->gem_base, size); 253 if (unlikely(r)) { 254 kfree(bo); 255 return r; 256 } 257 bo->adev = adev; 258 INIT_LIST_HEAD(&bo->list); 259 INIT_LIST_HEAD(&bo->va); 260 bo->initial_domain = domain & (AMDGPU_GEM_DOMAIN_VRAM | 261 AMDGPU_GEM_DOMAIN_GTT | 262 AMDGPU_GEM_DOMAIN_CPU | 263 AMDGPU_GEM_DOMAIN_GDS | 264 AMDGPU_GEM_DOMAIN_GWS | 265 AMDGPU_GEM_DOMAIN_OA); 266 267 bo->flags = flags; 268 269 /* For architectures that don't support WC memory, 270 * mask out the WC flag from the BO 271 */ 272 if (!drm_arch_can_wc_memory()) 273 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC; 274 275 amdgpu_fill_placement_to_bo(bo, placement); 276 /* Kernel allocation are uninterruptible */ 277 r = ttm_bo_init(&adev->mman.bdev, &bo->tbo, size, type, 278 &bo->placement, page_align, !kernel, NULL, 279 acc_size, sg, resv, &amdgpu_ttm_bo_destroy); 280 if (unlikely(r != 0)) { 281 return r; 282 } 283 *bo_ptr = bo; 284 285 trace_amdgpu_bo_create(bo); 286 287 return 0; 288 } 289 290 int amdgpu_bo_create(struct amdgpu_device *adev, 291 unsigned long size, int byte_align, 292 bool kernel, u32 domain, u64 flags, 293 struct sg_table *sg, 294 struct reservation_object *resv, 295 struct amdgpu_bo **bo_ptr) 296 { 297 struct ttm_placement placement = {0}; 298 struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1]; 299 300 memset(&placements, 0, 301 (AMDGPU_GEM_DOMAIN_MAX + 1) * sizeof(struct ttm_place)); 302 303 amdgpu_ttm_placement_init(adev, &placement, 304 placements, domain, flags); 305 306 return amdgpu_bo_create_restricted(adev, size, byte_align, kernel, 307 domain, flags, sg, &placement, 308 resv, bo_ptr); 309 } 310 311 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) 312 { 313 bool is_iomem; 314 int r; 315 316 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 317 return -EPERM; 318 319 if (bo->kptr) { 320 if (ptr) { 321 *ptr = bo->kptr; 322 } 323 return 0; 324 } 325 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap); 326 if (r) { 327 return r; 328 } 329 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 330 if (ptr) { 331 *ptr = bo->kptr; 332 } 333 return 0; 334 } 335 336 void amdgpu_bo_kunmap(struct amdgpu_bo *bo) 337 { 338 if (bo->kptr == NULL) 339 return; 340 bo->kptr = NULL; 341 ttm_bo_kunmap(&bo->kmap); 342 } 343 344 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo) 345 { 346 if (bo == NULL) 347 return NULL; 348 349 ttm_bo_reference(&bo->tbo); 350 return bo; 351 } 352 353 void amdgpu_bo_unref(struct amdgpu_bo **bo) 354 { 355 struct ttm_buffer_object *tbo; 356 357 if ((*bo) == NULL) 358 return; 359 360 tbo = &((*bo)->tbo); 361 ttm_bo_unref(&tbo); 362 if (tbo == NULL) 363 *bo = NULL; 364 } 365 366 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 367 u64 min_offset, u64 max_offset, 368 u64 *gpu_addr) 369 { 370 int r, i; 371 unsigned fpfn, lpfn; 372 373 if (amdgpu_ttm_tt_has_userptr(bo->tbo.ttm)) 374 return -EPERM; 375 376 if (WARN_ON_ONCE(min_offset > max_offset)) 377 return -EINVAL; 378 379 if (bo->pin_count) { 380 bo->pin_count++; 381 if (gpu_addr) 382 *gpu_addr = amdgpu_bo_gpu_offset(bo); 383 384 if (max_offset != 0) { 385 u64 domain_start; 386 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 387 domain_start = bo->adev->mc.vram_start; 388 else 389 domain_start = bo->adev->mc.gtt_start; 390 WARN_ON_ONCE(max_offset < 391 (amdgpu_bo_gpu_offset(bo) - domain_start)); 392 } 393 394 return 0; 395 } 396 amdgpu_ttm_placement_from_domain(bo, domain); 397 for (i = 0; i < bo->placement.num_placement; i++) { 398 /* force to pin into visible video ram */ 399 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) && 400 !(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) && 401 (!max_offset || max_offset > bo->adev->mc.visible_vram_size)) { 402 if (WARN_ON_ONCE(min_offset > 403 bo->adev->mc.visible_vram_size)) 404 return -EINVAL; 405 fpfn = min_offset >> PAGE_SHIFT; 406 lpfn = bo->adev->mc.visible_vram_size >> PAGE_SHIFT; 407 } else { 408 fpfn = min_offset >> PAGE_SHIFT; 409 lpfn = max_offset >> PAGE_SHIFT; 410 } 411 if (fpfn > bo->placements[i].fpfn) 412 bo->placements[i].fpfn = fpfn; 413 if (!bo->placements[i].lpfn || 414 (lpfn && lpfn < bo->placements[i].lpfn)) 415 bo->placements[i].lpfn = lpfn; 416 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT; 417 } 418 419 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 420 if (likely(r == 0)) { 421 bo->pin_count = 1; 422 if (gpu_addr != NULL) 423 *gpu_addr = amdgpu_bo_gpu_offset(bo); 424 if (domain == AMDGPU_GEM_DOMAIN_VRAM) 425 bo->adev->vram_pin_size += amdgpu_bo_size(bo); 426 else 427 bo->adev->gart_pin_size += amdgpu_bo_size(bo); 428 } else { 429 dev_err(bo->adev->dev, "%p pin failed\n", bo); 430 } 431 return r; 432 } 433 434 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr) 435 { 436 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr); 437 } 438 439 int amdgpu_bo_unpin(struct amdgpu_bo *bo) 440 { 441 int r, i; 442 443 if (!bo->pin_count) { 444 dev_warn(bo->adev->dev, "%p unpin not necessary\n", bo); 445 return 0; 446 } 447 bo->pin_count--; 448 if (bo->pin_count) 449 return 0; 450 for (i = 0; i < bo->placement.num_placement; i++) { 451 bo->placements[i].lpfn = 0; 452 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT; 453 } 454 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false); 455 if (likely(r == 0)) { 456 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 457 bo->adev->vram_pin_size -= amdgpu_bo_size(bo); 458 else 459 bo->adev->gart_pin_size -= amdgpu_bo_size(bo); 460 } else { 461 dev_err(bo->adev->dev, "%p validate failed for unpin\n", bo); 462 } 463 return r; 464 } 465 466 int amdgpu_bo_evict_vram(struct amdgpu_device *adev) 467 { 468 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 469 if (0 && (adev->flags & AMD_IS_APU)) { 470 /* Useless to evict on IGP chips */ 471 return 0; 472 } 473 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM); 474 } 475 476 void amdgpu_bo_force_delete(struct amdgpu_device *adev) 477 { 478 struct amdgpu_bo *bo, *n; 479 480 if (list_empty(&adev->gem.objects)) { 481 return; 482 } 483 dev_err(adev->dev, "Userspace still has active objects !\n"); 484 list_for_each_entry_safe(bo, n, &adev->gem.objects, list) { 485 dev_err(adev->dev, "%p %p %lu %lu force free\n", 486 &bo->gem_base, bo, (unsigned long)bo->gem_base.size, 487 *((unsigned long *)&bo->gem_base.refcount)); 488 mutex_lock(&bo->adev->gem.mutex); 489 list_del_init(&bo->list); 490 mutex_unlock(&bo->adev->gem.mutex); 491 /* this should unref the ttm bo */ 492 drm_gem_object_unreference_unlocked(&bo->gem_base); 493 } 494 } 495 496 int amdgpu_bo_init(struct amdgpu_device *adev) 497 { 498 /* Add an MTRR for the VRAM */ 499 adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base, 500 adev->mc.aper_size); 501 DRM_INFO("Detected VRAM RAM=%"PRIu64"M, BAR=%lluM\n", 502 adev->mc.mc_vram_size >> 20, 503 (unsigned long long)adev->mc.aper_size >> 20); 504 DRM_INFO("RAM width %dbits DDR\n", 505 adev->mc.vram_width); 506 return amdgpu_ttm_init(adev); 507 } 508 509 void amdgpu_bo_fini(struct amdgpu_device *adev) 510 { 511 amdgpu_ttm_fini(adev); 512 arch_phys_wc_del(adev->mc.vram_mtrr); 513 } 514 515 #ifndef __NetBSD__ /* XXX unused? */ 516 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 517 struct vm_area_struct *vma) 518 { 519 return ttm_fbdev_mmap(vma, &bo->tbo); 520 } 521 #endif 522 523 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags) 524 { 525 if (AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) 526 return -EINVAL; 527 528 bo->tiling_flags = tiling_flags; 529 return 0; 530 } 531 532 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) 533 { 534 lockdep_assert_held(&bo->tbo.resv->lock.base); 535 536 if (tiling_flags) 537 *tiling_flags = bo->tiling_flags; 538 } 539 540 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 541 uint32_t metadata_size, uint64_t flags) 542 { 543 void *buffer; 544 545 if (!metadata_size) { 546 if (bo->metadata_size) { 547 kfree(bo->metadata); 548 bo->metadata = NULL; 549 bo->metadata_size = 0; 550 } 551 return 0; 552 } 553 554 if (metadata == NULL) 555 return -EINVAL; 556 557 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL); 558 if (buffer == NULL) 559 return -ENOMEM; 560 561 kfree(bo->metadata); 562 bo->metadata_flags = flags; 563 bo->metadata = buffer; 564 bo->metadata_size = metadata_size; 565 566 return 0; 567 } 568 569 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 570 size_t buffer_size, uint32_t *metadata_size, 571 uint64_t *flags) 572 { 573 if (!buffer && !metadata_size) 574 return -EINVAL; 575 576 if (buffer) { 577 if (buffer_size < bo->metadata_size) 578 return -EINVAL; 579 580 if (bo->metadata_size) 581 memcpy(buffer, bo->metadata, bo->metadata_size); 582 } 583 584 if (metadata_size) 585 *metadata_size = bo->metadata_size; 586 if (flags) 587 *flags = bo->metadata_flags; 588 589 return 0; 590 } 591 592 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 593 struct ttm_mem_reg *new_mem) 594 { 595 struct amdgpu_bo *rbo; 596 597 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 598 return; 599 600 rbo = container_of(bo, struct amdgpu_bo, tbo); 601 amdgpu_vm_bo_invalidate(rbo->adev, rbo); 602 603 /* update statistics */ 604 if (!new_mem) 605 return; 606 607 /* move_notify is called before move happens */ 608 amdgpu_update_memory_usage(rbo->adev, &bo->mem, new_mem); 609 } 610 611 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 612 { 613 struct amdgpu_device *adev; 614 struct amdgpu_bo *abo; 615 unsigned long offset, size, lpfn; 616 int i, r; 617 618 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) 619 return 0; 620 621 abo = container_of(bo, struct amdgpu_bo, tbo); 622 adev = abo->adev; 623 if (bo->mem.mem_type != TTM_PL_VRAM) 624 return 0; 625 626 size = bo->mem.num_pages << PAGE_SHIFT; 627 offset = bo->mem.start << PAGE_SHIFT; 628 if ((offset + size) <= adev->mc.visible_vram_size) 629 return 0; 630 631 /* hurrah the memory is not visible ! */ 632 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM); 633 lpfn = adev->mc.visible_vram_size >> PAGE_SHIFT; 634 for (i = 0; i < abo->placement.num_placement; i++) { 635 /* Force into visible VRAM */ 636 if ((abo->placements[i].flags & TTM_PL_FLAG_VRAM) && 637 (!abo->placements[i].lpfn || abo->placements[i].lpfn > lpfn)) 638 abo->placements[i].lpfn = lpfn; 639 } 640 r = ttm_bo_validate(bo, &abo->placement, false, false); 641 if (unlikely(r == -ENOMEM)) { 642 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_GTT); 643 return ttm_bo_validate(bo, &abo->placement, false, false); 644 } else if (unlikely(r != 0)) { 645 return r; 646 } 647 648 offset = bo->mem.start << PAGE_SHIFT; 649 /* this should never happen */ 650 if ((offset + size) > adev->mc.visible_vram_size) 651 return -EINVAL; 652 653 return 0; 654 } 655 656 /** 657 * amdgpu_bo_fence - add fence to buffer object 658 * 659 * @bo: buffer object in question 660 * @fence: fence to add 661 * @shared: true if fence should be added shared 662 * 663 */ 664 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 665 bool shared) 666 { 667 struct reservation_object *resv = bo->tbo.resv; 668 669 if (shared) 670 reservation_object_add_shared_fence(resv, fence); 671 else 672 reservation_object_add_excl_fence(resv, fence); 673 } 674
Indexes created Sat Sep 20 22:09:52 GMT 2025