amdgpu_object.h revision 1.1
1 /* $NetBSD: amdgpu_object.h,v 1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2008 Advanced Micro Devices, Inc. 5 * Copyright 2008 Red Hat Inc. 6 * Copyright 2009 Jerome Glisse. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: Dave Airlie 27 * Alex Deucher 28 * Jerome Glisse 29 */ 30 #ifndef __AMDGPU_OBJECT_H__ 31 #define __AMDGPU_OBJECT_H__ 32 33 #include <drm/amdgpu_drm.h> 34 #include "amdgpu.h" 35 36 /** 37 * amdgpu_mem_type_to_domain - return domain corresponding to mem_type 38 * @mem_type: ttm memory type 39 * 40 * Returns corresponding domain of the ttm mem_type 41 */ 42 static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) 43 { 44 switch (mem_type) { 45 case TTM_PL_VRAM: 46 return AMDGPU_GEM_DOMAIN_VRAM; 47 case TTM_PL_TT: 48 return AMDGPU_GEM_DOMAIN_GTT; 49 case TTM_PL_SYSTEM: 50 return AMDGPU_GEM_DOMAIN_CPU; 51 case AMDGPU_PL_GDS: 52 return AMDGPU_GEM_DOMAIN_GDS; 53 case AMDGPU_PL_GWS: 54 return AMDGPU_GEM_DOMAIN_GWS; 55 case AMDGPU_PL_OA: 56 return AMDGPU_GEM_DOMAIN_OA; 57 default: 58 break; 59 } 60 return 0; 61 } 62 63 /** 64 * amdgpu_bo_reserve - reserve bo 65 * @bo: bo structure 66 * @no_intr: don't return -ERESTARTSYS on pending signal 67 * 68 * Returns: 69 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 70 * a signal. Release all buffer reservations and return to user-space. 71 */ 72 static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr) 73 { 74 int r; 75 76 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0); 77 if (unlikely(r != 0)) { 78 if (r != -ERESTARTSYS) 79 dev_err(bo->adev->dev, "%p reserve failed\n", bo); 80 return r; 81 } 82 return 0; 83 } 84 85 static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo) 86 { 87 ttm_bo_unreserve(&bo->tbo); 88 } 89 90 /** 91 * amdgpu_bo_gpu_offset - return GPU offset of bo 92 * @bo: amdgpu object for which we query the offset 93 * 94 * Returns current GPU offset of the object. 95 * 96 * Note: object should either be pinned or reserved when calling this 97 * function, it might be useful to add check for this for debugging. 98 */ 99 static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) 100 { 101 return bo->tbo.offset; 102 } 103 104 static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo) 105 { 106 return bo->tbo.num_pages << PAGE_SHIFT; 107 } 108 109 static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo) 110 { 111 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 112 } 113 114 static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo) 115 { 116 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE; 117 } 118 119 /** 120 * amdgpu_bo_mmap_offset - return mmap offset of bo 121 * @bo: amdgpu object for which we query the offset 122 * 123 * Returns mmap offset of the object. 124 */ 125 static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo) 126 { 127 return drm_vma_node_offset_addr(&bo->tbo.vma_node); 128 } 129 130 int amdgpu_bo_create(struct amdgpu_device *adev, 131 unsigned long size, int byte_align, 132 bool kernel, u32 domain, u64 flags, 133 struct sg_table *sg, 134 struct reservation_object *resv, 135 struct amdgpu_bo **bo_ptr); 136 int amdgpu_bo_create_restricted(struct amdgpu_device *adev, 137 unsigned long size, int byte_align, 138 bool kernel, u32 domain, u64 flags, 139 struct sg_table *sg, 140 struct ttm_placement *placement, 141 struct reservation_object *resv, 142 struct amdgpu_bo **bo_ptr); 143 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr); 144 void amdgpu_bo_kunmap(struct amdgpu_bo *bo); 145 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); 146 void amdgpu_bo_unref(struct amdgpu_bo **bo); 147 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr); 148 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, 149 u64 min_offset, u64 max_offset, 150 u64 *gpu_addr); 151 int amdgpu_bo_unpin(struct amdgpu_bo *bo); 152 int amdgpu_bo_evict_vram(struct amdgpu_device *adev); 153 void amdgpu_bo_force_delete(struct amdgpu_device *adev); 154 int amdgpu_bo_init(struct amdgpu_device *adev); 155 void amdgpu_bo_fini(struct amdgpu_device *adev); 156 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo, 157 struct vm_area_struct *vma); 158 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags); 159 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags); 160 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata, 161 uint32_t metadata_size, uint64_t flags); 162 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer, 163 size_t buffer_size, uint32_t *metadata_size, 164 uint64_t *flags); 165 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, 166 struct ttm_mem_reg *new_mem); 167 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 168 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence, 169 bool shared); 170 171 /* 172 * sub allocation 173 */ 174 175 static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo) 176 { 177 return sa_bo->manager->gpu_addr + sa_bo->soffset; 178 } 179 180 static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo) 181 { 182 return sa_bo->manager->cpu_ptr + sa_bo->soffset; 183 } 184 185 int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev, 186 struct amdgpu_sa_manager *sa_manager, 187 unsigned size, u32 align, u32 domain); 188 void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev, 189 struct amdgpu_sa_manager *sa_manager); 190 int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev, 191 struct amdgpu_sa_manager *sa_manager); 192 int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev, 193 struct amdgpu_sa_manager *sa_manager); 194 int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager, 195 struct amdgpu_sa_bo **sa_bo, 196 unsigned size, unsigned align); 197 void amdgpu_sa_bo_free(struct amdgpu_device *adev, 198 struct amdgpu_sa_bo **sa_bo, 199 struct fence *fence); 200 #if defined(CONFIG_DEBUG_FS) 201 void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager, 202 struct seq_file *m); 203 #endif 204 205 206 #endif 207
Indexes created Wed Sep 24 15:09:51 GMT 2025