amdgpu_ring.h revision 1.1
1 /* $NetBSD: amdgpu_ring.h,v 1.1 2021/12/18 20:11:10 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Christian Knig 25 */ 26 #ifndef __AMDGPU_RING_H__ 27 #define __AMDGPU_RING_H__ 28 29 #include <drm/amdgpu_drm.h> 30 #include <drm/gpu_scheduler.h> 31 #include <drm/drm_print.h> 32 33 /* max number of rings */ 34 #define AMDGPU_MAX_RINGS 28 35 #define AMDGPU_MAX_GFX_RINGS 2 36 #define AMDGPU_MAX_COMPUTE_RINGS 8 37 #define AMDGPU_MAX_VCE_RINGS 3 38 #define AMDGPU_MAX_UVD_ENC_RINGS 2 39 40 /* some special values for the owner field */ 41 #define AMDGPU_FENCE_OWNER_UNDEFINED ((void *)0ul) 42 #define AMDGPU_FENCE_OWNER_VM ((void *)1ul) 43 #define AMDGPU_FENCE_OWNER_KFD ((void *)2ul) 44 45 #define AMDGPU_FENCE_FLAG_64BIT (1 << 0) 46 #define AMDGPU_FENCE_FLAG_INT (1 << 1) 47 #define AMDGPU_FENCE_FLAG_TC_WB_ONLY (1 << 2) 48 49 #define to_amdgpu_ring(s) container_of((s), struct amdgpu_ring, sched) 50 51 enum amdgpu_ring_type { 52 AMDGPU_RING_TYPE_GFX, 53 AMDGPU_RING_TYPE_COMPUTE, 54 AMDGPU_RING_TYPE_SDMA, 55 AMDGPU_RING_TYPE_UVD, 56 AMDGPU_RING_TYPE_VCE, 57 AMDGPU_RING_TYPE_KIQ, 58 AMDGPU_RING_TYPE_UVD_ENC, 59 AMDGPU_RING_TYPE_VCN_DEC, 60 AMDGPU_RING_TYPE_VCN_ENC, 61 AMDGPU_RING_TYPE_VCN_JPEG 62 }; 63 64 struct amdgpu_device; 65 struct amdgpu_ring; 66 struct amdgpu_ib; 67 struct amdgpu_cs_parser; 68 struct amdgpu_job; 69 70 /* 71 * Fences. 72 */ 73 struct amdgpu_fence_driver { 74 uint64_t gpu_addr; 75 volatile uint32_t *cpu_addr; 76 /* sync_seq is protected by ring emission lock */ 77 uint32_t sync_seq; 78 atomic_t last_seq; 79 bool initialized; 80 struct amdgpu_irq_src *irq_src; 81 unsigned irq_type; 82 struct timer_list fallback_timer; 83 unsigned num_fences_mask; 84 spinlock_t lock; 85 struct dma_fence **fences; 86 }; 87 88 int amdgpu_fence_driver_init(struct amdgpu_device *adev); 89 void amdgpu_fence_driver_fini(struct amdgpu_device *adev); 90 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring); 91 92 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 93 unsigned num_hw_submission); 94 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring, 95 struct amdgpu_irq_src *irq_src, 96 unsigned irq_type); 97 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev); 98 void amdgpu_fence_driver_resume(struct amdgpu_device *adev); 99 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **fence, 100 unsigned flags); 101 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s); 102 bool amdgpu_fence_process(struct amdgpu_ring *ring); 103 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring); 104 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring, 105 uint32_t wait_seq, 106 signed long timeout); 107 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring); 108 109 /* 110 * Rings. 111 */ 112 113 /* provided by hw blocks that expose a ring buffer for commands */ 114 struct amdgpu_ring_funcs { 115 enum amdgpu_ring_type type; 116 uint32_t align_mask; 117 u32 nop; 118 bool support_64bit_ptrs; 119 bool no_user_fence; 120 unsigned vmhub; 121 unsigned extra_dw; 122 123 /* ring read/write ptr handling */ 124 u64 (*get_rptr)(struct amdgpu_ring *ring); 125 u64 (*get_wptr)(struct amdgpu_ring *ring); 126 void (*set_wptr)(struct amdgpu_ring *ring); 127 /* validating and patching of IBs */ 128 int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 129 int (*patch_cs_in_place)(struct amdgpu_cs_parser *p, uint32_t ib_idx); 130 /* constants to calculate how many DW are needed for an emit */ 131 unsigned emit_frame_size; 132 unsigned emit_ib_size; 133 /* command emit functions */ 134 void (*emit_ib)(struct amdgpu_ring *ring, 135 struct amdgpu_job *job, 136 struct amdgpu_ib *ib, 137 uint32_t flags); 138 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr, 139 uint64_t seq, unsigned flags); 140 void (*emit_pipeline_sync)(struct amdgpu_ring *ring); 141 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid, 142 uint64_t pd_addr); 143 void (*emit_hdp_flush)(struct amdgpu_ring *ring); 144 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid, 145 uint32_t gds_base, uint32_t gds_size, 146 uint32_t gws_base, uint32_t gws_size, 147 uint32_t oa_base, uint32_t oa_size); 148 /* testing functions */ 149 int (*test_ring)(struct amdgpu_ring *ring); 150 int (*test_ib)(struct amdgpu_ring *ring, long timeout); 151 /* insert NOP packets */ 152 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count); 153 void (*insert_start)(struct amdgpu_ring *ring); 154 void (*insert_end)(struct amdgpu_ring *ring); 155 /* pad the indirect buffer to the necessary number of dw */ 156 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 157 unsigned (*init_cond_exec)(struct amdgpu_ring *ring); 158 void (*patch_cond_exec)(struct amdgpu_ring *ring, unsigned offset); 159 /* note usage for clock and power gating */ 160 void (*begin_use)(struct amdgpu_ring *ring); 161 void (*end_use)(struct amdgpu_ring *ring); 162 void (*emit_switch_buffer) (struct amdgpu_ring *ring); 163 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags); 164 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg); 165 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); 166 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg, 167 uint32_t val, uint32_t mask); 168 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring, 169 uint32_t reg0, uint32_t reg1, 170 uint32_t ref, uint32_t mask); 171 void (*emit_tmz)(struct amdgpu_ring *ring, bool start); 172 /* priority functions */ 173 void (*set_priority) (struct amdgpu_ring *ring, 174 enum drm_sched_priority priority); 175 /* Try to soft recover the ring to make the fence signal */ 176 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid); 177 int (*preempt_ib)(struct amdgpu_ring *ring); 178 }; 179 180 struct amdgpu_ring { 181 struct amdgpu_device *adev; 182 const struct amdgpu_ring_funcs *funcs; 183 struct amdgpu_fence_driver fence_drv; 184 struct drm_gpu_scheduler sched; 185 186 struct amdgpu_bo *ring_obj; 187 volatile uint32_t *ring; 188 unsigned rptr_offs; 189 u64 wptr; 190 u64 wptr_old; 191 unsigned ring_size; 192 unsigned max_dw; 193 int count_dw; 194 uint64_t gpu_addr; 195 uint64_t ptr_mask; 196 uint32_t buf_mask; 197 u32 idx; 198 u32 me; 199 u32 pipe; 200 u32 queue; 201 struct amdgpu_bo *mqd_obj; 202 uint64_t mqd_gpu_addr; 203 void *mqd_ptr; 204 uint64_t eop_gpu_addr; 205 u32 doorbell_index; 206 bool use_doorbell; 207 bool use_pollmem; 208 unsigned wptr_offs; 209 unsigned fence_offs; 210 uint64_t current_ctx; 211 char name[16]; 212 u32 trail_seq; 213 unsigned trail_fence_offs; 214 u64 trail_fence_gpu_addr; 215 volatile u32 *trail_fence_cpu_addr; 216 unsigned cond_exe_offs; 217 u64 cond_exe_gpu_addr; 218 volatile u32 *cond_exe_cpu_addr; 219 unsigned vm_inv_eng; 220 struct dma_fence *vmid_wait; 221 bool has_compute_vm_bug; 222 223 atomic_t num_jobs[DRM_SCHED_PRIORITY_MAX]; 224 struct mutex priority_mutex; 225 /* protected by priority_mutex */ 226 int priority; 227 228 #if defined(CONFIG_DEBUG_FS) 229 struct dentry *ent; 230 #endif 231 }; 232 233 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib))) 234 #define amdgpu_ring_patch_cs_in_place(r, p, ib) ((r)->funcs->patch_cs_in_place((p), (ib))) 235 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r)) 236 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t)) 237 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r)) 238 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r)) 239 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r)) 240 #define amdgpu_ring_emit_ib(r, job, ib, flags) ((r)->funcs->emit_ib((r), (job), (ib), (flags))) 241 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r)) 242 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr)) 243 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags)) 244 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as)) 245 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r)) 246 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r)) 247 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d)) 248 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d)) 249 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v)) 250 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m)) 251 #define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m)) 252 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b)) 253 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib))) 254 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r)) 255 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o)) 256 #define amdgpu_ring_preempt_ib(r) (r)->funcs->preempt_ib(r) 257 258 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); 259 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count); 260 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib); 261 void amdgpu_ring_commit(struct amdgpu_ring *ring); 262 void amdgpu_ring_undo(struct amdgpu_ring *ring); 263 void amdgpu_ring_priority_get(struct amdgpu_ring *ring, 264 enum drm_sched_priority priority); 265 void amdgpu_ring_priority_put(struct amdgpu_ring *ring, 266 enum drm_sched_priority priority); 267 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring, 268 unsigned ring_size, struct amdgpu_irq_src *irq_src, 269 unsigned irq_type); 270 void amdgpu_ring_fini(struct amdgpu_ring *ring); 271 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring, 272 uint32_t reg0, uint32_t val0, 273 uint32_t reg1, uint32_t val1); 274 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid, 275 struct dma_fence *fence); 276 277 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, 278 bool cond_exec) 279 { 280 *ring->cond_exe_cpu_addr = cond_exec; 281 } 282 283 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) 284 { 285 int i = 0; 286 while (i <= ring->buf_mask) 287 ring->ring[i++] = ring->funcs->nop; 288 289 } 290 291 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) 292 { 293 if (ring->count_dw <= 0) 294 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 295 ring->ring[ring->wptr++ & ring->buf_mask] = v; 296 ring->wptr &= ring->ptr_mask; 297 ring->count_dw--; 298 } 299 300 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, 301 void *src, int count_dw) 302 { 303 unsigned occupied, chunk1, chunk2; 304 void *dst; 305 306 if (unlikely(ring->count_dw < count_dw)) 307 DRM_ERROR("amdgpu: writing more dwords to the ring than expected!\n"); 308 309 occupied = ring->wptr & ring->buf_mask; 310 dst = (void *)&ring->ring[occupied]; 311 chunk1 = ring->buf_mask + 1 - occupied; 312 chunk1 = (chunk1 >= count_dw) ? count_dw: chunk1; 313 chunk2 = count_dw - chunk1; 314 chunk1 <<= 2; 315 chunk2 <<= 2; 316 317 if (chunk1) 318 memcpy(dst, src, chunk1); 319 320 if (chunk2) { 321 src += chunk1; 322 dst = (void *)ring->ring; 323 memcpy(dst, src, chunk2); 324 } 325 326 ring->wptr += count_dw; 327 ring->wptr &= ring->ptr_mask; 328 ring->count_dw -= count_dw; 329 } 330 331 int amdgpu_ring_test_helper(struct amdgpu_ring *ring); 332 333 #endif 334
Indexes created Mon Sep 29 21:09:56 GMT 2025