amdgpu_si.c revision 1.1.1.1
1 /* $NetBSD: amdgpu_si.c,v 1.1.1.1 2021/12/18 20:11:11 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_si.c,v 1.1.1.1 2021/12/18 20:11:11 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <linux/pci.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_atombios.h" 36 #include "amdgpu_ih.h" 37 #include "amdgpu_uvd.h" 38 #include "amdgpu_vce.h" 39 #include "atom.h" 40 #include "amd_pcie.h" 41 #include "si_dpm.h" 42 #include "sid.h" 43 #include "si_ih.h" 44 #include "gfx_v6_0.h" 45 #include "gmc_v6_0.h" 46 #include "si_dma.h" 47 #include "dce_v6_0.h" 48 #include "si.h" 49 #include "dce_virtual.h" 50 #include "gca/gfx_6_0_d.h" 51 #include "oss/oss_1_0_d.h" 52 #include "gmc/gmc_6_0_d.h" 53 #include "dce/dce_6_0_d.h" 54 #include "uvd/uvd_4_0_d.h" 55 #include "bif/bif_3_0_d.h" 56 #include "bif/bif_3_0_sh_mask.h" 57 58 static const u32 tahiti_golden_registers[] = 59 { 60 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 61 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 62 mmDB_DEBUG, 0xffffffff, 0x00000000, 63 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 64 mmDB_DEBUG3, 0x0002021c, 0x00020200, 65 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 66 0x340c, 0x000000c0, 0x00800040, 67 0x360c, 0x000000c0, 0x00800040, 68 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 69 mmFBC_MISC, 0x00200000, 0x50100000, 70 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 71 mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff, 72 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 73 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 74 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 75 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 76 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 77 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 78 0x000c, 0xffffffff, 0x0040, 79 0x000d, 0x00000040, 0x00004040, 80 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 81 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 82 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 83 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 84 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 85 mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb, 86 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 87 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 88 mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40, 89 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 90 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8, 91 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 92 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 93 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 94 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 95 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 }; 97 98 static const u32 tahiti_golden_registers2[] = 99 { 100 mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001, 101 }; 102 103 static const u32 tahiti_golden_rlc_registers[] = 104 { 105 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 106 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 107 0x311f, 0xffffffff, 0x10104040, 108 0x3122, 0xffffffff, 0x0100000a, 109 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 110 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 111 mmUVD_CGC_GATE, 0x00000008, 0x00000000, 112 }; 113 114 static const u32 pitcairn_golden_registers[] = 115 { 116 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 117 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 118 mmDB_DEBUG, 0xffffffff, 0x00000000, 119 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 120 mmDB_DEBUG3, 0x0002021c, 0x00020200, 121 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 122 0x340c, 0x000300c0, 0x00800040, 123 0x360c, 0x000300c0, 0x00800040, 124 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 125 mmFBC_MISC, 0x00200000, 0x50100000, 126 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 127 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 128 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 129 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 130 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 131 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 132 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 133 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 134 0x000c, 0xffffffff, 0x0040, 135 0x000d, 0x00000040, 0x00004040, 136 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 137 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 138 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 139 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 140 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 141 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 142 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 143 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 144 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 145 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 146 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 147 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 148 }; 149 150 static const u32 pitcairn_golden_rlc_registers[] = 151 { 152 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 153 mmRLC_LB_PARAMS, 0xffffffff, 0x00601004, 154 0x311f, 0xffffffff, 0x10102020, 155 0x3122, 0xffffffff, 0x01000020, 156 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 157 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4, 158 }; 159 160 static const u32 verde_pg_init[] = 161 { 162 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000, 163 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff, 164 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 165 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 166 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 167 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 168 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 169 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007, 170 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff, 171 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 172 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 173 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 174 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 175 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 176 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000, 177 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff, 178 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 179 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 180 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 181 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 182 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 183 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200, 184 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff, 185 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 186 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 187 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 188 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 189 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 190 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16, 191 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff, 192 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 193 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 194 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 195 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 196 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 197 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e, 198 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff, 199 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 200 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 201 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 202 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 203 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 204 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 205 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff, 206 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0, 207 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800, 208 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 209 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 210 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4, 211 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e, 212 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 213 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 214 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8, 215 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500, 216 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12, 217 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c, 218 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d, 219 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c, 220 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a, 221 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e, 222 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d, 223 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546, 224 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30, 225 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e, 226 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c, 227 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f, 228 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f, 229 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567, 230 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42, 231 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f, 232 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45, 233 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572, 234 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48, 235 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575, 236 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c, 237 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801, 238 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67, 239 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a, 240 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a, 241 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d, 242 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87, 243 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851, 244 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba, 245 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891, 246 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc, 247 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893, 248 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe, 249 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895, 250 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2, 251 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899, 252 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6, 253 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d, 254 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca, 255 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1, 256 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc, 257 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3, 258 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce, 259 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5, 260 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3, 261 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd, 262 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142, 263 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a, 264 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1, 265 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144, 266 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b, 267 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165, 268 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d, 269 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173, 270 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d, 271 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184, 272 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f, 273 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b, 274 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998, 275 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9, 276 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7, 277 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af, 278 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc, 279 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1, 280 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800, 281 mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000, 282 mmGMCON_MISC2, 0xfc00, 0x2000, 283 mmGMCON_MISC3, 0xffffffff, 0xfc0, 284 mmMC_PMG_AUTO_CFG, 0x00000100, 0x100, 285 }; 286 287 static const u32 verde_golden_rlc_registers[] = 288 { 289 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 290 mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005, 291 0x311f, 0xffffffff, 0x10808020, 292 0x3122, 0xffffffff, 0x00800008, 293 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000, 294 mmRLC_LB_CNTL, 0xffffffff, 0x80010014, 295 }; 296 297 static const u32 verde_golden_registers[] = 298 { 299 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 300 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 301 mmDB_DEBUG, 0xffffffff, 0x00000000, 302 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 303 mmDB_DEBUG3, 0x0002021c, 0x00020200, 304 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 305 0x340c, 0x000300c0, 0x00800040, 306 0x360c, 0x000300c0, 0x00800040, 307 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 308 mmFBC_MISC, 0x00200000, 0x50100000, 309 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 310 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 311 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 312 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 313 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 314 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 315 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 316 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a, 317 0x000c, 0xffffffff, 0x0040, 318 0x000d, 0x00000040, 0x00004040, 319 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 320 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 321 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 322 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 323 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 324 mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003, 325 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 326 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032, 327 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 328 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 329 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 330 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 331 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 332 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 333 }; 334 335 static const u32 oland_golden_registers[] = 336 { 337 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 338 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 339 mmDB_DEBUG, 0xffffffff, 0x00000000, 340 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 341 mmDB_DEBUG3, 0x0002021c, 0x00020200, 342 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 343 0x340c, 0x000300c0, 0x00800040, 344 0x360c, 0x000300c0, 0x00800040, 345 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 346 mmFBC_MISC, 0x00200000, 0x50100000, 347 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 348 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 349 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 350 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 351 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 352 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 353 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 354 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082, 355 0x000c, 0xffffffff, 0x0040, 356 0x000d, 0x00000040, 0x00004040, 357 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 358 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 359 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 360 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 361 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 362 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 363 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 364 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 365 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 366 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 367 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 368 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 369 370 }; 371 372 static const u32 oland_golden_rlc_registers[] = 373 { 374 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 375 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 376 0x311f, 0xffffffff, 0x10104040, 377 0x3122, 0xffffffff, 0x0100000a, 378 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 379 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 380 }; 381 382 static const u32 hainan_golden_registers[] = 383 { 384 0x17bc, 0x00000030, 0x00000011, 385 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 386 mmDB_DEBUG, 0xffffffff, 0x00000000, 387 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 388 mmDB_DEBUG3, 0x0002021c, 0x00020200, 389 0x031e, 0x00000080, 0x00000000, 390 0x3430, 0xff000fff, 0x00000100, 391 0x340c, 0x000300c0, 0x00800040, 392 0x3630, 0xff000fff, 0x00000100, 393 0x360c, 0x000300c0, 0x00800040, 394 0x16ec, 0x000000f0, 0x00000070, 395 0x16f0, 0x00200000, 0x50100000, 396 0x1c0c, 0x31000311, 0x00000011, 397 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 398 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 399 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 400 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 401 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 402 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 403 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000, 404 0x000c, 0xffffffff, 0x0040, 405 0x000d, 0x00000040, 0x00004040, 406 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000, 407 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 408 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 409 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 410 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 411 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 412 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 413 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 414 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 415 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 416 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 417 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 418 }; 419 420 static const u32 hainan_golden_registers2[] = 421 { 422 mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003, 423 }; 424 425 static const u32 tahiti_mgcg_cgcg_init[] = 426 { 427 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 428 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 429 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 430 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 431 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 432 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 433 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 434 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 435 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 436 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 437 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 438 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 439 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 440 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 441 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 442 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 443 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 444 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 445 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 446 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 447 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 448 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 449 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 450 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 451 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 452 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 453 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 454 0x2458, 0xffffffff, 0x00010000, 455 0x2459, 0xffffffff, 0x00030002, 456 0x245a, 0xffffffff, 0x00040007, 457 0x245b, 0xffffffff, 0x00060005, 458 0x245c, 0xffffffff, 0x00090008, 459 0x245d, 0xffffffff, 0x00020001, 460 0x245e, 0xffffffff, 0x00040003, 461 0x245f, 0xffffffff, 0x00000007, 462 0x2460, 0xffffffff, 0x00060005, 463 0x2461, 0xffffffff, 0x00090008, 464 0x2462, 0xffffffff, 0x00030002, 465 0x2463, 0xffffffff, 0x00050004, 466 0x2464, 0xffffffff, 0x00000008, 467 0x2465, 0xffffffff, 0x00070006, 468 0x2466, 0xffffffff, 0x000a0009, 469 0x2467, 0xffffffff, 0x00040003, 470 0x2468, 0xffffffff, 0x00060005, 471 0x2469, 0xffffffff, 0x00000009, 472 0x246a, 0xffffffff, 0x00080007, 473 0x246b, 0xffffffff, 0x000b000a, 474 0x246c, 0xffffffff, 0x00050004, 475 0x246d, 0xffffffff, 0x00070006, 476 0x246e, 0xffffffff, 0x0008000b, 477 0x246f, 0xffffffff, 0x000a0009, 478 0x2470, 0xffffffff, 0x000d000c, 479 0x2471, 0xffffffff, 0x00060005, 480 0x2472, 0xffffffff, 0x00080007, 481 0x2473, 0xffffffff, 0x0000000b, 482 0x2474, 0xffffffff, 0x000a0009, 483 0x2475, 0xffffffff, 0x000d000c, 484 0x2476, 0xffffffff, 0x00070006, 485 0x2477, 0xffffffff, 0x00090008, 486 0x2478, 0xffffffff, 0x0000000c, 487 0x2479, 0xffffffff, 0x000b000a, 488 0x247a, 0xffffffff, 0x000e000d, 489 0x247b, 0xffffffff, 0x00080007, 490 0x247c, 0xffffffff, 0x000a0009, 491 0x247d, 0xffffffff, 0x0000000d, 492 0x247e, 0xffffffff, 0x000c000b, 493 0x247f, 0xffffffff, 0x000f000e, 494 0x2480, 0xffffffff, 0x00090008, 495 0x2481, 0xffffffff, 0x000b000a, 496 0x2482, 0xffffffff, 0x000c000f, 497 0x2483, 0xffffffff, 0x000e000d, 498 0x2484, 0xffffffff, 0x00110010, 499 0x2485, 0xffffffff, 0x000a0009, 500 0x2486, 0xffffffff, 0x000c000b, 501 0x2487, 0xffffffff, 0x0000000f, 502 0x2488, 0xffffffff, 0x000e000d, 503 0x2489, 0xffffffff, 0x00110010, 504 0x248a, 0xffffffff, 0x000b000a, 505 0x248b, 0xffffffff, 0x000d000c, 506 0x248c, 0xffffffff, 0x00000010, 507 0x248d, 0xffffffff, 0x000f000e, 508 0x248e, 0xffffffff, 0x00120011, 509 0x248f, 0xffffffff, 0x000c000b, 510 0x2490, 0xffffffff, 0x000e000d, 511 0x2491, 0xffffffff, 0x00000011, 512 0x2492, 0xffffffff, 0x0010000f, 513 0x2493, 0xffffffff, 0x00130012, 514 0x2494, 0xffffffff, 0x000d000c, 515 0x2495, 0xffffffff, 0x000f000e, 516 0x2496, 0xffffffff, 0x00100013, 517 0x2497, 0xffffffff, 0x00120011, 518 0x2498, 0xffffffff, 0x00150014, 519 0x2499, 0xffffffff, 0x000e000d, 520 0x249a, 0xffffffff, 0x0010000f, 521 0x249b, 0xffffffff, 0x00000013, 522 0x249c, 0xffffffff, 0x00120011, 523 0x249d, 0xffffffff, 0x00150014, 524 0x249e, 0xffffffff, 0x000f000e, 525 0x249f, 0xffffffff, 0x00110010, 526 0x24a0, 0xffffffff, 0x00000014, 527 0x24a1, 0xffffffff, 0x00130012, 528 0x24a2, 0xffffffff, 0x00160015, 529 0x24a3, 0xffffffff, 0x0010000f, 530 0x24a4, 0xffffffff, 0x00120011, 531 0x24a5, 0xffffffff, 0x00000015, 532 0x24a6, 0xffffffff, 0x00140013, 533 0x24a7, 0xffffffff, 0x00170016, 534 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 535 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 536 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 537 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 538 0x000c, 0xffffffff, 0x0000001c, 539 0x000d, 0x000f0000, 0x000f0000, 540 0x0583, 0xffffffff, 0x00000100, 541 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 542 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 543 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 544 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 545 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 546 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 547 0x157a, 0x00000001, 0x00000001, 548 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 549 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 550 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 551 0x3430, 0xfffffff0, 0x00000100, 552 0x3630, 0xfffffff0, 0x00000100, 553 }; 554 static const u32 pitcairn_mgcg_cgcg_init[] = 555 { 556 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 557 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 558 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 559 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 560 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 561 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 562 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 563 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 564 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 565 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 566 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 567 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 568 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 569 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 570 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 571 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 572 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 573 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 574 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 575 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 576 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 577 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 578 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 579 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 580 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 581 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 582 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 583 0x2458, 0xffffffff, 0x00010000, 584 0x2459, 0xffffffff, 0x00030002, 585 0x245a, 0xffffffff, 0x00040007, 586 0x245b, 0xffffffff, 0x00060005, 587 0x245c, 0xffffffff, 0x00090008, 588 0x245d, 0xffffffff, 0x00020001, 589 0x245e, 0xffffffff, 0x00040003, 590 0x245f, 0xffffffff, 0x00000007, 591 0x2460, 0xffffffff, 0x00060005, 592 0x2461, 0xffffffff, 0x00090008, 593 0x2462, 0xffffffff, 0x00030002, 594 0x2463, 0xffffffff, 0x00050004, 595 0x2464, 0xffffffff, 0x00000008, 596 0x2465, 0xffffffff, 0x00070006, 597 0x2466, 0xffffffff, 0x000a0009, 598 0x2467, 0xffffffff, 0x00040003, 599 0x2468, 0xffffffff, 0x00060005, 600 0x2469, 0xffffffff, 0x00000009, 601 0x246a, 0xffffffff, 0x00080007, 602 0x246b, 0xffffffff, 0x000b000a, 603 0x246c, 0xffffffff, 0x00050004, 604 0x246d, 0xffffffff, 0x00070006, 605 0x246e, 0xffffffff, 0x0008000b, 606 0x246f, 0xffffffff, 0x000a0009, 607 0x2470, 0xffffffff, 0x000d000c, 608 0x2480, 0xffffffff, 0x00090008, 609 0x2481, 0xffffffff, 0x000b000a, 610 0x2482, 0xffffffff, 0x000c000f, 611 0x2483, 0xffffffff, 0x000e000d, 612 0x2484, 0xffffffff, 0x00110010, 613 0x2485, 0xffffffff, 0x000a0009, 614 0x2486, 0xffffffff, 0x000c000b, 615 0x2487, 0xffffffff, 0x0000000f, 616 0x2488, 0xffffffff, 0x000e000d, 617 0x2489, 0xffffffff, 0x00110010, 618 0x248a, 0xffffffff, 0x000b000a, 619 0x248b, 0xffffffff, 0x000d000c, 620 0x248c, 0xffffffff, 0x00000010, 621 0x248d, 0xffffffff, 0x000f000e, 622 0x248e, 0xffffffff, 0x00120011, 623 0x248f, 0xffffffff, 0x000c000b, 624 0x2490, 0xffffffff, 0x000e000d, 625 0x2491, 0xffffffff, 0x00000011, 626 0x2492, 0xffffffff, 0x0010000f, 627 0x2493, 0xffffffff, 0x00130012, 628 0x2494, 0xffffffff, 0x000d000c, 629 0x2495, 0xffffffff, 0x000f000e, 630 0x2496, 0xffffffff, 0x00100013, 631 0x2497, 0xffffffff, 0x00120011, 632 0x2498, 0xffffffff, 0x00150014, 633 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 634 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 635 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 636 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 637 0x000c, 0xffffffff, 0x0000001c, 638 0x000d, 0x000f0000, 0x000f0000, 639 0x0583, 0xffffffff, 0x00000100, 640 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 641 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 642 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 643 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 644 0x157a, 0x00000001, 0x00000001, 645 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 646 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 647 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 648 0x3430, 0xfffffff0, 0x00000100, 649 0x3630, 0xfffffff0, 0x00000100, 650 }; 651 652 static const u32 verde_mgcg_cgcg_init[] = 653 { 654 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 655 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 656 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 657 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 658 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 659 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 660 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 661 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 662 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 663 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 664 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 665 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 666 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 667 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 668 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 669 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 670 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 671 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 672 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 673 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 674 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 675 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 676 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 677 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 678 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 679 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 680 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 681 0x2458, 0xffffffff, 0x00010000, 682 0x2459, 0xffffffff, 0x00030002, 683 0x245a, 0xffffffff, 0x00040007, 684 0x245b, 0xffffffff, 0x00060005, 685 0x245c, 0xffffffff, 0x00090008, 686 0x245d, 0xffffffff, 0x00020001, 687 0x245e, 0xffffffff, 0x00040003, 688 0x245f, 0xffffffff, 0x00000007, 689 0x2460, 0xffffffff, 0x00060005, 690 0x2461, 0xffffffff, 0x00090008, 691 0x2462, 0xffffffff, 0x00030002, 692 0x2463, 0xffffffff, 0x00050004, 693 0x2464, 0xffffffff, 0x00000008, 694 0x2465, 0xffffffff, 0x00070006, 695 0x2466, 0xffffffff, 0x000a0009, 696 0x2467, 0xffffffff, 0x00040003, 697 0x2468, 0xffffffff, 0x00060005, 698 0x2469, 0xffffffff, 0x00000009, 699 0x246a, 0xffffffff, 0x00080007, 700 0x246b, 0xffffffff, 0x000b000a, 701 0x246c, 0xffffffff, 0x00050004, 702 0x246d, 0xffffffff, 0x00070006, 703 0x246e, 0xffffffff, 0x0008000b, 704 0x246f, 0xffffffff, 0x000a0009, 705 0x2470, 0xffffffff, 0x000d000c, 706 0x2480, 0xffffffff, 0x00090008, 707 0x2481, 0xffffffff, 0x000b000a, 708 0x2482, 0xffffffff, 0x000c000f, 709 0x2483, 0xffffffff, 0x000e000d, 710 0x2484, 0xffffffff, 0x00110010, 711 0x2485, 0xffffffff, 0x000a0009, 712 0x2486, 0xffffffff, 0x000c000b, 713 0x2487, 0xffffffff, 0x0000000f, 714 0x2488, 0xffffffff, 0x000e000d, 715 0x2489, 0xffffffff, 0x00110010, 716 0x248a, 0xffffffff, 0x000b000a, 717 0x248b, 0xffffffff, 0x000d000c, 718 0x248c, 0xffffffff, 0x00000010, 719 0x248d, 0xffffffff, 0x000f000e, 720 0x248e, 0xffffffff, 0x00120011, 721 0x248f, 0xffffffff, 0x000c000b, 722 0x2490, 0xffffffff, 0x000e000d, 723 0x2491, 0xffffffff, 0x00000011, 724 0x2492, 0xffffffff, 0x0010000f, 725 0x2493, 0xffffffff, 0x00130012, 726 0x2494, 0xffffffff, 0x000d000c, 727 0x2495, 0xffffffff, 0x000f000e, 728 0x2496, 0xffffffff, 0x00100013, 729 0x2497, 0xffffffff, 0x00120011, 730 0x2498, 0xffffffff, 0x00150014, 731 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 732 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 733 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 734 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 735 0x000c, 0xffffffff, 0x0000001c, 736 0x000d, 0x000f0000, 0x000f0000, 737 0x0583, 0xffffffff, 0x00000100, 738 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 739 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 740 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 741 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 742 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 743 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 744 0x157a, 0x00000001, 0x00000001, 745 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 746 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 747 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 748 0x3430, 0xfffffff0, 0x00000100, 749 0x3630, 0xfffffff0, 0x00000100, 750 }; 751 752 static const u32 oland_mgcg_cgcg_init[] = 753 { 754 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 755 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 756 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 757 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 758 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 759 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 760 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 761 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 762 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 763 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 764 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 765 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 766 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 767 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 768 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 769 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 770 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 771 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 772 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 773 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 774 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 775 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 776 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 777 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 778 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 779 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 780 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 781 0x2458, 0xffffffff, 0x00010000, 782 0x2459, 0xffffffff, 0x00030002, 783 0x245a, 0xffffffff, 0x00040007, 784 0x245b, 0xffffffff, 0x00060005, 785 0x245c, 0xffffffff, 0x00090008, 786 0x245d, 0xffffffff, 0x00020001, 787 0x245e, 0xffffffff, 0x00040003, 788 0x245f, 0xffffffff, 0x00000007, 789 0x2460, 0xffffffff, 0x00060005, 790 0x2461, 0xffffffff, 0x00090008, 791 0x2462, 0xffffffff, 0x00030002, 792 0x2463, 0xffffffff, 0x00050004, 793 0x2464, 0xffffffff, 0x00000008, 794 0x2465, 0xffffffff, 0x00070006, 795 0x2466, 0xffffffff, 0x000a0009, 796 0x2467, 0xffffffff, 0x00040003, 797 0x2468, 0xffffffff, 0x00060005, 798 0x2469, 0xffffffff, 0x00000009, 799 0x246a, 0xffffffff, 0x00080007, 800 0x246b, 0xffffffff, 0x000b000a, 801 0x246c, 0xffffffff, 0x00050004, 802 0x246d, 0xffffffff, 0x00070006, 803 0x246e, 0xffffffff, 0x0008000b, 804 0x246f, 0xffffffff, 0x000a0009, 805 0x2470, 0xffffffff, 0x000d000c, 806 0x2471, 0xffffffff, 0x00060005, 807 0x2472, 0xffffffff, 0x00080007, 808 0x2473, 0xffffffff, 0x0000000b, 809 0x2474, 0xffffffff, 0x000a0009, 810 0x2475, 0xffffffff, 0x000d000c, 811 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 812 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 813 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 814 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 815 0x000c, 0xffffffff, 0x0000001c, 816 0x000d, 0x000f0000, 0x000f0000, 817 0x0583, 0xffffffff, 0x00000100, 818 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 819 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 820 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 821 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 822 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 823 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 824 0x157a, 0x00000001, 0x00000001, 825 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 826 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 827 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 828 0x3430, 0xfffffff0, 0x00000100, 829 0x3630, 0xfffffff0, 0x00000100, 830 }; 831 832 static const u32 hainan_mgcg_cgcg_init[] = 833 { 834 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 835 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 836 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 837 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 838 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 839 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 840 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 841 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 842 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 843 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 844 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 845 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 846 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 847 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 848 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 849 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 850 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 851 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 852 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 853 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 854 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 855 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 856 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 857 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 858 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 859 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 860 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 861 0x2458, 0xffffffff, 0x00010000, 862 0x2459, 0xffffffff, 0x00030002, 863 0x245a, 0xffffffff, 0x00040007, 864 0x245b, 0xffffffff, 0x00060005, 865 0x245c, 0xffffffff, 0x00090008, 866 0x245d, 0xffffffff, 0x00020001, 867 0x245e, 0xffffffff, 0x00040003, 868 0x245f, 0xffffffff, 0x00000007, 869 0x2460, 0xffffffff, 0x00060005, 870 0x2461, 0xffffffff, 0x00090008, 871 0x2462, 0xffffffff, 0x00030002, 872 0x2463, 0xffffffff, 0x00050004, 873 0x2464, 0xffffffff, 0x00000008, 874 0x2465, 0xffffffff, 0x00070006, 875 0x2466, 0xffffffff, 0x000a0009, 876 0x2467, 0xffffffff, 0x00040003, 877 0x2468, 0xffffffff, 0x00060005, 878 0x2469, 0xffffffff, 0x00000009, 879 0x246a, 0xffffffff, 0x00080007, 880 0x246b, 0xffffffff, 0x000b000a, 881 0x246c, 0xffffffff, 0x00050004, 882 0x246d, 0xffffffff, 0x00070006, 883 0x246e, 0xffffffff, 0x0008000b, 884 0x246f, 0xffffffff, 0x000a0009, 885 0x2470, 0xffffffff, 0x000d000c, 886 0x2471, 0xffffffff, 0x00060005, 887 0x2472, 0xffffffff, 0x00080007, 888 0x2473, 0xffffffff, 0x0000000b, 889 0x2474, 0xffffffff, 0x000a0009, 890 0x2475, 0xffffffff, 0x000d000c, 891 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 892 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 893 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 894 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 895 0x000c, 0xffffffff, 0x0000001c, 896 0x000d, 0x000f0000, 0x000f0000, 897 0x0583, 0xffffffff, 0x00000100, 898 0x0409, 0xffffffff, 0x00000100, 899 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 900 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 901 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 902 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 903 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 904 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 905 0x3430, 0xfffffff0, 0x00000100, 906 0x3630, 0xfffffff0, 0x00000100, 907 }; 908 909 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) 910 { 911 unsigned long flags; 912 u32 r; 913 914 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 915 WREG32(AMDGPU_PCIE_INDEX, reg); 916 (void)RREG32(AMDGPU_PCIE_INDEX); 917 r = RREG32(AMDGPU_PCIE_DATA); 918 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 919 return r; 920 } 921 922 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 923 { 924 unsigned long flags; 925 926 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 927 WREG32(AMDGPU_PCIE_INDEX, reg); 928 (void)RREG32(AMDGPU_PCIE_INDEX); 929 WREG32(AMDGPU_PCIE_DATA, v); 930 (void)RREG32(AMDGPU_PCIE_DATA); 931 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 932 } 933 934 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 935 { 936 unsigned long flags; 937 u32 r; 938 939 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 940 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 941 (void)RREG32(PCIE_PORT_INDEX); 942 r = RREG32(PCIE_PORT_DATA); 943 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 944 return r; 945 } 946 947 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 948 { 949 unsigned long flags; 950 951 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 952 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 953 (void)RREG32(PCIE_PORT_INDEX); 954 WREG32(PCIE_PORT_DATA, (v)); 955 (void)RREG32(PCIE_PORT_DATA); 956 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 957 } 958 959 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) 960 { 961 unsigned long flags; 962 u32 r; 963 964 spin_lock_irqsave(&adev->smc_idx_lock, flags); 965 WREG32(SMC_IND_INDEX_0, (reg)); 966 r = RREG32(SMC_IND_DATA_0); 967 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 968 return r; 969 } 970 971 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 972 { 973 unsigned long flags; 974 975 spin_lock_irqsave(&adev->smc_idx_lock, flags); 976 WREG32(SMC_IND_INDEX_0, (reg)); 977 WREG32(SMC_IND_DATA_0, (v)); 978 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 979 } 980 981 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { 982 {GRBM_STATUS}, 983 {mmGRBM_STATUS2}, 984 {mmGRBM_STATUS_SE0}, 985 {mmGRBM_STATUS_SE1}, 986 {mmSRBM_STATUS}, 987 {mmSRBM_STATUS2}, 988 {DMA_STATUS_REG + DMA0_REGISTER_OFFSET}, 989 {DMA_STATUS_REG + DMA1_REGISTER_OFFSET}, 990 {mmCP_STAT}, 991 {mmCP_STALLED_STAT1}, 992 {mmCP_STALLED_STAT2}, 993 {mmCP_STALLED_STAT3}, 994 {GB_ADDR_CONFIG}, 995 {MC_ARB_RAMCFG}, 996 {GB_TILE_MODE0}, 997 {GB_TILE_MODE1}, 998 {GB_TILE_MODE2}, 999 {GB_TILE_MODE3}, 1000 {GB_TILE_MODE4}, 1001 {GB_TILE_MODE5}, 1002 {GB_TILE_MODE6}, 1003 {GB_TILE_MODE7}, 1004 {GB_TILE_MODE8}, 1005 {GB_TILE_MODE9}, 1006 {GB_TILE_MODE10}, 1007 {GB_TILE_MODE11}, 1008 {GB_TILE_MODE12}, 1009 {GB_TILE_MODE13}, 1010 {GB_TILE_MODE14}, 1011 {GB_TILE_MODE15}, 1012 {GB_TILE_MODE16}, 1013 {GB_TILE_MODE17}, 1014 {GB_TILE_MODE18}, 1015 {GB_TILE_MODE19}, 1016 {GB_TILE_MODE20}, 1017 {GB_TILE_MODE21}, 1018 {GB_TILE_MODE22}, 1019 {GB_TILE_MODE23}, 1020 {GB_TILE_MODE24}, 1021 {GB_TILE_MODE25}, 1022 {GB_TILE_MODE26}, 1023 {GB_TILE_MODE27}, 1024 {GB_TILE_MODE28}, 1025 {GB_TILE_MODE29}, 1026 {GB_TILE_MODE30}, 1027 {GB_TILE_MODE31}, 1028 {CC_RB_BACKEND_DISABLE, true}, 1029 {GC_USER_RB_BACKEND_DISABLE, true}, 1030 {PA_SC_RASTER_CONFIG, true}, 1031 }; 1032 1033 static uint32_t si_get_register_value(struct amdgpu_device *adev, 1034 bool indexed, u32 se_num, 1035 u32 sh_num, u32 reg_offset) 1036 { 1037 if (indexed) { 1038 uint32_t val; 1039 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 1040 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1041 1042 switch (reg_offset) { 1043 case mmCC_RB_BACKEND_DISABLE: 1044 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 1045 case mmGC_USER_RB_BACKEND_DISABLE: 1046 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 1047 case mmPA_SC_RASTER_CONFIG: 1048 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 1049 } 1050 1051 mutex_lock(&adev->grbm_idx_mutex); 1052 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1053 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1054 1055 val = RREG32(reg_offset); 1056 1057 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1058 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1059 mutex_unlock(&adev->grbm_idx_mutex); 1060 return val; 1061 } else { 1062 unsigned idx; 1063 1064 switch (reg_offset) { 1065 case mmGB_ADDR_CONFIG: 1066 return adev->gfx.config.gb_addr_config; 1067 case mmMC_ARB_RAMCFG: 1068 return adev->gfx.config.mc_arb_ramcfg; 1069 case mmGB_TILE_MODE0: 1070 case mmGB_TILE_MODE1: 1071 case mmGB_TILE_MODE2: 1072 case mmGB_TILE_MODE3: 1073 case mmGB_TILE_MODE4: 1074 case mmGB_TILE_MODE5: 1075 case mmGB_TILE_MODE6: 1076 case mmGB_TILE_MODE7: 1077 case mmGB_TILE_MODE8: 1078 case mmGB_TILE_MODE9: 1079 case mmGB_TILE_MODE10: 1080 case mmGB_TILE_MODE11: 1081 case mmGB_TILE_MODE12: 1082 case mmGB_TILE_MODE13: 1083 case mmGB_TILE_MODE14: 1084 case mmGB_TILE_MODE15: 1085 case mmGB_TILE_MODE16: 1086 case mmGB_TILE_MODE17: 1087 case mmGB_TILE_MODE18: 1088 case mmGB_TILE_MODE19: 1089 case mmGB_TILE_MODE20: 1090 case mmGB_TILE_MODE21: 1091 case mmGB_TILE_MODE22: 1092 case mmGB_TILE_MODE23: 1093 case mmGB_TILE_MODE24: 1094 case mmGB_TILE_MODE25: 1095 case mmGB_TILE_MODE26: 1096 case mmGB_TILE_MODE27: 1097 case mmGB_TILE_MODE28: 1098 case mmGB_TILE_MODE29: 1099 case mmGB_TILE_MODE30: 1100 case mmGB_TILE_MODE31: 1101 idx = (reg_offset - mmGB_TILE_MODE0); 1102 return adev->gfx.config.tile_mode_array[idx]; 1103 default: 1104 return RREG32(reg_offset); 1105 } 1106 } 1107 } 1108 static int si_read_register(struct amdgpu_device *adev, u32 se_num, 1109 u32 sh_num, u32 reg_offset, u32 *value) 1110 { 1111 uint32_t i; 1112 1113 *value = 0; 1114 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { 1115 bool indexed = si_allowed_read_registers[i].grbm_indexed; 1116 1117 if (reg_offset != si_allowed_read_registers[i].reg_offset) 1118 continue; 1119 1120 *value = si_get_register_value(adev, indexed, se_num, sh_num, 1121 reg_offset); 1122 return 0; 1123 } 1124 return -EINVAL; 1125 } 1126 1127 static bool si_read_disabled_bios(struct amdgpu_device *adev) 1128 { 1129 u32 bus_cntl; 1130 u32 d1vga_control = 0; 1131 u32 d2vga_control = 0; 1132 u32 vga_render_control = 0; 1133 u32 rom_cntl; 1134 bool r; 1135 1136 bus_cntl = RREG32(R600_BUS_CNTL); 1137 if (adev->mode_info.num_crtc) { 1138 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 1139 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 1140 vga_render_control = RREG32(VGA_RENDER_CONTROL); 1141 } 1142 rom_cntl = RREG32(R600_ROM_CNTL); 1143 1144 /* enable the rom */ 1145 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 1146 if (adev->mode_info.num_crtc) { 1147 /* Disable VGA mode */ 1148 WREG32(AVIVO_D1VGA_CONTROL, 1149 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1150 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1151 WREG32(AVIVO_D2VGA_CONTROL, 1152 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1153 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1154 WREG32(VGA_RENDER_CONTROL, 1155 (vga_render_control & C_000300_VGA_VSTATUS_CNTL)); 1156 } 1157 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 1158 1159 r = amdgpu_read_bios(adev); 1160 1161 /* restore regs */ 1162 WREG32(R600_BUS_CNTL, bus_cntl); 1163 if (adev->mode_info.num_crtc) { 1164 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 1165 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 1166 WREG32(VGA_RENDER_CONTROL, vga_render_control); 1167 } 1168 WREG32(R600_ROM_CNTL, rom_cntl); 1169 return r; 1170 } 1171 1172 #define mmROM_INDEX 0x2A 1173 #define mmROM_DATA 0x2B 1174 1175 static bool si_read_bios_from_rom(struct amdgpu_device *adev, 1176 u8 *bios, u32 length_bytes) 1177 { 1178 u32 *dw_ptr; 1179 u32 i, length_dw; 1180 1181 if (bios == NULL) 1182 return false; 1183 if (length_bytes == 0) 1184 return false; 1185 /* APU vbios image is part of sbios image */ 1186 if (adev->flags & AMD_IS_APU) 1187 return false; 1188 1189 dw_ptr = (u32 *)bios; 1190 length_dw = ALIGN(length_bytes, 4) / 4; 1191 /* set rom index to 0 */ 1192 WREG32(mmROM_INDEX, 0); 1193 for (i = 0; i < length_dw; i++) 1194 dw_ptr[i] = RREG32(mmROM_DATA); 1195 1196 return true; 1197 } 1198 1199 //xxx: not implemented 1200 static int si_asic_reset(struct amdgpu_device *adev) 1201 { 1202 return 0; 1203 } 1204 1205 static bool si_asic_supports_baco(struct amdgpu_device *adev) 1206 { 1207 return false; 1208 } 1209 1210 static enum amd_reset_method 1211 si_asic_reset_method(struct amdgpu_device *adev) 1212 { 1213 return AMD_RESET_METHOD_LEGACY; 1214 } 1215 1216 static u32 si_get_config_memsize(struct amdgpu_device *adev) 1217 { 1218 return RREG32(mmCONFIG_MEMSIZE); 1219 } 1220 1221 static void si_vga_set_state(struct amdgpu_device *adev, bool state) 1222 { 1223 uint32_t temp; 1224 1225 temp = RREG32(CONFIG_CNTL); 1226 if (state == false) { 1227 temp &= ~(1<<0); 1228 temp |= (1<<1); 1229 } else { 1230 temp &= ~(1<<1); 1231 } 1232 WREG32(CONFIG_CNTL, temp); 1233 } 1234 1235 static u32 si_get_xclk(struct amdgpu_device *adev) 1236 { 1237 u32 reference_clock = adev->clock.spll.reference_freq; 1238 u32 tmp; 1239 1240 tmp = RREG32(CG_CLKPIN_CNTL_2); 1241 if (tmp & MUX_TCLK_TO_XCLK) 1242 return TCLK; 1243 1244 tmp = RREG32(CG_CLKPIN_CNTL); 1245 if (tmp & XTALIN_DIVIDE) 1246 return reference_clock / 4; 1247 1248 return reference_clock; 1249 } 1250 1251 //xxx:not implemented 1252 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1253 { 1254 return 0; 1255 } 1256 1257 static void si_detect_hw_virtualization(struct amdgpu_device *adev) 1258 { 1259 if (is_virtual_machine()) /* passthrough mode */ 1260 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 1261 } 1262 1263 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1264 { 1265 if (!ring || !ring->funcs->emit_wreg) { 1266 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1267 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1268 } else { 1269 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1270 } 1271 } 1272 1273 static void si_invalidate_hdp(struct amdgpu_device *adev, 1274 struct amdgpu_ring *ring) 1275 { 1276 if (!ring || !ring->funcs->emit_wreg) { 1277 WREG32(mmHDP_DEBUG0, 1); 1278 RREG32(mmHDP_DEBUG0); 1279 } else { 1280 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1281 } 1282 } 1283 1284 static bool si_need_full_reset(struct amdgpu_device *adev) 1285 { 1286 /* change this when we support soft reset */ 1287 return true; 1288 } 1289 1290 static bool si_need_reset_on_init(struct amdgpu_device *adev) 1291 { 1292 return false; 1293 } 1294 1295 static int si_get_pcie_lanes(struct amdgpu_device *adev) 1296 { 1297 u32 link_width_cntl; 1298 1299 if (adev->flags & AMD_IS_APU) 1300 return 0; 1301 1302 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1303 1304 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { 1305 case LC_LINK_WIDTH_X1: 1306 return 1; 1307 case LC_LINK_WIDTH_X2: 1308 return 2; 1309 case LC_LINK_WIDTH_X4: 1310 return 4; 1311 case LC_LINK_WIDTH_X8: 1312 return 8; 1313 case LC_LINK_WIDTH_X0: 1314 case LC_LINK_WIDTH_X16: 1315 default: 1316 return 16; 1317 } 1318 } 1319 1320 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) 1321 { 1322 u32 link_width_cntl, mask; 1323 1324 if (adev->flags & AMD_IS_APU) 1325 return; 1326 1327 switch (lanes) { 1328 case 0: 1329 mask = LC_LINK_WIDTH_X0; 1330 break; 1331 case 1: 1332 mask = LC_LINK_WIDTH_X1; 1333 break; 1334 case 2: 1335 mask = LC_LINK_WIDTH_X2; 1336 break; 1337 case 4: 1338 mask = LC_LINK_WIDTH_X4; 1339 break; 1340 case 8: 1341 mask = LC_LINK_WIDTH_X8; 1342 break; 1343 case 16: 1344 mask = LC_LINK_WIDTH_X16; 1345 break; 1346 default: 1347 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 1348 return; 1349 } 1350 1351 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1352 link_width_cntl &= ~LC_LINK_WIDTH_MASK; 1353 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; 1354 link_width_cntl |= (LC_RECONFIG_NOW | 1355 LC_RECONFIG_ARC_MISSING_ESCAPE); 1356 1357 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1358 } 1359 1360 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1361 uint64_t *count1) 1362 { 1363 uint32_t perfctr = 0; 1364 uint64_t cnt0_of, cnt1_of; 1365 int tmp; 1366 1367 /* This reports 0 on APUs, so return to avoid writing/reading registers 1368 * that may or may not be different from their GPU counterparts 1369 */ 1370 if (adev->flags & AMD_IS_APU) 1371 return; 1372 1373 /* Set the 2 events that we wish to watch, defined above */ 1374 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1375 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1376 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1377 1378 /* Write to enable desired perf counters */ 1379 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1380 /* Zero out and enable the perf counters 1381 * Write 0x5: 1382 * Bit 0 = Start all counters(1) 1383 * Bit 2 = Global counter reset enable(1) 1384 */ 1385 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1386 1387 msleep(1000); 1388 1389 /* Load the shadow and disable the perf counters 1390 * Write 0x2: 1391 * Bit 0 = Stop counters(0) 1392 * Bit 1 = Load the shadow counters(1) 1393 */ 1394 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1395 1396 /* Read register values to get any >32bit overflow */ 1397 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1398 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1399 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1400 1401 /* Get the values and add the overflow */ 1402 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1403 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1404 } 1405 1406 static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev) 1407 { 1408 uint64_t nak_r, nak_g; 1409 1410 /* Get the number of NAKs received and generated */ 1411 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1412 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1413 1414 /* Add the total number of NAKs, i.e the number of replays */ 1415 return (nak_r + nak_g); 1416 } 1417 1418 static const struct amdgpu_asic_funcs si_asic_funcs = 1419 { 1420 .read_disabled_bios = &si_read_disabled_bios, 1421 .read_bios_from_rom = &si_read_bios_from_rom, 1422 .read_register = &si_read_register, 1423 .reset = &si_asic_reset, 1424 .reset_method = &si_asic_reset_method, 1425 .set_vga_state = &si_vga_set_state, 1426 .get_xclk = &si_get_xclk, 1427 .set_uvd_clocks = &si_set_uvd_clocks, 1428 .set_vce_clocks = NULL, 1429 .get_pcie_lanes = &si_get_pcie_lanes, 1430 .set_pcie_lanes = &si_set_pcie_lanes, 1431 .get_config_memsize = &si_get_config_memsize, 1432 .flush_hdp = &si_flush_hdp, 1433 .invalidate_hdp = &si_invalidate_hdp, 1434 .need_full_reset = &si_need_full_reset, 1435 .get_pcie_usage = &si_get_pcie_usage, 1436 .need_reset_on_init = &si_need_reset_on_init, 1437 .get_pcie_replay_count = &si_get_pcie_replay_count, 1438 .supports_baco = &si_asic_supports_baco, 1439 }; 1440 1441 static uint32_t si_get_rev_id(struct amdgpu_device *adev) 1442 { 1443 return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1444 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1445 } 1446 1447 static int si_common_early_init(void *handle) 1448 { 1449 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1450 1451 adev->smc_rreg = &si_smc_rreg; 1452 adev->smc_wreg = &si_smc_wreg; 1453 adev->pcie_rreg = &si_pcie_rreg; 1454 adev->pcie_wreg = &si_pcie_wreg; 1455 adev->pciep_rreg = &si_pciep_rreg; 1456 adev->pciep_wreg = &si_pciep_wreg; 1457 adev->uvd_ctx_rreg = NULL; 1458 adev->uvd_ctx_wreg = NULL; 1459 adev->didt_rreg = NULL; 1460 adev->didt_wreg = NULL; 1461 1462 adev->asic_funcs = &si_asic_funcs; 1463 1464 adev->rev_id = si_get_rev_id(adev); 1465 adev->external_rev_id = 0xFF; 1466 switch (adev->asic_type) { 1467 case CHIP_TAHITI: 1468 adev->cg_flags = 1469 AMD_CG_SUPPORT_GFX_MGCG | 1470 AMD_CG_SUPPORT_GFX_MGLS | 1471 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1472 AMD_CG_SUPPORT_GFX_CGLS | 1473 AMD_CG_SUPPORT_GFX_CGTS | 1474 AMD_CG_SUPPORT_GFX_CP_LS | 1475 AMD_CG_SUPPORT_MC_MGCG | 1476 AMD_CG_SUPPORT_SDMA_MGCG | 1477 AMD_CG_SUPPORT_BIF_LS | 1478 AMD_CG_SUPPORT_VCE_MGCG | 1479 AMD_CG_SUPPORT_UVD_MGCG | 1480 AMD_CG_SUPPORT_HDP_LS | 1481 AMD_CG_SUPPORT_HDP_MGCG; 1482 adev->pg_flags = 0; 1483 adev->external_rev_id = (adev->rev_id == 0) ? 1 : 1484 (adev->rev_id == 1) ? 5 : 6; 1485 break; 1486 case CHIP_PITCAIRN: 1487 adev->cg_flags = 1488 AMD_CG_SUPPORT_GFX_MGCG | 1489 AMD_CG_SUPPORT_GFX_MGLS | 1490 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1491 AMD_CG_SUPPORT_GFX_CGLS | 1492 AMD_CG_SUPPORT_GFX_CGTS | 1493 AMD_CG_SUPPORT_GFX_CP_LS | 1494 AMD_CG_SUPPORT_GFX_RLC_LS | 1495 AMD_CG_SUPPORT_MC_LS | 1496 AMD_CG_SUPPORT_MC_MGCG | 1497 AMD_CG_SUPPORT_SDMA_MGCG | 1498 AMD_CG_SUPPORT_BIF_LS | 1499 AMD_CG_SUPPORT_VCE_MGCG | 1500 AMD_CG_SUPPORT_UVD_MGCG | 1501 AMD_CG_SUPPORT_HDP_LS | 1502 AMD_CG_SUPPORT_HDP_MGCG; 1503 adev->pg_flags = 0; 1504 adev->external_rev_id = adev->rev_id + 20; 1505 break; 1506 1507 case CHIP_VERDE: 1508 adev->cg_flags = 1509 AMD_CG_SUPPORT_GFX_MGCG | 1510 AMD_CG_SUPPORT_GFX_MGLS | 1511 AMD_CG_SUPPORT_GFX_CGLS | 1512 AMD_CG_SUPPORT_GFX_CGTS | 1513 AMD_CG_SUPPORT_GFX_CGTS_LS | 1514 AMD_CG_SUPPORT_GFX_CP_LS | 1515 AMD_CG_SUPPORT_MC_LS | 1516 AMD_CG_SUPPORT_MC_MGCG | 1517 AMD_CG_SUPPORT_SDMA_MGCG | 1518 AMD_CG_SUPPORT_SDMA_LS | 1519 AMD_CG_SUPPORT_BIF_LS | 1520 AMD_CG_SUPPORT_VCE_MGCG | 1521 AMD_CG_SUPPORT_UVD_MGCG | 1522 AMD_CG_SUPPORT_HDP_LS | 1523 AMD_CG_SUPPORT_HDP_MGCG; 1524 adev->pg_flags = 0; 1525 //??? 1526 adev->external_rev_id = adev->rev_id + 40; 1527 break; 1528 case CHIP_OLAND: 1529 adev->cg_flags = 1530 AMD_CG_SUPPORT_GFX_MGCG | 1531 AMD_CG_SUPPORT_GFX_MGLS | 1532 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1533 AMD_CG_SUPPORT_GFX_CGLS | 1534 AMD_CG_SUPPORT_GFX_CGTS | 1535 AMD_CG_SUPPORT_GFX_CP_LS | 1536 AMD_CG_SUPPORT_GFX_RLC_LS | 1537 AMD_CG_SUPPORT_MC_LS | 1538 AMD_CG_SUPPORT_MC_MGCG | 1539 AMD_CG_SUPPORT_SDMA_MGCG | 1540 AMD_CG_SUPPORT_BIF_LS | 1541 AMD_CG_SUPPORT_UVD_MGCG | 1542 AMD_CG_SUPPORT_HDP_LS | 1543 AMD_CG_SUPPORT_HDP_MGCG; 1544 adev->pg_flags = 0; 1545 adev->external_rev_id = 60; 1546 break; 1547 case CHIP_HAINAN: 1548 adev->cg_flags = 1549 AMD_CG_SUPPORT_GFX_MGCG | 1550 AMD_CG_SUPPORT_GFX_MGLS | 1551 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1552 AMD_CG_SUPPORT_GFX_CGLS | 1553 AMD_CG_SUPPORT_GFX_CGTS | 1554 AMD_CG_SUPPORT_GFX_CP_LS | 1555 AMD_CG_SUPPORT_GFX_RLC_LS | 1556 AMD_CG_SUPPORT_MC_LS | 1557 AMD_CG_SUPPORT_MC_MGCG | 1558 AMD_CG_SUPPORT_SDMA_MGCG | 1559 AMD_CG_SUPPORT_BIF_LS | 1560 AMD_CG_SUPPORT_HDP_LS | 1561 AMD_CG_SUPPORT_HDP_MGCG; 1562 adev->pg_flags = 0; 1563 adev->external_rev_id = 70; 1564 break; 1565 1566 default: 1567 return -EINVAL; 1568 } 1569 1570 return 0; 1571 } 1572 1573 static int si_common_sw_init(void *handle) 1574 { 1575 return 0; 1576 } 1577 1578 static int si_common_sw_fini(void *handle) 1579 { 1580 return 0; 1581 } 1582 1583 1584 static void si_init_golden_registers(struct amdgpu_device *adev) 1585 { 1586 switch (adev->asic_type) { 1587 case CHIP_TAHITI: 1588 amdgpu_device_program_register_sequence(adev, 1589 tahiti_golden_registers, 1590 ARRAY_SIZE(tahiti_golden_registers)); 1591 amdgpu_device_program_register_sequence(adev, 1592 tahiti_golden_rlc_registers, 1593 ARRAY_SIZE(tahiti_golden_rlc_registers)); 1594 amdgpu_device_program_register_sequence(adev, 1595 tahiti_mgcg_cgcg_init, 1596 ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 1597 amdgpu_device_program_register_sequence(adev, 1598 tahiti_golden_registers2, 1599 ARRAY_SIZE(tahiti_golden_registers2)); 1600 break; 1601 case CHIP_PITCAIRN: 1602 amdgpu_device_program_register_sequence(adev, 1603 pitcairn_golden_registers, 1604 ARRAY_SIZE(pitcairn_golden_registers)); 1605 amdgpu_device_program_register_sequence(adev, 1606 pitcairn_golden_rlc_registers, 1607 ARRAY_SIZE(pitcairn_golden_rlc_registers)); 1608 amdgpu_device_program_register_sequence(adev, 1609 pitcairn_mgcg_cgcg_init, 1610 ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 1611 break; 1612 case CHIP_VERDE: 1613 amdgpu_device_program_register_sequence(adev, 1614 verde_golden_registers, 1615 ARRAY_SIZE(verde_golden_registers)); 1616 amdgpu_device_program_register_sequence(adev, 1617 verde_golden_rlc_registers, 1618 ARRAY_SIZE(verde_golden_rlc_registers)); 1619 amdgpu_device_program_register_sequence(adev, 1620 verde_mgcg_cgcg_init, 1621 ARRAY_SIZE(verde_mgcg_cgcg_init)); 1622 amdgpu_device_program_register_sequence(adev, 1623 verde_pg_init, 1624 ARRAY_SIZE(verde_pg_init)); 1625 break; 1626 case CHIP_OLAND: 1627 amdgpu_device_program_register_sequence(adev, 1628 oland_golden_registers, 1629 ARRAY_SIZE(oland_golden_registers)); 1630 amdgpu_device_program_register_sequence(adev, 1631 oland_golden_rlc_registers, 1632 ARRAY_SIZE(oland_golden_rlc_registers)); 1633 amdgpu_device_program_register_sequence(adev, 1634 oland_mgcg_cgcg_init, 1635 ARRAY_SIZE(oland_mgcg_cgcg_init)); 1636 break; 1637 case CHIP_HAINAN: 1638 amdgpu_device_program_register_sequence(adev, 1639 hainan_golden_registers, 1640 ARRAY_SIZE(hainan_golden_registers)); 1641 amdgpu_device_program_register_sequence(adev, 1642 hainan_golden_registers2, 1643 ARRAY_SIZE(hainan_golden_registers2)); 1644 amdgpu_device_program_register_sequence(adev, 1645 hainan_mgcg_cgcg_init, 1646 ARRAY_SIZE(hainan_mgcg_cgcg_init)); 1647 break; 1648 1649 1650 default: 1651 BUG(); 1652 } 1653 } 1654 1655 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 1656 { 1657 struct pci_dev *root = adev->pdev->bus->self; 1658 u32 speed_cntl, current_data_rate; 1659 int i; 1660 u16 tmp16; 1661 1662 if (pci_is_root_bus(adev->pdev->bus)) 1663 return; 1664 1665 if (amdgpu_pcie_gen2 == 0) 1666 return; 1667 1668 if (adev->flags & AMD_IS_APU) 1669 return; 1670 1671 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1672 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 1673 return; 1674 1675 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1676 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> 1677 LC_CURRENT_DATA_RATE_SHIFT; 1678 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1679 if (current_data_rate == 2) { 1680 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1681 return; 1682 } 1683 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1684 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { 1685 if (current_data_rate == 1) { 1686 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1687 return; 1688 } 1689 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1690 } 1691 1692 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1693 return; 1694 1695 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1696 if (current_data_rate != 2) { 1697 u16 bridge_cfg, gpu_cfg; 1698 u16 bridge_cfg2, gpu_cfg2; 1699 u32 max_lw, current_lw, tmp; 1700 1701 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1702 &bridge_cfg); 1703 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1704 &gpu_cfg); 1705 1706 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1707 pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1708 1709 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1710 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1711 tmp16); 1712 1713 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 1714 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; 1715 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; 1716 1717 if (current_lw < max_lw) { 1718 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1719 if (tmp & LC_RENEGOTIATION_SUPPORT) { 1720 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); 1721 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); 1722 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; 1723 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); 1724 } 1725 } 1726 1727 for (i = 0; i < 10; i++) { 1728 pcie_capability_read_word(adev->pdev, 1729 PCI_EXP_DEVSTA, 1730 &tmp16); 1731 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1732 break; 1733 1734 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1735 &bridge_cfg); 1736 pcie_capability_read_word(adev->pdev, 1737 PCI_EXP_LNKCTL, 1738 &gpu_cfg); 1739 1740 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1741 &bridge_cfg2); 1742 pcie_capability_read_word(adev->pdev, 1743 PCI_EXP_LNKCTL2, 1744 &gpu_cfg2); 1745 1746 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1747 tmp |= LC_SET_QUIESCE; 1748 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1749 1750 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1751 tmp |= LC_REDO_EQ; 1752 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1753 1754 mdelay(100); 1755 1756 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1757 &tmp16); 1758 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1759 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1760 pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1761 tmp16); 1762 1763 pcie_capability_read_word(adev->pdev, 1764 PCI_EXP_LNKCTL, 1765 &tmp16); 1766 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1767 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1768 pcie_capability_write_word(adev->pdev, 1769 PCI_EXP_LNKCTL, 1770 tmp16); 1771 1772 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1773 &tmp16); 1774 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1775 PCI_EXP_LNKCTL2_TX_MARGIN); 1776 tmp16 |= (bridge_cfg2 & 1777 (PCI_EXP_LNKCTL2_ENTER_COMP | 1778 PCI_EXP_LNKCTL2_TX_MARGIN)); 1779 pcie_capability_write_word(root, 1780 PCI_EXP_LNKCTL2, 1781 tmp16); 1782 1783 pcie_capability_read_word(adev->pdev, 1784 PCI_EXP_LNKCTL2, 1785 &tmp16); 1786 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1787 PCI_EXP_LNKCTL2_TX_MARGIN); 1788 tmp16 |= (gpu_cfg2 & 1789 (PCI_EXP_LNKCTL2_ENTER_COMP | 1790 PCI_EXP_LNKCTL2_TX_MARGIN)); 1791 pcie_capability_write_word(adev->pdev, 1792 PCI_EXP_LNKCTL2, 1793 tmp16); 1794 1795 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1796 tmp &= ~LC_SET_QUIESCE; 1797 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1798 } 1799 } 1800 } 1801 1802 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; 1803 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 1804 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1805 1806 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1807 tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1808 1809 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1810 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1811 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1812 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1813 else 1814 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1815 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1816 1817 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1818 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; 1819 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1820 1821 for (i = 0; i < adev->usec_timeout; i++) { 1822 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1823 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) 1824 break; 1825 udelay(1); 1826 } 1827 } 1828 1829 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) 1830 { 1831 unsigned long flags; 1832 u32 r; 1833 1834 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1835 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 1836 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 1837 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1838 return r; 1839 } 1840 1841 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1842 { 1843 unsigned long flags; 1844 1845 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1846 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 1847 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 1848 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1849 } 1850 1851 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) 1852 { 1853 unsigned long flags; 1854 u32 r; 1855 1856 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1857 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 1858 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 1859 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1860 return r; 1861 } 1862 1863 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1864 { 1865 unsigned long flags; 1866 1867 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1868 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 1869 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 1870 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1871 } 1872 static void si_program_aspm(struct amdgpu_device *adev) 1873 { 1874 u32 data, orig; 1875 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1876 bool disable_clkreq = false; 1877 1878 if (amdgpu_aspm == 0) 1879 return; 1880 1881 if (adev->flags & AMD_IS_APU) 1882 return; 1883 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 1884 data &= ~LC_XMIT_N_FTS_MASK; 1885 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; 1886 if (orig != data) 1887 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data); 1888 1889 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3); 1890 data |= LC_GO_TO_RECOVERY; 1891 if (orig != data) 1892 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data); 1893 1894 orig = data = RREG32_PCIE(PCIE_P_CNTL); 1895 data |= P_IGNORE_EDB_ERR; 1896 if (orig != data) 1897 WREG32_PCIE(PCIE_P_CNTL, data); 1898 1899 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 1900 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK); 1901 data |= LC_PMI_TO_L1_DIS; 1902 if (!disable_l0s) 1903 data |= LC_L0S_INACTIVITY(7); 1904 1905 if (!disable_l1) { 1906 data |= LC_L1_INACTIVITY(7); 1907 data &= ~LC_PMI_TO_L1_DIS; 1908 if (orig != data) 1909 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 1910 1911 if (!disable_plloff_in_l1) { 1912 bool clk_req_support; 1913 1914 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 1915 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 1916 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 1917 if (orig != data) 1918 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 1919 1920 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 1921 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 1922 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 1923 if (orig != data) 1924 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 1925 1926 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 1927 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 1928 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 1929 if (orig != data) 1930 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 1931 1932 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 1933 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 1934 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 1935 if (orig != data) 1936 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 1937 1938 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { 1939 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 1940 data &= ~PLL_RAMP_UP_TIME_0_MASK; 1941 if (orig != data) 1942 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 1943 1944 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 1945 data &= ~PLL_RAMP_UP_TIME_1_MASK; 1946 if (orig != data) 1947 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 1948 1949 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2); 1950 data &= ~PLL_RAMP_UP_TIME_2_MASK; 1951 if (orig != data) 1952 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data); 1953 1954 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3); 1955 data &= ~PLL_RAMP_UP_TIME_3_MASK; 1956 if (orig != data) 1957 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data); 1958 1959 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 1960 data &= ~PLL_RAMP_UP_TIME_0_MASK; 1961 if (orig != data) 1962 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 1963 1964 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 1965 data &= ~PLL_RAMP_UP_TIME_1_MASK; 1966 if (orig != data) 1967 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 1968 1969 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2); 1970 data &= ~PLL_RAMP_UP_TIME_2_MASK; 1971 if (orig != data) 1972 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data); 1973 1974 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3); 1975 data &= ~PLL_RAMP_UP_TIME_3_MASK; 1976 if (orig != data) 1977 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data); 1978 } 1979 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1980 data &= ~LC_DYN_LANES_PWR_STATE_MASK; 1981 data |= LC_DYN_LANES_PWR_STATE(3); 1982 if (orig != data) 1983 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); 1984 1985 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL); 1986 data &= ~LS2_EXIT_TIME_MASK; 1987 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 1988 data |= LS2_EXIT_TIME(5); 1989 if (orig != data) 1990 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data); 1991 1992 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL); 1993 data &= ~LS2_EXIT_TIME_MASK; 1994 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 1995 data |= LS2_EXIT_TIME(5); 1996 if (orig != data) 1997 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data); 1998 1999 if (!disable_clkreq && 2000 !pci_is_root_bus(adev->pdev->bus)) { 2001 struct pci_dev *root = adev->pdev->bus->self; 2002 u32 lnkcap; 2003 2004 clk_req_support = false; 2005 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 2006 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 2007 clk_req_support = true; 2008 } else { 2009 clk_req_support = false; 2010 } 2011 2012 if (clk_req_support) { 2013 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2); 2014 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23; 2015 if (orig != data) 2016 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data); 2017 2018 orig = data = RREG32(THM_CLK_CNTL); 2019 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK); 2020 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1); 2021 if (orig != data) 2022 WREG32(THM_CLK_CNTL, data); 2023 2024 orig = data = RREG32(MISC_CLK_CNTL); 2025 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK); 2026 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1); 2027 if (orig != data) 2028 WREG32(MISC_CLK_CNTL, data); 2029 2030 orig = data = RREG32(CG_CLKPIN_CNTL); 2031 data &= ~BCLK_AS_XCLK; 2032 if (orig != data) 2033 WREG32(CG_CLKPIN_CNTL, data); 2034 2035 orig = data = RREG32(CG_CLKPIN_CNTL_2); 2036 data &= ~FORCE_BIF_REFCLK_EN; 2037 if (orig != data) 2038 WREG32(CG_CLKPIN_CNTL_2, data); 2039 2040 orig = data = RREG32(MPLL_BYPASSCLK_SEL); 2041 data &= ~MPLL_CLKOUT_SEL_MASK; 2042 data |= MPLL_CLKOUT_SEL(4); 2043 if (orig != data) 2044 WREG32(MPLL_BYPASSCLK_SEL, data); 2045 2046 orig = data = RREG32(SPLL_CNTL_MODE); 2047 data &= ~SPLL_REFCLK_SEL_MASK; 2048 if (orig != data) 2049 WREG32(SPLL_CNTL_MODE, data); 2050 } 2051 } 2052 } else { 2053 if (orig != data) 2054 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2055 } 2056 2057 orig = data = RREG32_PCIE(PCIE_CNTL2); 2058 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN; 2059 if (orig != data) 2060 WREG32_PCIE(PCIE_CNTL2, data); 2061 2062 if (!disable_l0s) { 2063 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 2064 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) { 2065 data = RREG32_PCIE(PCIE_LC_STATUS1); 2066 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) { 2067 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 2068 data &= ~LC_L0S_INACTIVITY_MASK; 2069 if (orig != data) 2070 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2071 } 2072 } 2073 } 2074 } 2075 2076 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) 2077 { 2078 int readrq; 2079 u16 v; 2080 2081 readrq = pcie_get_readrq(adev->pdev); 2082 v = ffs(readrq) - 8; 2083 if ((v == 0) || (v == 6) || (v == 7)) 2084 pcie_set_readrq(adev->pdev, 512); 2085 } 2086 2087 static int si_common_hw_init(void *handle) 2088 { 2089 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2090 2091 si_fix_pci_max_read_req_size(adev); 2092 si_init_golden_registers(adev); 2093 si_pcie_gen3_enable(adev); 2094 si_program_aspm(adev); 2095 2096 return 0; 2097 } 2098 2099 static int si_common_hw_fini(void *handle) 2100 { 2101 return 0; 2102 } 2103 2104 static int si_common_suspend(void *handle) 2105 { 2106 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2107 2108 return si_common_hw_fini(adev); 2109 } 2110 2111 static int si_common_resume(void *handle) 2112 { 2113 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2114 2115 return si_common_hw_init(adev); 2116 } 2117 2118 static bool si_common_is_idle(void *handle) 2119 { 2120 return true; 2121 } 2122 2123 static int si_common_wait_for_idle(void *handle) 2124 { 2125 return 0; 2126 } 2127 2128 static int si_common_soft_reset(void *handle) 2129 { 2130 return 0; 2131 } 2132 2133 static int si_common_set_clockgating_state(void *handle, 2134 enum amd_clockgating_state state) 2135 { 2136 return 0; 2137 } 2138 2139 static int si_common_set_powergating_state(void *handle, 2140 enum amd_powergating_state state) 2141 { 2142 return 0; 2143 } 2144 2145 static const struct amd_ip_funcs si_common_ip_funcs = { 2146 .name = "si_common", 2147 .early_init = si_common_early_init, 2148 .late_init = NULL, 2149 .sw_init = si_common_sw_init, 2150 .sw_fini = si_common_sw_fini, 2151 .hw_init = si_common_hw_init, 2152 .hw_fini = si_common_hw_fini, 2153 .suspend = si_common_suspend, 2154 .resume = si_common_resume, 2155 .is_idle = si_common_is_idle, 2156 .wait_for_idle = si_common_wait_for_idle, 2157 .soft_reset = si_common_soft_reset, 2158 .set_clockgating_state = si_common_set_clockgating_state, 2159 .set_powergating_state = si_common_set_powergating_state, 2160 }; 2161 2162 static const struct amdgpu_ip_block_version si_common_ip_block = 2163 { 2164 .type = AMD_IP_BLOCK_TYPE_COMMON, 2165 .major = 1, 2166 .minor = 0, 2167 .rev = 0, 2168 .funcs = &si_common_ip_funcs, 2169 }; 2170 2171 int si_set_ip_blocks(struct amdgpu_device *adev) 2172 { 2173 si_detect_hw_virtualization(adev); 2174 2175 switch (adev->asic_type) { 2176 case CHIP_VERDE: 2177 case CHIP_TAHITI: 2178 case CHIP_PITCAIRN: 2179 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2180 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2181 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2182 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2183 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2184 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2185 if (adev->enable_virtual_display) 2186 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2187 else 2188 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); 2189 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ 2190 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2191 break; 2192 case CHIP_OLAND: 2193 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2194 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2195 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2196 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2197 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2198 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2199 if (adev->enable_virtual_display) 2200 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2201 else 2202 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); 2203 2204 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ 2205 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2206 break; 2207 case CHIP_HAINAN: 2208 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2209 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2210 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2211 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2212 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2213 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2214 if (adev->enable_virtual_display) 2215 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2216 break; 2217 default: 2218 BUG(); 2219 } 2220 return 0; 2221 } 2222 2223
Indexes created Sun Sep 28 12:09:53 GMT 2025