amdgpu_si.c revision 1.3
1 /* $NetBSD: amdgpu_si.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_si.c,v 1.3 2021/12/19 12:21:29 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <linux/pci.h> 33 34 #include "amdgpu.h" 35 #include "amdgpu_atombios.h" 36 #include "amdgpu_ih.h" 37 #include "amdgpu_uvd.h" 38 #include "amdgpu_vce.h" 39 #include "atom.h" 40 #include "amd_pcie.h" 41 #include "si_dpm.h" 42 #include "sid.h" 43 #include "si_ih.h" 44 #include "gfx_v6_0.h" 45 #include "gmc_v6_0.h" 46 #include "si_dma.h" 47 #include "dce_v6_0.h" 48 #include "si.h" 49 #include "dce_virtual.h" 50 #include "gca/gfx_6_0_d.h" 51 #include "oss/oss_1_0_d.h" 52 #include "gmc/gmc_6_0_d.h" 53 #include "dce/dce_6_0_d.h" 54 #include "uvd/uvd_4_0_d.h" 55 #include "bif/bif_3_0_d.h" 56 #include "bif/bif_3_0_sh_mask.h" 57 58 #include <linux/nbsd-namespace.h> 59 60 static const u32 tahiti_golden_registers[] = 61 { 62 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 63 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 64 mmDB_DEBUG, 0xffffffff, 0x00000000, 65 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 66 mmDB_DEBUG3, 0x0002021c, 0x00020200, 67 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 68 0x340c, 0x000000c0, 0x00800040, 69 0x360c, 0x000000c0, 0x00800040, 70 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 71 mmFBC_MISC, 0x00200000, 0x50100000, 72 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 73 mmMC_ARB_WTM_CNTL_RD, 0x00000003, 0x000007ff, 74 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 75 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 76 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 77 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 78 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 79 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 80 0x000c, 0xffffffff, 0x0040, 81 0x000d, 0x00000040, 0x00004040, 82 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 83 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 84 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 85 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 86 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 87 mmTCP_ADDR_CONFIG, 0x00000200, 0x000002fb, 88 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x0000543b, 89 mmTCP_CHAN_STEER_LO, 0xffffffff, 0xa9210876, 90 mmVGT_FIFO_DEPTHS, 0xffffffff, 0x000fff40, 91 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 92 mmVM_CONTEXT0_CNTL, 0x20000000, 0x20fffed8, 93 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 94 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 95 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 96 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 97 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 98 }; 99 100 static const u32 tahiti_golden_registers2[] = 101 { 102 mmMCIF_MEM_CONTROL, 0x00000001, 0x00000001, 103 }; 104 105 static const u32 tahiti_golden_rlc_registers[] = 106 { 107 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 108 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 109 0x311f, 0xffffffff, 0x10104040, 110 0x3122, 0xffffffff, 0x0100000a, 111 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 112 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 113 mmUVD_CGC_GATE, 0x00000008, 0x00000000, 114 }; 115 116 static const u32 pitcairn_golden_registers[] = 117 { 118 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 119 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 120 mmDB_DEBUG, 0xffffffff, 0x00000000, 121 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 122 mmDB_DEBUG3, 0x0002021c, 0x00020200, 123 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 124 0x340c, 0x000300c0, 0x00800040, 125 0x360c, 0x000300c0, 0x00800040, 126 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 127 mmFBC_MISC, 0x00200000, 0x50100000, 128 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 129 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 130 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 131 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 132 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 133 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 134 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 135 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x2a00126a, 136 0x000c, 0xffffffff, 0x0040, 137 0x000d, 0x00000040, 0x00004040, 138 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 139 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 140 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 141 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, 142 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 143 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x32761054, 144 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 145 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 146 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 147 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 148 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 149 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 150 }; 151 152 static const u32 pitcairn_golden_rlc_registers[] = 153 { 154 mmGB_ADDR_CONFIG, 0xffffffff, 0x12011003, 155 mmRLC_LB_PARAMS, 0xffffffff, 0x00601004, 156 0x311f, 0xffffffff, 0x10102020, 157 0x3122, 0xffffffff, 0x01000020, 158 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 159 mmRLC_LB_CNTL, 0xffffffff, 0x800000a4, 160 }; 161 162 static const u32 verde_pg_init[] = 163 { 164 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x40000, 165 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x200010ff, 166 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 167 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 168 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 169 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 170 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 171 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x7007, 172 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x300010ff, 173 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 174 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 175 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 176 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 177 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 178 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x400000, 179 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x100010ff, 180 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 181 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 182 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 183 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 184 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 185 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x120200, 186 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x500010ff, 187 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 188 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 189 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 190 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 191 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 192 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x1e1e16, 193 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x600010ff, 194 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 195 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 196 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 197 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 198 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 199 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x171f1e, 200 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x700010ff, 201 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 202 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 203 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 204 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 205 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 206 mmGMCON_PGFSM_WRITE, 0xffffffff, 0x0, 207 mmGMCON_PGFSM_CONFIG, 0xffffffff, 0x9ff, 208 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x0, 209 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10000800, 210 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 211 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf, 212 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4, 213 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1000051e, 214 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 215 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xffff, 216 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x8, 217 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x80500, 218 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x12, 219 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x9050c, 220 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1d, 221 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xb052c, 222 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2a, 223 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1053e, 224 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x2d, 225 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10546, 226 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x30, 227 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xa054e, 228 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3c, 229 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1055f, 230 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x3f, 231 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10567, 232 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x42, 233 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1056f, 234 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x45, 235 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x10572, 236 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x48, 237 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20575, 238 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x4c, 239 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x190801, 240 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x67, 241 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1082a, 242 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x6a, 243 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1b082d, 244 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x87, 245 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x310851, 246 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xba, 247 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x891, 248 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbc, 249 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x893, 250 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xbe, 251 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20895, 252 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc2, 253 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x20899, 254 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xc6, 255 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2089d, 256 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xca, 257 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a1, 258 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xcc, 259 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x8a3, 260 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xce, 261 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x308a5, 262 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0xd3, 263 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x6d08cd, 264 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x142, 265 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x2000095a, 266 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x1, 267 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x144, 268 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x301f095b, 269 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x165, 270 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc094d, 271 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x173, 272 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xf096d, 273 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x184, 274 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x15097f, 275 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x19b, 276 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xc0998, 277 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1a9, 278 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x409a7, 279 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1af, 280 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0xcdc, 281 mmGMCON_RENG_RAM_INDEX, 0xffffffff, 0x1b1, 282 mmGMCON_RENG_RAM_DATA, 0xffffffff, 0x800, 283 mmGMCON_RENG_EXECUTE, 0xffffffff, 0x6c9b2000, 284 mmGMCON_MISC2, 0xfc00, 0x2000, 285 mmGMCON_MISC3, 0xffffffff, 0xfc0, 286 mmMC_PMG_AUTO_CFG, 0x00000100, 0x100, 287 }; 288 289 static const u32 verde_golden_rlc_registers[] = 290 { 291 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 292 mmRLC_LB_PARAMS, 0xffffffff, 0x033f1005, 293 0x311f, 0xffffffff, 0x10808020, 294 0x3122, 0xffffffff, 0x00800008, 295 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00001000, 296 mmRLC_LB_CNTL, 0xffffffff, 0x80010014, 297 }; 298 299 static const u32 verde_golden_registers[] = 300 { 301 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 302 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 303 mmDB_DEBUG, 0xffffffff, 0x00000000, 304 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 305 mmDB_DEBUG3, 0x0002021c, 0x00020200, 306 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 307 0x340c, 0x000300c0, 0x00800040, 308 0x360c, 0x000300c0, 0x00800040, 309 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 310 mmFBC_MISC, 0x00200000, 0x50100000, 311 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 312 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 313 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 314 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 315 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 316 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 317 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 318 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x0000124a, 319 0x000c, 0xffffffff, 0x0040, 320 0x000d, 0x00000040, 0x00004040, 321 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 322 mmSQ_DED_CNT, 0x01ff1f3f, 0x00000000, 323 mmSQ_SEC_CNT, 0x01ff1f3f, 0x00000000, 324 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 325 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 326 mmTCP_ADDR_CONFIG, 0x000003ff, 0x00000003, 327 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 328 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00001032, 329 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 330 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 331 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 332 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 333 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 334 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 335 }; 336 337 static const u32 oland_golden_registers[] = 338 { 339 mmAZALIA_SCLK_CONTROL, 0x00000030, 0x00000011, 340 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 341 mmDB_DEBUG, 0xffffffff, 0x00000000, 342 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 343 mmDB_DEBUG3, 0x0002021c, 0x00020200, 344 mmDCI_CLK_CNTL, 0x00000080, 0x00000000, 345 0x340c, 0x000300c0, 0x00800040, 346 0x360c, 0x000300c0, 0x00800040, 347 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, 348 mmFBC_MISC, 0x00200000, 0x50100000, 349 mmDIG0_HDMI_CONTROL, 0x31000311, 0x00000011, 350 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 351 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 352 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 353 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 354 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 355 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 356 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000082, 357 0x000c, 0xffffffff, 0x0040, 358 0x000d, 0x00000040, 0x00004040, 359 mmSPI_CONFIG_CNTL, 0x07ffffff, 0x03000000, 360 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 361 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 362 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, 363 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 364 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 365 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 366 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 367 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 368 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 369 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 370 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 371 372 }; 373 374 static const u32 oland_golden_rlc_registers[] = 375 { 376 mmGB_ADDR_CONFIG, 0xffffffff, 0x02010002, 377 mmRLC_LB_PARAMS, 0xffffffff, 0x00601005, 378 0x311f, 0xffffffff, 0x10104040, 379 0x3122, 0xffffffff, 0x0100000a, 380 mmRLC_LB_CNTR_MAX, 0xffffffff, 0x00000800, 381 mmRLC_LB_CNTL, 0xffffffff, 0x800000f4, 382 }; 383 384 static const u32 hainan_golden_registers[] = 385 { 386 0x17bc, 0x00000030, 0x00000011, 387 mmCB_HW_CONTROL, 0x00010000, 0x00018208, 388 mmDB_DEBUG, 0xffffffff, 0x00000000, 389 mmDB_DEBUG2, 0xf00fffff, 0x00000400, 390 mmDB_DEBUG3, 0x0002021c, 0x00020200, 391 0x031e, 0x00000080, 0x00000000, 392 0x3430, 0xff000fff, 0x00000100, 393 0x340c, 0x000300c0, 0x00800040, 394 0x3630, 0xff000fff, 0x00000100, 395 0x360c, 0x000300c0, 0x00800040, 396 0x16ec, 0x000000f0, 0x00000070, 397 0x16f0, 0x00200000, 0x50100000, 398 0x1c0c, 0x31000311, 0x00000011, 399 mmMC_SEQ_PMG_PG_HWCNTL, 0x00073ffe, 0x000022a2, 400 mmMC_XPB_P2P_BAR_CFG, 0x000007ff, 0x00000000, 401 mmPA_CL_ENHANCE, 0xf000001f, 0x00000007, 402 mmPA_SC_FORCE_EOV_MAX_CNTS, 0xffffffff, 0x00ffffff, 403 mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000, 404 mmPA_SC_MODE_CNTL_1, 0x07ffffff, 0x4e000000, 405 mmPA_SC_RASTER_CONFIG, 0x3f3f3fff, 0x00000000, 406 0x000c, 0xffffffff, 0x0040, 407 0x000d, 0x00000040, 0x00004040, 408 mmSPI_CONFIG_CNTL, 0x03e00000, 0x03600000, 409 mmSX_DEBUG_1, 0x0000007f, 0x00000020, 410 mmTA_CNTL_AUX, 0x00010000, 0x00010000, 411 mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f1, 412 mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, 413 mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, 414 mmVGT_GS_VERTEX_REUSE, 0x0000001f, 0x00000010, 415 mmVM_L2_CG, 0x000c0fc0, 0x000c0400, 416 mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0xffffffff, 417 mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, 418 mmVM_PRT_APERTURE2_LOW_ADDR, 0x0fffffff, 0x0fffffff, 419 mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff, 420 }; 421 422 static const u32 hainan_golden_registers2[] = 423 { 424 mmGB_ADDR_CONFIG, 0xffffffff, 0x2011003, 425 }; 426 427 static const u32 tahiti_mgcg_cgcg_init[] = 428 { 429 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 430 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 431 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 432 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 433 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 434 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 435 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 436 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 437 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 438 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 439 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 440 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 441 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 442 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 443 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 444 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 445 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 446 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 447 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 448 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 449 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 450 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 451 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 452 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 453 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 454 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 455 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 456 0x2458, 0xffffffff, 0x00010000, 457 0x2459, 0xffffffff, 0x00030002, 458 0x245a, 0xffffffff, 0x00040007, 459 0x245b, 0xffffffff, 0x00060005, 460 0x245c, 0xffffffff, 0x00090008, 461 0x245d, 0xffffffff, 0x00020001, 462 0x245e, 0xffffffff, 0x00040003, 463 0x245f, 0xffffffff, 0x00000007, 464 0x2460, 0xffffffff, 0x00060005, 465 0x2461, 0xffffffff, 0x00090008, 466 0x2462, 0xffffffff, 0x00030002, 467 0x2463, 0xffffffff, 0x00050004, 468 0x2464, 0xffffffff, 0x00000008, 469 0x2465, 0xffffffff, 0x00070006, 470 0x2466, 0xffffffff, 0x000a0009, 471 0x2467, 0xffffffff, 0x00040003, 472 0x2468, 0xffffffff, 0x00060005, 473 0x2469, 0xffffffff, 0x00000009, 474 0x246a, 0xffffffff, 0x00080007, 475 0x246b, 0xffffffff, 0x000b000a, 476 0x246c, 0xffffffff, 0x00050004, 477 0x246d, 0xffffffff, 0x00070006, 478 0x246e, 0xffffffff, 0x0008000b, 479 0x246f, 0xffffffff, 0x000a0009, 480 0x2470, 0xffffffff, 0x000d000c, 481 0x2471, 0xffffffff, 0x00060005, 482 0x2472, 0xffffffff, 0x00080007, 483 0x2473, 0xffffffff, 0x0000000b, 484 0x2474, 0xffffffff, 0x000a0009, 485 0x2475, 0xffffffff, 0x000d000c, 486 0x2476, 0xffffffff, 0x00070006, 487 0x2477, 0xffffffff, 0x00090008, 488 0x2478, 0xffffffff, 0x0000000c, 489 0x2479, 0xffffffff, 0x000b000a, 490 0x247a, 0xffffffff, 0x000e000d, 491 0x247b, 0xffffffff, 0x00080007, 492 0x247c, 0xffffffff, 0x000a0009, 493 0x247d, 0xffffffff, 0x0000000d, 494 0x247e, 0xffffffff, 0x000c000b, 495 0x247f, 0xffffffff, 0x000f000e, 496 0x2480, 0xffffffff, 0x00090008, 497 0x2481, 0xffffffff, 0x000b000a, 498 0x2482, 0xffffffff, 0x000c000f, 499 0x2483, 0xffffffff, 0x000e000d, 500 0x2484, 0xffffffff, 0x00110010, 501 0x2485, 0xffffffff, 0x000a0009, 502 0x2486, 0xffffffff, 0x000c000b, 503 0x2487, 0xffffffff, 0x0000000f, 504 0x2488, 0xffffffff, 0x000e000d, 505 0x2489, 0xffffffff, 0x00110010, 506 0x248a, 0xffffffff, 0x000b000a, 507 0x248b, 0xffffffff, 0x000d000c, 508 0x248c, 0xffffffff, 0x00000010, 509 0x248d, 0xffffffff, 0x000f000e, 510 0x248e, 0xffffffff, 0x00120011, 511 0x248f, 0xffffffff, 0x000c000b, 512 0x2490, 0xffffffff, 0x000e000d, 513 0x2491, 0xffffffff, 0x00000011, 514 0x2492, 0xffffffff, 0x0010000f, 515 0x2493, 0xffffffff, 0x00130012, 516 0x2494, 0xffffffff, 0x000d000c, 517 0x2495, 0xffffffff, 0x000f000e, 518 0x2496, 0xffffffff, 0x00100013, 519 0x2497, 0xffffffff, 0x00120011, 520 0x2498, 0xffffffff, 0x00150014, 521 0x2499, 0xffffffff, 0x000e000d, 522 0x249a, 0xffffffff, 0x0010000f, 523 0x249b, 0xffffffff, 0x00000013, 524 0x249c, 0xffffffff, 0x00120011, 525 0x249d, 0xffffffff, 0x00150014, 526 0x249e, 0xffffffff, 0x000f000e, 527 0x249f, 0xffffffff, 0x00110010, 528 0x24a0, 0xffffffff, 0x00000014, 529 0x24a1, 0xffffffff, 0x00130012, 530 0x24a2, 0xffffffff, 0x00160015, 531 0x24a3, 0xffffffff, 0x0010000f, 532 0x24a4, 0xffffffff, 0x00120011, 533 0x24a5, 0xffffffff, 0x00000015, 534 0x24a6, 0xffffffff, 0x00140013, 535 0x24a7, 0xffffffff, 0x00170016, 536 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 537 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 538 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 539 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 540 0x000c, 0xffffffff, 0x0000001c, 541 0x000d, 0x000f0000, 0x000f0000, 542 0x0583, 0xffffffff, 0x00000100, 543 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 544 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 545 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 546 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 547 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 548 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 549 0x157a, 0x00000001, 0x00000001, 550 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 551 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 552 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 553 0x3430, 0xfffffff0, 0x00000100, 554 0x3630, 0xfffffff0, 0x00000100, 555 }; 556 static const u32 pitcairn_mgcg_cgcg_init[] = 557 { 558 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 559 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 560 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 561 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 562 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 563 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 564 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 565 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 566 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 567 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 568 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 569 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 570 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 571 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 572 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 573 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 574 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 575 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 576 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 577 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 578 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 579 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 580 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 581 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 582 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 583 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 584 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 585 0x2458, 0xffffffff, 0x00010000, 586 0x2459, 0xffffffff, 0x00030002, 587 0x245a, 0xffffffff, 0x00040007, 588 0x245b, 0xffffffff, 0x00060005, 589 0x245c, 0xffffffff, 0x00090008, 590 0x245d, 0xffffffff, 0x00020001, 591 0x245e, 0xffffffff, 0x00040003, 592 0x245f, 0xffffffff, 0x00000007, 593 0x2460, 0xffffffff, 0x00060005, 594 0x2461, 0xffffffff, 0x00090008, 595 0x2462, 0xffffffff, 0x00030002, 596 0x2463, 0xffffffff, 0x00050004, 597 0x2464, 0xffffffff, 0x00000008, 598 0x2465, 0xffffffff, 0x00070006, 599 0x2466, 0xffffffff, 0x000a0009, 600 0x2467, 0xffffffff, 0x00040003, 601 0x2468, 0xffffffff, 0x00060005, 602 0x2469, 0xffffffff, 0x00000009, 603 0x246a, 0xffffffff, 0x00080007, 604 0x246b, 0xffffffff, 0x000b000a, 605 0x246c, 0xffffffff, 0x00050004, 606 0x246d, 0xffffffff, 0x00070006, 607 0x246e, 0xffffffff, 0x0008000b, 608 0x246f, 0xffffffff, 0x000a0009, 609 0x2470, 0xffffffff, 0x000d000c, 610 0x2480, 0xffffffff, 0x00090008, 611 0x2481, 0xffffffff, 0x000b000a, 612 0x2482, 0xffffffff, 0x000c000f, 613 0x2483, 0xffffffff, 0x000e000d, 614 0x2484, 0xffffffff, 0x00110010, 615 0x2485, 0xffffffff, 0x000a0009, 616 0x2486, 0xffffffff, 0x000c000b, 617 0x2487, 0xffffffff, 0x0000000f, 618 0x2488, 0xffffffff, 0x000e000d, 619 0x2489, 0xffffffff, 0x00110010, 620 0x248a, 0xffffffff, 0x000b000a, 621 0x248b, 0xffffffff, 0x000d000c, 622 0x248c, 0xffffffff, 0x00000010, 623 0x248d, 0xffffffff, 0x000f000e, 624 0x248e, 0xffffffff, 0x00120011, 625 0x248f, 0xffffffff, 0x000c000b, 626 0x2490, 0xffffffff, 0x000e000d, 627 0x2491, 0xffffffff, 0x00000011, 628 0x2492, 0xffffffff, 0x0010000f, 629 0x2493, 0xffffffff, 0x00130012, 630 0x2494, 0xffffffff, 0x000d000c, 631 0x2495, 0xffffffff, 0x000f000e, 632 0x2496, 0xffffffff, 0x00100013, 633 0x2497, 0xffffffff, 0x00120011, 634 0x2498, 0xffffffff, 0x00150014, 635 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 636 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 637 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 638 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 639 0x000c, 0xffffffff, 0x0000001c, 640 0x000d, 0x000f0000, 0x000f0000, 641 0x0583, 0xffffffff, 0x00000100, 642 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 643 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 644 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 645 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 646 0x157a, 0x00000001, 0x00000001, 647 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 648 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 649 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 650 0x3430, 0xfffffff0, 0x00000100, 651 0x3630, 0xfffffff0, 0x00000100, 652 }; 653 654 static const u32 verde_mgcg_cgcg_init[] = 655 { 656 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 657 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 658 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 659 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 660 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 661 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 662 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 663 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 664 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 665 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 666 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 667 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 668 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 669 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 670 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 671 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 672 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 673 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 674 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 675 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 676 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 677 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 678 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 679 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 680 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 681 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 682 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 683 0x2458, 0xffffffff, 0x00010000, 684 0x2459, 0xffffffff, 0x00030002, 685 0x245a, 0xffffffff, 0x00040007, 686 0x245b, 0xffffffff, 0x00060005, 687 0x245c, 0xffffffff, 0x00090008, 688 0x245d, 0xffffffff, 0x00020001, 689 0x245e, 0xffffffff, 0x00040003, 690 0x245f, 0xffffffff, 0x00000007, 691 0x2460, 0xffffffff, 0x00060005, 692 0x2461, 0xffffffff, 0x00090008, 693 0x2462, 0xffffffff, 0x00030002, 694 0x2463, 0xffffffff, 0x00050004, 695 0x2464, 0xffffffff, 0x00000008, 696 0x2465, 0xffffffff, 0x00070006, 697 0x2466, 0xffffffff, 0x000a0009, 698 0x2467, 0xffffffff, 0x00040003, 699 0x2468, 0xffffffff, 0x00060005, 700 0x2469, 0xffffffff, 0x00000009, 701 0x246a, 0xffffffff, 0x00080007, 702 0x246b, 0xffffffff, 0x000b000a, 703 0x246c, 0xffffffff, 0x00050004, 704 0x246d, 0xffffffff, 0x00070006, 705 0x246e, 0xffffffff, 0x0008000b, 706 0x246f, 0xffffffff, 0x000a0009, 707 0x2470, 0xffffffff, 0x000d000c, 708 0x2480, 0xffffffff, 0x00090008, 709 0x2481, 0xffffffff, 0x000b000a, 710 0x2482, 0xffffffff, 0x000c000f, 711 0x2483, 0xffffffff, 0x000e000d, 712 0x2484, 0xffffffff, 0x00110010, 713 0x2485, 0xffffffff, 0x000a0009, 714 0x2486, 0xffffffff, 0x000c000b, 715 0x2487, 0xffffffff, 0x0000000f, 716 0x2488, 0xffffffff, 0x000e000d, 717 0x2489, 0xffffffff, 0x00110010, 718 0x248a, 0xffffffff, 0x000b000a, 719 0x248b, 0xffffffff, 0x000d000c, 720 0x248c, 0xffffffff, 0x00000010, 721 0x248d, 0xffffffff, 0x000f000e, 722 0x248e, 0xffffffff, 0x00120011, 723 0x248f, 0xffffffff, 0x000c000b, 724 0x2490, 0xffffffff, 0x000e000d, 725 0x2491, 0xffffffff, 0x00000011, 726 0x2492, 0xffffffff, 0x0010000f, 727 0x2493, 0xffffffff, 0x00130012, 728 0x2494, 0xffffffff, 0x000d000c, 729 0x2495, 0xffffffff, 0x000f000e, 730 0x2496, 0xffffffff, 0x00100013, 731 0x2497, 0xffffffff, 0x00120011, 732 0x2498, 0xffffffff, 0x00150014, 733 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 734 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 735 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 736 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 737 0x000c, 0xffffffff, 0x0000001c, 738 0x000d, 0x000f0000, 0x000f0000, 739 0x0583, 0xffffffff, 0x00000100, 740 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 741 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 742 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 743 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 744 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 745 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 746 0x157a, 0x00000001, 0x00000001, 747 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 748 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 749 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 750 0x3430, 0xfffffff0, 0x00000100, 751 0x3630, 0xfffffff0, 0x00000100, 752 }; 753 754 static const u32 oland_mgcg_cgcg_init[] = 755 { 756 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 757 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 758 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 759 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 760 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 761 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 762 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 763 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 764 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 765 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 766 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 767 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 768 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 769 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 770 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 771 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 772 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 773 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 774 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 775 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 776 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 777 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 778 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 779 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 780 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 781 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 782 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 783 0x2458, 0xffffffff, 0x00010000, 784 0x2459, 0xffffffff, 0x00030002, 785 0x245a, 0xffffffff, 0x00040007, 786 0x245b, 0xffffffff, 0x00060005, 787 0x245c, 0xffffffff, 0x00090008, 788 0x245d, 0xffffffff, 0x00020001, 789 0x245e, 0xffffffff, 0x00040003, 790 0x245f, 0xffffffff, 0x00000007, 791 0x2460, 0xffffffff, 0x00060005, 792 0x2461, 0xffffffff, 0x00090008, 793 0x2462, 0xffffffff, 0x00030002, 794 0x2463, 0xffffffff, 0x00050004, 795 0x2464, 0xffffffff, 0x00000008, 796 0x2465, 0xffffffff, 0x00070006, 797 0x2466, 0xffffffff, 0x000a0009, 798 0x2467, 0xffffffff, 0x00040003, 799 0x2468, 0xffffffff, 0x00060005, 800 0x2469, 0xffffffff, 0x00000009, 801 0x246a, 0xffffffff, 0x00080007, 802 0x246b, 0xffffffff, 0x000b000a, 803 0x246c, 0xffffffff, 0x00050004, 804 0x246d, 0xffffffff, 0x00070006, 805 0x246e, 0xffffffff, 0x0008000b, 806 0x246f, 0xffffffff, 0x000a0009, 807 0x2470, 0xffffffff, 0x000d000c, 808 0x2471, 0xffffffff, 0x00060005, 809 0x2472, 0xffffffff, 0x00080007, 810 0x2473, 0xffffffff, 0x0000000b, 811 0x2474, 0xffffffff, 0x000a0009, 812 0x2475, 0xffffffff, 0x000d000c, 813 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 814 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 815 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 816 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 817 0x000c, 0xffffffff, 0x0000001c, 818 0x000d, 0x000f0000, 0x000f0000, 819 0x0583, 0xffffffff, 0x00000100, 820 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100, 821 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000, 822 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 823 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 824 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 825 mmCGTT_DRM_CLK_CTRL0, 0xff000fff, 0x00000100, 826 0x157a, 0x00000001, 0x00000001, 827 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 828 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 829 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 830 0x3430, 0xfffffff0, 0x00000100, 831 0x3630, 0xfffffff0, 0x00000100, 832 }; 833 834 static const u32 hainan_mgcg_cgcg_init[] = 835 { 836 mmRLC_CGTT_MGCG_OVERRIDE, 0xffffffff, 0xfffffffc, 837 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 838 mmCB_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 839 mmCGTT_BCI_CLK_CTRL, 0xffffffff, 0x00000100, 840 mmCGTT_CP_CLK_CTRL, 0xffffffff, 0x00000100, 841 mmCGTT_GDS_CLK_CTRL, 0xffffffff, 0x00000100, 842 mmCGTT_IA_CLK_CTRL, 0xffffffff, 0x06000100, 843 mmCGTT_PA_CLK_CTRL, 0xffffffff, 0x00000100, 844 mmCGTT_PC_CLK_CTRL, 0xffffffff, 0x00000100, 845 mmCGTT_RLC_CLK_CTRL, 0xffffffff, 0x00000100, 846 mmCGTT_SC_CLK_CTRL, 0xffffffff, 0x00000100, 847 mmCGTT_SPI_CLK_CTRL, 0xffffffff, 0x00000100, 848 mmCGTT_SQ_CLK_CTRL, 0xffffffff, 0x00000100, 849 mmCGTT_SQG_CLK_CTRL, 0xffffffff, 0x00000100, 850 mmCGTT_SX_CLK_CTRL0, 0xffffffff, 0x00000100, 851 mmCGTT_SX_CLK_CTRL1, 0xffffffff, 0x00000100, 852 mmCGTT_SX_CLK_CTRL2, 0xffffffff, 0x00000100, 853 mmCGTT_SX_CLK_CTRL3, 0xffffffff, 0x00000100, 854 mmCGTT_TCI_CLK_CTRL, 0xffffffff, 0x00000100, 855 mmCGTT_TCP_CLK_CTRL, 0xffffffff, 0x00000100, 856 mmCGTT_VGT_CLK_CTRL, 0xffffffff, 0x06000100, 857 mmDB_CGTT_CLK_CTRL_0, 0xffffffff, 0x00000100, 858 mmTA_CGTT_CTRL, 0xffffffff, 0x00000100, 859 mmTCA_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 860 mmTCC_CGTT_SCLK_CTRL, 0xffffffff, 0x00000100, 861 mmTD_CGTT_CTRL, 0xffffffff, 0x00000100, 862 mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, 863 0x2458, 0xffffffff, 0x00010000, 864 0x2459, 0xffffffff, 0x00030002, 865 0x245a, 0xffffffff, 0x00040007, 866 0x245b, 0xffffffff, 0x00060005, 867 0x245c, 0xffffffff, 0x00090008, 868 0x245d, 0xffffffff, 0x00020001, 869 0x245e, 0xffffffff, 0x00040003, 870 0x245f, 0xffffffff, 0x00000007, 871 0x2460, 0xffffffff, 0x00060005, 872 0x2461, 0xffffffff, 0x00090008, 873 0x2462, 0xffffffff, 0x00030002, 874 0x2463, 0xffffffff, 0x00050004, 875 0x2464, 0xffffffff, 0x00000008, 876 0x2465, 0xffffffff, 0x00070006, 877 0x2466, 0xffffffff, 0x000a0009, 878 0x2467, 0xffffffff, 0x00040003, 879 0x2468, 0xffffffff, 0x00060005, 880 0x2469, 0xffffffff, 0x00000009, 881 0x246a, 0xffffffff, 0x00080007, 882 0x246b, 0xffffffff, 0x000b000a, 883 0x246c, 0xffffffff, 0x00050004, 884 0x246d, 0xffffffff, 0x00070006, 885 0x246e, 0xffffffff, 0x0008000b, 886 0x246f, 0xffffffff, 0x000a0009, 887 0x2470, 0xffffffff, 0x000d000c, 888 0x2471, 0xffffffff, 0x00060005, 889 0x2472, 0xffffffff, 0x00080007, 890 0x2473, 0xffffffff, 0x0000000b, 891 0x2474, 0xffffffff, 0x000a0009, 892 0x2475, 0xffffffff, 0x000d000c, 893 mmCGTS_SM_CTRL_REG, 0xffffffff, 0x96940200, 894 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100, 895 mmRLC_GCPM_GENERAL_3, 0xffffffff, 0x00000080, 896 mmRLC_CGCG_CGLS_CTRL, 0xffffffff, 0x0020003f, 897 0x000c, 0xffffffff, 0x0000001c, 898 0x000d, 0x000f0000, 0x000f0000, 899 0x0583, 0xffffffff, 0x00000100, 900 0x0409, 0xffffffff, 0x00000100, 901 mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104, 902 mmMC_CITF_MISC_WR_CG, 0x000c0000, 0x000c0000, 903 mmMC_CITF_MISC_RD_CG, 0x000c0000, 0x000c0000, 904 mmHDP_MEM_POWER_LS, 0x00000001, 0x00000001, 905 mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104, 906 mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, 907 0x3430, 0xfffffff0, 0x00000100, 908 0x3630, 0xfffffff0, 0x00000100, 909 }; 910 911 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg) 912 { 913 unsigned long flags; 914 u32 r; 915 916 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 917 WREG32(AMDGPU_PCIE_INDEX, reg); 918 (void)RREG32(AMDGPU_PCIE_INDEX); 919 r = RREG32(AMDGPU_PCIE_DATA); 920 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 921 return r; 922 } 923 924 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 925 { 926 unsigned long flags; 927 928 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 929 WREG32(AMDGPU_PCIE_INDEX, reg); 930 (void)RREG32(AMDGPU_PCIE_INDEX); 931 WREG32(AMDGPU_PCIE_DATA, v); 932 (void)RREG32(AMDGPU_PCIE_DATA); 933 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 934 } 935 936 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) 937 { 938 unsigned long flags; 939 u32 r; 940 941 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 942 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 943 (void)RREG32(PCIE_PORT_INDEX); 944 r = RREG32(PCIE_PORT_DATA); 945 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 946 return r; 947 } 948 949 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 950 { 951 unsigned long flags; 952 953 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 954 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 955 (void)RREG32(PCIE_PORT_INDEX); 956 WREG32(PCIE_PORT_DATA, (v)); 957 (void)RREG32(PCIE_PORT_DATA); 958 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 959 } 960 961 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) 962 { 963 unsigned long flags; 964 u32 r; 965 966 spin_lock_irqsave(&adev->smc_idx_lock, flags); 967 WREG32(SMC_IND_INDEX_0, (reg)); 968 r = RREG32(SMC_IND_DATA_0); 969 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 970 return r; 971 } 972 973 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 974 { 975 unsigned long flags; 976 977 spin_lock_irqsave(&adev->smc_idx_lock, flags); 978 WREG32(SMC_IND_INDEX_0, (reg)); 979 WREG32(SMC_IND_DATA_0, (v)); 980 spin_unlock_irqrestore(&adev->smc_idx_lock, flags); 981 } 982 983 static struct amdgpu_allowed_register_entry si_allowed_read_registers[] = { 984 {GRBM_STATUS}, 985 {mmGRBM_STATUS2}, 986 {mmGRBM_STATUS_SE0}, 987 {mmGRBM_STATUS_SE1}, 988 {mmSRBM_STATUS}, 989 {mmSRBM_STATUS2}, 990 {DMA_STATUS_REG + DMA0_REGISTER_OFFSET}, 991 {DMA_STATUS_REG + DMA1_REGISTER_OFFSET}, 992 {mmCP_STAT}, 993 {mmCP_STALLED_STAT1}, 994 {mmCP_STALLED_STAT2}, 995 {mmCP_STALLED_STAT3}, 996 {GB_ADDR_CONFIG}, 997 {MC_ARB_RAMCFG}, 998 {GB_TILE_MODE0}, 999 {GB_TILE_MODE1}, 1000 {GB_TILE_MODE2}, 1001 {GB_TILE_MODE3}, 1002 {GB_TILE_MODE4}, 1003 {GB_TILE_MODE5}, 1004 {GB_TILE_MODE6}, 1005 {GB_TILE_MODE7}, 1006 {GB_TILE_MODE8}, 1007 {GB_TILE_MODE9}, 1008 {GB_TILE_MODE10}, 1009 {GB_TILE_MODE11}, 1010 {GB_TILE_MODE12}, 1011 {GB_TILE_MODE13}, 1012 {GB_TILE_MODE14}, 1013 {GB_TILE_MODE15}, 1014 {GB_TILE_MODE16}, 1015 {GB_TILE_MODE17}, 1016 {GB_TILE_MODE18}, 1017 {GB_TILE_MODE19}, 1018 {GB_TILE_MODE20}, 1019 {GB_TILE_MODE21}, 1020 {GB_TILE_MODE22}, 1021 {GB_TILE_MODE23}, 1022 {GB_TILE_MODE24}, 1023 {GB_TILE_MODE25}, 1024 {GB_TILE_MODE26}, 1025 {GB_TILE_MODE27}, 1026 {GB_TILE_MODE28}, 1027 {GB_TILE_MODE29}, 1028 {GB_TILE_MODE30}, 1029 {GB_TILE_MODE31}, 1030 {CC_RB_BACKEND_DISABLE, true}, 1031 {GC_USER_RB_BACKEND_DISABLE, true}, 1032 {PA_SC_RASTER_CONFIG, true}, 1033 }; 1034 1035 static uint32_t si_get_register_value(struct amdgpu_device *adev, 1036 bool indexed, u32 se_num, 1037 u32 sh_num, u32 reg_offset) 1038 { 1039 if (indexed) { 1040 uint32_t val; 1041 unsigned se_idx = (se_num == 0xffffffff) ? 0 : se_num; 1042 unsigned sh_idx = (sh_num == 0xffffffff) ? 0 : sh_num; 1043 1044 switch (reg_offset) { 1045 case mmCC_RB_BACKEND_DISABLE: 1046 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable; 1047 case mmGC_USER_RB_BACKEND_DISABLE: 1048 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable; 1049 case mmPA_SC_RASTER_CONFIG: 1050 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config; 1051 } 1052 1053 mutex_lock(&adev->grbm_idx_mutex); 1054 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1055 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff); 1056 1057 val = RREG32(reg_offset); 1058 1059 if (se_num != 0xffffffff || sh_num != 0xffffffff) 1060 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff); 1061 mutex_unlock(&adev->grbm_idx_mutex); 1062 return val; 1063 } else { 1064 unsigned idx; 1065 1066 switch (reg_offset) { 1067 case mmGB_ADDR_CONFIG: 1068 return adev->gfx.config.gb_addr_config; 1069 case mmMC_ARB_RAMCFG: 1070 return adev->gfx.config.mc_arb_ramcfg; 1071 case mmGB_TILE_MODE0: 1072 case mmGB_TILE_MODE1: 1073 case mmGB_TILE_MODE2: 1074 case mmGB_TILE_MODE3: 1075 case mmGB_TILE_MODE4: 1076 case mmGB_TILE_MODE5: 1077 case mmGB_TILE_MODE6: 1078 case mmGB_TILE_MODE7: 1079 case mmGB_TILE_MODE8: 1080 case mmGB_TILE_MODE9: 1081 case mmGB_TILE_MODE10: 1082 case mmGB_TILE_MODE11: 1083 case mmGB_TILE_MODE12: 1084 case mmGB_TILE_MODE13: 1085 case mmGB_TILE_MODE14: 1086 case mmGB_TILE_MODE15: 1087 case mmGB_TILE_MODE16: 1088 case mmGB_TILE_MODE17: 1089 case mmGB_TILE_MODE18: 1090 case mmGB_TILE_MODE19: 1091 case mmGB_TILE_MODE20: 1092 case mmGB_TILE_MODE21: 1093 case mmGB_TILE_MODE22: 1094 case mmGB_TILE_MODE23: 1095 case mmGB_TILE_MODE24: 1096 case mmGB_TILE_MODE25: 1097 case mmGB_TILE_MODE26: 1098 case mmGB_TILE_MODE27: 1099 case mmGB_TILE_MODE28: 1100 case mmGB_TILE_MODE29: 1101 case mmGB_TILE_MODE30: 1102 case mmGB_TILE_MODE31: 1103 idx = (reg_offset - mmGB_TILE_MODE0); 1104 return adev->gfx.config.tile_mode_array[idx]; 1105 default: 1106 return RREG32(reg_offset); 1107 } 1108 } 1109 } 1110 static int si_read_register(struct amdgpu_device *adev, u32 se_num, 1111 u32 sh_num, u32 reg_offset, u32 *value) 1112 { 1113 uint32_t i; 1114 1115 *value = 0; 1116 for (i = 0; i < ARRAY_SIZE(si_allowed_read_registers); i++) { 1117 bool indexed = si_allowed_read_registers[i].grbm_indexed; 1118 1119 if (reg_offset != si_allowed_read_registers[i].reg_offset) 1120 continue; 1121 1122 *value = si_get_register_value(adev, indexed, se_num, sh_num, 1123 reg_offset); 1124 return 0; 1125 } 1126 return -EINVAL; 1127 } 1128 1129 static bool si_read_disabled_bios(struct amdgpu_device *adev) 1130 { 1131 u32 bus_cntl; 1132 u32 d1vga_control = 0; 1133 u32 d2vga_control = 0; 1134 u32 vga_render_control = 0; 1135 u32 rom_cntl; 1136 bool r; 1137 1138 bus_cntl = RREG32(R600_BUS_CNTL); 1139 if (adev->mode_info.num_crtc) { 1140 d1vga_control = RREG32(AVIVO_D1VGA_CONTROL); 1141 d2vga_control = RREG32(AVIVO_D2VGA_CONTROL); 1142 vga_render_control = RREG32(VGA_RENDER_CONTROL); 1143 } 1144 rom_cntl = RREG32(R600_ROM_CNTL); 1145 1146 /* enable the rom */ 1147 WREG32(R600_BUS_CNTL, (bus_cntl & ~R600_BIOS_ROM_DIS)); 1148 if (adev->mode_info.num_crtc) { 1149 /* Disable VGA mode */ 1150 WREG32(AVIVO_D1VGA_CONTROL, 1151 (d1vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1152 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1153 WREG32(AVIVO_D2VGA_CONTROL, 1154 (d2vga_control & ~(AVIVO_DVGA_CONTROL_MODE_ENABLE | 1155 AVIVO_DVGA_CONTROL_TIMING_SELECT))); 1156 WREG32(VGA_RENDER_CONTROL, 1157 (vga_render_control & C_000300_VGA_VSTATUS_CNTL)); 1158 } 1159 WREG32(R600_ROM_CNTL, rom_cntl | R600_SCK_OVERWRITE); 1160 1161 r = amdgpu_read_bios(adev); 1162 1163 /* restore regs */ 1164 WREG32(R600_BUS_CNTL, bus_cntl); 1165 if (adev->mode_info.num_crtc) { 1166 WREG32(AVIVO_D1VGA_CONTROL, d1vga_control); 1167 WREG32(AVIVO_D2VGA_CONTROL, d2vga_control); 1168 WREG32(VGA_RENDER_CONTROL, vga_render_control); 1169 } 1170 WREG32(R600_ROM_CNTL, rom_cntl); 1171 return r; 1172 } 1173 1174 #define mmROM_INDEX 0x2A 1175 #define mmROM_DATA 0x2B 1176 1177 static bool si_read_bios_from_rom(struct amdgpu_device *adev, 1178 u8 *bios, u32 length_bytes) 1179 { 1180 u32 *dw_ptr; 1181 u32 i, length_dw; 1182 1183 if (bios == NULL) 1184 return false; 1185 if (length_bytes == 0) 1186 return false; 1187 /* APU vbios image is part of sbios image */ 1188 if (adev->flags & AMD_IS_APU) 1189 return false; 1190 1191 dw_ptr = (u32 *)bios; 1192 length_dw = ALIGN(length_bytes, 4) / 4; 1193 /* set rom index to 0 */ 1194 WREG32(mmROM_INDEX, 0); 1195 for (i = 0; i < length_dw; i++) 1196 dw_ptr[i] = RREG32(mmROM_DATA); 1197 1198 return true; 1199 } 1200 1201 //xxx: not implemented 1202 static int si_asic_reset(struct amdgpu_device *adev) 1203 { 1204 return 0; 1205 } 1206 1207 static bool si_asic_supports_baco(struct amdgpu_device *adev) 1208 { 1209 return false; 1210 } 1211 1212 static enum amd_reset_method 1213 si_asic_reset_method(struct amdgpu_device *adev) 1214 { 1215 return AMD_RESET_METHOD_LEGACY; 1216 } 1217 1218 static u32 si_get_config_memsize(struct amdgpu_device *adev) 1219 { 1220 return RREG32(mmCONFIG_MEMSIZE); 1221 } 1222 1223 static void si_vga_set_state(struct amdgpu_device *adev, bool state) 1224 { 1225 uint32_t temp; 1226 1227 temp = RREG32(CONFIG_CNTL); 1228 if (state == false) { 1229 temp &= ~(1<<0); 1230 temp |= (1<<1); 1231 } else { 1232 temp &= ~(1<<1); 1233 } 1234 WREG32(CONFIG_CNTL, temp); 1235 } 1236 1237 static u32 si_get_xclk(struct amdgpu_device *adev) 1238 { 1239 u32 reference_clock = adev->clock.spll.reference_freq; 1240 u32 tmp; 1241 1242 tmp = RREG32(CG_CLKPIN_CNTL_2); 1243 if (tmp & MUX_TCLK_TO_XCLK) 1244 return TCLK; 1245 1246 tmp = RREG32(CG_CLKPIN_CNTL); 1247 if (tmp & XTALIN_DIVIDE) 1248 return reference_clock / 4; 1249 1250 return reference_clock; 1251 } 1252 1253 //xxx:not implemented 1254 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk) 1255 { 1256 return 0; 1257 } 1258 1259 static void si_detect_hw_virtualization(struct amdgpu_device *adev) 1260 { 1261 if (is_virtual_machine()) /* passthrough mode */ 1262 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE; 1263 } 1264 1265 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) 1266 { 1267 if (!ring || !ring->funcs->emit_wreg) { 1268 WREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1269 RREG32(mmHDP_MEM_COHERENCY_FLUSH_CNTL); 1270 } else { 1271 amdgpu_ring_emit_wreg(ring, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 1); 1272 } 1273 } 1274 1275 static void si_invalidate_hdp(struct amdgpu_device *adev, 1276 struct amdgpu_ring *ring) 1277 { 1278 if (!ring || !ring->funcs->emit_wreg) { 1279 WREG32(mmHDP_DEBUG0, 1); 1280 RREG32(mmHDP_DEBUG0); 1281 } else { 1282 amdgpu_ring_emit_wreg(ring, mmHDP_DEBUG0, 1); 1283 } 1284 } 1285 1286 static bool si_need_full_reset(struct amdgpu_device *adev) 1287 { 1288 /* change this when we support soft reset */ 1289 return true; 1290 } 1291 1292 static bool si_need_reset_on_init(struct amdgpu_device *adev) 1293 { 1294 return false; 1295 } 1296 1297 static int si_get_pcie_lanes(struct amdgpu_device *adev) 1298 { 1299 u32 link_width_cntl; 1300 1301 if (adev->flags & AMD_IS_APU) 1302 return 0; 1303 1304 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1305 1306 switch ((link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT) { 1307 case LC_LINK_WIDTH_X1: 1308 return 1; 1309 case LC_LINK_WIDTH_X2: 1310 return 2; 1311 case LC_LINK_WIDTH_X4: 1312 return 4; 1313 case LC_LINK_WIDTH_X8: 1314 return 8; 1315 case LC_LINK_WIDTH_X0: 1316 case LC_LINK_WIDTH_X16: 1317 default: 1318 return 16; 1319 } 1320 } 1321 1322 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes) 1323 { 1324 u32 link_width_cntl, mask; 1325 1326 if (adev->flags & AMD_IS_APU) 1327 return; 1328 1329 switch (lanes) { 1330 case 0: 1331 mask = LC_LINK_WIDTH_X0; 1332 break; 1333 case 1: 1334 mask = LC_LINK_WIDTH_X1; 1335 break; 1336 case 2: 1337 mask = LC_LINK_WIDTH_X2; 1338 break; 1339 case 4: 1340 mask = LC_LINK_WIDTH_X4; 1341 break; 1342 case 8: 1343 mask = LC_LINK_WIDTH_X8; 1344 break; 1345 case 16: 1346 mask = LC_LINK_WIDTH_X16; 1347 break; 1348 default: 1349 DRM_ERROR("invalid pcie lane request: %d\n", lanes); 1350 return; 1351 } 1352 1353 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1354 link_width_cntl &= ~LC_LINK_WIDTH_MASK; 1355 link_width_cntl |= mask << LC_LINK_WIDTH_SHIFT; 1356 link_width_cntl |= (LC_RECONFIG_NOW | 1357 LC_RECONFIG_ARC_MISSING_ESCAPE); 1358 1359 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl); 1360 } 1361 1362 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0, 1363 uint64_t *count1) 1364 { 1365 uint32_t perfctr = 0; 1366 uint64_t cnt0_of, cnt1_of; 1367 int tmp; 1368 1369 /* This reports 0 on APUs, so return to avoid writing/reading registers 1370 * that may or may not be different from their GPU counterparts 1371 */ 1372 if (adev->flags & AMD_IS_APU) 1373 return; 1374 1375 /* Set the 2 events that we wish to watch, defined above */ 1376 /* Reg 40 is # received msgs, Reg 104 is # of posted requests sent */ 1377 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT0_SEL, 40); 1378 perfctr = REG_SET_FIELD(perfctr, PCIE_PERF_CNTL_TXCLK, EVENT1_SEL, 104); 1379 1380 /* Write to enable desired perf counters */ 1381 WREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK, perfctr); 1382 /* Zero out and enable the perf counters 1383 * Write 0x5: 1384 * Bit 0 = Start all counters(1) 1385 * Bit 2 = Global counter reset enable(1) 1386 */ 1387 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000005); 1388 1389 msleep(1000); 1390 1391 /* Load the shadow and disable the perf counters 1392 * Write 0x2: 1393 * Bit 0 = Stop counters(0) 1394 * Bit 1 = Load the shadow counters(1) 1395 */ 1396 WREG32_PCIE(ixPCIE_PERF_COUNT_CNTL, 0x00000002); 1397 1398 /* Read register values to get any >32bit overflow */ 1399 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); 1400 cnt0_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER0_UPPER); 1401 cnt1_of = REG_GET_FIELD(tmp, PCIE_PERF_CNTL_TXCLK, COUNTER1_UPPER); 1402 1403 /* Get the values and add the overflow */ 1404 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); 1405 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); 1406 } 1407 1408 static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev) 1409 { 1410 uint64_t nak_r, nak_g; 1411 1412 /* Get the number of NAKs received and generated */ 1413 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); 1414 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); 1415 1416 /* Add the total number of NAKs, i.e the number of replays */ 1417 return (nak_r + nak_g); 1418 } 1419 1420 static const struct amdgpu_asic_funcs si_asic_funcs = 1421 { 1422 .read_disabled_bios = &si_read_disabled_bios, 1423 .read_bios_from_rom = &si_read_bios_from_rom, 1424 .read_register = &si_read_register, 1425 .reset = &si_asic_reset, 1426 .reset_method = &si_asic_reset_method, 1427 .set_vga_state = &si_vga_set_state, 1428 .get_xclk = &si_get_xclk, 1429 .set_uvd_clocks = &si_set_uvd_clocks, 1430 .set_vce_clocks = NULL, 1431 .get_pcie_lanes = &si_get_pcie_lanes, 1432 .set_pcie_lanes = &si_set_pcie_lanes, 1433 .get_config_memsize = &si_get_config_memsize, 1434 .flush_hdp = &si_flush_hdp, 1435 .invalidate_hdp = &si_invalidate_hdp, 1436 .need_full_reset = &si_need_full_reset, 1437 .get_pcie_usage = &si_get_pcie_usage, 1438 .need_reset_on_init = &si_need_reset_on_init, 1439 .get_pcie_replay_count = &si_get_pcie_replay_count, 1440 .supports_baco = &si_asic_supports_baco, 1441 }; 1442 1443 static uint32_t si_get_rev_id(struct amdgpu_device *adev) 1444 { 1445 return (RREG32(CC_DRM_ID_STRAPS) & CC_DRM_ID_STRAPS__ATI_REV_ID_MASK) 1446 >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; 1447 } 1448 1449 static int si_common_early_init(void *handle) 1450 { 1451 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 1452 1453 adev->smc_rreg = &si_smc_rreg; 1454 adev->smc_wreg = &si_smc_wreg; 1455 adev->pcie_rreg = &si_pcie_rreg; 1456 adev->pcie_wreg = &si_pcie_wreg; 1457 adev->pciep_rreg = &si_pciep_rreg; 1458 adev->pciep_wreg = &si_pciep_wreg; 1459 adev->uvd_ctx_rreg = NULL; 1460 adev->uvd_ctx_wreg = NULL; 1461 adev->didt_rreg = NULL; 1462 adev->didt_wreg = NULL; 1463 1464 adev->asic_funcs = &si_asic_funcs; 1465 1466 adev->rev_id = si_get_rev_id(adev); 1467 adev->external_rev_id = 0xFF; 1468 switch (adev->asic_type) { 1469 case CHIP_TAHITI: 1470 adev->cg_flags = 1471 AMD_CG_SUPPORT_GFX_MGCG | 1472 AMD_CG_SUPPORT_GFX_MGLS | 1473 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1474 AMD_CG_SUPPORT_GFX_CGLS | 1475 AMD_CG_SUPPORT_GFX_CGTS | 1476 AMD_CG_SUPPORT_GFX_CP_LS | 1477 AMD_CG_SUPPORT_MC_MGCG | 1478 AMD_CG_SUPPORT_SDMA_MGCG | 1479 AMD_CG_SUPPORT_BIF_LS | 1480 AMD_CG_SUPPORT_VCE_MGCG | 1481 AMD_CG_SUPPORT_UVD_MGCG | 1482 AMD_CG_SUPPORT_HDP_LS | 1483 AMD_CG_SUPPORT_HDP_MGCG; 1484 adev->pg_flags = 0; 1485 adev->external_rev_id = (adev->rev_id == 0) ? 1 : 1486 (adev->rev_id == 1) ? 5 : 6; 1487 break; 1488 case CHIP_PITCAIRN: 1489 adev->cg_flags = 1490 AMD_CG_SUPPORT_GFX_MGCG | 1491 AMD_CG_SUPPORT_GFX_MGLS | 1492 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1493 AMD_CG_SUPPORT_GFX_CGLS | 1494 AMD_CG_SUPPORT_GFX_CGTS | 1495 AMD_CG_SUPPORT_GFX_CP_LS | 1496 AMD_CG_SUPPORT_GFX_RLC_LS | 1497 AMD_CG_SUPPORT_MC_LS | 1498 AMD_CG_SUPPORT_MC_MGCG | 1499 AMD_CG_SUPPORT_SDMA_MGCG | 1500 AMD_CG_SUPPORT_BIF_LS | 1501 AMD_CG_SUPPORT_VCE_MGCG | 1502 AMD_CG_SUPPORT_UVD_MGCG | 1503 AMD_CG_SUPPORT_HDP_LS | 1504 AMD_CG_SUPPORT_HDP_MGCG; 1505 adev->pg_flags = 0; 1506 adev->external_rev_id = adev->rev_id + 20; 1507 break; 1508 1509 case CHIP_VERDE: 1510 adev->cg_flags = 1511 AMD_CG_SUPPORT_GFX_MGCG | 1512 AMD_CG_SUPPORT_GFX_MGLS | 1513 AMD_CG_SUPPORT_GFX_CGLS | 1514 AMD_CG_SUPPORT_GFX_CGTS | 1515 AMD_CG_SUPPORT_GFX_CGTS_LS | 1516 AMD_CG_SUPPORT_GFX_CP_LS | 1517 AMD_CG_SUPPORT_MC_LS | 1518 AMD_CG_SUPPORT_MC_MGCG | 1519 AMD_CG_SUPPORT_SDMA_MGCG | 1520 AMD_CG_SUPPORT_SDMA_LS | 1521 AMD_CG_SUPPORT_BIF_LS | 1522 AMD_CG_SUPPORT_VCE_MGCG | 1523 AMD_CG_SUPPORT_UVD_MGCG | 1524 AMD_CG_SUPPORT_HDP_LS | 1525 AMD_CG_SUPPORT_HDP_MGCG; 1526 adev->pg_flags = 0; 1527 //??? 1528 adev->external_rev_id = adev->rev_id + 40; 1529 break; 1530 case CHIP_OLAND: 1531 adev->cg_flags = 1532 AMD_CG_SUPPORT_GFX_MGCG | 1533 AMD_CG_SUPPORT_GFX_MGLS | 1534 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1535 AMD_CG_SUPPORT_GFX_CGLS | 1536 AMD_CG_SUPPORT_GFX_CGTS | 1537 AMD_CG_SUPPORT_GFX_CP_LS | 1538 AMD_CG_SUPPORT_GFX_RLC_LS | 1539 AMD_CG_SUPPORT_MC_LS | 1540 AMD_CG_SUPPORT_MC_MGCG | 1541 AMD_CG_SUPPORT_SDMA_MGCG | 1542 AMD_CG_SUPPORT_BIF_LS | 1543 AMD_CG_SUPPORT_UVD_MGCG | 1544 AMD_CG_SUPPORT_HDP_LS | 1545 AMD_CG_SUPPORT_HDP_MGCG; 1546 adev->pg_flags = 0; 1547 adev->external_rev_id = 60; 1548 break; 1549 case CHIP_HAINAN: 1550 adev->cg_flags = 1551 AMD_CG_SUPPORT_GFX_MGCG | 1552 AMD_CG_SUPPORT_GFX_MGLS | 1553 /*AMD_CG_SUPPORT_GFX_CGCG |*/ 1554 AMD_CG_SUPPORT_GFX_CGLS | 1555 AMD_CG_SUPPORT_GFX_CGTS | 1556 AMD_CG_SUPPORT_GFX_CP_LS | 1557 AMD_CG_SUPPORT_GFX_RLC_LS | 1558 AMD_CG_SUPPORT_MC_LS | 1559 AMD_CG_SUPPORT_MC_MGCG | 1560 AMD_CG_SUPPORT_SDMA_MGCG | 1561 AMD_CG_SUPPORT_BIF_LS | 1562 AMD_CG_SUPPORT_HDP_LS | 1563 AMD_CG_SUPPORT_HDP_MGCG; 1564 adev->pg_flags = 0; 1565 adev->external_rev_id = 70; 1566 break; 1567 1568 default: 1569 return -EINVAL; 1570 } 1571 1572 return 0; 1573 } 1574 1575 static int si_common_sw_init(void *handle) 1576 { 1577 return 0; 1578 } 1579 1580 static int si_common_sw_fini(void *handle) 1581 { 1582 return 0; 1583 } 1584 1585 1586 static void si_init_golden_registers(struct amdgpu_device *adev) 1587 { 1588 switch (adev->asic_type) { 1589 case CHIP_TAHITI: 1590 amdgpu_device_program_register_sequence(adev, 1591 tahiti_golden_registers, 1592 ARRAY_SIZE(tahiti_golden_registers)); 1593 amdgpu_device_program_register_sequence(adev, 1594 tahiti_golden_rlc_registers, 1595 ARRAY_SIZE(tahiti_golden_rlc_registers)); 1596 amdgpu_device_program_register_sequence(adev, 1597 tahiti_mgcg_cgcg_init, 1598 ARRAY_SIZE(tahiti_mgcg_cgcg_init)); 1599 amdgpu_device_program_register_sequence(adev, 1600 tahiti_golden_registers2, 1601 ARRAY_SIZE(tahiti_golden_registers2)); 1602 break; 1603 case CHIP_PITCAIRN: 1604 amdgpu_device_program_register_sequence(adev, 1605 pitcairn_golden_registers, 1606 ARRAY_SIZE(pitcairn_golden_registers)); 1607 amdgpu_device_program_register_sequence(adev, 1608 pitcairn_golden_rlc_registers, 1609 ARRAY_SIZE(pitcairn_golden_rlc_registers)); 1610 amdgpu_device_program_register_sequence(adev, 1611 pitcairn_mgcg_cgcg_init, 1612 ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); 1613 break; 1614 case CHIP_VERDE: 1615 amdgpu_device_program_register_sequence(adev, 1616 verde_golden_registers, 1617 ARRAY_SIZE(verde_golden_registers)); 1618 amdgpu_device_program_register_sequence(adev, 1619 verde_golden_rlc_registers, 1620 ARRAY_SIZE(verde_golden_rlc_registers)); 1621 amdgpu_device_program_register_sequence(adev, 1622 verde_mgcg_cgcg_init, 1623 ARRAY_SIZE(verde_mgcg_cgcg_init)); 1624 amdgpu_device_program_register_sequence(adev, 1625 verde_pg_init, 1626 ARRAY_SIZE(verde_pg_init)); 1627 break; 1628 case CHIP_OLAND: 1629 amdgpu_device_program_register_sequence(adev, 1630 oland_golden_registers, 1631 ARRAY_SIZE(oland_golden_registers)); 1632 amdgpu_device_program_register_sequence(adev, 1633 oland_golden_rlc_registers, 1634 ARRAY_SIZE(oland_golden_rlc_registers)); 1635 amdgpu_device_program_register_sequence(adev, 1636 oland_mgcg_cgcg_init, 1637 ARRAY_SIZE(oland_mgcg_cgcg_init)); 1638 break; 1639 case CHIP_HAINAN: 1640 amdgpu_device_program_register_sequence(adev, 1641 hainan_golden_registers, 1642 ARRAY_SIZE(hainan_golden_registers)); 1643 amdgpu_device_program_register_sequence(adev, 1644 hainan_golden_registers2, 1645 ARRAY_SIZE(hainan_golden_registers2)); 1646 amdgpu_device_program_register_sequence(adev, 1647 hainan_mgcg_cgcg_init, 1648 ARRAY_SIZE(hainan_mgcg_cgcg_init)); 1649 break; 1650 1651 1652 default: 1653 BUG(); 1654 } 1655 } 1656 1657 static void si_pcie_gen3_enable(struct amdgpu_device *adev) 1658 { 1659 #ifndef __NetBSD__ /* XXX amdgpu pcie */ 1660 struct pci_dev *root = adev->pdev->bus->self; 1661 u32 speed_cntl, current_data_rate; 1662 int i; 1663 u16 tmp16; 1664 1665 if (pci_is_root_bus(adev->pdev->bus)) 1666 return; 1667 1668 if (amdgpu_pcie_gen2 == 0) 1669 return; 1670 1671 if (adev->flags & AMD_IS_APU) 1672 return; 1673 1674 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 | 1675 CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3))) 1676 return; 1677 1678 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1679 current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> 1680 LC_CURRENT_DATA_RATE_SHIFT; 1681 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1682 if (current_data_rate == 2) { 1683 DRM_INFO("PCIE gen 3 link speeds already enabled\n"); 1684 return; 1685 } 1686 DRM_INFO("enabling PCIE gen 3 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1687 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) { 1688 if (current_data_rate == 1) { 1689 DRM_INFO("PCIE gen 2 link speeds already enabled\n"); 1690 return; 1691 } 1692 DRM_INFO("enabling PCIE gen 2 link speeds, disable with amdgpu.pcie_gen2=0\n"); 1693 } 1694 1695 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev)) 1696 return; 1697 1698 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) { 1699 if (current_data_rate != 2) { 1700 u16 bridge_cfg, gpu_cfg; 1701 u16 bridge_cfg2, gpu_cfg2; 1702 u32 max_lw, current_lw, tmp; 1703 1704 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1705 &bridge_cfg); 1706 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL, 1707 &gpu_cfg); 1708 1709 tmp16 = bridge_cfg | PCI_EXP_LNKCTL_HAWD; 1710 pcie_capability_write_word(root, PCI_EXP_LNKCTL, tmp16); 1711 1712 tmp16 = gpu_cfg | PCI_EXP_LNKCTL_HAWD; 1713 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL, 1714 tmp16); 1715 1716 tmp = RREG32_PCIE(PCIE_LC_STATUS1); 1717 max_lw = (tmp & LC_DETECTED_LINK_WIDTH_MASK) >> LC_DETECTED_LINK_WIDTH_SHIFT; 1718 current_lw = (tmp & LC_OPERATING_LINK_WIDTH_MASK) >> LC_OPERATING_LINK_WIDTH_SHIFT; 1719 1720 if (current_lw < max_lw) { 1721 tmp = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1722 if (tmp & LC_RENEGOTIATION_SUPPORT) { 1723 tmp &= ~(LC_LINK_WIDTH_MASK | LC_UPCONFIGURE_DIS); 1724 tmp |= (max_lw << LC_LINK_WIDTH_SHIFT); 1725 tmp |= LC_UPCONFIGURE_SUPPORT | LC_RENEGOTIATE_EN | LC_RECONFIG_NOW; 1726 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, tmp); 1727 } 1728 } 1729 1730 for (i = 0; i < 10; i++) { 1731 pcie_capability_read_word(adev->pdev, 1732 PCI_EXP_DEVSTA, 1733 &tmp16); 1734 if (tmp16 & PCI_EXP_DEVSTA_TRPND) 1735 break; 1736 1737 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1738 &bridge_cfg); 1739 pcie_capability_read_word(adev->pdev, 1740 PCI_EXP_LNKCTL, 1741 &gpu_cfg); 1742 1743 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1744 &bridge_cfg2); 1745 pcie_capability_read_word(adev->pdev, 1746 PCI_EXP_LNKCTL2, 1747 &gpu_cfg2); 1748 1749 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1750 tmp |= LC_SET_QUIESCE; 1751 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1752 1753 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1754 tmp |= LC_REDO_EQ; 1755 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1756 1757 mdelay(100); 1758 1759 pcie_capability_read_word(root, PCI_EXP_LNKCTL, 1760 &tmp16); 1761 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1762 tmp16 |= (bridge_cfg & PCI_EXP_LNKCTL_HAWD); 1763 pcie_capability_write_word(root, PCI_EXP_LNKCTL, 1764 tmp16); 1765 1766 pcie_capability_read_word(adev->pdev, 1767 PCI_EXP_LNKCTL, 1768 &tmp16); 1769 tmp16 &= ~PCI_EXP_LNKCTL_HAWD; 1770 tmp16 |= (gpu_cfg & PCI_EXP_LNKCTL_HAWD); 1771 pcie_capability_write_word(adev->pdev, 1772 PCI_EXP_LNKCTL, 1773 tmp16); 1774 1775 pcie_capability_read_word(root, PCI_EXP_LNKCTL2, 1776 &tmp16); 1777 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1778 PCI_EXP_LNKCTL2_TX_MARGIN); 1779 tmp16 |= (bridge_cfg2 & 1780 (PCI_EXP_LNKCTL2_ENTER_COMP | 1781 PCI_EXP_LNKCTL2_TX_MARGIN)); 1782 pcie_capability_write_word(root, 1783 PCI_EXP_LNKCTL2, 1784 tmp16); 1785 1786 pcie_capability_read_word(adev->pdev, 1787 PCI_EXP_LNKCTL2, 1788 &tmp16); 1789 tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP | 1790 PCI_EXP_LNKCTL2_TX_MARGIN); 1791 tmp16 |= (gpu_cfg2 & 1792 (PCI_EXP_LNKCTL2_ENTER_COMP | 1793 PCI_EXP_LNKCTL2_TX_MARGIN)); 1794 pcie_capability_write_word(adev->pdev, 1795 PCI_EXP_LNKCTL2, 1796 tmp16); 1797 1798 tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4); 1799 tmp &= ~LC_SET_QUIESCE; 1800 WREG32_PCIE_PORT(PCIE_LC_CNTL4, tmp); 1801 } 1802 } 1803 } 1804 1805 speed_cntl |= LC_FORCE_EN_SW_SPEED_CHANGE | LC_FORCE_DIS_HW_SPEED_CHANGE; 1806 speed_cntl &= ~LC_FORCE_DIS_SW_SPEED_CHANGE; 1807 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1808 1809 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16); 1810 tmp16 &= ~PCI_EXP_LNKCTL2_TLS; 1811 1812 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) 1813 tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */ 1814 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) 1815 tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */ 1816 else 1817 tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */ 1818 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16); 1819 1820 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1821 speed_cntl |= LC_INITIATE_LINK_SPEED_CHANGE; 1822 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl); 1823 1824 for (i = 0; i < adev->usec_timeout; i++) { 1825 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); 1826 if ((speed_cntl & LC_INITIATE_LINK_SPEED_CHANGE) == 0) 1827 break; 1828 udelay(1); 1829 } 1830 #endif /* __NetBSD__ */ 1831 } 1832 1833 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg) 1834 { 1835 unsigned long flags; 1836 u32 r; 1837 1838 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1839 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 1840 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 1841 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1842 return r; 1843 } 1844 1845 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1846 { 1847 unsigned long flags; 1848 1849 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1850 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 1851 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 1852 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1853 } 1854 1855 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) 1856 { 1857 unsigned long flags; 1858 u32 r; 1859 1860 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1861 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 1862 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 1863 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1864 return r; 1865 } 1866 1867 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v) 1868 { 1869 unsigned long flags; 1870 1871 spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1872 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 1873 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 1874 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1875 } 1876 static void si_program_aspm(struct amdgpu_device *adev) 1877 { 1878 u32 data, orig; 1879 bool disable_l0s = false, disable_l1 = false, disable_plloff_in_l1 = false; 1880 bool disable_clkreq = false; 1881 1882 if (amdgpu_aspm == 0) 1883 return; 1884 1885 if (adev->flags & AMD_IS_APU) 1886 return; 1887 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 1888 data &= ~LC_XMIT_N_FTS_MASK; 1889 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN; 1890 if (orig != data) 1891 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data); 1892 1893 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3); 1894 data |= LC_GO_TO_RECOVERY; 1895 if (orig != data) 1896 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data); 1897 1898 orig = data = RREG32_PCIE(PCIE_P_CNTL); 1899 data |= P_IGNORE_EDB_ERR; 1900 if (orig != data) 1901 WREG32_PCIE(PCIE_P_CNTL, data); 1902 1903 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 1904 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK); 1905 data |= LC_PMI_TO_L1_DIS; 1906 if (!disable_l0s) 1907 data |= LC_L0S_INACTIVITY(7); 1908 1909 if (!disable_l1) { 1910 data |= LC_L1_INACTIVITY(7); 1911 data &= ~LC_PMI_TO_L1_DIS; 1912 if (orig != data) 1913 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 1914 1915 if (!disable_plloff_in_l1) { 1916 bool clk_req_support; 1917 1918 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 1919 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 1920 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 1921 if (orig != data) 1922 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 1923 1924 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 1925 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 1926 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 1927 if (orig != data) 1928 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 1929 1930 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 1931 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK); 1932 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7); 1933 if (orig != data) 1934 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 1935 1936 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 1937 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK); 1938 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7); 1939 if (orig != data) 1940 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 1941 1942 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) { 1943 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0); 1944 data &= ~PLL_RAMP_UP_TIME_0_MASK; 1945 if (orig != data) 1946 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data); 1947 1948 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1); 1949 data &= ~PLL_RAMP_UP_TIME_1_MASK; 1950 if (orig != data) 1951 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data); 1952 1953 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2); 1954 data &= ~PLL_RAMP_UP_TIME_2_MASK; 1955 if (orig != data) 1956 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data); 1957 1958 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3); 1959 data &= ~PLL_RAMP_UP_TIME_3_MASK; 1960 if (orig != data) 1961 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data); 1962 1963 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0); 1964 data &= ~PLL_RAMP_UP_TIME_0_MASK; 1965 if (orig != data) 1966 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data); 1967 1968 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1); 1969 data &= ~PLL_RAMP_UP_TIME_1_MASK; 1970 if (orig != data) 1971 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data); 1972 1973 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2); 1974 data &= ~PLL_RAMP_UP_TIME_2_MASK; 1975 if (orig != data) 1976 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data); 1977 1978 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3); 1979 data &= ~PLL_RAMP_UP_TIME_3_MASK; 1980 if (orig != data) 1981 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data); 1982 } 1983 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL); 1984 data &= ~LC_DYN_LANES_PWR_STATE_MASK; 1985 data |= LC_DYN_LANES_PWR_STATE(3); 1986 if (orig != data) 1987 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data); 1988 1989 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL); 1990 data &= ~LS2_EXIT_TIME_MASK; 1991 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 1992 data |= LS2_EXIT_TIME(5); 1993 if (orig != data) 1994 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data); 1995 1996 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL); 1997 data &= ~LS2_EXIT_TIME_MASK; 1998 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN)) 1999 data |= LS2_EXIT_TIME(5); 2000 if (orig != data) 2001 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data); 2002 2003 if (!disable_clkreq && 2004 !pci_is_root_bus(adev->pdev->bus)) { 2005 #ifdef __NetBSD__ /* XXX amdgpu pcie */ 2006 clk_req_support = false; 2007 #else 2008 struct pci_dev *root = adev->pdev->bus->self; 2009 u32 lnkcap; 2010 2011 clk_req_support = false; 2012 pcie_capability_read_dword(root, PCI_EXP_LNKCAP, &lnkcap); 2013 if (lnkcap & PCI_EXP_LNKCAP_CLKPM) 2014 clk_req_support = true; 2015 #endif 2016 } else { 2017 clk_req_support = false; 2018 } 2019 2020 if (clk_req_support) { 2021 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2); 2022 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23; 2023 if (orig != data) 2024 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data); 2025 2026 orig = data = RREG32(THM_CLK_CNTL); 2027 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK); 2028 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1); 2029 if (orig != data) 2030 WREG32(THM_CLK_CNTL, data); 2031 2032 orig = data = RREG32(MISC_CLK_CNTL); 2033 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK); 2034 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1); 2035 if (orig != data) 2036 WREG32(MISC_CLK_CNTL, data); 2037 2038 orig = data = RREG32(CG_CLKPIN_CNTL); 2039 data &= ~BCLK_AS_XCLK; 2040 if (orig != data) 2041 WREG32(CG_CLKPIN_CNTL, data); 2042 2043 orig = data = RREG32(CG_CLKPIN_CNTL_2); 2044 data &= ~FORCE_BIF_REFCLK_EN; 2045 if (orig != data) 2046 WREG32(CG_CLKPIN_CNTL_2, data); 2047 2048 orig = data = RREG32(MPLL_BYPASSCLK_SEL); 2049 data &= ~MPLL_CLKOUT_SEL_MASK; 2050 data |= MPLL_CLKOUT_SEL(4); 2051 if (orig != data) 2052 WREG32(MPLL_BYPASSCLK_SEL, data); 2053 2054 orig = data = RREG32(SPLL_CNTL_MODE); 2055 data &= ~SPLL_REFCLK_SEL_MASK; 2056 if (orig != data) 2057 WREG32(SPLL_CNTL_MODE, data); 2058 } 2059 } 2060 } else { 2061 if (orig != data) 2062 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2063 } 2064 2065 orig = data = RREG32_PCIE(PCIE_CNTL2); 2066 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN; 2067 if (orig != data) 2068 WREG32_PCIE(PCIE_CNTL2, data); 2069 2070 if (!disable_l0s) { 2071 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL); 2072 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) { 2073 data = RREG32_PCIE(PCIE_LC_STATUS1); 2074 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) { 2075 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL); 2076 data &= ~LC_L0S_INACTIVITY_MASK; 2077 if (orig != data) 2078 WREG32_PCIE_PORT(PCIE_LC_CNTL, data); 2079 } 2080 } 2081 } 2082 } 2083 2084 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) 2085 { 2086 #ifndef __NetBSD__ /* XXX amdgpu pcie */ 2087 int readrq; 2088 u16 v; 2089 2090 readrq = pcie_get_readrq(adev->pdev); 2091 v = ffs(readrq) - 8; 2092 if ((v == 0) || (v == 6) || (v == 7)) 2093 pcie_set_readrq(adev->pdev, 512); 2094 #endif 2095 } 2096 2097 static int si_common_hw_init(void *handle) 2098 { 2099 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2100 2101 si_fix_pci_max_read_req_size(adev); 2102 si_init_golden_registers(adev); 2103 si_pcie_gen3_enable(adev); 2104 si_program_aspm(adev); 2105 2106 return 0; 2107 } 2108 2109 static int si_common_hw_fini(void *handle) 2110 { 2111 return 0; 2112 } 2113 2114 static int si_common_suspend(void *handle) 2115 { 2116 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2117 2118 return si_common_hw_fini(adev); 2119 } 2120 2121 static int si_common_resume(void *handle) 2122 { 2123 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 2124 2125 return si_common_hw_init(adev); 2126 } 2127 2128 static bool si_common_is_idle(void *handle) 2129 { 2130 return true; 2131 } 2132 2133 static int si_common_wait_for_idle(void *handle) 2134 { 2135 return 0; 2136 } 2137 2138 static int si_common_soft_reset(void *handle) 2139 { 2140 return 0; 2141 } 2142 2143 static int si_common_set_clockgating_state(void *handle, 2144 enum amd_clockgating_state state) 2145 { 2146 return 0; 2147 } 2148 2149 static int si_common_set_powergating_state(void *handle, 2150 enum amd_powergating_state state) 2151 { 2152 return 0; 2153 } 2154 2155 static const struct amd_ip_funcs si_common_ip_funcs = { 2156 .name = "si_common", 2157 .early_init = si_common_early_init, 2158 .late_init = NULL, 2159 .sw_init = si_common_sw_init, 2160 .sw_fini = si_common_sw_fini, 2161 .hw_init = si_common_hw_init, 2162 .hw_fini = si_common_hw_fini, 2163 .suspend = si_common_suspend, 2164 .resume = si_common_resume, 2165 .is_idle = si_common_is_idle, 2166 .wait_for_idle = si_common_wait_for_idle, 2167 .soft_reset = si_common_soft_reset, 2168 .set_clockgating_state = si_common_set_clockgating_state, 2169 .set_powergating_state = si_common_set_powergating_state, 2170 }; 2171 2172 static const struct amdgpu_ip_block_version si_common_ip_block = 2173 { 2174 .type = AMD_IP_BLOCK_TYPE_COMMON, 2175 .major = 1, 2176 .minor = 0, 2177 .rev = 0, 2178 .funcs = &si_common_ip_funcs, 2179 }; 2180 2181 int si_set_ip_blocks(struct amdgpu_device *adev) 2182 { 2183 si_detect_hw_virtualization(adev); 2184 2185 switch (adev->asic_type) { 2186 case CHIP_VERDE: 2187 case CHIP_TAHITI: 2188 case CHIP_PITCAIRN: 2189 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2190 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2191 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2192 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2193 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2194 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2195 if (adev->enable_virtual_display) 2196 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2197 else 2198 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block); 2199 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ 2200 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2201 break; 2202 case CHIP_OLAND: 2203 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2204 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2205 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2206 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2207 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2208 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2209 if (adev->enable_virtual_display) 2210 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2211 else 2212 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block); 2213 2214 /* amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block); */ 2215 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */ 2216 break; 2217 case CHIP_HAINAN: 2218 amdgpu_device_ip_block_add(adev, &si_common_ip_block); 2219 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block); 2220 amdgpu_device_ip_block_add(adev, &si_ih_ip_block); 2221 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block); 2222 amdgpu_device_ip_block_add(adev, &si_dma_ip_block); 2223 amdgpu_device_ip_block_add(adev, &si_smu_ip_block); 2224 if (adev->enable_virtual_display) 2225 amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block); 2226 break; 2227 default: 2228 BUG(); 2229 } 2230 return 0; 2231 } 2232 2233
Indexes created Sun Sep 28 12:09:53 GMT 2025