amdgpu_ucode.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_ucode.c,v 1.1.1.2 2021/12/18 20:11:12 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #include <sys/cdefs.h> 27 __KERNEL_RCSID(0, "$NetBSD: amdgpu_ucode.c,v 1.1.1.2 2021/12/18 20:11:12 riastradh Exp $"); 28 29 #include <linux/firmware.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 33 #include "amdgpu.h" 34 #include "amdgpu_ucode.h" 35 36 static void amdgpu_ucode_print_common_hdr(const struct common_firmware_header *hdr) 37 { 38 DRM_DEBUG("size_bytes: %u\n", le32_to_cpu(hdr->size_bytes)); 39 DRM_DEBUG("header_size_bytes: %u\n", le32_to_cpu(hdr->header_size_bytes)); 40 DRM_DEBUG("header_version_major: %u\n", le16_to_cpu(hdr->header_version_major)); 41 DRM_DEBUG("header_version_minor: %u\n", le16_to_cpu(hdr->header_version_minor)); 42 DRM_DEBUG("ip_version_major: %u\n", le16_to_cpu(hdr->ip_version_major)); 43 DRM_DEBUG("ip_version_minor: %u\n", le16_to_cpu(hdr->ip_version_minor)); 44 DRM_DEBUG("ucode_version: 0x%08x\n", le32_to_cpu(hdr->ucode_version)); 45 DRM_DEBUG("ucode_size_bytes: %u\n", le32_to_cpu(hdr->ucode_size_bytes)); 46 DRM_DEBUG("ucode_array_offset_bytes: %u\n", 47 le32_to_cpu(hdr->ucode_array_offset_bytes)); 48 DRM_DEBUG("crc32: 0x%08x\n", le32_to_cpu(hdr->crc32)); 49 } 50 51 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr) 52 { 53 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 54 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 55 56 DRM_DEBUG("MC\n"); 57 amdgpu_ucode_print_common_hdr(hdr); 58 59 if (version_major == 1) { 60 const struct mc_firmware_header_v1_0 *mc_hdr = 61 container_of(hdr, struct mc_firmware_header_v1_0, header); 62 63 DRM_DEBUG("io_debug_size_bytes: %u\n", 64 le32_to_cpu(mc_hdr->io_debug_size_bytes)); 65 DRM_DEBUG("io_debug_array_offset_bytes: %u\n", 66 le32_to_cpu(mc_hdr->io_debug_array_offset_bytes)); 67 } else { 68 DRM_ERROR("Unknown MC ucode version: %u.%u\n", version_major, version_minor); 69 } 70 } 71 72 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr) 73 { 74 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 75 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 76 77 DRM_DEBUG("SMC\n"); 78 amdgpu_ucode_print_common_hdr(hdr); 79 80 if (version_major == 1) { 81 const struct smc_firmware_header_v1_0 *smc_hdr = 82 container_of(hdr, struct smc_firmware_header_v1_0, header); 83 84 DRM_DEBUG("ucode_start_addr: %u\n", le32_to_cpu(smc_hdr->ucode_start_addr)); 85 } else if (version_major == 2) { 86 const struct smc_firmware_header_v1_0 *v1_hdr = 87 container_of(hdr, struct smc_firmware_header_v1_0, header); 88 const struct smc_firmware_header_v2_0 *v2_hdr = 89 container_of(v1_hdr, struct smc_firmware_header_v2_0, v1_0); 90 91 DRM_DEBUG("ppt_offset_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_offset_bytes)); 92 DRM_DEBUG("ppt_size_bytes: %u\n", le32_to_cpu(v2_hdr->ppt_size_bytes)); 93 } else { 94 DRM_ERROR("Unknown SMC ucode version: %u.%u\n", version_major, version_minor); 95 } 96 } 97 98 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) 99 { 100 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 101 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 102 103 DRM_DEBUG("GFX\n"); 104 amdgpu_ucode_print_common_hdr(hdr); 105 106 if (version_major == 1) { 107 const struct gfx_firmware_header_v1_0 *gfx_hdr = 108 container_of(hdr, struct gfx_firmware_header_v1_0, header); 109 110 DRM_DEBUG("ucode_feature_version: %u\n", 111 le32_to_cpu(gfx_hdr->ucode_feature_version)); 112 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(gfx_hdr->jt_offset)); 113 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(gfx_hdr->jt_size)); 114 } else { 115 DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor); 116 } 117 } 118 119 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) 120 { 121 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 122 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 123 124 DRM_DEBUG("RLC\n"); 125 amdgpu_ucode_print_common_hdr(hdr); 126 127 if (version_major == 1) { 128 const struct rlc_firmware_header_v1_0 *rlc_hdr = 129 container_of(hdr, struct rlc_firmware_header_v1_0, header); 130 131 DRM_DEBUG("ucode_feature_version: %u\n", 132 le32_to_cpu(rlc_hdr->ucode_feature_version)); 133 DRM_DEBUG("save_and_restore_offset: %u\n", 134 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 135 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 136 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 137 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 138 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 139 DRM_DEBUG("master_pkt_description_offset: %u\n", 140 le32_to_cpu(rlc_hdr->master_pkt_description_offset)); 141 } else if (version_major == 2) { 142 const struct rlc_firmware_header_v2_0 *rlc_hdr = 143 container_of(hdr, struct rlc_firmware_header_v2_0, header); 144 145 DRM_DEBUG("ucode_feature_version: %u\n", 146 le32_to_cpu(rlc_hdr->ucode_feature_version)); 147 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(rlc_hdr->jt_offset)); 148 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(rlc_hdr->jt_size)); 149 DRM_DEBUG("save_and_restore_offset: %u\n", 150 le32_to_cpu(rlc_hdr->save_and_restore_offset)); 151 DRM_DEBUG("clear_state_descriptor_offset: %u\n", 152 le32_to_cpu(rlc_hdr->clear_state_descriptor_offset)); 153 DRM_DEBUG("avail_scratch_ram_locations: %u\n", 154 le32_to_cpu(rlc_hdr->avail_scratch_ram_locations)); 155 DRM_DEBUG("reg_restore_list_size: %u\n", 156 le32_to_cpu(rlc_hdr->reg_restore_list_size)); 157 DRM_DEBUG("reg_list_format_start: %u\n", 158 le32_to_cpu(rlc_hdr->reg_list_format_start)); 159 DRM_DEBUG("reg_list_format_separate_start: %u\n", 160 le32_to_cpu(rlc_hdr->reg_list_format_separate_start)); 161 DRM_DEBUG("starting_offsets_start: %u\n", 162 le32_to_cpu(rlc_hdr->starting_offsets_start)); 163 DRM_DEBUG("reg_list_format_size_bytes: %u\n", 164 le32_to_cpu(rlc_hdr->reg_list_format_size_bytes)); 165 DRM_DEBUG("reg_list_format_array_offset_bytes: %u\n", 166 le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes)); 167 DRM_DEBUG("reg_list_size_bytes: %u\n", 168 le32_to_cpu(rlc_hdr->reg_list_size_bytes)); 169 DRM_DEBUG("reg_list_array_offset_bytes: %u\n", 170 le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes)); 171 DRM_DEBUG("reg_list_format_separate_size_bytes: %u\n", 172 le32_to_cpu(rlc_hdr->reg_list_format_separate_size_bytes)); 173 DRM_DEBUG("reg_list_format_separate_array_offset_bytes: %u\n", 174 le32_to_cpu(rlc_hdr->reg_list_format_separate_array_offset_bytes)); 175 DRM_DEBUG("reg_list_separate_size_bytes: %u\n", 176 le32_to_cpu(rlc_hdr->reg_list_separate_size_bytes)); 177 DRM_DEBUG("reg_list_separate_array_offset_bytes: %u\n", 178 le32_to_cpu(rlc_hdr->reg_list_separate_array_offset_bytes)); 179 if (version_minor == 1) { 180 const struct rlc_firmware_header_v2_1 *v2_1 = 181 container_of(rlc_hdr, struct rlc_firmware_header_v2_1, v2_0); 182 DRM_DEBUG("reg_list_format_direct_reg_list_length: %u\n", 183 le32_to_cpu(v2_1->reg_list_format_direct_reg_list_length)); 184 DRM_DEBUG("save_restore_list_cntl_ucode_ver: %u\n", 185 le32_to_cpu(v2_1->save_restore_list_cntl_ucode_ver)); 186 DRM_DEBUG("save_restore_list_cntl_feature_ver: %u\n", 187 le32_to_cpu(v2_1->save_restore_list_cntl_feature_ver)); 188 DRM_DEBUG("save_restore_list_cntl_size_bytes %u\n", 189 le32_to_cpu(v2_1->save_restore_list_cntl_size_bytes)); 190 DRM_DEBUG("save_restore_list_cntl_offset_bytes: %u\n", 191 le32_to_cpu(v2_1->save_restore_list_cntl_offset_bytes)); 192 DRM_DEBUG("save_restore_list_gpm_ucode_ver: %u\n", 193 le32_to_cpu(v2_1->save_restore_list_gpm_ucode_ver)); 194 DRM_DEBUG("save_restore_list_gpm_feature_ver: %u\n", 195 le32_to_cpu(v2_1->save_restore_list_gpm_feature_ver)); 196 DRM_DEBUG("save_restore_list_gpm_size_bytes %u\n", 197 le32_to_cpu(v2_1->save_restore_list_gpm_size_bytes)); 198 DRM_DEBUG("save_restore_list_gpm_offset_bytes: %u\n", 199 le32_to_cpu(v2_1->save_restore_list_gpm_offset_bytes)); 200 DRM_DEBUG("save_restore_list_srm_ucode_ver: %u\n", 201 le32_to_cpu(v2_1->save_restore_list_srm_ucode_ver)); 202 DRM_DEBUG("save_restore_list_srm_feature_ver: %u\n", 203 le32_to_cpu(v2_1->save_restore_list_srm_feature_ver)); 204 DRM_DEBUG("save_restore_list_srm_size_bytes %u\n", 205 le32_to_cpu(v2_1->save_restore_list_srm_size_bytes)); 206 DRM_DEBUG("save_restore_list_srm_offset_bytes: %u\n", 207 le32_to_cpu(v2_1->save_restore_list_srm_offset_bytes)); 208 } 209 } else { 210 DRM_ERROR("Unknown RLC ucode version: %u.%u\n", version_major, version_minor); 211 } 212 } 213 214 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr) 215 { 216 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 217 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 218 219 DRM_DEBUG("SDMA\n"); 220 amdgpu_ucode_print_common_hdr(hdr); 221 222 if (version_major == 1) { 223 const struct sdma_firmware_header_v1_0 *sdma_hdr = 224 container_of(hdr, struct sdma_firmware_header_v1_0, header); 225 226 DRM_DEBUG("ucode_feature_version: %u\n", 227 le32_to_cpu(sdma_hdr->ucode_feature_version)); 228 DRM_DEBUG("ucode_change_version: %u\n", 229 le32_to_cpu(sdma_hdr->ucode_change_version)); 230 DRM_DEBUG("jt_offset: %u\n", le32_to_cpu(sdma_hdr->jt_offset)); 231 DRM_DEBUG("jt_size: %u\n", le32_to_cpu(sdma_hdr->jt_size)); 232 if (version_minor >= 1) { 233 const struct sdma_firmware_header_v1_1 *sdma_v1_1_hdr = 234 container_of(sdma_hdr, struct sdma_firmware_header_v1_1, v1_0); 235 DRM_DEBUG("digest_size: %u\n", le32_to_cpu(sdma_v1_1_hdr->digest_size)); 236 } 237 } else { 238 DRM_ERROR("Unknown SDMA ucode version: %u.%u\n", 239 version_major, version_minor); 240 } 241 } 242 243 void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr) 244 { 245 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 246 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 247 248 DRM_DEBUG("PSP\n"); 249 amdgpu_ucode_print_common_hdr(hdr); 250 251 if (version_major == 1) { 252 const struct psp_firmware_header_v1_0 *psp_hdr = 253 container_of(hdr, struct psp_firmware_header_v1_0, header); 254 255 DRM_DEBUG("ucode_feature_version: %u\n", 256 le32_to_cpu(psp_hdr->ucode_feature_version)); 257 DRM_DEBUG("sos_offset_bytes: %u\n", 258 le32_to_cpu(psp_hdr->sos_offset_bytes)); 259 DRM_DEBUG("sos_size_bytes: %u\n", 260 le32_to_cpu(psp_hdr->sos_size_bytes)); 261 if (version_minor == 1) { 262 const struct psp_firmware_header_v1_1 *psp_hdr_v1_1 = 263 container_of(psp_hdr, struct psp_firmware_header_v1_1, v1_0); 264 DRM_DEBUG("toc_header_version: %u\n", 265 le32_to_cpu(psp_hdr_v1_1->toc_header_version)); 266 DRM_DEBUG("toc_offset_bytes: %u\n", 267 le32_to_cpu(psp_hdr_v1_1->toc_offset_bytes)); 268 DRM_DEBUG("toc_size_bytes: %u\n", 269 le32_to_cpu(psp_hdr_v1_1->toc_size_bytes)); 270 DRM_DEBUG("kdb_header_version: %u\n", 271 le32_to_cpu(psp_hdr_v1_1->kdb_header_version)); 272 DRM_DEBUG("kdb_offset_bytes: %u\n", 273 le32_to_cpu(psp_hdr_v1_1->kdb_offset_bytes)); 274 DRM_DEBUG("kdb_size_bytes: %u\n", 275 le32_to_cpu(psp_hdr_v1_1->kdb_size_bytes)); 276 } 277 if (version_minor == 2) { 278 const struct psp_firmware_header_v1_2 *psp_hdr_v1_2 = 279 container_of(psp_hdr, struct psp_firmware_header_v1_2, v1_0); 280 DRM_DEBUG("kdb_header_version: %u\n", 281 le32_to_cpu(psp_hdr_v1_2->kdb_header_version)); 282 DRM_DEBUG("kdb_offset_bytes: %u\n", 283 le32_to_cpu(psp_hdr_v1_2->kdb_offset_bytes)); 284 DRM_DEBUG("kdb_size_bytes: %u\n", 285 le32_to_cpu(psp_hdr_v1_2->kdb_size_bytes)); 286 } 287 } else { 288 DRM_ERROR("Unknown PSP ucode version: %u.%u\n", 289 version_major, version_minor); 290 } 291 } 292 293 void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr) 294 { 295 uint16_t version_major = le16_to_cpu(hdr->header_version_major); 296 uint16_t version_minor = le16_to_cpu(hdr->header_version_minor); 297 298 DRM_DEBUG("GPU_INFO\n"); 299 amdgpu_ucode_print_common_hdr(hdr); 300 301 if (version_major == 1) { 302 const struct gpu_info_firmware_header_v1_0 *gpu_info_hdr = 303 container_of(hdr, struct gpu_info_firmware_header_v1_0, header); 304 305 DRM_DEBUG("version_major: %u\n", 306 le16_to_cpu(gpu_info_hdr->version_major)); 307 DRM_DEBUG("version_minor: %u\n", 308 le16_to_cpu(gpu_info_hdr->version_minor)); 309 } else { 310 DRM_ERROR("Unknown gpu_info ucode version: %u.%u\n", version_major, version_minor); 311 } 312 } 313 314 int amdgpu_ucode_validate(const struct firmware *fw) 315 { 316 const struct common_firmware_header *hdr = 317 (const struct common_firmware_header *)fw->data; 318 319 if (fw->size == le32_to_cpu(hdr->size_bytes)) 320 return 0; 321 322 return -EINVAL; 323 } 324 325 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 326 uint16_t hdr_major, uint16_t hdr_minor) 327 { 328 if ((hdr->common.header_version_major == hdr_major) && 329 (hdr->common.header_version_minor == hdr_minor)) 330 return false; 331 return true; 332 } 333 334 enum amdgpu_firmware_load_type 335 amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type) 336 { 337 switch (adev->asic_type) { 338 #ifdef CONFIG_DRM_AMDGPU_SI 339 case CHIP_TAHITI: 340 case CHIP_PITCAIRN: 341 case CHIP_VERDE: 342 case CHIP_OLAND: 343 case CHIP_HAINAN: 344 return AMDGPU_FW_LOAD_DIRECT; 345 #endif 346 #ifdef CONFIG_DRM_AMDGPU_CIK 347 case CHIP_BONAIRE: 348 case CHIP_KAVERI: 349 case CHIP_KABINI: 350 case CHIP_HAWAII: 351 case CHIP_MULLINS: 352 return AMDGPU_FW_LOAD_DIRECT; 353 #endif 354 case CHIP_TOPAZ: 355 case CHIP_TONGA: 356 case CHIP_FIJI: 357 case CHIP_CARRIZO: 358 case CHIP_STONEY: 359 case CHIP_POLARIS10: 360 case CHIP_POLARIS11: 361 case CHIP_POLARIS12: 362 case CHIP_VEGAM: 363 return AMDGPU_FW_LOAD_SMU; 364 case CHIP_VEGA10: 365 case CHIP_RAVEN: 366 case CHIP_VEGA12: 367 case CHIP_VEGA20: 368 case CHIP_ARCTURUS: 369 case CHIP_RENOIR: 370 case CHIP_NAVI10: 371 case CHIP_NAVI14: 372 case CHIP_NAVI12: 373 if (!load_type) 374 return AMDGPU_FW_LOAD_DIRECT; 375 else 376 return AMDGPU_FW_LOAD_PSP; 377 378 default: 379 DRM_ERROR("Unknown firmware load type\n"); 380 } 381 382 return AMDGPU_FW_LOAD_DIRECT; 383 } 384 385 #define FW_VERSION_ATTR(name, mode, field) \ 386 static ssize_t show_##name(struct device *dev, \ 387 struct device_attribute *attr, \ 388 char *buf) \ 389 { \ 390 struct drm_device *ddev = dev_get_drvdata(dev); \ 391 struct amdgpu_device *adev = ddev->dev_private; \ 392 \ 393 return snprintf(buf, PAGE_SIZE, "0x%08x\n", adev->field); \ 394 } \ 395 static DEVICE_ATTR(name, mode, show_##name, NULL) 396 397 FW_VERSION_ATTR(vce_fw_version, 0444, vce.fw_version); 398 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version); 399 FW_VERSION_ATTR(mc_fw_version, 0444, gmc.fw_version); 400 FW_VERSION_ATTR(me_fw_version, 0444, gfx.me_fw_version); 401 FW_VERSION_ATTR(pfp_fw_version, 0444, gfx.pfp_fw_version); 402 FW_VERSION_ATTR(ce_fw_version, 0444, gfx.ce_fw_version); 403 FW_VERSION_ATTR(rlc_fw_version, 0444, gfx.rlc_fw_version); 404 FW_VERSION_ATTR(rlc_srlc_fw_version, 0444, gfx.rlc_srlc_fw_version); 405 FW_VERSION_ATTR(rlc_srlg_fw_version, 0444, gfx.rlc_srlg_fw_version); 406 FW_VERSION_ATTR(rlc_srls_fw_version, 0444, gfx.rlc_srls_fw_version); 407 FW_VERSION_ATTR(mec_fw_version, 0444, gfx.mec_fw_version); 408 FW_VERSION_ATTR(mec2_fw_version, 0444, gfx.mec2_fw_version); 409 FW_VERSION_ATTR(sos_fw_version, 0444, psp.sos_fw_version); 410 FW_VERSION_ATTR(asd_fw_version, 0444, psp.asd_fw_version); 411 FW_VERSION_ATTR(ta_ras_fw_version, 0444, psp.ta_fw_version); 412 FW_VERSION_ATTR(ta_xgmi_fw_version, 0444, psp.ta_fw_version); 413 FW_VERSION_ATTR(smc_fw_version, 0444, pm.fw_version); 414 FW_VERSION_ATTR(sdma_fw_version, 0444, sdma.instance[0].fw_version); 415 FW_VERSION_ATTR(sdma2_fw_version, 0444, sdma.instance[1].fw_version); 416 FW_VERSION_ATTR(vcn_fw_version, 0444, vcn.fw_version); 417 FW_VERSION_ATTR(dmcu_fw_version, 0444, dm.dmcu_fw_version); 418 419 static struct attribute *fw_attrs[] = { 420 &dev_attr_vce_fw_version.attr, &dev_attr_uvd_fw_version.attr, 421 &dev_attr_mc_fw_version.attr, &dev_attr_me_fw_version.attr, 422 &dev_attr_pfp_fw_version.attr, &dev_attr_ce_fw_version.attr, 423 &dev_attr_rlc_fw_version.attr, &dev_attr_rlc_srlc_fw_version.attr, 424 &dev_attr_rlc_srlg_fw_version.attr, &dev_attr_rlc_srls_fw_version.attr, 425 &dev_attr_mec_fw_version.attr, &dev_attr_mec2_fw_version.attr, 426 &dev_attr_sos_fw_version.attr, &dev_attr_asd_fw_version.attr, 427 &dev_attr_ta_ras_fw_version.attr, &dev_attr_ta_xgmi_fw_version.attr, 428 &dev_attr_smc_fw_version.attr, &dev_attr_sdma_fw_version.attr, 429 &dev_attr_sdma2_fw_version.attr, &dev_attr_vcn_fw_version.attr, 430 &dev_attr_dmcu_fw_version.attr, NULL 431 }; 432 433 static const struct attribute_group fw_attr_group = { 434 .name = "fw_version", 435 .attrs = fw_attrs 436 }; 437 438 int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev) 439 { 440 return sysfs_create_group(&adev->dev->kobj, &fw_attr_group); 441 } 442 443 void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev) 444 { 445 sysfs_remove_group(&adev->dev->kobj, &fw_attr_group); 446 } 447 448 static int amdgpu_ucode_init_single_fw(struct amdgpu_device *adev, 449 struct amdgpu_firmware_info *ucode, 450 uint64_t mc_addr, void *kptr) 451 { 452 const struct common_firmware_header *header = NULL; 453 const struct gfx_firmware_header_v1_0 *cp_hdr = NULL; 454 const struct dmcu_firmware_header_v1_0 *dmcu_hdr = NULL; 455 const struct dmcub_firmware_header_v1_0 *dmcub_hdr = NULL; 456 457 if (NULL == ucode->fw) 458 return 0; 459 460 ucode->mc_addr = mc_addr; 461 ucode->kaddr = kptr; 462 463 if (ucode->ucode_id == AMDGPU_UCODE_ID_STORAGE) 464 return 0; 465 466 header = (const struct common_firmware_header *)ucode->fw->data; 467 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 468 dmcu_hdr = (const struct dmcu_firmware_header_v1_0 *)ucode->fw->data; 469 dmcub_hdr = (const struct dmcub_firmware_header_v1_0 *)ucode->fw->data; 470 471 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP || 472 (ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1 && 473 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2 && 474 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC1_JT && 475 ucode->ucode_id != AMDGPU_UCODE_ID_CP_MEC2_JT && 476 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL && 477 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM && 478 ucode->ucode_id != AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM && 479 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_ERAM && 480 ucode->ucode_id != AMDGPU_UCODE_ID_DMCU_INTV && 481 ucode->ucode_id != AMDGPU_UCODE_ID_DMCUB)) { 482 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes); 483 484 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 485 le32_to_cpu(header->ucode_array_offset_bytes)), 486 ucode->ucode_size); 487 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1 || 488 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2) { 489 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 490 le32_to_cpu(cp_hdr->jt_size) * 4; 491 492 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 493 le32_to_cpu(header->ucode_array_offset_bytes)), 494 ucode->ucode_size); 495 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT || 496 ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT) { 497 ucode->ucode_size = le32_to_cpu(cp_hdr->jt_size) * 4; 498 499 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 500 le32_to_cpu(header->ucode_array_offset_bytes) + 501 le32_to_cpu(cp_hdr->jt_offset) * 4), 502 ucode->ucode_size); 503 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_ERAM) { 504 ucode->ucode_size = le32_to_cpu(header->ucode_size_bytes) - 505 le32_to_cpu(dmcu_hdr->intv_size_bytes); 506 507 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 508 le32_to_cpu(header->ucode_array_offset_bytes)), 509 ucode->ucode_size); 510 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCU_INTV) { 511 ucode->ucode_size = le32_to_cpu(dmcu_hdr->intv_size_bytes); 512 513 memcpy(ucode->kaddr, (void *)((uint8_t *)ucode->fw->data + 514 le32_to_cpu(header->ucode_array_offset_bytes) + 515 le32_to_cpu(dmcu_hdr->intv_offset_bytes)), 516 ucode->ucode_size); 517 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_DMCUB) { 518 ucode->ucode_size = le32_to_cpu(dmcub_hdr->inst_const_bytes); 519 memcpy(ucode->kaddr, 520 (void *)((uint8_t *)ucode->fw->data + 521 le32_to_cpu(header->ucode_array_offset_bytes)), 522 ucode->ucode_size); 523 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL) { 524 ucode->ucode_size = adev->gfx.rlc.save_restore_list_cntl_size_bytes; 525 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_cntl, 526 ucode->ucode_size); 527 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM) { 528 ucode->ucode_size = adev->gfx.rlc.save_restore_list_gpm_size_bytes; 529 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_gpm, 530 ucode->ucode_size); 531 } else if (ucode->ucode_id == AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM) { 532 ucode->ucode_size = adev->gfx.rlc.save_restore_list_srm_size_bytes; 533 memcpy(ucode->kaddr, adev->gfx.rlc.save_restore_list_srm, 534 ucode->ucode_size); 535 } 536 537 return 0; 538 } 539 540 static int amdgpu_ucode_patch_jt(struct amdgpu_firmware_info *ucode, 541 uint64_t mc_addr, void *kptr) 542 { 543 const struct gfx_firmware_header_v1_0 *header = NULL; 544 const struct common_firmware_header *comm_hdr = NULL; 545 uint8_t* src_addr = NULL; 546 uint8_t* dst_addr = NULL; 547 548 if (NULL == ucode->fw) 549 return 0; 550 551 comm_hdr = (const struct common_firmware_header *)ucode->fw->data; 552 header = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 553 dst_addr = ucode->kaddr + 554 ALIGN(le32_to_cpu(comm_hdr->ucode_size_bytes), 555 PAGE_SIZE); 556 src_addr = (uint8_t *)ucode->fw->data + 557 le32_to_cpu(comm_hdr->ucode_array_offset_bytes) + 558 (le32_to_cpu(header->jt_offset) * 4); 559 memcpy(dst_addr, src_addr, le32_to_cpu(header->jt_size) * 4); 560 561 return 0; 562 } 563 564 int amdgpu_ucode_create_bo(struct amdgpu_device *adev) 565 { 566 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) { 567 amdgpu_bo_create_kernel(adev, adev->firmware.fw_size, PAGE_SIZE, 568 amdgpu_sriov_vf(adev) ? AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT, 569 &adev->firmware.fw_buf, 570 &adev->firmware.fw_buf_mc, 571 &adev->firmware.fw_buf_ptr); 572 if (!adev->firmware.fw_buf) { 573 dev_err(adev->dev, "failed to create kernel buffer for firmware.fw_buf\n"); 574 return -ENOMEM; 575 } else if (amdgpu_sriov_vf(adev)) { 576 memset(adev->firmware.fw_buf_ptr, 0, adev->firmware.fw_size); 577 } 578 } 579 return 0; 580 } 581 582 void amdgpu_ucode_free_bo(struct amdgpu_device *adev) 583 { 584 if (adev->firmware.load_type != AMDGPU_FW_LOAD_DIRECT) 585 amdgpu_bo_free_kernel(&adev->firmware.fw_buf, 586 &adev->firmware.fw_buf_mc, 587 &adev->firmware.fw_buf_ptr); 588 } 589 590 int amdgpu_ucode_init_bo(struct amdgpu_device *adev) 591 { 592 uint64_t fw_offset = 0; 593 int i; 594 struct amdgpu_firmware_info *ucode = NULL; 595 596 /* for baremetal, the ucode is allocated in gtt, so don't need to fill the bo when reset/suspend */ 597 if (!amdgpu_sriov_vf(adev) && (adev->in_gpu_reset || adev->in_suspend)) 598 return 0; 599 /* 600 * if SMU loaded firmware, it needn't add SMC, UVD, and VCE 601 * ucode info here 602 */ 603 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 604 if (amdgpu_sriov_vf(adev)) 605 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 3; 606 else 607 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM - 4; 608 } else { 609 adev->firmware.max_ucodes = AMDGPU_UCODE_ID_MAXIMUM; 610 } 611 612 for (i = 0; i < adev->firmware.max_ucodes; i++) { 613 ucode = &adev->firmware.ucode[i]; 614 if (ucode->fw) { 615 amdgpu_ucode_init_single_fw(adev, ucode, adev->firmware.fw_buf_mc + fw_offset, 616 adev->firmware.fw_buf_ptr + fw_offset); 617 if (i == AMDGPU_UCODE_ID_CP_MEC1 && 618 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 619 const struct gfx_firmware_header_v1_0 *cp_hdr; 620 cp_hdr = (const struct gfx_firmware_header_v1_0 *)ucode->fw->data; 621 amdgpu_ucode_patch_jt(ucode, adev->firmware.fw_buf_mc + fw_offset, 622 adev->firmware.fw_buf_ptr + fw_offset); 623 fw_offset += ALIGN(le32_to_cpu(cp_hdr->jt_size) << 2, PAGE_SIZE); 624 } 625 fw_offset += ALIGN(ucode->ucode_size, PAGE_SIZE); 626 } 627 } 628 return 0; 629 } 630
Indexes created Tue Sep 23 21:09:50 GMT 2025