amdgpu_ucode.h revision 1.1.1.1
1 /* $NetBSD: amdgpu_ucode.h,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef __AMDGPU_UCODE_H__ 26 #define __AMDGPU_UCODE_H__ 27 28 struct common_firmware_header { 29 uint32_t size_bytes; /* size of the entire header+image(s) in bytes */ 30 uint32_t header_size_bytes; /* size of just the header in bytes */ 31 uint16_t header_version_major; /* header version */ 32 uint16_t header_version_minor; /* header version */ 33 uint16_t ip_version_major; /* IP version */ 34 uint16_t ip_version_minor; /* IP version */ 35 uint32_t ucode_version; 36 uint32_t ucode_size_bytes; /* size of ucode in bytes */ 37 uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */ 38 uint32_t crc32; /* crc32 checksum of the payload */ 39 }; 40 41 /* version_major=1, version_minor=0 */ 42 struct mc_firmware_header_v1_0 { 43 struct common_firmware_header header; 44 uint32_t io_debug_size_bytes; /* size of debug array in dwords */ 45 uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */ 46 }; 47 48 /* version_major=1, version_minor=0 */ 49 struct smc_firmware_header_v1_0 { 50 struct common_firmware_header header; 51 uint32_t ucode_start_addr; 52 }; 53 54 /* version_major=1, version_minor=0 */ 55 struct gfx_firmware_header_v1_0 { 56 struct common_firmware_header header; 57 uint32_t ucode_feature_version; 58 uint32_t jt_offset; /* jt location */ 59 uint32_t jt_size; /* size of jt */ 60 }; 61 62 /* version_major=1, version_minor=0 */ 63 struct rlc_firmware_header_v1_0 { 64 struct common_firmware_header header; 65 uint32_t ucode_feature_version; 66 uint32_t save_and_restore_offset; 67 uint32_t clear_state_descriptor_offset; 68 uint32_t avail_scratch_ram_locations; 69 uint32_t master_pkt_description_offset; 70 }; 71 72 /* version_major=2, version_minor=0 */ 73 struct rlc_firmware_header_v2_0 { 74 struct common_firmware_header header; 75 uint32_t ucode_feature_version; 76 uint32_t jt_offset; /* jt location */ 77 uint32_t jt_size; /* size of jt */ 78 uint32_t save_and_restore_offset; 79 uint32_t clear_state_descriptor_offset; 80 uint32_t avail_scratch_ram_locations; 81 uint32_t reg_restore_list_size; 82 uint32_t reg_list_format_start; 83 uint32_t reg_list_format_separate_start; 84 uint32_t starting_offsets_start; 85 uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */ 86 uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */ 87 uint32_t reg_list_size_bytes; /* size of reg list array in bytes */ 88 uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */ 89 uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */ 90 uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */ 91 uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */ 92 uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */ 93 }; 94 95 /* version_major=1, version_minor=0 */ 96 struct sdma_firmware_header_v1_0 { 97 struct common_firmware_header header; 98 uint32_t ucode_feature_version; 99 uint32_t ucode_change_version; 100 uint32_t jt_offset; /* jt location */ 101 uint32_t jt_size; /* size of jt */ 102 }; 103 104 /* version_major=1, version_minor=1 */ 105 struct sdma_firmware_header_v1_1 { 106 struct sdma_firmware_header_v1_0 v1_0; 107 uint32_t digest_size; 108 }; 109 110 /* header is fixed size */ 111 union amdgpu_firmware_header { 112 struct common_firmware_header common; 113 struct mc_firmware_header_v1_0 mc; 114 struct smc_firmware_header_v1_0 smc; 115 struct gfx_firmware_header_v1_0 gfx; 116 struct rlc_firmware_header_v1_0 rlc; 117 struct rlc_firmware_header_v2_0 rlc_v2_0; 118 struct sdma_firmware_header_v1_0 sdma; 119 struct sdma_firmware_header_v1_1 sdma_v1_1; 120 uint8_t raw[0x100]; 121 }; 122 123 /* 124 * fw loading support 125 */ 126 enum AMDGPU_UCODE_ID { 127 AMDGPU_UCODE_ID_SDMA0 = 0, 128 AMDGPU_UCODE_ID_SDMA1, 129 AMDGPU_UCODE_ID_CP_CE, 130 AMDGPU_UCODE_ID_CP_PFP, 131 AMDGPU_UCODE_ID_CP_ME, 132 AMDGPU_UCODE_ID_CP_MEC1, 133 AMDGPU_UCODE_ID_CP_MEC2, 134 AMDGPU_UCODE_ID_RLC_G, 135 AMDGPU_UCODE_ID_MAXIMUM, 136 }; 137 138 /* engine firmware status */ 139 enum AMDGPU_UCODE_STATUS { 140 AMDGPU_UCODE_STATUS_INVALID, 141 AMDGPU_UCODE_STATUS_NOT_LOADED, 142 AMDGPU_UCODE_STATUS_LOADED, 143 }; 144 145 /* conform to smu_ucode_xfer_cz.h */ 146 #define AMDGPU_SDMA0_UCODE_LOADED 0x00000001 147 #define AMDGPU_SDMA1_UCODE_LOADED 0x00000002 148 #define AMDGPU_CPCE_UCODE_LOADED 0x00000004 149 #define AMDGPU_CPPFP_UCODE_LOADED 0x00000008 150 #define AMDGPU_CPME_UCODE_LOADED 0x00000010 151 #define AMDGPU_CPMEC1_UCODE_LOADED 0x00000020 152 #define AMDGPU_CPMEC2_UCODE_LOADED 0x00000040 153 #define AMDGPU_CPRLC_UCODE_LOADED 0x00000100 154 155 /* amdgpu firmware info */ 156 struct amdgpu_firmware_info { 157 /* ucode ID */ 158 enum AMDGPU_UCODE_ID ucode_id; 159 /* request_firmware */ 160 const struct firmware *fw; 161 /* starting mc address */ 162 uint64_t mc_addr; 163 /* kernel linear address */ 164 void *kaddr; 165 }; 166 167 void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr); 168 void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr); 169 void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr); 170 void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr); 171 void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr); 172 int amdgpu_ucode_validate(const struct firmware *fw); 173 bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr, 174 uint16_t hdr_major, uint16_t hdr_minor); 175 int amdgpu_ucode_init_bo(struct amdgpu_device *adev); 176 int amdgpu_ucode_fini_bo(struct amdgpu_device *adev); 177 178 #endif 179
Indexes created Wed Sep 24 15:09:51 GMT 2025