amdgpu_uvd.c revision 1.1.1.2
1 /* $NetBSD: amdgpu_uvd.c,v 1.1.1.2 2021/12/18 20:11:12 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation the rights to use, copy, modify, merge, publish, 11 * distribute, sub license, and/or sell copies of the Software, and to 12 * permit persons to whom the Software is furnished to do so, subject to 13 * the following conditions: 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * The above copyright notice and this permission notice (including the 24 * next paragraph) shall be included in all copies or substantial portions 25 * of the Software. 26 * 27 */ 28 /* 29 * Authors: 30 * Christian Knig <deathsimple (at) vodafone.de> 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: amdgpu_uvd.c,v 1.1.1.2 2021/12/18 20:11:12 riastradh Exp $"); 35 36 #include <linux/firmware.h> 37 #include <linux/module.h> 38 39 #include <drm/drm.h> 40 41 #include "amdgpu.h" 42 #include "amdgpu_pm.h" 43 #include "amdgpu_uvd.h" 44 #include "cikd.h" 45 #include "uvd/uvd_4_2_d.h" 46 47 #include "amdgpu_ras.h" 48 49 /* 1 second timeout */ 50 #define UVD_IDLE_TIMEOUT msecs_to_jiffies(1000) 51 52 /* Firmware versions for VI */ 53 #define FW_1_65_10 ((1 << 24) | (65 << 16) | (10 << 8)) 54 #define FW_1_87_11 ((1 << 24) | (87 << 16) | (11 << 8)) 55 #define FW_1_87_12 ((1 << 24) | (87 << 16) | (12 << 8)) 56 #define FW_1_37_15 ((1 << 24) | (37 << 16) | (15 << 8)) 57 58 /* Polaris10/11 firmware version */ 59 #define FW_1_66_16 ((1 << 24) | (66 << 16) | (16 << 8)) 60 61 /* Firmware Names */ 62 #ifdef CONFIG_DRM_AMDGPU_CIK 63 #define FIRMWARE_BONAIRE "amdgpu/bonaire_uvd.bin" 64 #define FIRMWARE_KABINI "amdgpu/kabini_uvd.bin" 65 #define FIRMWARE_KAVERI "amdgpu/kaveri_uvd.bin" 66 #define FIRMWARE_HAWAII "amdgpu/hawaii_uvd.bin" 67 #define FIRMWARE_MULLINS "amdgpu/mullins_uvd.bin" 68 #endif 69 #define FIRMWARE_TONGA "amdgpu/tonga_uvd.bin" 70 #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" 71 #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" 72 #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" 73 #define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" 74 #define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" 75 #define FIRMWARE_POLARIS12 "amdgpu/polaris12_uvd.bin" 76 #define FIRMWARE_VEGAM "amdgpu/vegam_uvd.bin" 77 78 #define FIRMWARE_VEGA10 "amdgpu/vega10_uvd.bin" 79 #define FIRMWARE_VEGA12 "amdgpu/vega12_uvd.bin" 80 #define FIRMWARE_VEGA20 "amdgpu/vega20_uvd.bin" 81 82 /* These are common relative offsets for all asics, from uvd_7_0_offset.h, */ 83 #define UVD_GPCOM_VCPU_CMD 0x03c3 84 #define UVD_GPCOM_VCPU_DATA0 0x03c4 85 #define UVD_GPCOM_VCPU_DATA1 0x03c5 86 #define UVD_NO_OP 0x03ff 87 #define UVD_BASE_SI 0x3800 88 89 /** 90 * amdgpu_uvd_cs_ctx - Command submission parser context 91 * 92 * Used for emulating virtual memory support on UVD 4.2. 93 */ 94 struct amdgpu_uvd_cs_ctx { 95 struct amdgpu_cs_parser *parser; 96 unsigned reg, count; 97 unsigned data0, data1; 98 unsigned idx; 99 unsigned ib_idx; 100 101 /* does the IB has a msg command */ 102 bool has_msg_cmd; 103 104 /* minimum buffer sizes */ 105 unsigned *buf_sizes; 106 }; 107 108 #ifdef CONFIG_DRM_AMDGPU_CIK 109 MODULE_FIRMWARE(FIRMWARE_BONAIRE); 110 MODULE_FIRMWARE(FIRMWARE_KABINI); 111 MODULE_FIRMWARE(FIRMWARE_KAVERI); 112 MODULE_FIRMWARE(FIRMWARE_HAWAII); 113 MODULE_FIRMWARE(FIRMWARE_MULLINS); 114 #endif 115 MODULE_FIRMWARE(FIRMWARE_TONGA); 116 MODULE_FIRMWARE(FIRMWARE_CARRIZO); 117 MODULE_FIRMWARE(FIRMWARE_FIJI); 118 MODULE_FIRMWARE(FIRMWARE_STONEY); 119 MODULE_FIRMWARE(FIRMWARE_POLARIS10); 120 MODULE_FIRMWARE(FIRMWARE_POLARIS11); 121 MODULE_FIRMWARE(FIRMWARE_POLARIS12); 122 MODULE_FIRMWARE(FIRMWARE_VEGAM); 123 124 MODULE_FIRMWARE(FIRMWARE_VEGA10); 125 MODULE_FIRMWARE(FIRMWARE_VEGA12); 126 MODULE_FIRMWARE(FIRMWARE_VEGA20); 127 128 static void amdgpu_uvd_idle_work_handler(struct work_struct *work); 129 130 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) 131 { 132 unsigned long bo_size; 133 const char *fw_name; 134 const struct common_firmware_header *hdr; 135 unsigned family_id; 136 int i, j, r; 137 138 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); 139 140 switch (adev->asic_type) { 141 #ifdef CONFIG_DRM_AMDGPU_CIK 142 case CHIP_BONAIRE: 143 fw_name = FIRMWARE_BONAIRE; 144 break; 145 case CHIP_KABINI: 146 fw_name = FIRMWARE_KABINI; 147 break; 148 case CHIP_KAVERI: 149 fw_name = FIRMWARE_KAVERI; 150 break; 151 case CHIP_HAWAII: 152 fw_name = FIRMWARE_HAWAII; 153 break; 154 case CHIP_MULLINS: 155 fw_name = FIRMWARE_MULLINS; 156 break; 157 #endif 158 case CHIP_TONGA: 159 fw_name = FIRMWARE_TONGA; 160 break; 161 case CHIP_FIJI: 162 fw_name = FIRMWARE_FIJI; 163 break; 164 case CHIP_CARRIZO: 165 fw_name = FIRMWARE_CARRIZO; 166 break; 167 case CHIP_STONEY: 168 fw_name = FIRMWARE_STONEY; 169 break; 170 case CHIP_POLARIS10: 171 fw_name = FIRMWARE_POLARIS10; 172 break; 173 case CHIP_POLARIS11: 174 fw_name = FIRMWARE_POLARIS11; 175 break; 176 case CHIP_POLARIS12: 177 fw_name = FIRMWARE_POLARIS12; 178 break; 179 case CHIP_VEGA10: 180 fw_name = FIRMWARE_VEGA10; 181 break; 182 case CHIP_VEGA12: 183 fw_name = FIRMWARE_VEGA12; 184 break; 185 case CHIP_VEGAM: 186 fw_name = FIRMWARE_VEGAM; 187 break; 188 case CHIP_VEGA20: 189 fw_name = FIRMWARE_VEGA20; 190 break; 191 default: 192 return -EINVAL; 193 } 194 195 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); 196 if (r) { 197 dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", 198 fw_name); 199 return r; 200 } 201 202 r = amdgpu_ucode_validate(adev->uvd.fw); 203 if (r) { 204 dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", 205 fw_name); 206 release_firmware(adev->uvd.fw); 207 adev->uvd.fw = NULL; 208 return r; 209 } 210 211 /* Set the default UVD handles that the firmware can handle */ 212 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; 213 214 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 215 family_id = le32_to_cpu(hdr->ucode_version) & 0xff; 216 217 if (adev->asic_type < CHIP_VEGA20) { 218 unsigned version_major, version_minor; 219 220 version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff; 221 version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 222 DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", 223 version_major, version_minor, family_id); 224 225 /* 226 * Limit the number of UVD handles depending on microcode major 227 * and minor versions. The firmware version which has 40 UVD 228 * instances support is 1.80. So all subsequent versions should 229 * also have the same support. 230 */ 231 if ((version_major > 0x01) || 232 ((version_major == 0x01) && (version_minor >= 0x50))) 233 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 234 235 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | 236 (family_id << 8)); 237 238 if ((adev->asic_type == CHIP_POLARIS10 || 239 adev->asic_type == CHIP_POLARIS11) && 240 (adev->uvd.fw_version < FW_1_66_16)) 241 DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", 242 version_major, version_minor); 243 } else { 244 unsigned int enc_major, enc_minor, dec_minor; 245 246 dec_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff; 247 enc_minor = (le32_to_cpu(hdr->ucode_version) >> 24) & 0x3f; 248 enc_major = (le32_to_cpu(hdr->ucode_version) >> 30) & 0x3; 249 DRM_INFO("Found UVD firmware ENC: %hu.%hu DEC: .%hu Family ID: %hu\n", 250 enc_major, enc_minor, dec_minor, family_id); 251 252 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; 253 254 adev->uvd.fw_version = le32_to_cpu(hdr->ucode_version); 255 } 256 257 bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE 258 + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles; 259 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) 260 bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); 261 262 for (j = 0; j < adev->uvd.num_uvd_inst; j++) { 263 if (adev->uvd.harvest_config & (1 << j)) 264 continue; 265 r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, 266 AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.inst[j].vcpu_bo, 267 &adev->uvd.inst[j].gpu_addr, &adev->uvd.inst[j].cpu_addr); 268 if (r) { 269 dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r); 270 return r; 271 } 272 } 273 274 for (i = 0; i < adev->uvd.max_handles; ++i) { 275 atomic_set(&adev->uvd.handles[i], 0); 276 adev->uvd.filp[i] = NULL; 277 } 278 279 /* from uvd v5.0 HW addressing capacity increased to 64 bits */ 280 if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) 281 adev->uvd.address_64_bit = true; 282 283 switch (adev->asic_type) { 284 case CHIP_TONGA: 285 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; 286 break; 287 case CHIP_CARRIZO: 288 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; 289 break; 290 case CHIP_FIJI: 291 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; 292 break; 293 case CHIP_STONEY: 294 adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; 295 break; 296 default: 297 adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10; 298 } 299 300 return 0; 301 } 302 303 int amdgpu_uvd_sw_fini(struct amdgpu_device *adev) 304 { 305 int i, j; 306 307 cancel_delayed_work_sync(&adev->uvd.idle_work); 308 drm_sched_entity_destroy(&adev->uvd.entity); 309 310 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 311 if (adev->uvd.harvest_config & (1 << j)) 312 continue; 313 kvfree(adev->uvd.inst[j].saved_bo); 314 315 amdgpu_bo_free_kernel(&adev->uvd.inst[j].vcpu_bo, 316 &adev->uvd.inst[j].gpu_addr, 317 (void **)&adev->uvd.inst[j].cpu_addr); 318 319 amdgpu_ring_fini(&adev->uvd.inst[j].ring); 320 321 for (i = 0; i < AMDGPU_MAX_UVD_ENC_RINGS; ++i) 322 amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]); 323 } 324 release_firmware(adev->uvd.fw); 325 326 return 0; 327 } 328 329 /** 330 * amdgpu_uvd_entity_init - init entity 331 * 332 * @adev: amdgpu_device pointer 333 * 334 */ 335 int amdgpu_uvd_entity_init(struct amdgpu_device *adev) 336 { 337 struct amdgpu_ring *ring; 338 struct drm_gpu_scheduler *sched; 339 int r; 340 341 ring = &adev->uvd.inst[0].ring; 342 sched = &ring->sched; 343 r = drm_sched_entity_init(&adev->uvd.entity, DRM_SCHED_PRIORITY_NORMAL, 344 &sched, 1, NULL); 345 if (r) { 346 DRM_ERROR("Failed setting up UVD kernel entity.\n"); 347 return r; 348 } 349 350 return 0; 351 } 352 353 int amdgpu_uvd_suspend(struct amdgpu_device *adev) 354 { 355 unsigned size; 356 void *ptr; 357 int i, j; 358 bool in_ras_intr = amdgpu_ras_intr_triggered(); 359 360 cancel_delayed_work_sync(&adev->uvd.idle_work); 361 362 /* only valid for physical mode */ 363 if (adev->asic_type < CHIP_POLARIS10) { 364 for (i = 0; i < adev->uvd.max_handles; ++i) 365 if (atomic_read(&adev->uvd.handles[i])) 366 break; 367 368 if (i == adev->uvd.max_handles) 369 return 0; 370 } 371 372 for (j = 0; j < adev->uvd.num_uvd_inst; ++j) { 373 if (adev->uvd.harvest_config & (1 << j)) 374 continue; 375 if (adev->uvd.inst[j].vcpu_bo == NULL) 376 continue; 377 378 size = amdgpu_bo_size(adev->uvd.inst[j].vcpu_bo); 379 ptr = adev->uvd.inst[j].cpu_addr; 380 381 adev->uvd.inst[j].saved_bo = kvmalloc(size, GFP_KERNEL); 382 if (!adev->uvd.inst[j].saved_bo) 383 return -ENOMEM; 384 385 /* re-write 0 since err_event_athub will corrupt VCPU buffer */ 386 if (in_ras_intr) 387 memset(adev->uvd.inst[j].saved_bo, 0, size); 388 else 389 memcpy_fromio(adev->uvd.inst[j].saved_bo, ptr, size); 390 } 391 392 if (in_ras_intr) 393 DRM_WARN("UVD VCPU state may lost due to RAS ERREVENT_ATHUB_INTERRUPT\n"); 394 395 return 0; 396 } 397 398 int amdgpu_uvd_resume(struct amdgpu_device *adev) 399 { 400 unsigned size; 401 void *ptr; 402 int i; 403 404 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { 405 if (adev->uvd.harvest_config & (1 << i)) 406 continue; 407 if (adev->uvd.inst[i].vcpu_bo == NULL) 408 return -EINVAL; 409 410 size = amdgpu_bo_size(adev->uvd.inst[i].vcpu_bo); 411 ptr = adev->uvd.inst[i].cpu_addr; 412 413 if (adev->uvd.inst[i].saved_bo != NULL) { 414 memcpy_toio(ptr, adev->uvd.inst[i].saved_bo, size); 415 kvfree(adev->uvd.inst[i].saved_bo); 416 adev->uvd.inst[i].saved_bo = NULL; 417 } else { 418 const struct common_firmware_header *hdr; 419 unsigned offset; 420 421 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; 422 if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 423 offset = le32_to_cpu(hdr->ucode_array_offset_bytes); 424 memcpy_toio(adev->uvd.inst[i].cpu_addr, adev->uvd.fw->data + offset, 425 le32_to_cpu(hdr->ucode_size_bytes)); 426 size -= le32_to_cpu(hdr->ucode_size_bytes); 427 ptr += le32_to_cpu(hdr->ucode_size_bytes); 428 } 429 memset_io(ptr, 0, size); 430 /* to restore uvd fence seq */ 431 amdgpu_fence_driver_force_completion(&adev->uvd.inst[i].ring); 432 } 433 } 434 return 0; 435 } 436 437 void amdgpu_uvd_free_handles(struct amdgpu_device *adev, struct drm_file *filp) 438 { 439 struct amdgpu_ring *ring = &adev->uvd.inst[0].ring; 440 int i, r; 441 442 for (i = 0; i < adev->uvd.max_handles; ++i) { 443 uint32_t handle = atomic_read(&adev->uvd.handles[i]); 444 445 if (handle != 0 && adev->uvd.filp[i] == filp) { 446 struct dma_fence *fence; 447 448 r = amdgpu_uvd_get_destroy_msg(ring, handle, false, 449 &fence); 450 if (r) { 451 DRM_ERROR("Error destroying UVD %d!\n", r); 452 continue; 453 } 454 455 dma_fence_wait(fence, false); 456 dma_fence_put(fence); 457 458 adev->uvd.filp[i] = NULL; 459 atomic_set(&adev->uvd.handles[i], 0); 460 } 461 } 462 } 463 464 static void amdgpu_uvd_force_into_uvd_segment(struct amdgpu_bo *abo) 465 { 466 int i; 467 for (i = 0; i < abo->placement.num_placement; ++i) { 468 abo->placements[i].fpfn = 0 >> PAGE_SHIFT; 469 abo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; 470 } 471 } 472 473 static u64 amdgpu_uvd_get_addr_from_ctx(struct amdgpu_uvd_cs_ctx *ctx) 474 { 475 uint32_t lo, hi; 476 uint64_t addr; 477 478 lo = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data0); 479 hi = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->data1); 480 addr = ((uint64_t)lo) | (((uint64_t)hi) << 32); 481 482 return addr; 483 } 484 485 /** 486 * amdgpu_uvd_cs_pass1 - first parsing round 487 * 488 * @ctx: UVD parser context 489 * 490 * Make sure UVD message and feedback buffers are in VRAM and 491 * nobody is violating an 256MB boundary. 492 */ 493 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) 494 { 495 struct ttm_operation_ctx tctx = { false, false }; 496 struct amdgpu_bo_va_mapping *mapping; 497 struct amdgpu_bo *bo; 498 uint32_t cmd; 499 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 500 int r = 0; 501 502 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 503 if (r) { 504 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 505 return r; 506 } 507 508 if (!ctx->parser->adev->uvd.address_64_bit) { 509 /* check if it's a message or feedback command */ 510 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 511 if (cmd == 0x0 || cmd == 0x3) { 512 /* yes, force it into VRAM */ 513 uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM; 514 amdgpu_bo_placement_from_domain(bo, domain); 515 } 516 amdgpu_uvd_force_into_uvd_segment(bo); 517 518 r = ttm_bo_validate(&bo->tbo, &bo->placement, &tctx); 519 } 520 521 return r; 522 } 523 524 /** 525 * amdgpu_uvd_cs_msg_decode - handle UVD decode message 526 * 527 * @msg: pointer to message structure 528 * @buf_sizes: returned buffer sizes 529 * 530 * Peek into the decode message and calculate the necessary buffer sizes. 531 */ 532 static int amdgpu_uvd_cs_msg_decode(struct amdgpu_device *adev, uint32_t *msg, 533 unsigned buf_sizes[]) 534 { 535 unsigned stream_type = msg[4]; 536 unsigned width = msg[6]; 537 unsigned height = msg[7]; 538 unsigned dpb_size = msg[9]; 539 unsigned pitch = msg[28]; 540 unsigned level = msg[57]; 541 542 unsigned width_in_mb = width / 16; 543 unsigned height_in_mb = ALIGN(height / 16, 2); 544 unsigned fs_in_mb = width_in_mb * height_in_mb; 545 546 unsigned image_size, tmp, min_dpb_size, num_dpb_buffer; 547 unsigned min_ctx_size = ~0; 548 549 image_size = width * height; 550 image_size += image_size / 2; 551 image_size = ALIGN(image_size, 1024); 552 553 switch (stream_type) { 554 case 0: /* H264 */ 555 switch(level) { 556 case 30: 557 num_dpb_buffer = 8100 / fs_in_mb; 558 break; 559 case 31: 560 num_dpb_buffer = 18000 / fs_in_mb; 561 break; 562 case 32: 563 num_dpb_buffer = 20480 / fs_in_mb; 564 break; 565 case 41: 566 num_dpb_buffer = 32768 / fs_in_mb; 567 break; 568 case 42: 569 num_dpb_buffer = 34816 / fs_in_mb; 570 break; 571 case 50: 572 num_dpb_buffer = 110400 / fs_in_mb; 573 break; 574 case 51: 575 num_dpb_buffer = 184320 / fs_in_mb; 576 break; 577 default: 578 num_dpb_buffer = 184320 / fs_in_mb; 579 break; 580 } 581 num_dpb_buffer++; 582 if (num_dpb_buffer > 17) 583 num_dpb_buffer = 17; 584 585 /* reference picture buffer */ 586 min_dpb_size = image_size * num_dpb_buffer; 587 588 /* macroblock context buffer */ 589 min_dpb_size += width_in_mb * height_in_mb * num_dpb_buffer * 192; 590 591 /* IT surface buffer */ 592 min_dpb_size += width_in_mb * height_in_mb * 32; 593 break; 594 595 case 1: /* VC1 */ 596 597 /* reference picture buffer */ 598 min_dpb_size = image_size * 3; 599 600 /* CONTEXT_BUFFER */ 601 min_dpb_size += width_in_mb * height_in_mb * 128; 602 603 /* IT surface buffer */ 604 min_dpb_size += width_in_mb * 64; 605 606 /* DB surface buffer */ 607 min_dpb_size += width_in_mb * 128; 608 609 /* BP */ 610 tmp = max(width_in_mb, height_in_mb); 611 min_dpb_size += ALIGN(tmp * 7 * 16, 64); 612 break; 613 614 case 3: /* MPEG2 */ 615 616 /* reference picture buffer */ 617 min_dpb_size = image_size * 3; 618 break; 619 620 case 4: /* MPEG4 */ 621 622 /* reference picture buffer */ 623 min_dpb_size = image_size * 3; 624 625 /* CM */ 626 min_dpb_size += width_in_mb * height_in_mb * 64; 627 628 /* IT surface buffer */ 629 min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); 630 break; 631 632 case 7: /* H264 Perf */ 633 switch(level) { 634 case 30: 635 num_dpb_buffer = 8100 / fs_in_mb; 636 break; 637 case 31: 638 num_dpb_buffer = 18000 / fs_in_mb; 639 break; 640 case 32: 641 num_dpb_buffer = 20480 / fs_in_mb; 642 break; 643 case 41: 644 num_dpb_buffer = 32768 / fs_in_mb; 645 break; 646 case 42: 647 num_dpb_buffer = 34816 / fs_in_mb; 648 break; 649 case 50: 650 num_dpb_buffer = 110400 / fs_in_mb; 651 break; 652 case 51: 653 num_dpb_buffer = 184320 / fs_in_mb; 654 break; 655 default: 656 num_dpb_buffer = 184320 / fs_in_mb; 657 break; 658 } 659 num_dpb_buffer++; 660 if (num_dpb_buffer > 17) 661 num_dpb_buffer = 17; 662 663 /* reference picture buffer */ 664 min_dpb_size = image_size * num_dpb_buffer; 665 666 if (!adev->uvd.use_ctx_buf){ 667 /* macroblock context buffer */ 668 min_dpb_size += 669 width_in_mb * height_in_mb * num_dpb_buffer * 192; 670 671 /* IT surface buffer */ 672 min_dpb_size += width_in_mb * height_in_mb * 32; 673 } else { 674 /* macroblock context buffer */ 675 min_ctx_size = 676 width_in_mb * height_in_mb * num_dpb_buffer * 192; 677 } 678 break; 679 680 case 8: /* MJPEG */ 681 min_dpb_size = 0; 682 break; 683 684 case 16: /* H265 */ 685 image_size = (ALIGN(width, 16) * ALIGN(height, 16) * 3) / 2; 686 image_size = ALIGN(image_size, 256); 687 688 num_dpb_buffer = (le32_to_cpu(msg[59]) & 0xff) + 2; 689 min_dpb_size = image_size * num_dpb_buffer; 690 min_ctx_size = ((width + 255) / 16) * ((height + 255) / 16) 691 * 16 * num_dpb_buffer + 52 * 1024; 692 break; 693 694 default: 695 DRM_ERROR("UVD codec not handled %d!\n", stream_type); 696 return -EINVAL; 697 } 698 699 if (width > pitch) { 700 DRM_ERROR("Invalid UVD decoding target pitch!\n"); 701 return -EINVAL; 702 } 703 704 if (dpb_size < min_dpb_size) { 705 DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", 706 dpb_size, min_dpb_size); 707 return -EINVAL; 708 } 709 710 buf_sizes[0x1] = dpb_size; 711 buf_sizes[0x2] = image_size; 712 buf_sizes[0x4] = min_ctx_size; 713 /* store image width to adjust nb memory pstate */ 714 adev->uvd.decode_image_width = width; 715 return 0; 716 } 717 718 /** 719 * amdgpu_uvd_cs_msg - handle UVD message 720 * 721 * @ctx: UVD parser context 722 * @bo: buffer object containing the message 723 * @offset: offset into the buffer object 724 * 725 * Peek into the UVD message and extract the session id. 726 * Make sure that we don't open up to many sessions. 727 */ 728 static int amdgpu_uvd_cs_msg(struct amdgpu_uvd_cs_ctx *ctx, 729 struct amdgpu_bo *bo, unsigned offset) 730 { 731 struct amdgpu_device *adev = ctx->parser->adev; 732 int32_t *msg, msg_type, handle; 733 void *ptr; 734 long r; 735 int i; 736 737 if (offset & 0x3F) { 738 DRM_ERROR("UVD messages must be 64 byte aligned!\n"); 739 return -EINVAL; 740 } 741 742 r = amdgpu_bo_kmap(bo, &ptr); 743 if (r) { 744 DRM_ERROR("Failed mapping the UVD) message (%ld)!\n", r); 745 return r; 746 } 747 748 msg = ptr + offset; 749 750 msg_type = msg[1]; 751 handle = msg[2]; 752 753 if (handle == 0) { 754 DRM_ERROR("Invalid UVD handle!\n"); 755 return -EINVAL; 756 } 757 758 switch (msg_type) { 759 case 0: 760 /* it's a create msg, calc image size (width * height) */ 761 amdgpu_bo_kunmap(bo); 762 763 /* try to alloc a new handle */ 764 for (i = 0; i < adev->uvd.max_handles; ++i) { 765 if (atomic_read(&adev->uvd.handles[i]) == handle) { 766 DRM_ERROR(")Handle 0x%x already in use!\n", 767 handle); 768 return -EINVAL; 769 } 770 771 if (!atomic_cmpxchg(&adev->uvd.handles[i], 0, handle)) { 772 adev->uvd.filp[i] = ctx->parser->filp; 773 return 0; 774 } 775 } 776 777 DRM_ERROR("No more free UVD handles!\n"); 778 return -ENOSPC; 779 780 case 1: 781 /* it's a decode msg, calc buffer sizes */ 782 r = amdgpu_uvd_cs_msg_decode(adev, msg, ctx->buf_sizes); 783 amdgpu_bo_kunmap(bo); 784 if (r) 785 return r; 786 787 /* validate the handle */ 788 for (i = 0; i < adev->uvd.max_handles; ++i) { 789 if (atomic_read(&adev->uvd.handles[i]) == handle) { 790 if (adev->uvd.filp[i] != ctx->parser->filp) { 791 DRM_ERROR("UVD handle collision detected!\n"); 792 return -EINVAL; 793 } 794 return 0; 795 } 796 } 797 798 DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); 799 return -ENOENT; 800 801 case 2: 802 /* it's a destroy msg, free the handle */ 803 for (i = 0; i < adev->uvd.max_handles; ++i) 804 atomic_cmpxchg(&adev->uvd.handles[i], handle, 0); 805 amdgpu_bo_kunmap(bo); 806 return 0; 807 808 default: 809 DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); 810 return -EINVAL; 811 } 812 BUG(); 813 return -EINVAL; 814 } 815 816 /** 817 * amdgpu_uvd_cs_pass2 - second parsing round 818 * 819 * @ctx: UVD parser context 820 * 821 * Patch buffer addresses, make sure buffer sizes are correct. 822 */ 823 static int amdgpu_uvd_cs_pass2(struct amdgpu_uvd_cs_ctx *ctx) 824 { 825 struct amdgpu_bo_va_mapping *mapping; 826 struct amdgpu_bo *bo; 827 uint32_t cmd; 828 uint64_t start, end; 829 uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx); 830 int r; 831 832 r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping); 833 if (r) { 834 DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr); 835 return r; 836 } 837 838 start = amdgpu_bo_gpu_offset(bo); 839 840 end = (mapping->last + 1 - mapping->start); 841 end = end * AMDGPU_GPU_PAGE_SIZE + start; 842 843 addr -= mapping->start * AMDGPU_GPU_PAGE_SIZE; 844 start += addr; 845 846 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data0, 847 lower_32_bits(start)); 848 amdgpu_set_ib_value(ctx->parser, ctx->ib_idx, ctx->data1, 849 upper_32_bits(start)); 850 851 cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1; 852 if (cmd < 0x4) { 853 if ((end - start) < ctx->buf_sizes[cmd]) { 854 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 855 (unsigned)(end - start), 856 ctx->buf_sizes[cmd]); 857 return -EINVAL; 858 } 859 860 } else if (cmd == 0x206) { 861 if ((end - start) < ctx->buf_sizes[4]) { 862 DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, 863 (unsigned)(end - start), 864 ctx->buf_sizes[4]); 865 return -EINVAL; 866 } 867 } else if ((cmd != 0x100) && (cmd != 0x204)) { 868 DRM_ERROR("invalid UVD command %X!\n", cmd); 869 return -EINVAL; 870 } 871 872 if (!ctx->parser->adev->uvd.address_64_bit) { 873 if ((start >> 28) != ((end - 1) >> 28)) { 874 DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", 875 start, end); 876 return -EINVAL; 877 } 878 879 if ((cmd == 0 || cmd == 0x3) && 880 (start >> 28) != (ctx->parser->adev->uvd.inst->gpu_addr >> 28)) { 881 DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", 882 start, end); 883 return -EINVAL; 884 } 885 } 886 887 if (cmd == 0) { 888 ctx->has_msg_cmd = true; 889 r = amdgpu_uvd_cs_msg(ctx, bo, addr); 890 if (r) 891 return r; 892 } else if (!ctx->has_msg_cmd) { 893 DRM_ERROR("Message needed before other commands are send!\n"); 894 return -EINVAL; 895 } 896 897 return 0; 898 } 899 900 /** 901 * amdgpu_uvd_cs_reg - parse register writes 902 * 903 * @ctx: UVD parser context 904 * @cb: callback function 905 * 906 * Parse the register writes, call cb on each complete command. 907 */ 908 static int amdgpu_uvd_cs_reg(struct amdgpu_uvd_cs_ctx *ctx, 909 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 910 { 911 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 912 int i, r; 913 914 ctx->idx++; 915 for (i = 0; i <= ctx->count; ++i) { 916 unsigned reg = ctx->reg + i; 917 918 if (ctx->idx >= ib->length_dw) { 919 DRM_ERROR("Register command after end of CS!\n"); 920 return -EINVAL; 921 } 922 923 switch (reg) { 924 case mmUVD_GPCOM_VCPU_DATA0: 925 ctx->data0 = ctx->idx; 926 break; 927 case mmUVD_GPCOM_VCPU_DATA1: 928 ctx->data1 = ctx->idx; 929 break; 930 case mmUVD_GPCOM_VCPU_CMD: 931 r = cb(ctx); 932 if (r) 933 return r; 934 break; 935 case mmUVD_ENGINE_CNTL: 936 case mmUVD_NO_OP: 937 break; 938 default: 939 DRM_ERROR("Invalid reg 0x%X!\n", reg); 940 return -EINVAL; 941 } 942 ctx->idx++; 943 } 944 return 0; 945 } 946 947 /** 948 * amdgpu_uvd_cs_packets - parse UVD packets 949 * 950 * @ctx: UVD parser context 951 * @cb: callback function 952 * 953 * Parse the command stream packets. 954 */ 955 static int amdgpu_uvd_cs_packets(struct amdgpu_uvd_cs_ctx *ctx, 956 int (*cb)(struct amdgpu_uvd_cs_ctx *ctx)) 957 { 958 struct amdgpu_ib *ib = &ctx->parser->job->ibs[ctx->ib_idx]; 959 int r; 960 961 for (ctx->idx = 0 ; ctx->idx < ib->length_dw; ) { 962 uint32_t cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx); 963 unsigned type = CP_PACKET_GET_TYPE(cmd); 964 switch (type) { 965 case PACKET_TYPE0: 966 ctx->reg = CP_PACKET0_GET_REG(cmd); 967 ctx->count = CP_PACKET_GET_COUNT(cmd); 968 r = amdgpu_uvd_cs_reg(ctx, cb); 969 if (r) 970 return r; 971 break; 972 case PACKET_TYPE2: 973 ++ctx->idx; 974 break; 975 default: 976 DRM_ERROR("Unknown packet type %d !\n", type); 977 return -EINVAL; 978 } 979 } 980 return 0; 981 } 982 983 /** 984 * amdgpu_uvd_ring_parse_cs - UVD command submission parser 985 * 986 * @parser: Command submission parser context 987 * 988 * Parse the command stream, patch in addresses as necessary. 989 */ 990 int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser, uint32_t ib_idx) 991 { 992 struct amdgpu_uvd_cs_ctx ctx = {}; 993 unsigned buf_sizes[] = { 994 [0x00000000] = 2048, 995 [0x00000001] = 0xFFFFFFFF, 996 [0x00000002] = 0xFFFFFFFF, 997 [0x00000003] = 2048, 998 [0x00000004] = 0xFFFFFFFF, 999 }; 1000 struct amdgpu_ib *ib = &parser->job->ibs[ib_idx]; 1001 int r; 1002 1003 parser->job->vm = NULL; 1004 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo); 1005 1006 if (ib->length_dw % 16) { 1007 DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", 1008 ib->length_dw); 1009 return -EINVAL; 1010 } 1011 1012 ctx.parser = parser; 1013 ctx.buf_sizes = buf_sizes; 1014 ctx.ib_idx = ib_idx; 1015 1016 /* first round only required on chips without UVD 64 bit address support */ 1017 if (!parser->adev->uvd.address_64_bit) { 1018 /* first round, make sure the buffers are actually in the UVD segment */ 1019 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass1); 1020 if (r) 1021 return r; 1022 } 1023 1024 /* second round, patch buffer addresses into the command stream */ 1025 r = amdgpu_uvd_cs_packets(&ctx, amdgpu_uvd_cs_pass2); 1026 if (r) 1027 return r; 1028 1029 if (!ctx.has_msg_cmd) { 1030 DRM_ERROR("UVD-IBs need a msg command!\n"); 1031 return -EINVAL; 1032 } 1033 1034 return 0; 1035 } 1036 1037 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, 1038 bool direct, struct dma_fence **fence) 1039 { 1040 struct amdgpu_device *adev = ring->adev; 1041 struct dma_fence *f = NULL; 1042 struct amdgpu_job *job; 1043 struct amdgpu_ib *ib; 1044 uint32_t data[4]; 1045 uint64_t addr; 1046 long r; 1047 int i; 1048 unsigned offset_idx = 0; 1049 unsigned offset[3] = { UVD_BASE_SI, 0, 0 }; 1050 1051 amdgpu_bo_kunmap(bo); 1052 amdgpu_bo_unpin(bo); 1053 1054 if (!ring->adev->uvd.address_64_bit) { 1055 struct ttm_operation_ctx ctx = { true, false }; 1056 1057 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM); 1058 amdgpu_uvd_force_into_uvd_segment(bo); 1059 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 1060 if (r) 1061 goto err; 1062 } 1063 1064 r = amdgpu_job_alloc_with_ib(adev, 64, &job); 1065 if (r) 1066 goto err; 1067 1068 if (adev->asic_type >= CHIP_VEGA10) { 1069 offset_idx = 1 + ring->me; 1070 offset[1] = adev->reg_offset[UVD_HWIP][0][1]; 1071 offset[2] = adev->reg_offset[UVD_HWIP][1][1]; 1072 } 1073 1074 data[0] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA0, 0); 1075 data[1] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_DATA1, 0); 1076 data[2] = PACKET0(offset[offset_idx] + UVD_GPCOM_VCPU_CMD, 0); 1077 data[3] = PACKET0(offset[offset_idx] + UVD_NO_OP, 0); 1078 1079 ib = &job->ibs[0]; 1080 addr = amdgpu_bo_gpu_offset(bo); 1081 ib->ptr[0] = data[0]; 1082 ib->ptr[1] = addr; 1083 ib->ptr[2] = data[1]; 1084 ib->ptr[3] = addr >> 32; 1085 ib->ptr[4] = data[2]; 1086 ib->ptr[5] = 0; 1087 for (i = 6; i < 16; i += 2) { 1088 ib->ptr[i] = data[3]; 1089 ib->ptr[i+1] = 0; 1090 } 1091 ib->length_dw = 16; 1092 1093 if (direct) { 1094 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, 1095 true, false, 1096 msecs_to_jiffies(10)); 1097 if (r == 0) 1098 r = -ETIMEDOUT; 1099 if (r < 0) 1100 goto err_free; 1101 1102 r = amdgpu_job_submit_direct(job, ring, &f); 1103 if (r) 1104 goto err_free; 1105 } else { 1106 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.base.resv, 1107 AMDGPU_FENCE_OWNER_UNDEFINED, false); 1108 if (r) 1109 goto err_free; 1110 1111 r = amdgpu_job_submit(job, &adev->uvd.entity, 1112 AMDGPU_FENCE_OWNER_UNDEFINED, &f); 1113 if (r) 1114 goto err_free; 1115 } 1116 1117 amdgpu_bo_fence(bo, f, false); 1118 amdgpu_bo_unreserve(bo); 1119 amdgpu_bo_unref(&bo); 1120 1121 if (fence) 1122 *fence = dma_fence_get(f); 1123 dma_fence_put(f); 1124 1125 return 0; 1126 1127 err_free: 1128 amdgpu_job_free(job); 1129 1130 err: 1131 amdgpu_bo_unreserve(bo); 1132 amdgpu_bo_unref(&bo); 1133 return r; 1134 } 1135 1136 /* multiple fence commands without any stream commands in between can 1137 crash the vcpu so just try to emmit a dummy create/destroy msg to 1138 avoid this */ 1139 int amdgpu_uvd_get_create_msg(struct amdgpu_ring *ring, uint32_t handle, 1140 struct dma_fence **fence) 1141 { 1142 struct amdgpu_device *adev = ring->adev; 1143 struct amdgpu_bo *bo = NULL; 1144 uint32_t *msg; 1145 int r, i; 1146 1147 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1148 AMDGPU_GEM_DOMAIN_VRAM, 1149 &bo, NULL, (void **)&msg); 1150 if (r) 1151 return r; 1152 1153 /* stitch together an UVD create msg */ 1154 msg[0] = cpu_to_le32(0x00000de4); 1155 msg[1] = cpu_to_le32(0x00000000); 1156 msg[2] = cpu_to_le32(handle); 1157 msg[3] = cpu_to_le32(0x00000000); 1158 msg[4] = cpu_to_le32(0x00000000); 1159 msg[5] = cpu_to_le32(0x00000000); 1160 msg[6] = cpu_to_le32(0x00000000); 1161 msg[7] = cpu_to_le32(0x00000780); 1162 msg[8] = cpu_to_le32(0x00000440); 1163 msg[9] = cpu_to_le32(0x00000000); 1164 msg[10] = cpu_to_le32(0x01b37000); 1165 for (i = 11; i < 1024; ++i) 1166 msg[i] = cpu_to_le32(0x0); 1167 1168 return amdgpu_uvd_send_msg(ring, bo, true, fence); 1169 } 1170 1171 int amdgpu_uvd_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle, 1172 bool direct, struct dma_fence **fence) 1173 { 1174 struct amdgpu_device *adev = ring->adev; 1175 struct amdgpu_bo *bo = NULL; 1176 uint32_t *msg; 1177 int r, i; 1178 1179 r = amdgpu_bo_create_reserved(adev, 1024, PAGE_SIZE, 1180 AMDGPU_GEM_DOMAIN_VRAM, 1181 &bo, NULL, (void **)&msg); 1182 if (r) 1183 return r; 1184 1185 /* stitch together an UVD destroy msg */ 1186 msg[0] = cpu_to_le32(0x00000de4); 1187 msg[1] = cpu_to_le32(0x00000002); 1188 msg[2] = cpu_to_le32(handle); 1189 msg[3] = cpu_to_le32(0x00000000); 1190 for (i = 4; i < 1024; ++i) 1191 msg[i] = cpu_to_le32(0x0); 1192 1193 return amdgpu_uvd_send_msg(ring, bo, direct, fence); 1194 } 1195 1196 static void amdgpu_uvd_idle_work_handler(struct work_struct *work) 1197 { 1198 struct amdgpu_device *adev = 1199 container_of(work, struct amdgpu_device, uvd.idle_work.work); 1200 unsigned fences = 0, i, j; 1201 1202 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) { 1203 if (adev->uvd.harvest_config & (1 << i)) 1204 continue; 1205 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring); 1206 for (j = 0; j < adev->uvd.num_enc_rings; ++j) { 1207 fences += amdgpu_fence_count_emitted(&adev->uvd.inst[i].ring_enc[j]); 1208 } 1209 } 1210 1211 if (fences == 0) { 1212 if (adev->pm.dpm_enabled) { 1213 amdgpu_dpm_enable_uvd(adev, false); 1214 } else { 1215 amdgpu_asic_set_uvd_clocks(adev, 0, 0); 1216 /* shutdown the UVD block */ 1217 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1218 AMD_PG_STATE_GATE); 1219 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1220 AMD_CG_STATE_GATE); 1221 } 1222 } else { 1223 schedule_delayed_work(&adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1224 } 1225 } 1226 1227 void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) 1228 { 1229 struct amdgpu_device *adev = ring->adev; 1230 bool set_clocks; 1231 1232 if (amdgpu_sriov_vf(adev)) 1233 return; 1234 1235 set_clocks = !cancel_delayed_work_sync(&adev->uvd.idle_work); 1236 if (set_clocks) { 1237 if (adev->pm.dpm_enabled) { 1238 amdgpu_dpm_enable_uvd(adev, true); 1239 } else { 1240 amdgpu_asic_set_uvd_clocks(adev, 53300, 40000); 1241 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1242 AMD_CG_STATE_UNGATE); 1243 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_UVD, 1244 AMD_PG_STATE_UNGATE); 1245 } 1246 } 1247 } 1248 1249 void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) 1250 { 1251 if (!amdgpu_sriov_vf(ring->adev)) 1252 schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); 1253 } 1254 1255 /** 1256 * amdgpu_uvd_ring_test_ib - test ib execution 1257 * 1258 * @ring: amdgpu_ring pointer 1259 * 1260 * Test if we can successfully execute an IB 1261 */ 1262 int amdgpu_uvd_ring_test_ib(struct amdgpu_ring *ring, long timeout) 1263 { 1264 struct dma_fence *fence; 1265 long r; 1266 1267 r = amdgpu_uvd_get_create_msg(ring, 1, NULL); 1268 if (r) 1269 goto error; 1270 1271 r = amdgpu_uvd_get_destroy_msg(ring, 1, true, &fence); 1272 if (r) 1273 goto error; 1274 1275 r = dma_fence_wait_timeout(fence, false, timeout); 1276 if (r == 0) 1277 r = -ETIMEDOUT; 1278 else if (r > 0) 1279 r = 0; 1280 1281 dma_fence_put(fence); 1282 1283 error: 1284 return r; 1285 } 1286 1287 /** 1288 * amdgpu_uvd_used_handles - returns used UVD handles 1289 * 1290 * @adev: amdgpu_device pointer 1291 * 1292 * Returns the number of UVD handles in use 1293 */ 1294 uint32_t amdgpu_uvd_used_handles(struct amdgpu_device *adev) 1295 { 1296 unsigned i; 1297 uint32_t used_handles = 0; 1298 1299 for (i = 0; i < adev->uvd.max_handles; ++i) { 1300 /* 1301 * Handles can be freed in any order, and not 1302 * necessarily linear. So we need to count 1303 * all non-zero handles. 1304 */ 1305 if (atomic_read(&adev->uvd.handles[i])) 1306 used_handles++; 1307 } 1308 1309 return used_handles; 1310 } 1311
Indexes created Mon Sep 29 21:09:56 GMT 2025