cikd.h revision 1.1.1.1
1 /* $NetBSD: cikd.h,v 1.1.1.1 2018/08/27 01:34:44 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef CIK_H 27 #define CIK_H 28 29 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 30 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 31 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 32 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 33 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 34 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 35 #define MC_SEQ_MISC0__MT__HBM 0x60000000 36 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 37 38 #define CP_ME_TABLE_SIZE 96 39 40 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 41 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 42 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 43 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 44 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 45 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 46 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 47 48 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 49 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 50 51 #define CIK_RB_BITMAP_WIDTH_PER_SH 2 52 #define HAWAII_RB_BITMAP_WIDTH_PER_SH 4 53 54 #define AMDGPU_NUM_OF_VMIDS 8 55 56 #define PIPEID(x) ((x) << 0) 57 #define MEID(x) ((x) << 2) 58 #define VMID(x) ((x) << 4) 59 #define QUEUEID(x) ((x) << 8) 60 61 #define mmCC_DRM_ID_STRAPS 0x1559 62 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 63 64 #define mmCHUB_CONTROL 0x619 65 #define BYPASS_VM (1 << 0) 66 67 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 68 69 #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 70 #define LUT_10BIT_BYPASS_EN (1 << 8) 71 72 # define CURSOR_MONO 0 73 # define CURSOR_24_1 1 74 # define CURSOR_24_8_PRE_MULT 2 75 # define CURSOR_24_8_UNPRE_MULT 3 76 # define CURSOR_URGENT_ALWAYS 0 77 # define CURSOR_URGENT_1_8 1 78 # define CURSOR_URGENT_1_4 2 79 # define CURSOR_URGENT_3_8 3 80 # define CURSOR_URGENT_1_2 4 81 82 # define GRPH_DEPTH_8BPP 0 83 # define GRPH_DEPTH_16BPP 1 84 # define GRPH_DEPTH_32BPP 2 85 /* 8 BPP */ 86 # define GRPH_FORMAT_INDEXED 0 87 /* 16 BPP */ 88 # define GRPH_FORMAT_ARGB1555 0 89 # define GRPH_FORMAT_ARGB565 1 90 # define GRPH_FORMAT_ARGB4444 2 91 # define GRPH_FORMAT_AI88 3 92 # define GRPH_FORMAT_MONO16 4 93 # define GRPH_FORMAT_BGRA5551 5 94 /* 32 BPP */ 95 # define GRPH_FORMAT_ARGB8888 0 96 # define GRPH_FORMAT_ARGB2101010 1 97 # define GRPH_FORMAT_32BPP_DIG 2 98 # define GRPH_FORMAT_8B_ARGB2101010 3 99 # define GRPH_FORMAT_BGRA1010102 4 100 # define GRPH_FORMAT_8B_BGRA1010102 5 101 # define GRPH_FORMAT_RGB111110 6 102 # define GRPH_FORMAT_BGR101111 7 103 # define ADDR_SURF_MACRO_TILE_ASPECT_1 0 104 # define ADDR_SURF_MACRO_TILE_ASPECT_2 1 105 # define ADDR_SURF_MACRO_TILE_ASPECT_4 2 106 # define ADDR_SURF_MACRO_TILE_ASPECT_8 3 107 # define GRPH_ARRAY_LINEAR_GENERAL 0 108 # define GRPH_ARRAY_LINEAR_ALIGNED 1 109 # define GRPH_ARRAY_1D_TILED_THIN1 2 110 # define GRPH_ARRAY_2D_TILED_THIN1 4 111 # define DISPLAY_MICRO_TILING 0 112 # define THIN_MICRO_TILING 1 113 # define DEPTH_MICRO_TILING 2 114 # define ROTATED_MICRO_TILING 4 115 # define GRPH_ENDIAN_NONE 0 116 # define GRPH_ENDIAN_8IN16 1 117 # define GRPH_ENDIAN_8IN32 2 118 # define GRPH_ENDIAN_8IN64 3 119 # define GRPH_RED_SEL_R 0 120 # define GRPH_RED_SEL_G 1 121 # define GRPH_RED_SEL_B 2 122 # define GRPH_RED_SEL_A 3 123 # define GRPH_GREEN_SEL_G 0 124 # define GRPH_GREEN_SEL_B 1 125 # define GRPH_GREEN_SEL_A 2 126 # define GRPH_GREEN_SEL_R 3 127 # define GRPH_BLUE_SEL_B 0 128 # define GRPH_BLUE_SEL_A 1 129 # define GRPH_BLUE_SEL_R 2 130 # define GRPH_BLUE_SEL_G 3 131 # define GRPH_ALPHA_SEL_A 0 132 # define GRPH_ALPHA_SEL_R 1 133 # define GRPH_ALPHA_SEL_G 2 134 # define GRPH_ALPHA_SEL_B 3 135 # define INPUT_GAMMA_USE_LUT 0 136 # define INPUT_GAMMA_BYPASS 1 137 # define INPUT_GAMMA_SRGB_24 2 138 # define INPUT_GAMMA_XVYCC_222 3 139 140 # define INPUT_CSC_BYPASS 0 141 # define INPUT_CSC_PROG_COEFF 1 142 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 143 144 # define OUTPUT_CSC_BYPASS 0 145 # define OUTPUT_CSC_TV_RGB 1 146 # define OUTPUT_CSC_YCBCR_601 2 147 # define OUTPUT_CSC_YCBCR_709 3 148 # define OUTPUT_CSC_PROG_COEFF 4 149 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 150 151 # define DEGAMMA_BYPASS 0 152 # define DEGAMMA_SRGB_24 1 153 # define DEGAMMA_XVYCC_222 2 154 # define GAMUT_REMAP_BYPASS 0 155 # define GAMUT_REMAP_PROG_COEFF 1 156 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 157 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 158 159 # define REGAMMA_BYPASS 0 160 # define REGAMMA_SRGB_24 1 161 # define REGAMMA_XVYCC_222 2 162 # define REGAMMA_PROG_A 3 163 # define REGAMMA_PROG_B 4 164 165 # define FMT_CLAMP_6BPC 0 166 # define FMT_CLAMP_8BPC 1 167 # define FMT_CLAMP_10BPC 2 168 169 # define HDMI_24BIT_DEEP_COLOR 0 170 # define HDMI_30BIT_DEEP_COLOR 1 171 # define HDMI_36BIT_DEEP_COLOR 2 172 # define HDMI_ACR_HW 0 173 # define HDMI_ACR_32 1 174 # define HDMI_ACR_44 2 175 # define HDMI_ACR_48 3 176 # define HDMI_ACR_X1 1 177 # define HDMI_ACR_X2 2 178 # define HDMI_ACR_X4 4 179 # define AFMT_AVI_INFO_Y_RGB 0 180 # define AFMT_AVI_INFO_Y_YCBCR422 1 181 # define AFMT_AVI_INFO_Y_YCBCR444 2 182 183 #define NO_AUTO 0 184 #define ES_AUTO 1 185 #define GS_AUTO 2 186 #define ES_AND_GS_AUTO 3 187 188 # define ARRAY_MODE(x) ((x) << 2) 189 # define PIPE_CONFIG(x) ((x) << 6) 190 # define TILE_SPLIT(x) ((x) << 11) 191 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 192 # define SAMPLE_SPLIT(x) ((x) << 25) 193 # define BANK_WIDTH(x) ((x) << 0) 194 # define BANK_HEIGHT(x) ((x) << 2) 195 # define MACRO_TILE_ASPECT(x) ((x) << 4) 196 # define NUM_BANKS(x) ((x) << 6) 197 198 #define MSG_ENTER_RLC_SAFE_MODE 1 199 #define MSG_EXIT_RLC_SAFE_MODE 0 200 201 /* 202 * PM4 203 */ 204 #define PACKET_TYPE0 0 205 #define PACKET_TYPE1 1 206 #define PACKET_TYPE2 2 207 #define PACKET_TYPE3 3 208 209 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 210 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 211 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 212 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 213 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 214 ((reg) & 0xFFFF) | \ 215 ((n) & 0x3FFF) << 16) 216 #define CP_PACKET2 0x80000000 217 #define PACKET2_PAD_SHIFT 0 218 #define PACKET2_PAD_MASK (0x3fffffff << 0) 219 220 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 221 222 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 223 (((op) & 0xFF) << 8) | \ 224 ((n) & 0x3FFF) << 16) 225 226 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 227 228 /* Packet 3 types */ 229 #define PACKET3_NOP 0x10 230 #define PACKET3_SET_BASE 0x11 231 #define PACKET3_BASE_INDEX(x) ((x) << 0) 232 #define CE_PARTITION_BASE 3 233 #define PACKET3_CLEAR_STATE 0x12 234 #define PACKET3_INDEX_BUFFER_SIZE 0x13 235 #define PACKET3_DISPATCH_DIRECT 0x15 236 #define PACKET3_DISPATCH_INDIRECT 0x16 237 #define PACKET3_ATOMIC_GDS 0x1D 238 #define PACKET3_ATOMIC_MEM 0x1E 239 #define PACKET3_OCCLUSION_QUERY 0x1F 240 #define PACKET3_SET_PREDICATION 0x20 241 #define PACKET3_REG_RMW 0x21 242 #define PACKET3_COND_EXEC 0x22 243 #define PACKET3_PRED_EXEC 0x23 244 #define PACKET3_DRAW_INDIRECT 0x24 245 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 246 #define PACKET3_INDEX_BASE 0x26 247 #define PACKET3_DRAW_INDEX_2 0x27 248 #define PACKET3_CONTEXT_CONTROL 0x28 249 #define PACKET3_INDEX_TYPE 0x2A 250 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 251 #define PACKET3_DRAW_INDEX_AUTO 0x2D 252 #define PACKET3_NUM_INSTANCES 0x2F 253 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 254 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 255 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 256 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 257 #define PACKET3_DRAW_PREAMBLE 0x36 258 #define PACKET3_WRITE_DATA 0x37 259 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 260 /* 0 - register 261 * 1 - memory (sync - via GRBM) 262 * 2 - gl2 263 * 3 - gds 264 * 4 - reserved 265 * 5 - memory (async - direct) 266 */ 267 #define WR_ONE_ADDR (1 << 16) 268 #define WR_CONFIRM (1 << 20) 269 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 270 /* 0 - LRU 271 * 1 - Stream 272 */ 273 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 274 /* 0 - me 275 * 1 - pfp 276 * 2 - ce 277 */ 278 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 279 #define PACKET3_MEM_SEMAPHORE 0x39 280 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 281 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 282 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 283 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 284 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 285 #define PACKET3_COPY_DW 0x3B 286 #define PACKET3_WAIT_REG_MEM 0x3C 287 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 288 /* 0 - always 289 * 1 - < 290 * 2 - <= 291 * 3 - == 292 * 4 - != 293 * 5 - >= 294 * 6 - > 295 */ 296 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 297 /* 0 - reg 298 * 1 - mem 299 */ 300 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 301 /* 0 - wait_reg_mem 302 * 1 - wr_wait_wr_reg 303 */ 304 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 305 /* 0 - me 306 * 1 - pfp 307 */ 308 #define PACKET3_INDIRECT_BUFFER 0x3F 309 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 310 #define INDIRECT_BUFFER_VALID (1 << 23) 311 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 312 /* 0 - LRU 313 * 1 - Stream 314 * 2 - Bypass 315 */ 316 #define PACKET3_COPY_DATA 0x40 317 #define PACKET3_PFP_SYNC_ME 0x42 318 #define PACKET3_SURFACE_SYNC 0x43 319 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 320 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 321 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 322 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 323 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 324 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 325 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 326 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 327 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 328 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 329 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 330 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 331 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 332 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 333 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 334 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 335 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 336 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 337 # define PACKET3_CB_ACTION_ENA (1 << 25) 338 # define PACKET3_DB_ACTION_ENA (1 << 26) 339 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 340 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 341 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 342 #define PACKET3_COND_WRITE 0x45 343 #define PACKET3_EVENT_WRITE 0x46 344 #define EVENT_TYPE(x) ((x) << 0) 345 #define EVENT_INDEX(x) ((x) << 8) 346 /* 0 - any non-TS event 347 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 348 * 2 - SAMPLE_PIPELINESTAT 349 * 3 - SAMPLE_STREAMOUTSTAT* 350 * 4 - *S_PARTIAL_FLUSH 351 * 5 - EOP events 352 * 6 - EOS events 353 */ 354 #define PACKET3_EVENT_WRITE_EOP 0x47 355 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 356 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 357 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 358 #define EOP_TCL1_ACTION_EN (1 << 16) 359 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 360 #define EOP_TCL2_VOLATILE (1 << 24) 361 #define EOP_CACHE_POLICY(x) ((x) << 25) 362 /* 0 - LRU 363 * 1 - Stream 364 * 2 - Bypass 365 */ 366 #define DATA_SEL(x) ((x) << 29) 367 /* 0 - discard 368 * 1 - send low 32bit data 369 * 2 - send 64bit data 370 * 3 - send 64bit GPU counter value 371 * 4 - send 64bit sys counter value 372 */ 373 #define INT_SEL(x) ((x) << 24) 374 /* 0 - none 375 * 1 - interrupt only (DATA_SEL = 0) 376 * 2 - interrupt when data write is confirmed 377 */ 378 #define DST_SEL(x) ((x) << 16) 379 /* 0 - MC 380 * 1 - TC/L2 381 */ 382 #define PACKET3_EVENT_WRITE_EOS 0x48 383 #define PACKET3_RELEASE_MEM 0x49 384 #define PACKET3_PREAMBLE_CNTL 0x4A 385 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 386 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 387 #define PACKET3_DMA_DATA 0x50 388 /* 1. header 389 * 2. CONTROL 390 * 3. SRC_ADDR_LO or DATA [31:0] 391 * 4. SRC_ADDR_HI [31:0] 392 * 5. DST_ADDR_LO [31:0] 393 * 6. DST_ADDR_HI [7:0] 394 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 395 */ 396 /* CONTROL */ 397 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 398 /* 0 - ME 399 * 1 - PFP 400 */ 401 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 402 /* 0 - LRU 403 * 1 - Stream 404 * 2 - Bypass 405 */ 406 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 407 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 408 /* 0 - DST_ADDR using DAS 409 * 1 - GDS 410 * 3 - DST_ADDR using L2 411 */ 412 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 413 /* 0 - LRU 414 * 1 - Stream 415 * 2 - Bypass 416 */ 417 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 418 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 419 /* 0 - SRC_ADDR using SAS 420 * 1 - GDS 421 * 2 - DATA 422 * 3 - SRC_ADDR using L2 423 */ 424 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 425 /* COMMAND */ 426 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 427 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 428 /* 0 - none 429 * 1 - 8 in 16 430 * 2 - 8 in 32 431 * 3 - 8 in 64 432 */ 433 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 434 /* 0 - none 435 * 1 - 8 in 16 436 * 2 - 8 in 32 437 * 3 - 8 in 64 438 */ 439 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 440 /* 0 - memory 441 * 1 - register 442 */ 443 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 444 /* 0 - memory 445 * 1 - register 446 */ 447 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 448 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 449 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 450 #define PACKET3_AQUIRE_MEM 0x58 451 #define PACKET3_REWIND 0x59 452 #define PACKET3_LOAD_UCONFIG_REG 0x5E 453 #define PACKET3_LOAD_SH_REG 0x5F 454 #define PACKET3_LOAD_CONFIG_REG 0x60 455 #define PACKET3_LOAD_CONTEXT_REG 0x61 456 #define PACKET3_SET_CONFIG_REG 0x68 457 #define PACKET3_SET_CONFIG_REG_START 0x00002000 458 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 459 #define PACKET3_SET_CONTEXT_REG 0x69 460 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 461 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 462 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 463 #define PACKET3_SET_SH_REG 0x76 464 #define PACKET3_SET_SH_REG_START 0x00002c00 465 #define PACKET3_SET_SH_REG_END 0x00003000 466 #define PACKET3_SET_SH_REG_OFFSET 0x77 467 #define PACKET3_SET_QUEUE_REG 0x78 468 #define PACKET3_SET_UCONFIG_REG 0x79 469 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 470 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 471 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 472 #define PACKET3_SCRATCH_RAM_READ 0x7E 473 #define PACKET3_LOAD_CONST_RAM 0x80 474 #define PACKET3_WRITE_CONST_RAM 0x81 475 #define PACKET3_DUMP_CONST_RAM 0x83 476 #define PACKET3_INCREMENT_CE_COUNTER 0x84 477 #define PACKET3_INCREMENT_DE_COUNTER 0x85 478 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 479 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 480 #define PACKET3_SWITCH_BUFFER 0x8B 481 482 /* SDMA - first instance at 0xd000, second at 0xd800 */ 483 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 484 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 485 #define SDMA_MAX_INSTANCE 2 486 487 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 488 (((sub_op) & 0xFF) << 8) | \ 489 (((op) & 0xFF) << 0)) 490 /* sDMA opcodes */ 491 #define SDMA_OPCODE_NOP 0 492 # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 493 #define SDMA_OPCODE_COPY 1 494 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 495 # define SDMA_COPY_SUB_OPCODE_TILED 1 496 # define SDMA_COPY_SUB_OPCODE_SOA 3 497 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 498 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 499 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 500 #define SDMA_OPCODE_WRITE 2 501 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 502 # define SDMA_WRTIE_SUB_OPCODE_TILED 1 503 #define SDMA_OPCODE_INDIRECT_BUFFER 4 504 #define SDMA_OPCODE_FENCE 5 505 #define SDMA_OPCODE_TRAP 6 506 #define SDMA_OPCODE_SEMAPHORE 7 507 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 508 /* 0 - increment 509 * 1 - write 1 510 */ 511 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 512 /* 0 - wait 513 * 1 - signal 514 */ 515 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 516 /* mailbox */ 517 #define SDMA_OPCODE_POLL_REG_MEM 8 518 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 519 /* 0 - wait_reg_mem 520 * 1 - wr_wait_wr_reg 521 */ 522 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 523 /* 0 - always 524 * 1 - < 525 * 2 - <= 526 * 3 - == 527 * 4 - != 528 * 5 - >= 529 * 6 - > 530 */ 531 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 532 /* 0 = register 533 * 1 = memory 534 */ 535 #define SDMA_OPCODE_COND_EXEC 9 536 #define SDMA_OPCODE_CONSTANT_FILL 11 537 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 538 /* 0 = byte fill 539 * 2 = DW fill 540 */ 541 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 542 #define SDMA_OPCODE_TIMESTAMP 13 543 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 544 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 545 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 546 #define SDMA_OPCODE_SRBM_WRITE 14 547 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 548 /* byte mask */ 549 550 #define VCE_CMD_NO_OP 0x00000000 551 #define VCE_CMD_END 0x00000001 552 #define VCE_CMD_IB 0x00000002 553 #define VCE_CMD_FENCE 0x00000003 554 #define VCE_CMD_TRAP 0x00000004 555 #define VCE_CMD_IB_AUTO 0x00000005 556 #define VCE_CMD_SEMAPHORE 0x00000006 557 558 /* if PTR32, these are the bases for scratch and lds */ 559 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 560 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 561 562 #define KFD_CIK_SDMA_QUEUE_OFFSET 0x200 563 564 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 565 enum { 566 MTYPE_CACHED = 0, 567 MTYPE_NONCACHED = 3 568 }; 569 570 #endif 571
Indexes created Wed Oct 01 15:09:59 GMT 2025