sislands_smc.h revision 1.1
1 /* $NetBSD: sislands_smc.h,v 1.1 2021/12/18 20:11:14 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #ifndef PP_SISLANDS_SMC_H 26 #define PP_SISLANDS_SMC_H 27 28 #include "ppsmc.h" 29 30 #pragma pack(push, 1) 31 32 #define SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 16 33 34 struct PP_SIslands_Dpm2PerfLevel 35 { 36 uint8_t MaxPS; 37 uint8_t TgtAct; 38 uint8_t MaxPS_StepInc; 39 uint8_t MaxPS_StepDec; 40 uint8_t PSSamplingTime; 41 uint8_t NearTDPDec; 42 uint8_t AboveSafeInc; 43 uint8_t BelowSafeInc; 44 uint8_t PSDeltaLimit; 45 uint8_t PSDeltaWin; 46 uint16_t PwrEfficiencyRatio; 47 uint8_t Reserved[4]; 48 }; 49 50 typedef struct PP_SIslands_Dpm2PerfLevel PP_SIslands_Dpm2PerfLevel; 51 52 struct PP_SIslands_DPM2Status 53 { 54 uint32_t dpm2Flags; 55 uint8_t CurrPSkip; 56 uint8_t CurrPSkipPowerShift; 57 uint8_t CurrPSkipTDP; 58 uint8_t CurrPSkipOCP; 59 uint8_t MaxSPLLIndex; 60 uint8_t MinSPLLIndex; 61 uint8_t CurrSPLLIndex; 62 uint8_t InfSweepMode; 63 uint8_t InfSweepDir; 64 uint8_t TDPexceeded; 65 uint8_t reserved; 66 uint8_t SwitchDownThreshold; 67 uint32_t SwitchDownCounter; 68 uint32_t SysScalingFactor; 69 }; 70 71 typedef struct PP_SIslands_DPM2Status PP_SIslands_DPM2Status; 72 73 struct PP_SIslands_DPM2Parameters 74 { 75 uint32_t TDPLimit; 76 uint32_t NearTDPLimit; 77 uint32_t SafePowerLimit; 78 uint32_t PowerBoostLimit; 79 uint32_t MinLimitDelta; 80 }; 81 typedef struct PP_SIslands_DPM2Parameters PP_SIslands_DPM2Parameters; 82 83 struct PP_SIslands_PAPMStatus 84 { 85 uint32_t EstimatedDGPU_T; 86 uint32_t EstimatedDGPU_P; 87 uint32_t EstimatedAPU_T; 88 uint32_t EstimatedAPU_P; 89 uint8_t dGPU_T_Limit_Exceeded; 90 uint8_t reserved[3]; 91 }; 92 typedef struct PP_SIslands_PAPMStatus PP_SIslands_PAPMStatus; 93 94 struct PP_SIslands_PAPMParameters 95 { 96 uint32_t NearTDPLimitTherm; 97 uint32_t NearTDPLimitPAPM; 98 uint32_t PlatformPowerLimit; 99 uint32_t dGPU_T_Limit; 100 uint32_t dGPU_T_Warning; 101 uint32_t dGPU_T_Hysteresis; 102 }; 103 typedef struct PP_SIslands_PAPMParameters PP_SIslands_PAPMParameters; 104 105 struct SISLANDS_SMC_SCLK_VALUE 106 { 107 uint32_t vCG_SPLL_FUNC_CNTL; 108 uint32_t vCG_SPLL_FUNC_CNTL_2; 109 uint32_t vCG_SPLL_FUNC_CNTL_3; 110 uint32_t vCG_SPLL_FUNC_CNTL_4; 111 uint32_t vCG_SPLL_SPREAD_SPECTRUM; 112 uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; 113 uint32_t sclk_value; 114 }; 115 116 typedef struct SISLANDS_SMC_SCLK_VALUE SISLANDS_SMC_SCLK_VALUE; 117 118 struct SISLANDS_SMC_MCLK_VALUE 119 { 120 uint32_t vMPLL_FUNC_CNTL; 121 uint32_t vMPLL_FUNC_CNTL_1; 122 uint32_t vMPLL_FUNC_CNTL_2; 123 uint32_t vMPLL_AD_FUNC_CNTL; 124 uint32_t vMPLL_DQ_FUNC_CNTL; 125 uint32_t vMCLK_PWRMGT_CNTL; 126 uint32_t vDLL_CNTL; 127 uint32_t vMPLL_SS; 128 uint32_t vMPLL_SS2; 129 uint32_t mclk_value; 130 }; 131 132 typedef struct SISLANDS_SMC_MCLK_VALUE SISLANDS_SMC_MCLK_VALUE; 133 134 struct SISLANDS_SMC_VOLTAGE_VALUE 135 { 136 uint16_t value; 137 uint8_t index; 138 uint8_t phase_settings; 139 }; 140 141 typedef struct SISLANDS_SMC_VOLTAGE_VALUE SISLANDS_SMC_VOLTAGE_VALUE; 142 143 struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL 144 { 145 uint8_t ACIndex; 146 uint8_t displayWatermark; 147 uint8_t gen2PCIE; 148 uint8_t UVDWatermark; 149 uint8_t VCEWatermark; 150 uint8_t strobeMode; 151 uint8_t mcFlags; 152 uint8_t padding; 153 uint32_t aT; 154 uint32_t bSP; 155 SISLANDS_SMC_SCLK_VALUE sclk; 156 SISLANDS_SMC_MCLK_VALUE mclk; 157 SISLANDS_SMC_VOLTAGE_VALUE vddc; 158 SISLANDS_SMC_VOLTAGE_VALUE mvdd; 159 SISLANDS_SMC_VOLTAGE_VALUE vddci; 160 SISLANDS_SMC_VOLTAGE_VALUE std_vddc; 161 uint8_t hysteresisUp; 162 uint8_t hysteresisDown; 163 uint8_t stateFlags; 164 uint8_t arbRefreshState; 165 uint32_t SQPowerThrottle; 166 uint32_t SQPowerThrottle_2; 167 uint32_t MaxPoweredUpCU; 168 SISLANDS_SMC_VOLTAGE_VALUE high_temp_vddc; 169 SISLANDS_SMC_VOLTAGE_VALUE low_temp_vddc; 170 uint32_t reserved[2]; 171 PP_SIslands_Dpm2PerfLevel dpm2; 172 }; 173 174 #define SISLANDS_SMC_STROBE_RATIO 0x0F 175 #define SISLANDS_SMC_STROBE_ENABLE 0x10 176 177 #define SISLANDS_SMC_MC_EDC_RD_FLAG 0x01 178 #define SISLANDS_SMC_MC_EDC_WR_FLAG 0x02 179 #define SISLANDS_SMC_MC_RTT_ENABLE 0x04 180 #define SISLANDS_SMC_MC_STUTTER_EN 0x08 181 #define SISLANDS_SMC_MC_PG_EN 0x10 182 183 typedef struct SISLANDS_SMC_HW_PERFORMANCE_LEVEL SISLANDS_SMC_HW_PERFORMANCE_LEVEL; 184 185 struct SISLANDS_SMC_SWSTATE 186 { 187 uint8_t flags; 188 uint8_t levelCount; 189 uint8_t padding2; 190 uint8_t padding3; 191 SISLANDS_SMC_HW_PERFORMANCE_LEVEL levels[1]; 192 }; 193 194 typedef struct SISLANDS_SMC_SWSTATE SISLANDS_SMC_SWSTATE; 195 196 #define SISLANDS_SMC_VOLTAGEMASK_VDDC 0 197 #define SISLANDS_SMC_VOLTAGEMASK_MVDD 1 198 #define SISLANDS_SMC_VOLTAGEMASK_VDDCI 2 199 #define SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING 3 200 #define SISLANDS_SMC_VOLTAGEMASK_MAX 4 201 202 struct SISLANDS_SMC_VOLTAGEMASKTABLE 203 { 204 uint32_t lowMask[SISLANDS_SMC_VOLTAGEMASK_MAX]; 205 }; 206 207 typedef struct SISLANDS_SMC_VOLTAGEMASKTABLE SISLANDS_SMC_VOLTAGEMASKTABLE; 208 209 #define SISLANDS_MAX_NO_VREG_STEPS 32 210 211 struct SISLANDS_SMC_STATETABLE 212 { 213 uint8_t thermalProtectType; 214 uint8_t systemFlags; 215 uint8_t maxVDDCIndexInPPTable; 216 uint8_t extraFlags; 217 uint32_t lowSMIO[SISLANDS_MAX_NO_VREG_STEPS]; 218 SISLANDS_SMC_VOLTAGEMASKTABLE voltageMaskTable; 219 SISLANDS_SMC_VOLTAGEMASKTABLE phaseMaskTable; 220 PP_SIslands_DPM2Parameters dpm2Params; 221 SISLANDS_SMC_SWSTATE initialState; 222 SISLANDS_SMC_SWSTATE ACPIState; 223 SISLANDS_SMC_SWSTATE ULVState; 224 SISLANDS_SMC_SWSTATE driverState; 225 SISLANDS_SMC_HW_PERFORMANCE_LEVEL dpmLevels[SISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1]; 226 }; 227 228 typedef struct SISLANDS_SMC_STATETABLE SISLANDS_SMC_STATETABLE; 229 230 #define SI_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 231 #define SI_SMC_SOFT_REGISTER_delay_vreg 0xC 232 #define SI_SMC_SOFT_REGISTER_delay_acpi 0x28 233 #define SI_SMC_SOFT_REGISTER_seq_index 0x5C 234 #define SI_SMC_SOFT_REGISTER_mvdd_chg_time 0x60 235 #define SI_SMC_SOFT_REGISTER_mclk_switch_lim 0x70 236 #define SI_SMC_SOFT_REGISTER_watermark_threshold 0x78 237 #define SI_SMC_SOFT_REGISTER_phase_shedding_delay 0x88 238 #define SI_SMC_SOFT_REGISTER_ulv_volt_change_delay 0x8C 239 #define SI_SMC_SOFT_REGISTER_mc_block_delay 0x98 240 #define SI_SMC_SOFT_REGISTER_ticks_per_us 0xA8 241 #define SI_SMC_SOFT_REGISTER_crtc_index 0xC4 242 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min 0xC8 243 #define SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max 0xCC 244 #define SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width 0xF4 245 #define SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen 0xFC 246 #define SI_SMC_SOFT_REGISTER_vr_hot_gpio 0x100 247 #define SI_SMC_SOFT_REGISTER_svi_rework_plat_type 0x118 248 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd 0x11c 249 #define SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc 0x120 250 251 struct PP_SIslands_FanTable 252 { 253 uint8_t fdo_mode; 254 uint8_t padding; 255 int16_t temp_min; 256 int16_t temp_med; 257 int16_t temp_max; 258 int16_t slope1; 259 int16_t slope2; 260 int16_t fdo_min; 261 int16_t hys_up; 262 int16_t hys_down; 263 int16_t hys_slope; 264 int16_t temp_resp_lim; 265 int16_t temp_curr; 266 int16_t slope_curr; 267 int16_t pwm_curr; 268 uint32_t refresh_period; 269 int16_t fdo_max; 270 uint8_t temp_src; 271 int8_t padding2; 272 }; 273 274 typedef struct PP_SIslands_FanTable PP_SIslands_FanTable; 275 276 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16 277 #define SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES 32 278 279 #define SMC_SISLANDS_SCALE_I 7 280 #define SMC_SISLANDS_SCALE_R 12 281 282 struct PP_SIslands_CacConfig 283 { 284 uint16_t cac_lkge_lut[SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES]; 285 uint32_t lkge_lut_V0; 286 uint32_t lkge_lut_Vstep; 287 uint32_t WinTime; 288 uint32_t R_LL; 289 uint32_t calculation_repeats; 290 uint32_t l2numWin_TDP; 291 uint32_t dc_cac; 292 uint8_t lts_truncate_n; 293 uint8_t SHIFT_N; 294 uint8_t log2_PG_LKG_SCALE; 295 uint8_t cac_temp; 296 uint32_t lkge_lut_T0; 297 uint32_t lkge_lut_Tstep; 298 }; 299 300 typedef struct PP_SIslands_CacConfig PP_SIslands_CacConfig; 301 302 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE 16 303 #define SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT 20 304 305 struct SMC_SIslands_MCRegisterAddress 306 { 307 uint16_t s0; 308 uint16_t s1; 309 }; 310 311 typedef struct SMC_SIslands_MCRegisterAddress SMC_SIslands_MCRegisterAddress; 312 313 struct SMC_SIslands_MCRegisterSet 314 { 315 uint32_t value[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 316 }; 317 318 typedef struct SMC_SIslands_MCRegisterSet SMC_SIslands_MCRegisterSet; 319 320 struct SMC_SIslands_MCRegisters 321 { 322 uint8_t last; 323 uint8_t reserved[3]; 324 SMC_SIslands_MCRegisterAddress address[SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE]; 325 SMC_SIslands_MCRegisterSet data[SMC_SISLANDS_MC_REGISTER_ARRAY_SET_COUNT]; 326 }; 327 328 typedef struct SMC_SIslands_MCRegisters SMC_SIslands_MCRegisters; 329 330 struct SMC_SIslands_MCArbDramTimingRegisterSet 331 { 332 uint32_t mc_arb_dram_timing; 333 uint32_t mc_arb_dram_timing2; 334 uint8_t mc_arb_rfsh_rate; 335 uint8_t mc_arb_burst_time; 336 uint8_t padding[2]; 337 }; 338 339 typedef struct SMC_SIslands_MCArbDramTimingRegisterSet SMC_SIslands_MCArbDramTimingRegisterSet; 340 341 struct SMC_SIslands_MCArbDramTimingRegisters 342 { 343 uint8_t arb_current; 344 uint8_t reserved[3]; 345 SMC_SIslands_MCArbDramTimingRegisterSet data[16]; 346 }; 347 348 typedef struct SMC_SIslands_MCArbDramTimingRegisters SMC_SIslands_MCArbDramTimingRegisters; 349 350 struct SMC_SISLANDS_SPLL_DIV_TABLE 351 { 352 uint32_t freq[256]; 353 uint32_t ss[256]; 354 }; 355 356 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK 0x01ffffff 357 #define SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT 0 358 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK 0xfe000000 359 #define SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT 25 360 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK 0x000fffff 361 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT 0 362 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK 0xfff00000 363 #define SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT 20 364 365 typedef struct SMC_SISLANDS_SPLL_DIV_TABLE SMC_SISLANDS_SPLL_DIV_TABLE; 366 367 #define SMC_SISLANDS_DTE_MAX_FILTER_STAGES 5 368 369 #define SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE 16 370 371 struct Smc_SIslands_DTE_Configuration 372 { 373 uint32_t tau[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 374 uint32_t R[SMC_SISLANDS_DTE_MAX_FILTER_STAGES]; 375 uint32_t K; 376 uint32_t T0; 377 uint32_t MaxT; 378 uint8_t WindowSize; 379 uint8_t Tdep_count; 380 uint8_t temp_select; 381 uint8_t DTE_mode; 382 uint8_t T_limits[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 383 uint32_t Tdep_tau[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 384 uint32_t Tdep_R[SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE]; 385 uint32_t Tthreshold; 386 }; 387 388 typedef struct Smc_SIslands_DTE_Configuration Smc_SIslands_DTE_Configuration; 389 390 #define SMC_SISLANDS_DTE_STATUS_FLAG_DTE_ON 1 391 392 #define SISLANDS_SMC_FIRMWARE_HEADER_LOCATION 0x10000 393 394 #define SISLANDS_SMC_FIRMWARE_HEADER_version 0x0 395 #define SISLANDS_SMC_FIRMWARE_HEADER_flags 0x4 396 #define SISLANDS_SMC_FIRMWARE_HEADER_softRegisters 0xC 397 #define SISLANDS_SMC_FIRMWARE_HEADER_stateTable 0x10 398 #define SISLANDS_SMC_FIRMWARE_HEADER_fanTable 0x14 399 #define SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable 0x18 400 #define SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable 0x24 401 #define SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable 0x30 402 #define SISLANDS_SMC_FIRMWARE_HEADER_spllTable 0x38 403 #define SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration 0x40 404 #define SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters 0x48 405 406 #pragma pack(pop) 407 408 int amdgpu_si_copy_bytes_to_smc(struct amdgpu_device *adev, 409 u32 smc_start_address, 410 const u8 *src, u32 byte_count, u32 limit); 411 void amdgpu_si_start_smc(struct amdgpu_device *adev); 412 void amdgpu_si_reset_smc(struct amdgpu_device *adev); 413 int amdgpu_si_program_jump_on_start(struct amdgpu_device *adev); 414 void amdgpu_si_smc_clock(struct amdgpu_device *adev, bool enable); 415 bool amdgpu_si_is_smc_running(struct amdgpu_device *adev); 416 PPSMC_Result amdgpu_si_send_msg_to_smc(struct amdgpu_device *adev, PPSMC_Msg msg); 417 PPSMC_Result amdgpu_si_wait_for_smc_inactive(struct amdgpu_device *adev); 418 int amdgpu_si_load_smc_ucode(struct amdgpu_device *adev, u32 limit); 419 int amdgpu_si_read_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 420 u32 *value, u32 limit); 421 int amdgpu_si_write_smc_sram_dword(struct amdgpu_device *adev, u32 smc_address, 422 u32 value, u32 limit); 423 424 #endif 425 426
Indexes created Sun Oct 19 02:09:48 GMT 2025