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kfd_dbgdev.h revision 1.1.1.1 
      1 /*	$NetBSD: kfd_dbgdev.h,v 1.1.1.1 2018/08/27 01:34:46 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2014 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  */
     24 
     25 #ifndef KFD_DBGDEV_H_
     26 #define KFD_DBGDEV_H_
     27 
     28 enum {
     29 	SQ_CMD_VMID_OFFSET = 28,
     30 	ADDRESS_WATCH_CNTL_OFFSET = 24
     31 };
     32 
     33 enum {
     34 	PRIV_QUEUE_SYNC_TIME_MS = 200
     35 };
     36 
     37 /* CONTEXT reg space definition */
     38 enum {
     39 	CONTEXT_REG_BASE = 0xA000,
     40 	CONTEXT_REG_END = 0xA400,
     41 	CONTEXT_REG_SIZE = CONTEXT_REG_END - CONTEXT_REG_BASE
     42 };
     43 
     44 /* USER CONFIG reg space definition */
     45 enum {
     46 	USERCONFIG_REG_BASE = 0xC000,
     47 	USERCONFIG_REG_END = 0x10000,
     48 	USERCONFIG_REG_SIZE = USERCONFIG_REG_END - USERCONFIG_REG_BASE
     49 };
     50 
     51 /* CONFIG reg space definition */
     52 enum {
     53 	AMD_CONFIG_REG_BASE = 0x2000,	/* in dwords */
     54 	AMD_CONFIG_REG_END = 0x2B00,
     55 	AMD_CONFIG_REG_SIZE = AMD_CONFIG_REG_END - AMD_CONFIG_REG_BASE
     56 };
     57 
     58 /* SH reg space definition */
     59 enum {
     60 	SH_REG_BASE = 0x2C00,
     61 	SH_REG_END = 0x3000,
     62 	SH_REG_SIZE = SH_REG_END - SH_REG_BASE
     63 };
     64 
     65 enum SQ_IND_CMD_CMD {
     66 	SQ_IND_CMD_CMD_NULL = 0x00000000,
     67 	SQ_IND_CMD_CMD_HALT = 0x00000001,
     68 	SQ_IND_CMD_CMD_RESUME = 0x00000002,
     69 	SQ_IND_CMD_CMD_KILL = 0x00000003,
     70 	SQ_IND_CMD_CMD_DEBUG = 0x00000004,
     71 	SQ_IND_CMD_CMD_TRAP = 0x00000005,
     72 };
     73 
     74 enum SQ_IND_CMD_MODE {
     75 	SQ_IND_CMD_MODE_SINGLE = 0x00000000,
     76 	SQ_IND_CMD_MODE_BROADCAST = 0x00000001,
     77 	SQ_IND_CMD_MODE_BROADCAST_QUEUE = 0x00000002,
     78 	SQ_IND_CMD_MODE_BROADCAST_PIPE = 0x00000003,
     79 	SQ_IND_CMD_MODE_BROADCAST_ME = 0x00000004,
     80 };
     81 
     82 union SQ_IND_INDEX_BITS {
     83 	struct {
     84 		uint32_t wave_id:4;
     85 		uint32_t simd_id:2;
     86 		uint32_t thread_id:6;
     87 		 uint32_t:1;
     88 		uint32_t force_read:1;
     89 		uint32_t read_timeout:1;
     90 		uint32_t unindexed:1;
     91 		uint32_t index:16;
     92 
     93 	} bitfields, bits;
     94 	uint32_t u32All;
     95 	signed int i32All;
     96 	float f32All;
     97 };
     98 
     99 union SQ_IND_CMD_BITS {
    100 	struct {
    101 		uint32_t data:32;
    102 	} bitfields, bits;
    103 	uint32_t u32All;
    104 	signed int i32All;
    105 	float f32All;
    106 };
    107 
    108 union SQ_CMD_BITS {
    109 	struct {
    110 		uint32_t cmd:3;
    111 		 uint32_t:1;
    112 		uint32_t mode:3;
    113 		uint32_t check_vmid:1;
    114 		uint32_t trap_id:3;
    115 		 uint32_t:5;
    116 		uint32_t wave_id:4;
    117 		uint32_t simd_id:2;
    118 		 uint32_t:2;
    119 		uint32_t queue_id:3;
    120 		 uint32_t:1;
    121 		uint32_t vm_id:4;
    122 	} bitfields, bits;
    123 	uint32_t u32All;
    124 	signed int i32All;
    125 	float f32All;
    126 };
    127 
    128 union SQ_IND_DATA_BITS {
    129 	struct {
    130 		uint32_t data:32;
    131 	} bitfields, bits;
    132 	uint32_t u32All;
    133 	signed int i32All;
    134 	float f32All;
    135 };
    136 
    137 union GRBM_GFX_INDEX_BITS {
    138 	struct {
    139 		uint32_t instance_index:8;
    140 		uint32_t sh_index:8;
    141 		uint32_t se_index:8;
    142 		 uint32_t:5;
    143 		uint32_t sh_broadcast_writes:1;
    144 		uint32_t instance_broadcast_writes:1;
    145 		uint32_t se_broadcast_writes:1;
    146 	} bitfields, bits;
    147 	uint32_t u32All;
    148 	signed int i32All;
    149 	float f32All;
    150 };
    151 
    152 union TCP_WATCH_ADDR_H_BITS {
    153 	struct {
    154 		uint32_t addr:16;
    155 		 uint32_t:16;
    156 
    157 	} bitfields, bits;
    158 	uint32_t u32All;
    159 	signed int i32All;
    160 	float f32All;
    161 };
    162 
    163 union TCP_WATCH_ADDR_L_BITS {
    164 	struct {
    165 		uint32_t:6;
    166 		uint32_t addr:26;
    167 	} bitfields, bits;
    168 	uint32_t u32All;
    169 	signed int i32All;
    170 	float f32All;
    171 };
    172 
    173 enum {
    174 	QUEUESTATE__INVALID = 0, /* so by default we'll get invalid state */
    175 	QUEUESTATE__ACTIVE_COMPLETION_PENDING,
    176 	QUEUESTATE__ACTIVE
    177 };
    178 
    179 union ULARGE_INTEGER {
    180 	struct {
    181 		uint32_t low_part;
    182 		uint32_t high_part;
    183 	} u;
    184 	unsigned long long quad_part;
    185 };
    186 
    187 
    188 #define KFD_CIK_VMID_START_OFFSET (8)
    189 #define KFD_CIK_VMID_END_OFFSET (KFD_CIK_VMID_START_OFFSET + (8))
    190 
    191 
    192 void kfd_dbgdev_init(struct kfd_dbgdev *pdbgdev, struct kfd_dev *pdev,
    193 			enum DBGDEV_TYPE type);
    194 
    195 #endif	/* KFD_DBGDEV_H_ */
    196