kfd_dbgmgr.h revision 1.1
1 /* $NetBSD: kfd_dbgmgr.h,v 1.1 2018/08/27 01:34:46 riastradh Exp $ */ 2 3 /* 4 * Copyright 2014 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef KFD_DBGMGR_H_ 27 #define KFD_DBGMGR_H_ 28 29 #include "kfd_priv.h" 30 31 /* must align with hsakmttypes definition */ 32 #pragma pack(push, 4) 33 34 enum HSA_DBG_WAVEOP { 35 HSA_DBG_WAVEOP_HALT = 1, /* Halts a wavefront */ 36 HSA_DBG_WAVEOP_RESUME = 2, /* Resumes a wavefront */ 37 HSA_DBG_WAVEOP_KILL = 3, /* Kills a wavefront */ 38 HSA_DBG_WAVEOP_DEBUG = 4, /* Causes wavefront to enter 39 debug mode */ 40 HSA_DBG_WAVEOP_TRAP = 5, /* Causes wavefront to take 41 a trap */ 42 HSA_DBG_NUM_WAVEOP = 5, 43 HSA_DBG_MAX_WAVEOP = 0xFFFFFFFF 44 }; 45 46 enum HSA_DBG_WAVEMODE { 47 /* send command to a single wave */ 48 HSA_DBG_WAVEMODE_SINGLE = 0, 49 /* 50 * Broadcast to all wavefronts of all processes is not 51 * supported for HSA user mode 52 */ 53 54 /* send to waves within current process */ 55 HSA_DBG_WAVEMODE_BROADCAST_PROCESS = 2, 56 /* send to waves within current process on CU */ 57 HSA_DBG_WAVEMODE_BROADCAST_PROCESS_CU = 3, 58 HSA_DBG_NUM_WAVEMODE = 3, 59 HSA_DBG_MAX_WAVEMODE = 0xFFFFFFFF 60 }; 61 62 enum HSA_DBG_WAVEMSG_TYPE { 63 HSA_DBG_WAVEMSG_AUTO = 0, 64 HSA_DBG_WAVEMSG_USER = 1, 65 HSA_DBG_WAVEMSG_ERROR = 2, 66 HSA_DBG_NUM_WAVEMSG, 67 HSA_DBG_MAX_WAVEMSG = 0xFFFFFFFF 68 }; 69 70 enum HSA_DBG_WATCH_MODE { 71 HSA_DBG_WATCH_READ = 0, /* Read operations only */ 72 HSA_DBG_WATCH_NONREAD = 1, /* Write or Atomic operations only */ 73 HSA_DBG_WATCH_ATOMIC = 2, /* Atomic Operations only */ 74 HSA_DBG_WATCH_ALL = 3, /* Read, Write or Atomic operations */ 75 HSA_DBG_WATCH_NUM, 76 HSA_DBG_WATCH_SIZE = 0xFFFFFFFF 77 }; 78 79 /* This structure is hardware specific and may change in the future */ 80 struct HsaDbgWaveMsgAMDGen2 { 81 union { 82 struct ui32 { 83 uint32_t UserData:8; /* user data */ 84 uint32_t ShaderArray:1; /* Shader array */ 85 uint32_t Priv:1; /* Privileged */ 86 uint32_t Reserved0:4; /* This field is reserved, 87 should be 0 */ 88 uint32_t WaveId:4; /* wave id */ 89 uint32_t SIMD:2; /* SIMD id */ 90 uint32_t HSACU:4; /* Compute unit */ 91 uint32_t ShaderEngine:2;/* Shader engine */ 92 uint32_t MessageType:2; /* see HSA_DBG_WAVEMSG_TYPE */ 93 uint32_t Reserved1:4; /* This field is reserved, 94 should be 0 */ 95 } ui32; 96 uint32_t Value; 97 }; 98 uint32_t Reserved2; 99 }; 100 101 union HsaDbgWaveMessageAMD { 102 struct HsaDbgWaveMsgAMDGen2 WaveMsgInfoGen2; 103 /* for future HsaDbgWaveMsgAMDGen3; */ 104 }; 105 106 struct HsaDbgWaveMessage { 107 void *MemoryVA; /* ptr to associated host-accessible data */ 108 union HsaDbgWaveMessageAMD DbgWaveMsg; 109 }; 110 111 /* 112 * TODO: This definitions to be MOVED to kfd_event, once it is implemented. 113 * 114 * HSA sync primitive, Event and HW Exception notification API definitions. 115 * The API functions allow the runtime to define a so-called sync-primitive, 116 * a SW object combining a user-mode provided "syncvar" and a scheduler event 117 * that can be signaled through a defined GPU interrupt. A syncvar is 118 * a process virtual memory location of a certain size that can be accessed 119 * by CPU and GPU shader code within the process to set and query the content 120 * within that memory. The definition of the content is determined by the HSA 121 * runtime and potentially GPU shader code interfacing with the HSA runtime. 122 * The syncvar values may be commonly written through an PM4 WRITE_DATA packet 123 * in the user mode instruction stream. The OS scheduler event is typically 124 * associated and signaled by an interrupt issued by the GPU, but other HSA 125 * system interrupt conditions from other HW (e.g. IOMMUv2) may be surfaced 126 * by the KFD by this mechanism, too. */ 127 128 /* these are the new definitions for events */ 129 enum HSA_EVENTTYPE { 130 HSA_EVENTTYPE_SIGNAL = 0, /* user-mode generated GPU signal */ 131 HSA_EVENTTYPE_NODECHANGE = 1, /* HSA node change (attach/detach) */ 132 HSA_EVENTTYPE_DEVICESTATECHANGE = 2, /* HSA device state change 133 (start/stop) */ 134 HSA_EVENTTYPE_HW_EXCEPTION = 3, /* GPU shader exception event */ 135 HSA_EVENTTYPE_SYSTEM_EVENT = 4, /* GPU SYSCALL with parameter info */ 136 HSA_EVENTTYPE_DEBUG_EVENT = 5, /* GPU signal for debugging */ 137 HSA_EVENTTYPE_PROFILE_EVENT = 6,/* GPU signal for profiling */ 138 HSA_EVENTTYPE_QUEUE_EVENT = 7, /* GPU signal queue idle state 139 (EOP pm4) */ 140 /* ... */ 141 HSA_EVENTTYPE_MAXID, 142 HSA_EVENTTYPE_TYPE_SIZE = 0xFFFFFFFF 143 }; 144 145 /* Sub-definitions for various event types: Syncvar */ 146 struct HsaSyncVar { 147 union SyncVar { 148 void *UserData; /* pointer to user mode data */ 149 uint64_t UserDataPtrValue; /* 64bit compatibility of value */ 150 } SyncVar; 151 uint64_t SyncVarSize; 152 }; 153 154 /* Sub-definitions for various event types: NodeChange */ 155 156 enum HSA_EVENTTYPE_NODECHANGE_FLAGS { 157 HSA_EVENTTYPE_NODECHANGE_ADD = 0, 158 HSA_EVENTTYPE_NODECHANGE_REMOVE = 1, 159 HSA_EVENTTYPE_NODECHANGE_SIZE = 0xFFFFFFFF 160 }; 161 162 struct HsaNodeChange { 163 /* HSA node added/removed on the platform */ 164 enum HSA_EVENTTYPE_NODECHANGE_FLAGS Flags; 165 }; 166 167 /* Sub-definitions for various event types: DeviceStateChange */ 168 enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS { 169 /* device started (and available) */ 170 HSA_EVENTTYPE_DEVICESTATUSCHANGE_START = 0, 171 /* device stopped (i.e. unavailable) */ 172 HSA_EVENTTYPE_DEVICESTATUSCHANGE_STOP = 1, 173 HSA_EVENTTYPE_DEVICESTATUSCHANGE_SIZE = 0xFFFFFFFF 174 }; 175 176 enum HSA_DEVICE { 177 HSA_DEVICE_CPU = 0, 178 HSA_DEVICE_GPU = 1, 179 MAX_HSA_DEVICE = 2 180 }; 181 182 struct HsaDeviceStateChange { 183 uint32_t NodeId; /* F-NUMA node that contains the device */ 184 enum HSA_DEVICE Device; /* device type: GPU or CPU */ 185 enum HSA_EVENTTYPE_DEVICESTATECHANGE_FLAGS Flags; /* event flags */ 186 }; 187 188 struct HsaEventData { 189 enum HSA_EVENTTYPE EventType; /* event type */ 190 union EventData { 191 /* 192 * return data associated with HSA_EVENTTYPE_SIGNAL 193 * and other events 194 */ 195 struct HsaSyncVar SyncVar; 196 197 /* data associated with HSA_EVENTTYPE_NODE_CHANGE */ 198 struct HsaNodeChange NodeChangeState; 199 200 /* data associated with HSA_EVENTTYPE_DEVICE_STATE_CHANGE */ 201 struct HsaDeviceStateChange DeviceState; 202 } EventData; 203 204 /* the following data entries are internal to the KFD & thunk itself */ 205 206 /* internal thunk store for Event data (OsEventHandle) */ 207 uint64_t HWData1; 208 /* internal thunk store for Event data (HWAddress) */ 209 uint64_t HWData2; 210 /* internal thunk store for Event data (HWData) */ 211 uint32_t HWData3; 212 }; 213 214 struct HsaEventDescriptor { 215 /* event type to allocate */ 216 enum HSA_EVENTTYPE EventType; 217 /* H-NUMA node containing GPU device that is event source */ 218 uint32_t NodeId; 219 /* pointer to user mode syncvar data, syncvar->UserDataPtrValue 220 * may be NULL 221 */ 222 struct HsaSyncVar SyncVar; 223 }; 224 225 struct HsaEvent { 226 uint32_t EventId; 227 struct HsaEventData EventData; 228 }; 229 230 #pragma pack(pop) 231 232 enum DBGDEV_TYPE { 233 DBGDEV_TYPE_ILLEGAL = 0, 234 DBGDEV_TYPE_NODIQ = 1, 235 DBGDEV_TYPE_DIQ = 2, 236 DBGDEV_TYPE_TEST = 3 237 }; 238 239 struct dbg_address_watch_info { 240 struct kfd_process *process; 241 enum HSA_DBG_WATCH_MODE *watch_mode; 242 uint64_t *watch_address; 243 uint64_t *watch_mask; 244 struct HsaEvent *watch_event; 245 uint32_t num_watch_points; 246 }; 247 248 struct dbg_wave_control_info { 249 struct kfd_process *process; 250 uint32_t trapId; 251 enum HSA_DBG_WAVEOP operand; 252 enum HSA_DBG_WAVEMODE mode; 253 struct HsaDbgWaveMessage dbgWave_msg; 254 }; 255 256 struct kfd_dbgdev { 257 258 /* The device that owns this data. */ 259 struct kfd_dev *dev; 260 261 /* kernel queue for DIQ */ 262 struct kernel_queue *kq; 263 264 /* a pointer to the pqm of the calling process */ 265 struct process_queue_manager *pqm; 266 267 /* type of debug device ( DIQ, non DIQ, etc. ) */ 268 enum DBGDEV_TYPE type; 269 270 /* virtualized function pointers to device dbg */ 271 int (*dbgdev_register)(struct kfd_dbgdev *dbgdev); 272 int (*dbgdev_unregister)(struct kfd_dbgdev *dbgdev); 273 int (*dbgdev_address_watch)(struct kfd_dbgdev *dbgdev, 274 struct dbg_address_watch_info *adw_info); 275 int (*dbgdev_wave_control)(struct kfd_dbgdev *dbgdev, 276 struct dbg_wave_control_info *wac_info); 277 278 }; 279 280 struct kfd_dbgmgr { 281 unsigned int pasid; 282 struct kfd_dev *dev; 283 struct kfd_dbgdev *dbgdev; 284 }; 285 286 /* prototypes for debug manager functions */ 287 struct mutex *kfd_get_dbgmgr_mutex(void); 288 void kfd_dbgmgr_destroy(struct kfd_dbgmgr *pmgr); 289 bool kfd_dbgmgr_create(struct kfd_dbgmgr **ppmgr, struct kfd_dev *pdev); 290 long kfd_dbgmgr_register(struct kfd_dbgmgr *pmgr, struct kfd_process *p); 291 long kfd_dbgmgr_unregister(struct kfd_dbgmgr *pmgr, struct kfd_process *p); 292 long kfd_dbgmgr_wave_control(struct kfd_dbgmgr *pmgr, 293 struct dbg_wave_control_info *wac_info); 294 long kfd_dbgmgr_address_watch(struct kfd_dbgmgr *pmgr, 295 struct dbg_address_watch_info *adw_info); 296 #endif /* KFD_DBGMGR_H_ */ 297
Indexes created Sat Oct 25 10:09:55 GMT 2025