atombios.h revision 1.2.6.2
1 /* $NetBSD: atombios.h,v 1.2.6.2 2019/06/10 22:07:59 christos Exp $ */ 2 3 /* 4 * Copyright 2006-2007 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 26 /****************************************************************************/ 27 /*Portion I: Definitions shared between VBIOS and Driver */ 28 /****************************************************************************/ 29 30 #ifndef _ATOMBIOS_H 31 #define _ATOMBIOS_H 32 33 #define ATOM_VERSION_MAJOR 0x00020000 34 #define ATOM_VERSION_MINOR 0x00000002 35 36 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 37 38 /* Endianness should be specified before inclusion, 39 * default to little endian 40 */ 41 #ifndef ATOM_BIG_ENDIAN 42 #error Endian not specified 43 #endif 44 45 #ifdef _H2INC 46 #ifndef ULONG 47 typedef unsigned long ULONG; 48 #endif 49 50 #ifndef UCHAR 51 typedef unsigned char UCHAR; 52 #endif 53 54 #ifndef USHORT 55 typedef unsigned short USHORT; 56 #endif 57 #endif 58 59 #define ATOM_DAC_A 0 60 #define ATOM_DAC_B 1 61 #define ATOM_EXT_DAC 2 62 63 #define ATOM_CRTC1 0 64 #define ATOM_CRTC2 1 65 #define ATOM_CRTC3 2 66 #define ATOM_CRTC4 3 67 #define ATOM_CRTC5 4 68 #define ATOM_CRTC6 5 69 70 #define ATOM_UNDERLAY_PIPE0 16 71 #define ATOM_UNDERLAY_PIPE1 17 72 73 #define ATOM_CRTC_INVALID 0xFF 74 75 #define ATOM_DIGA 0 76 #define ATOM_DIGB 1 77 78 #define ATOM_PPLL1 0 79 #define ATOM_PPLL2 1 80 #define ATOM_DCPLL 2 81 #define ATOM_PPLL0 2 82 #define ATOM_PPLL3 3 83 84 #define ATOM_EXT_PLL1 8 85 #define ATOM_EXT_PLL2 9 86 #define ATOM_EXT_CLOCK 10 87 #define ATOM_PPLL_INVALID 0xFF 88 89 #define ENCODER_REFCLK_SRC_P1PLL 0 90 #define ENCODER_REFCLK_SRC_P2PLL 1 91 #define ENCODER_REFCLK_SRC_DCPLL 2 92 #define ENCODER_REFCLK_SRC_EXTCLK 3 93 #define ENCODER_REFCLK_SRC_INVALID 0xFF 94 95 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 96 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 97 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 98 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 99 100 #define ATOM_DISABLE 0 101 #define ATOM_ENABLE 1 102 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 103 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 104 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 105 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 106 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 107 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 108 #define ATOM_INIT (ATOM_DISABLE+7) 109 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 110 111 #define ATOM_BLANKING 1 112 #define ATOM_BLANKING_OFF 0 113 114 115 #define ATOM_CRT1 0 116 #define ATOM_CRT2 1 117 118 #define ATOM_TV_NTSC 1 119 #define ATOM_TV_NTSCJ 2 120 #define ATOM_TV_PAL 3 121 #define ATOM_TV_PALM 4 122 #define ATOM_TV_PALCN 5 123 #define ATOM_TV_PALN 6 124 #define ATOM_TV_PAL60 7 125 #define ATOM_TV_SECAM 8 126 #define ATOM_TV_CV 16 127 128 #define ATOM_DAC1_PS2 1 129 #define ATOM_DAC1_CV 2 130 #define ATOM_DAC1_NTSC 3 131 #define ATOM_DAC1_PAL 4 132 133 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 134 #define ATOM_DAC2_CV ATOM_DAC1_CV 135 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 136 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 137 138 #define ATOM_PM_ON 0 139 #define ATOM_PM_STANDBY 1 140 #define ATOM_PM_SUSPEND 2 141 #define ATOM_PM_OFF 3 142 143 // For ATOM_LVDS_INFO_V12 144 // Bit0:{=0:single, =1:dual}, 145 // Bit1 {=0:666RGB, =1:888RGB}, 146 // Bit2:3:{Grey level} 147 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 148 #define ATOM_PANEL_MISC_DUAL 0x00000001 149 #define ATOM_PANEL_MISC_888RGB 0x00000002 150 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 151 #define ATOM_PANEL_MISC_FPDI 0x00000010 152 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 153 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 154 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 155 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 156 157 #define MEMTYPE_DDR1 "DDR1" 158 #define MEMTYPE_DDR2 "DDR2" 159 #define MEMTYPE_DDR3 "DDR3" 160 #define MEMTYPE_DDR4 "DDR4" 161 162 #define ASIC_BUS_TYPE_PCI "PCI" 163 #define ASIC_BUS_TYPE_AGP "AGP" 164 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 165 166 //Maximum size of that FireGL flag string 167 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 168 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 169 170 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 171 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 172 173 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 174 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 175 176 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 177 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 178 179 #pragma pack(1) // BIOS data must use byte aligment 180 181 // Define offset to location of ROM header. 182 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 183 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 184 185 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 186 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 187 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 188 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 189 190 /****************************************************************************/ 191 // Common header for all tables (Data table, Command table). 192 // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 193 // And the pointer actually points to this header. 194 /****************************************************************************/ 195 196 typedef struct _ATOM_COMMON_TABLE_HEADER 197 { 198 USHORT usStructureSize; 199 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 200 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 201 //Image can't be updated, while Driver needs to carry the new table! 202 }ATOM_COMMON_TABLE_HEADER; 203 204 /****************************************************************************/ 205 // Structure stores the ROM header. 206 /****************************************************************************/ 207 typedef struct _ATOM_ROM_HEADER 208 { 209 ATOM_COMMON_TABLE_HEADER sHeader; 210 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 211 //atombios should init it as "ATOM", don't change the position 212 USHORT usBiosRuntimeSegmentAddress; 213 USHORT usProtectedModeInfoOffset; 214 USHORT usConfigFilenameOffset; 215 USHORT usCRC_BlockOffset; 216 USHORT usBIOS_BootupMessageOffset; 217 USHORT usInt10Offset; 218 USHORT usPciBusDevInitCode; 219 USHORT usIoBaseAddress; 220 USHORT usSubsystemVendorID; 221 USHORT usSubsystemID; 222 USHORT usPCI_InfoOffset; 223 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 224 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 225 UCHAR ucExtendedFunctionCode; 226 UCHAR ucReserved; 227 }ATOM_ROM_HEADER; 228 229 //==============================Command Table Portion==================================== 230 231 232 /****************************************************************************/ 233 // Structures used in Command.mtb 234 /****************************************************************************/ 235 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 236 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 237 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 238 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 239 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 240 USHORT DIGxEncoderControl; //Only used by Bios 241 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 242 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 243 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 244 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 245 USHORT GPIOPinControl; //Atomic Table, only used by Bios 246 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 247 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 248 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 249 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 250 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 251 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 252 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 253 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 254 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 255 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 256 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 257 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 258 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 259 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 260 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 261 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 262 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 263 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 264 USHORT GetConditionalGoldenSetting; //Only used by Bios 265 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 266 USHORT PatchMCSetting; //only used by BIOS 267 USHORT MC_SEQ_Control; //only used by BIOS 268 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 269 USHORT EnableScaler; //Atomic Table, used only by Bios 270 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 271 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 272 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 273 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 274 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 275 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 276 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 277 USHORT SetCRTC_Replication; //Atomic Table, used only by Bios 278 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 279 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 280 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 281 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 282 USHORT EnableHW_IconCursor; //Atomic Table, only used by Bios 283 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 284 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 285 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 286 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 287 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 288 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 289 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 290 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 291 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 292 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 293 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 294 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 295 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 296 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 297 USHORT MemoryRefreshConversion; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 298 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 299 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 300 USHORT MemoryTraining; //Atomic Table, used only by Bios 301 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 302 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 303 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 304 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 305 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 306 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 307 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 308 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 309 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 310 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 311 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 312 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 313 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 314 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 315 USHORT DPEncoderService; //Function Table,only used by Bios 316 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 317 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 318 319 // For backward compatible 320 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 321 #define DPTranslatorControl DIG2EncoderControl 322 #define UNIPHYTransmitterControl DIG1TransmitterControl 323 #define LVTMATransmitterControl DIG2TransmitterControl 324 #define SetCRTC_DPM_State GetConditionalGoldenSetting 325 #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 326 #define HPDInterruptService ReadHWAssistedI2CStatus 327 #define EnableVGA_Access GetSCLKOverMCLKRatio 328 #define EnableYUV GetDispObjectInfo 329 #define DynamicClockGating EnableDispPowerGating 330 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 331 #define DAC2OutputControl ReadEfuseValue 332 333 #define TMDSAEncoderControl PatchMCSetting 334 #define LVDSEncoderControl MC_SEQ_Control 335 #define LCD1OutputControl HW_Misc_Operation 336 #define TV1OutputControl Gfx_Harvesting 337 #define TVEncoderControl SMC_Init 338 339 typedef struct _ATOM_MASTER_COMMAND_TABLE 340 { 341 ATOM_COMMON_TABLE_HEADER sHeader; 342 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 343 }ATOM_MASTER_COMMAND_TABLE; 344 345 /****************************************************************************/ 346 // Structures used in every command table 347 /****************************************************************************/ 348 typedef struct _ATOM_TABLE_ATTRIBUTE 349 { 350 #if ATOM_BIG_ENDIAN 351 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 352 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 353 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 354 #else 355 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 356 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 357 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 358 #endif 359 }ATOM_TABLE_ATTRIBUTE; 360 361 /****************************************************************************/ 362 // Common header for all command tables. 363 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 364 // And the pointer actually points to this header. 365 /****************************************************************************/ 366 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 367 { 368 ATOM_COMMON_TABLE_HEADER CommonHeader; 369 ATOM_TABLE_ATTRIBUTE TableAttribute; 370 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 371 372 /****************************************************************************/ 373 // Structures used by ComputeMemoryEnginePLLTable 374 /****************************************************************************/ 375 376 #define COMPUTE_MEMORY_PLL_PARAM 1 377 #define COMPUTE_ENGINE_PLL_PARAM 2 378 #define ADJUST_MC_SETTING_PARAM 3 379 380 /****************************************************************************/ 381 // Structures used by AdjustMemoryControllerTable 382 /****************************************************************************/ 383 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 384 { 385 #if ATOM_BIG_ENDIAN 386 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 387 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 388 ULONG ulClockFreq:24; 389 #else 390 ULONG ulClockFreq:24; 391 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 392 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 393 #endif 394 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 395 #define POINTER_RETURN_FLAG 0x80 396 397 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 398 { 399 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 400 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 401 UCHAR ucReserved; //may expand to return larger Fbdiv later 402 UCHAR ucFbDiv; //return value 403 UCHAR ucPostDiv; //return value 404 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 405 406 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 407 { 408 ULONG ulClock; //When return, [23:0] return real clock 409 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 410 USHORT usFbDiv; //return Feedback value to be written to register 411 UCHAR ucPostDiv; //return post div to be written to register 412 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 413 414 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 415 416 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 417 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 418 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 419 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 420 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 421 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 422 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 423 424 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 425 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 426 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 427 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 428 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 429 #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 430 431 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 432 { 433 #if ATOM_BIG_ENDIAN 434 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 435 ULONG ulClockFreq:24; // in unit of 10kHz 436 #else 437 ULONG ulClockFreq:24; // in unit of 10kHz 438 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 439 #endif 440 }ATOM_COMPUTE_CLOCK_FREQ; 441 442 typedef struct _ATOM_S_MPLL_FB_DIVIDER 443 { 444 USHORT usFbDivFrac; 445 USHORT usFbDiv; 446 }ATOM_S_MPLL_FB_DIVIDER; 447 448 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 449 { 450 union 451 { 452 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 453 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 454 }; 455 UCHAR ucRefDiv; //Output Parameter 456 UCHAR ucPostDiv; //Output Parameter 457 UCHAR ucCntlFlag; //Output Parameter 458 UCHAR ucReserved; 459 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 460 461 // ucCntlFlag 462 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 463 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 464 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 465 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 466 467 468 // V4 are only used for APU which PLL outside GPU 469 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 470 { 471 #if ATOM_BIG_ENDIAN 472 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 473 ULONG ulClock:24; //Input= target clock, output = actual clock 474 #else 475 ULONG ulClock:24; //Input= target clock, output = actual clock 476 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 477 #endif 478 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 479 480 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 481 { 482 union 483 { 484 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 485 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 486 }; 487 UCHAR ucRefDiv; //Output Parameter 488 UCHAR ucPostDiv; //Output Parameter 489 union 490 { 491 UCHAR ucCntlFlag; //Output Flags 492 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 493 }; 494 UCHAR ucReserved; 495 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 496 497 498 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 499 { 500 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 501 ULONG ulReserved[2]; 502 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 503 504 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 505 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 506 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 507 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 508 509 510 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 511 { 512 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 513 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 514 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 515 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 516 UCHAR ucPllCntlFlag; //Output Flags: control flag 517 UCHAR ucReserved; 518 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 519 520 //ucPllCntlFlag 521 #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 522 523 524 // ucInputFlag 525 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 526 527 // use for ComputeMemoryClockParamTable 528 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 529 { 530 union 531 { 532 ULONG ulClock; 533 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 534 }; 535 UCHAR ucDllSpeed; //Output 536 UCHAR ucPostDiv; //Output 537 union{ 538 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 539 UCHAR ucPllCntlFlag; //Output: 540 }; 541 UCHAR ucBWCntl; 542 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 543 544 // definition of ucInputFlag 545 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 546 // definition of ucPllCntlFlag 547 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 548 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 549 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 550 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 551 552 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 553 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 554 555 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 556 { 557 ATOM_COMPUTE_CLOCK_FREQ ulClock; 558 ULONG ulReserved[2]; 559 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 560 561 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 562 { 563 ATOM_COMPUTE_CLOCK_FREQ ulClock; 564 ULONG ulMemoryClock; 565 ULONG ulReserved; 566 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 567 568 /****************************************************************************/ 569 // Structures used by SetEngineClockTable 570 /****************************************************************************/ 571 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 572 { 573 ULONG ulTargetEngineClock; //In 10Khz unit 574 }SET_ENGINE_CLOCK_PARAMETERS; 575 576 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 577 { 578 ULONG ulTargetEngineClock; //In 10Khz unit 579 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 580 }SET_ENGINE_CLOCK_PS_ALLOCATION; 581 582 /****************************************************************************/ 583 // Structures used by SetMemoryClockTable 584 /****************************************************************************/ 585 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 586 { 587 ULONG ulTargetMemoryClock; //In 10Khz unit 588 }SET_MEMORY_CLOCK_PARAMETERS; 589 590 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 591 { 592 ULONG ulTargetMemoryClock; //In 10Khz unit 593 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 594 }SET_MEMORY_CLOCK_PS_ALLOCATION; 595 596 /****************************************************************************/ 597 // Structures used by ASIC_Init.ctb 598 /****************************************************************************/ 599 typedef struct _ASIC_INIT_PARAMETERS 600 { 601 ULONG ulDefaultEngineClock; //In 10Khz unit 602 ULONG ulDefaultMemoryClock; //In 10Khz unit 603 }ASIC_INIT_PARAMETERS; 604 605 typedef struct _ASIC_INIT_PS_ALLOCATION 606 { 607 ASIC_INIT_PARAMETERS sASICInitClocks; 608 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 609 }ASIC_INIT_PS_ALLOCATION; 610 611 typedef struct _ASIC_INIT_CLOCK_PARAMETERS 612 { 613 ULONG ulClkFreqIn10Khz:24; 614 ULONG ucClkFlag:8; 615 }ASIC_INIT_CLOCK_PARAMETERS; 616 617 typedef struct _ASIC_INIT_PARAMETERS_V1_2 618 { 619 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 620 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 621 }ASIC_INIT_PARAMETERS_V1_2; 622 623 typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 624 { 625 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 626 ULONG ulReserved[8]; 627 }ASIC_INIT_PS_ALLOCATION_V1_2; 628 629 /****************************************************************************/ 630 // Structure used by DynamicClockGatingTable.ctb 631 /****************************************************************************/ 632 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 633 { 634 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 635 UCHAR ucPadding[3]; 636 }DYNAMIC_CLOCK_GATING_PARAMETERS; 637 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 638 639 /****************************************************************************/ 640 // Structure used by EnableDispPowerGatingTable.ctb 641 /****************************************************************************/ 642 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 643 { 644 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 645 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 646 UCHAR ucPadding[2]; 647 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 648 649 typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 650 { 651 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 652 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 653 UCHAR ucPadding[2]; 654 ULONG ulReserved[4]; 655 }ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 656 657 /****************************************************************************/ 658 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 659 /****************************************************************************/ 660 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 661 { 662 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 663 UCHAR ucPadding[3]; 664 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 665 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 666 667 /****************************************************************************/ 668 // Structures used by DAC_LoadDetectionTable.ctb 669 /****************************************************************************/ 670 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 671 { 672 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 673 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 674 UCHAR ucMisc; //Valid only when table revision =1.3 and above 675 }DAC_LOAD_DETECTION_PARAMETERS; 676 677 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 678 #define DAC_LOAD_MISC_YPrPb 0x01 679 680 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 681 { 682 DAC_LOAD_DETECTION_PARAMETERS sDacload; 683 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 684 }DAC_LOAD_DETECTION_PS_ALLOCATION; 685 686 /****************************************************************************/ 687 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 688 /****************************************************************************/ 689 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 690 { 691 USHORT usPixelClock; // in 10KHz; for bios convenient 692 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 693 UCHAR ucAction; // 0: turn off encoder 694 // 1: setup and turn on encoder 695 // 7: ATOM_ENCODER_INIT Initialize DAC 696 }DAC_ENCODER_CONTROL_PARAMETERS; 697 698 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 699 700 /****************************************************************************/ 701 // Structures used by DIG1EncoderControlTable 702 // DIG2EncoderControlTable 703 // ExternalEncoderControlTable 704 /****************************************************************************/ 705 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 706 { 707 USHORT usPixelClock; // in 10KHz; for bios convenient 708 UCHAR ucConfig; 709 // [2] Link Select: 710 // =0: PHY linkA if bfLane<3 711 // =1: PHY linkB if bfLanes<3 712 // =0: PHY linkA+B if bfLanes=3 713 // [3] Transmitter Sel 714 // =0: UNIPHY or PCIEPHY 715 // =1: LVTMA 716 UCHAR ucAction; // =0: turn off encoder 717 // =1: turn on encoder 718 UCHAR ucEncoderMode; 719 // =0: DP encoder 720 // =1: LVDS encoder 721 // =2: DVI encoder 722 // =3: HDMI encoder 723 // =4: SDVO encoder 724 UCHAR ucLaneNum; // how many lanes to enable 725 UCHAR ucReserved[2]; 726 }DIG_ENCODER_CONTROL_PARAMETERS; 727 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 728 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 729 730 //ucConfig 731 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 732 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 733 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 734 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 735 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 736 #define ATOM_ENCODER_CONFIG_LINKA 0x00 737 #define ATOM_ENCODER_CONFIG_LINKB 0x04 738 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 739 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 740 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 741 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 742 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 743 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 744 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 745 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 746 // ucAction 747 // ATOM_ENABLE: Enable Encoder 748 // ATOM_DISABLE: Disable Encoder 749 750 //ucEncoderMode 751 #define ATOM_ENCODER_MODE_DP 0 752 #define ATOM_ENCODER_MODE_LVDS 1 753 #define ATOM_ENCODER_MODE_DVI 2 754 #define ATOM_ENCODER_MODE_HDMI 3 755 #define ATOM_ENCODER_MODE_SDVO 4 756 #define ATOM_ENCODER_MODE_DP_AUDIO 5 757 #define ATOM_ENCODER_MODE_TV 13 758 #define ATOM_ENCODER_MODE_CV 14 759 #define ATOM_ENCODER_MODE_CRT 15 760 #define ATOM_ENCODER_MODE_DVO 16 761 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 762 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 763 764 765 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 766 { 767 #if ATOM_BIG_ENDIAN 768 UCHAR ucReserved1:2; 769 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 770 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 771 UCHAR ucReserved:1; 772 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 773 #else 774 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 775 UCHAR ucReserved:1; 776 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 777 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 778 UCHAR ucReserved1:2; 779 #endif 780 }ATOM_DIG_ENCODER_CONFIG_V2; 781 782 783 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 784 { 785 USHORT usPixelClock; // in 10KHz; for bios convenient 786 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 787 UCHAR ucAction; 788 UCHAR ucEncoderMode; 789 // =0: DP encoder 790 // =1: LVDS encoder 791 // =2: DVI encoder 792 // =3: HDMI encoder 793 // =4: SDVO encoder 794 UCHAR ucLaneNum; // how many lanes to enable 795 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 796 UCHAR ucReserved; 797 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 798 799 //ucConfig 800 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 801 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 802 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 803 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 804 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 805 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 806 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 807 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 808 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 809 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 810 811 // ucAction: 812 // ATOM_DISABLE 813 // ATOM_ENABLE 814 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 815 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 816 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 817 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 818 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 819 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 820 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 821 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 822 #define ATOM_ENCODER_CMD_SETUP 0x0f 823 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 824 825 // ucStatus 826 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 827 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 828 829 //ucTableFormatRevision=1 830 //ucTableContentRevision=3 831 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 832 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 833 { 834 #if ATOM_BIG_ENDIAN 835 UCHAR ucReserved1:1; 836 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 837 UCHAR ucReserved:3; 838 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 839 #else 840 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 841 UCHAR ucReserved:3; 842 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 843 UCHAR ucReserved1:1; 844 #endif 845 }ATOM_DIG_ENCODER_CONFIG_V3; 846 847 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 848 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 849 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 850 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 851 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 852 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 853 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 854 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 855 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 856 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 857 858 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 859 { 860 USHORT usPixelClock; // in 10KHz; for bios convenient 861 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 862 UCHAR ucAction; 863 union{ 864 UCHAR ucEncoderMode; 865 // =0: DP encoder 866 // =1: LVDS encoder 867 // =2: DVI encoder 868 // =3: HDMI encoder 869 // =4: SDVO encoder 870 // =5: DP audio 871 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 872 // =0: external DP 873 // =0x1: internal DP2 874 // =0x11: internal DP1 for NutMeg/Travis DP translator 875 }; 876 UCHAR ucLaneNum; // how many lanes to enable 877 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 878 UCHAR ucReserved; 879 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 880 881 //ucTableFormatRevision=1 882 //ucTableContentRevision=4 883 // start from NI 884 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 885 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 886 { 887 #if ATOM_BIG_ENDIAN 888 UCHAR ucReserved1:1; 889 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 890 UCHAR ucReserved:2; 891 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 892 #else 893 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 894 UCHAR ucReserved:2; 895 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 896 UCHAR ucReserved1:1; 897 #endif 898 }ATOM_DIG_ENCODER_CONFIG_V4; 899 900 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 901 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 902 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 903 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 904 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 905 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 906 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 907 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 908 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 909 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 910 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 911 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 912 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 913 914 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 915 { 916 USHORT usPixelClock; // in 10KHz; for bios convenient 917 union{ 918 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 919 UCHAR ucConfig; 920 }; 921 UCHAR ucAction; 922 union{ 923 UCHAR ucEncoderMode; 924 // =0: DP encoder 925 // =1: LVDS encoder 926 // =2: DVI encoder 927 // =3: HDMI encoder 928 // =4: SDVO encoder 929 // =5: DP audio 930 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 931 // =0: external DP 932 // =0x1: internal DP2 933 // =0x11: internal DP1 for NutMeg/Travis DP translator 934 }; 935 UCHAR ucLaneNum; // how many lanes to enable 936 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 937 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 938 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 939 940 // define ucBitPerColor: 941 #define PANEL_BPC_UNDEFINE 0x00 942 #define PANEL_6BIT_PER_COLOR 0x01 943 #define PANEL_8BIT_PER_COLOR 0x02 944 #define PANEL_10BIT_PER_COLOR 0x03 945 #define PANEL_12BIT_PER_COLOR 0x04 946 #define PANEL_16BIT_PER_COLOR 0x05 947 948 //define ucPanelMode 949 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 950 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 951 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 952 953 /****************************************************************************/ 954 // Structures used by UNIPHYTransmitterControlTable 955 // LVTMATransmitterControlTable 956 // DVOOutputControlTable 957 /****************************************************************************/ 958 typedef struct _ATOM_DP_VS_MODE 959 { 960 UCHAR ucLaneSel; 961 UCHAR ucLaneSet; 962 }ATOM_DP_VS_MODE; 963 964 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 965 { 966 union 967 { 968 USHORT usPixelClock; // in 10KHz; for bios convenient 969 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 970 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 971 }; 972 UCHAR ucConfig; 973 // [0]=0: 4 lane Link, 974 // =1: 8 lane Link ( Dual Links TMDS ) 975 // [1]=0: InCoherent mode 976 // =1: Coherent Mode 977 // [2] Link Select: 978 // =0: PHY linkA if bfLane<3 979 // =1: PHY linkB if bfLanes<3 980 // =0: PHY linkA+B if bfLanes=3 981 // [5:4]PCIE lane Sel 982 // =0: lane 0~3 or 0~7 983 // =1: lane 4~7 984 // =2: lane 8~11 or 8~15 985 // =3: lane 12~15 986 UCHAR ucAction; // =0: turn off encoder 987 // =1: turn on encoder 988 UCHAR ucReserved[4]; 989 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 990 991 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 992 993 //ucInitInfo 994 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 995 996 //ucConfig 997 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 998 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 999 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1000 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1001 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1002 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1003 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1004 1005 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1006 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1007 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1008 1009 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1010 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1011 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1012 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1013 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1014 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1015 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1016 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1017 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1018 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1019 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1020 1021 //ucAction 1022 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 1023 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 1024 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1025 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1026 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1027 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1028 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1029 #define ATOM_TRANSMITTER_ACTION_INIT 7 1030 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1031 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1032 #define ATOM_TRANSMITTER_ACTION_SETUP 10 1033 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1034 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1035 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1036 1037 // Following are used for DigTransmitterControlTable ver1.2 1038 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1039 { 1040 #if ATOM_BIG_ENDIAN 1041 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1042 // =1 Dig Transmitter 2 ( Uniphy CD ) 1043 // =2 Dig Transmitter 3 ( Uniphy EF ) 1044 UCHAR ucReserved:1; 1045 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1046 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1047 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1048 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1049 1050 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1051 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1052 #else 1053 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1054 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1055 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1056 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1057 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1058 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1059 UCHAR ucReserved:1; 1060 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1061 // =1 Dig Transmitter 2 ( Uniphy CD ) 1062 // =2 Dig Transmitter 3 ( Uniphy EF ) 1063 #endif 1064 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1065 1066 //ucConfig 1067 //Bit0 1068 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1069 1070 //Bit1 1071 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1072 1073 //Bit2 1074 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1075 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1076 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1077 1078 // Bit3 1079 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1080 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1081 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1082 1083 // Bit4 1084 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1085 1086 // Bit7:6 1087 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1088 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1089 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1090 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1091 1092 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1093 { 1094 union 1095 { 1096 USHORT usPixelClock; // in 10KHz; for bios convenient 1097 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1098 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1099 }; 1100 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1101 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1102 UCHAR ucReserved[4]; 1103 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1104 1105 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1106 { 1107 #if ATOM_BIG_ENDIAN 1108 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1109 // =1 Dig Transmitter 2 ( Uniphy CD ) 1110 // =2 Dig Transmitter 3 ( Uniphy EF ) 1111 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1112 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1113 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1114 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1115 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1116 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1117 #else 1118 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1119 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1120 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1121 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1122 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1123 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1124 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1125 // =1 Dig Transmitter 2 ( Uniphy CD ) 1126 // =2 Dig Transmitter 3 ( Uniphy EF ) 1127 #endif 1128 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1129 1130 1131 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1132 { 1133 union 1134 { 1135 USHORT usPixelClock; // in 10KHz; for bios convenient 1136 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1137 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1138 }; 1139 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1140 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1141 UCHAR ucLaneNum; 1142 UCHAR ucReserved[3]; 1143 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1144 1145 //ucConfig 1146 //Bit0 1147 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1148 1149 //Bit1 1150 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1151 1152 //Bit2 1153 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1154 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1155 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1156 1157 // Bit3 1158 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1159 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1160 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1161 1162 // Bit5:4 1163 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1164 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1165 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1166 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1167 1168 // Bit7:6 1169 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1170 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1171 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1172 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1173 1174 1175 /****************************************************************************/ 1176 // Structures used by UNIPHYTransmitterControlTable V1.4 1177 // ASIC Families: NI 1178 // ucTableFormatRevision=1 1179 // ucTableContentRevision=4 1180 /****************************************************************************/ 1181 typedef struct _ATOM_DP_VS_MODE_V4 1182 { 1183 UCHAR ucLaneSel; 1184 union 1185 { 1186 UCHAR ucLaneSet; 1187 struct { 1188 #if ATOM_BIG_ENDIAN 1189 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1190 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1191 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1192 #else 1193 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1194 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1195 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1196 #endif 1197 }; 1198 }; 1199 }ATOM_DP_VS_MODE_V4; 1200 1201 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1202 { 1203 #if ATOM_BIG_ENDIAN 1204 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1205 // =1 Dig Transmitter 2 ( Uniphy CD ) 1206 // =2 Dig Transmitter 3 ( Uniphy EF ) 1207 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1208 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1209 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1210 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1211 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1212 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1213 #else 1214 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1215 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1216 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1217 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1218 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1219 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1220 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1221 // =1 Dig Transmitter 2 ( Uniphy CD ) 1222 // =2 Dig Transmitter 3 ( Uniphy EF ) 1223 #endif 1224 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1225 1226 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1227 { 1228 union 1229 { 1230 USHORT usPixelClock; // in 10KHz; for bios convenient 1231 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1232 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1233 }; 1234 union 1235 { 1236 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1237 UCHAR ucConfig; 1238 }; 1239 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1240 UCHAR ucLaneNum; 1241 UCHAR ucReserved[3]; 1242 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1243 1244 //ucConfig 1245 //Bit0 1246 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1247 //Bit1 1248 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1249 //Bit2 1250 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1251 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1252 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1253 // Bit3 1254 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1255 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1256 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1257 // Bit5:4 1258 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1259 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1260 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1261 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1262 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1263 // Bit7:6 1264 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1265 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1266 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1267 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1268 1269 1270 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1271 { 1272 #if ATOM_BIG_ENDIAN 1273 UCHAR ucReservd1:1; 1274 UCHAR ucHPDSel:3; 1275 UCHAR ucPhyClkSrcId:2; 1276 UCHAR ucCoherentMode:1; 1277 UCHAR ucReserved:1; 1278 #else 1279 UCHAR ucReserved:1; 1280 UCHAR ucCoherentMode:1; 1281 UCHAR ucPhyClkSrcId:2; 1282 UCHAR ucHPDSel:3; 1283 UCHAR ucReservd1:1; 1284 #endif 1285 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1286 1287 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1288 { 1289 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1290 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1291 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1292 UCHAR ucLaneNum; // indicate lane number 1-8 1293 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1294 UCHAR ucDigMode; // indicate DIG mode 1295 union{ 1296 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1297 UCHAR ucConfig; 1298 }; 1299 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1300 UCHAR ucDPLaneSet; 1301 UCHAR ucReserved; 1302 UCHAR ucReserved1; 1303 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1304 1305 //ucPhyId 1306 #define ATOM_PHY_ID_UNIPHYA 0 1307 #define ATOM_PHY_ID_UNIPHYB 1 1308 #define ATOM_PHY_ID_UNIPHYC 2 1309 #define ATOM_PHY_ID_UNIPHYD 3 1310 #define ATOM_PHY_ID_UNIPHYE 4 1311 #define ATOM_PHY_ID_UNIPHYF 5 1312 #define ATOM_PHY_ID_UNIPHYG 6 1313 1314 // ucDigEncoderSel 1315 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1316 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1317 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1318 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1319 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1320 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1321 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1322 1323 // ucDigMode 1324 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1325 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1326 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1327 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1328 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1329 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1330 1331 // ucDPLaneSet 1332 #define DP_LANE_SET__0DB_0_4V 0x00 1333 #define DP_LANE_SET__0DB_0_6V 0x01 1334 #define DP_LANE_SET__0DB_0_8V 0x02 1335 #define DP_LANE_SET__0DB_1_2V 0x03 1336 #define DP_LANE_SET__3_5DB_0_4V 0x08 1337 #define DP_LANE_SET__3_5DB_0_6V 0x09 1338 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1339 #define DP_LANE_SET__6DB_0_4V 0x10 1340 #define DP_LANE_SET__6DB_0_6V 0x11 1341 #define DP_LANE_SET__9_5DB_0_4V 0x18 1342 1343 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1344 // Bit1 1345 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1346 1347 // Bit3:2 1348 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1349 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1350 1351 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1352 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1353 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1354 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1355 // Bit6:4 1356 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1357 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1358 1359 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1360 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1361 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1362 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1363 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1364 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1365 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1366 1367 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1368 1369 1370 /****************************************************************************/ 1371 // Structures used by ExternalEncoderControlTable V1.3 1372 // ASIC Families: Evergreen, Llano, NI 1373 // ucTableFormatRevision=1 1374 // ucTableContentRevision=3 1375 /****************************************************************************/ 1376 1377 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1378 { 1379 union{ 1380 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1381 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1382 }; 1383 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1384 UCHAR ucAction; // 1385 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1386 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1387 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1388 UCHAR ucReserved; 1389 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1390 1391 // ucAction 1392 #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1393 #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1394 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1395 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1396 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1397 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1398 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1399 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1400 1401 // ucConfig 1402 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1403 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1404 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1405 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1406 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1407 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1408 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1409 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1410 1411 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1412 { 1413 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1414 ULONG ulReserved[2]; 1415 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1416 1417 1418 /****************************************************************************/ 1419 // Structures used by DAC1OuputControlTable 1420 // DAC2OuputControlTable 1421 // LVTMAOutputControlTable (Before DEC30) 1422 // TMDSAOutputControlTable (Before DEC30) 1423 /****************************************************************************/ 1424 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1425 { 1426 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1427 // When the display is LCD, in addition to above: 1428 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1429 // ATOM_LCD_SELFTEST_STOP 1430 1431 UCHAR aucPadding[3]; // padding to DWORD aligned 1432 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1433 1434 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1435 1436 1437 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1438 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1439 1440 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1441 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1442 1443 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1444 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1445 1446 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1447 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1448 1449 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1450 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1451 1452 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1453 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1454 1455 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1456 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1457 1458 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1459 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1460 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1461 1462 1463 typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1464 { 1465 // Possible value of ucAction 1466 // ATOM_TRANSMITTER_ACTION_LCD_BLON 1467 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1468 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1469 // ATOM_TRANSMITTER_ACTION_POWER_ON 1470 // ATOM_TRANSMITTER_ACTION_POWER_OFF 1471 UCHAR ucAction; 1472 UCHAR ucBriLevel; 1473 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1474 }LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1475 1476 1477 1478 /****************************************************************************/ 1479 // Structures used by BlankCRTCTable 1480 /****************************************************************************/ 1481 typedef struct _BLANK_CRTC_PARAMETERS 1482 { 1483 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1484 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1485 USHORT usBlackColorRCr; 1486 USHORT usBlackColorGY; 1487 USHORT usBlackColorBCb; 1488 }BLANK_CRTC_PARAMETERS; 1489 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1490 1491 /****************************************************************************/ 1492 // Structures used by EnableCRTCTable 1493 // EnableCRTCMemReqTable 1494 // UpdateCRTC_DoubleBufferRegistersTable 1495 /****************************************************************************/ 1496 typedef struct _ENABLE_CRTC_PARAMETERS 1497 { 1498 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1499 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1500 UCHAR ucPadding[2]; 1501 }ENABLE_CRTC_PARAMETERS; 1502 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1503 1504 /****************************************************************************/ 1505 // Structures used by SetCRTC_OverScanTable 1506 /****************************************************************************/ 1507 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1508 { 1509 USHORT usOverscanRight; // right 1510 USHORT usOverscanLeft; // left 1511 USHORT usOverscanBottom; // bottom 1512 USHORT usOverscanTop; // top 1513 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1514 UCHAR ucPadding[3]; 1515 }SET_CRTC_OVERSCAN_PARAMETERS; 1516 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1517 1518 /****************************************************************************/ 1519 // Structures used by SetCRTC_ReplicationTable 1520 /****************************************************************************/ 1521 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1522 { 1523 UCHAR ucH_Replication; // horizontal replication 1524 UCHAR ucV_Replication; // vertical replication 1525 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1526 UCHAR ucPadding; 1527 }SET_CRTC_REPLICATION_PARAMETERS; 1528 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1529 1530 /****************************************************************************/ 1531 // Structures used by SelectCRTC_SourceTable 1532 /****************************************************************************/ 1533 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1534 { 1535 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1536 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1537 UCHAR ucPadding[2]; 1538 }SELECT_CRTC_SOURCE_PARAMETERS; 1539 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1540 1541 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1542 { 1543 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1544 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1545 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1546 UCHAR ucPadding; 1547 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1548 1549 //ucEncoderID 1550 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1551 //#define ASIC_INT_TV_ENCODER_ID 0x02 1552 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1553 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1554 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1555 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1556 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1557 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1558 1559 //ucEncodeMode 1560 //#define ATOM_ENCODER_MODE_DP 0 1561 //#define ATOM_ENCODER_MODE_LVDS 1 1562 //#define ATOM_ENCODER_MODE_DVI 2 1563 //#define ATOM_ENCODER_MODE_HDMI 3 1564 //#define ATOM_ENCODER_MODE_SDVO 4 1565 //#define ATOM_ENCODER_MODE_TV 13 1566 //#define ATOM_ENCODER_MODE_CV 14 1567 //#define ATOM_ENCODER_MODE_CRT 15 1568 1569 1570 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1571 { 1572 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1573 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1574 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1575 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1576 }SELECT_CRTC_SOURCE_PARAMETERS_V3; 1577 1578 1579 /****************************************************************************/ 1580 // Structures used by SetPixelClockTable 1581 // GetPixelClockTable 1582 /****************************************************************************/ 1583 //Major revision=1., Minor revision=1 1584 typedef struct _PIXEL_CLOCK_PARAMETERS 1585 { 1586 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1587 // 0 means disable PPLL 1588 USHORT usRefDiv; // Reference divider 1589 USHORT usFbDiv; // feedback divider 1590 UCHAR ucPostDiv; // post divider 1591 UCHAR ucFracFbDiv; // fractional feedback divider 1592 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1593 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1594 UCHAR ucCRTC; // Which CRTC uses this Ppll 1595 UCHAR ucPadding; 1596 }PIXEL_CLOCK_PARAMETERS; 1597 1598 //Major revision=1., Minor revision=2, add ucMiscIfno 1599 //ucMiscInfo: 1600 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1601 #define MISC_DEVICE_INDEX_MASK 0xF0 1602 #define MISC_DEVICE_INDEX_SHIFT 4 1603 1604 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1605 { 1606 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1607 // 0 means disable PPLL 1608 USHORT usRefDiv; // Reference divider 1609 USHORT usFbDiv; // feedback divider 1610 UCHAR ucPostDiv; // post divider 1611 UCHAR ucFracFbDiv; // fractional feedback divider 1612 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1613 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1614 UCHAR ucCRTC; // Which CRTC uses this Ppll 1615 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1616 }PIXEL_CLOCK_PARAMETERS_V2; 1617 1618 //Major revision=1., Minor revision=3, structure/definition change 1619 //ucEncoderMode: 1620 //ATOM_ENCODER_MODE_DP 1621 //ATOM_ENOCDER_MODE_LVDS 1622 //ATOM_ENOCDER_MODE_DVI 1623 //ATOM_ENOCDER_MODE_HDMI 1624 //ATOM_ENOCDER_MODE_SDVO 1625 //ATOM_ENCODER_MODE_TV 13 1626 //ATOM_ENCODER_MODE_CV 14 1627 //ATOM_ENCODER_MODE_CRT 15 1628 1629 //ucDVOConfig 1630 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1631 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1632 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1633 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1634 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1635 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1636 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1637 1638 //ucMiscInfo: also changed, see below 1639 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1640 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1641 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1642 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1643 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1644 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1645 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1646 // V1.4 for RoadRunner 1647 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1648 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1649 1650 1651 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1652 { 1653 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1654 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1655 USHORT usRefDiv; // Reference divider 1656 USHORT usFbDiv; // feedback divider 1657 UCHAR ucPostDiv; // post divider 1658 UCHAR ucFracFbDiv; // fractional feedback divider 1659 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1660 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1661 union 1662 { 1663 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1664 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1665 }; 1666 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1667 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1668 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1669 }PIXEL_CLOCK_PARAMETERS_V3; 1670 1671 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1672 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1673 1674 1675 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1676 { 1677 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1678 // drive the pixel clock. not used for DCPLL case. 1679 union{ 1680 UCHAR ucReserved; 1681 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1682 }; 1683 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1684 // 0 means disable PPLL/DCPLL. 1685 USHORT usFbDiv; // feedback divider integer part. 1686 UCHAR ucPostDiv; // post divider. 1687 UCHAR ucRefDiv; // Reference divider 1688 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1689 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1690 // indicate which graphic encoder will be used. 1691 UCHAR ucEncoderMode; // Encoder mode: 1692 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1693 // bit[1]= when VGA timing is used. 1694 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1695 // bit[4]= RefClock source for PPLL. 1696 // =0: XTLAIN( default mode ) 1697 // =1: other external clock source, which is pre-defined 1698 // by VBIOS depend on the feature required. 1699 // bit[7:5]: reserved. 1700 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1701 1702 }PIXEL_CLOCK_PARAMETERS_V5; 1703 1704 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1705 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1706 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1707 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1708 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1709 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1710 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1711 1712 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1713 { 1714 #if ATOM_BIG_ENDIAN 1715 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1716 // drive the pixel clock. not used for DCPLL case. 1717 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1718 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1719 #else 1720 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1721 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1722 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1723 // drive the pixel clock. not used for DCPLL case. 1724 #endif 1725 }CRTC_PIXEL_CLOCK_FREQ; 1726 1727 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1728 { 1729 union{ 1730 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1731 ULONG ulDispEngClkFreq; // dispclk frequency 1732 }; 1733 USHORT usFbDiv; // feedback divider integer part. 1734 UCHAR ucPostDiv; // post divider. 1735 UCHAR ucRefDiv; // Reference divider 1736 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1737 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1738 // indicate which graphic encoder will be used. 1739 UCHAR ucEncoderMode; // Encoder mode: 1740 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1741 // bit[1]= when VGA timing is used. 1742 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1743 // bit[4]= RefClock source for PPLL. 1744 // =0: XTLAIN( default mode ) 1745 // =1: other external clock source, which is pre-defined 1746 // by VBIOS depend on the feature required. 1747 // bit[7:5]: reserved. 1748 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1749 1750 }PIXEL_CLOCK_PARAMETERS_V6; 1751 1752 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1753 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1754 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1755 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1756 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1757 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1758 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1759 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1760 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1761 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1762 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1763 #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 1764 1765 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 1766 { 1767 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 1768 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 1769 1770 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 1771 { 1772 UCHAR ucStatus; 1773 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 1774 UCHAR ucReserved[2]; 1775 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 1776 1777 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 1778 { 1779 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 1780 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 1781 1782 1783 /****************************************************************************/ 1784 // Structures used by AdjustDisplayPllTable 1785 /****************************************************************************/ 1786 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 1787 { 1788 USHORT usPixelClock; 1789 UCHAR ucTransmitterID; 1790 UCHAR ucEncodeMode; 1791 union 1792 { 1793 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 1794 UCHAR ucConfig; //if none DVO, not defined yet 1795 }; 1796 UCHAR ucReserved[3]; 1797 }ADJUST_DISPLAY_PLL_PARAMETERS; 1798 1799 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 1800 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 1801 1802 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 1803 { 1804 USHORT usPixelClock; // target pixel clock 1805 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 1806 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 1807 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 1808 UCHAR ucExtTransmitterID; // external encoder id. 1809 UCHAR ucReserved[2]; 1810 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 1811 1812 // usDispPllConfig v1.2 for RoadRunner 1813 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 1814 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 1815 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 1816 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 1817 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 1818 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 1819 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 1820 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 1821 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 1822 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 1823 1824 1825 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 1826 { 1827 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 1828 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 1829 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 1830 UCHAR ucReserved[2]; 1831 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 1832 1833 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 1834 { 1835 union 1836 { 1837 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 1838 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 1839 }; 1840 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 1841 1842 /****************************************************************************/ 1843 // Structures used by EnableYUVTable 1844 /****************************************************************************/ 1845 typedef struct _ENABLE_YUV_PARAMETERS 1846 { 1847 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 1848 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 1849 UCHAR ucPadding[2]; 1850 }ENABLE_YUV_PARAMETERS; 1851 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 1852 1853 /****************************************************************************/ 1854 // Structures used by GetMemoryClockTable 1855 /****************************************************************************/ 1856 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 1857 { 1858 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 1859 } GET_MEMORY_CLOCK_PARAMETERS; 1860 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 1861 1862 /****************************************************************************/ 1863 // Structures used by GetEngineClockTable 1864 /****************************************************************************/ 1865 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 1866 { 1867 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 1868 } GET_ENGINE_CLOCK_PARAMETERS; 1869 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 1870 1871 /****************************************************************************/ 1872 // Following Structures and constant may be obsolete 1873 /****************************************************************************/ 1874 //Maxium 8 bytes,the data read in will be placed in the parameter space. 1875 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 1876 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1877 { 1878 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1879 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 1880 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 1881 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 1882 UCHAR ucSlaveAddr; //Read from which slave 1883 UCHAR ucLineNumber; //Read from which HW assisted line 1884 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 1885 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 1886 1887 1888 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 1889 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 1890 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 1891 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 1892 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 1893 1894 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1895 { 1896 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1897 USHORT usByteOffset; //Write to which byte 1898 //Upper portion of usByteOffset is Format of data 1899 //1bytePS+offsetPS 1900 //2bytesPS+offsetPS 1901 //blockID+offsetPS 1902 //blockID+offsetID 1903 //blockID+counterID+offsetID 1904 UCHAR ucData; //PS data1 1905 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 1906 UCHAR ucSlaveAddr; //Write to which slave 1907 UCHAR ucLineNumber; //Write from which HW assisted line 1908 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 1909 1910 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1911 1912 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 1913 { 1914 USHORT usPrescale; //Ratio between Engine clock and I2C clock 1915 UCHAR ucSlaveAddr; //Write to which slave 1916 UCHAR ucLineNumber; //Write from which HW assisted line 1917 }SET_UP_HW_I2C_DATA_PARAMETERS; 1918 1919 /**************************************************************************/ 1920 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 1921 1922 1923 /****************************************************************************/ 1924 // Structures used by PowerConnectorDetectionTable 1925 /****************************************************************************/ 1926 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 1927 { 1928 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1929 UCHAR ucPwrBehaviorId; 1930 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1931 }POWER_CONNECTOR_DETECTION_PARAMETERS; 1932 1933 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 1934 { 1935 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 1936 UCHAR ucReserved; 1937 USHORT usPwrBudget; //how much power currently boot to in unit of watt 1938 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 1939 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 1940 1941 1942 /****************************LVDS SS Command Table Definitions**********************/ 1943 1944 /****************************************************************************/ 1945 // Structures used by EnableSpreadSpectrumOnPPLLTable 1946 /****************************************************************************/ 1947 typedef struct _ENABLE_LVDS_SS_PARAMETERS 1948 { 1949 USHORT usSpreadSpectrumPercentage; 1950 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1951 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 1952 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1953 UCHAR ucPadding[3]; 1954 }ENABLE_LVDS_SS_PARAMETERS; 1955 1956 //ucTableFormatRevision=1,ucTableContentRevision=2 1957 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 1958 { 1959 USHORT usSpreadSpectrumPercentage; 1960 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1961 UCHAR ucSpreadSpectrumStep; // 1962 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 1963 UCHAR ucSpreadSpectrumDelay; 1964 UCHAR ucSpreadSpectrumRange; 1965 UCHAR ucPadding; 1966 }ENABLE_LVDS_SS_PARAMETERS_V2; 1967 1968 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 1969 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 1970 { 1971 USHORT usSpreadSpectrumPercentage; 1972 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 1973 UCHAR ucSpreadSpectrumStep; // 1974 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1975 UCHAR ucSpreadSpectrumDelay; 1976 UCHAR ucSpreadSpectrumRange; 1977 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 1978 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 1979 1980 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 1981 { 1982 USHORT usSpreadSpectrumPercentage; 1983 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 1984 // Bit[1]: 1-Ext. 0-Int. 1985 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 1986 // Bits[7:4] reserved 1987 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1988 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 1989 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 1990 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 1991 1992 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 1993 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 1994 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 1995 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 1996 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 1997 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 1998 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 1999 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2000 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2001 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2002 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2003 2004 // Used by DCE5.0 2005 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2006 { 2007 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2008 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2009 // Bit[1]: 1-Ext. 0-Int. 2010 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2011 // Bits[7:4] reserved 2012 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2013 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2014 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2015 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2016 2017 2018 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2019 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2020 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2021 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2022 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2023 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2024 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2025 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2026 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2027 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2028 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2029 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2030 2031 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2032 2033 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2034 { 2035 PIXEL_CLOCK_PARAMETERS sPCLKInput; 2036 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2037 }SET_PIXEL_CLOCK_PS_ALLOCATION; 2038 2039 2040 2041 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2042 2043 /****************************************************************************/ 2044 // Structures used by ### 2045 /****************************************************************************/ 2046 typedef struct _MEMORY_TRAINING_PARAMETERS 2047 { 2048 ULONG ulTargetMemoryClock; //In 10Khz unit 2049 }MEMORY_TRAINING_PARAMETERS; 2050 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2051 2052 2053 typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2054 { 2055 USHORT usMemTrainingMode; 2056 USHORT usReserved; 2057 }MEMORY_TRAINING_PARAMETERS_V1_2; 2058 2059 //usMemTrainingMode 2060 #define NORMAL_MEMORY_TRAINING_MODE 0 2061 #define ENTER_DRAM_SELFREFRESH_MODE 1 2062 #define EXIT_DRAM_SELFRESH_MODE 2 2063 2064 /****************************LVDS and other encoder command table definitions **********************/ 2065 2066 2067 /****************************************************************************/ 2068 // Structures used by LVDSEncoderControlTable (Before DEC30) 2069 // LVTMAEncoderControlTable (Before DEC30) 2070 // TMDSAEncoderControlTable (Before DEC30) 2071 /****************************************************************************/ 2072 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2073 { 2074 USHORT usPixelClock; // in 10KHz; for bios convenient 2075 UCHAR ucMisc; // bit0=0: Enable single link 2076 // =1: Enable dual link 2077 // Bit1=0: 666RGB 2078 // =1: 888RGB 2079 UCHAR ucAction; // 0: turn off encoder 2080 // 1: setup and turn on encoder 2081 }LVDS_ENCODER_CONTROL_PARAMETERS; 2082 2083 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2084 2085 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2086 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2087 2088 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2089 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2090 2091 //ucTableFormatRevision=1,ucTableContentRevision=2 2092 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2093 { 2094 USHORT usPixelClock; // in 10KHz; for bios convenient 2095 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2096 UCHAR ucAction; // 0: turn off encoder 2097 // 1: setup and turn on encoder 2098 UCHAR ucTruncate; // bit0=0: Disable truncate 2099 // =1: Enable truncate 2100 // bit4=0: 666RGB 2101 // =1: 888RGB 2102 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2103 // =1: Enable spatial dithering 2104 // bit4=0: 666RGB 2105 // =1: 888RGB 2106 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2107 // =1: Enable temporal dithering 2108 // bit4=0: 666RGB 2109 // =1: 888RGB 2110 // bit5=0: Gray level 2 2111 // =1: Gray level 4 2112 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2113 // =1: 25FRC_SEL pattern F 2114 // bit6:5=0: 50FRC_SEL pattern A 2115 // =1: 50FRC_SEL pattern B 2116 // =2: 50FRC_SEL pattern C 2117 // =3: 50FRC_SEL pattern D 2118 // bit7=0: 75FRC_SEL pattern E 2119 // =1: 75FRC_SEL pattern F 2120 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2121 2122 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2123 2124 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2125 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2126 2127 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2128 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2129 2130 2131 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2132 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2133 2134 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2135 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2136 2137 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2138 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2139 2140 /****************************************************************************/ 2141 // Structures used by ### 2142 /****************************************************************************/ 2143 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2144 { 2145 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2146 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2147 UCHAR ucPadding[2]; 2148 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2149 2150 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2151 { 2152 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2153 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2154 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2155 2156 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2157 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2158 { 2159 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2160 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2161 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2162 2163 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2164 { 2165 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2166 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2167 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2168 2169 /****************************************************************************/ 2170 // Structures used by DVOEncoderControlTable 2171 /****************************************************************************/ 2172 //ucTableFormatRevision=1,ucTableContentRevision=3 2173 //ucDVOConfig: 2174 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2175 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2176 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2177 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2178 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2179 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2180 #define DVO_ENCODER_CONFIG_24BIT 0x08 2181 2182 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2183 { 2184 USHORT usPixelClock; 2185 UCHAR ucDVOConfig; 2186 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2187 UCHAR ucReseved[4]; 2188 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2189 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2190 2191 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2192 { 2193 USHORT usPixelClock; 2194 UCHAR ucDVOConfig; 2195 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2196 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2197 UCHAR ucReseved[3]; 2198 }DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2199 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2200 2201 2202 //ucTableFormatRevision=1 2203 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2204 // bit1=0: non-coherent mode 2205 // =1: coherent mode 2206 2207 //========================================================================================== 2208 //Only change is here next time when changing encoder parameter definitions again! 2209 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2210 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2211 2212 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2213 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2214 2215 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2216 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2217 2218 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2219 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2220 2221 //========================================================================================== 2222 #define PANEL_ENCODER_MISC_DUAL 0x01 2223 #define PANEL_ENCODER_MISC_COHERENT 0x02 2224 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2225 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2226 2227 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2228 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2229 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2230 2231 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2232 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2233 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2234 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2235 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2236 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2237 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2238 #define PANEL_ENCODER_25FRC_MASK 0x10 2239 #define PANEL_ENCODER_25FRC_E 0x00 2240 #define PANEL_ENCODER_25FRC_F 0x10 2241 #define PANEL_ENCODER_50FRC_MASK 0x60 2242 #define PANEL_ENCODER_50FRC_A 0x00 2243 #define PANEL_ENCODER_50FRC_B 0x20 2244 #define PANEL_ENCODER_50FRC_C 0x40 2245 #define PANEL_ENCODER_50FRC_D 0x60 2246 #define PANEL_ENCODER_75FRC_MASK 0x80 2247 #define PANEL_ENCODER_75FRC_E 0x00 2248 #define PANEL_ENCODER_75FRC_F 0x80 2249 2250 /****************************************************************************/ 2251 // Structures used by SetVoltageTable 2252 /****************************************************************************/ 2253 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2254 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2255 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2256 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2257 #define SET_VOLTAGE_INIT_MODE 5 2258 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2259 2260 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2261 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2262 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2263 2264 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2265 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2266 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2267 2268 typedef struct _SET_VOLTAGE_PARAMETERS 2269 { 2270 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2271 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2272 UCHAR ucVoltageIndex; // An index to tell which voltage level 2273 UCHAR ucReserved; 2274 }SET_VOLTAGE_PARAMETERS; 2275 2276 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2277 { 2278 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2279 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2280 USHORT usVoltageLevel; // real voltage level 2281 }SET_VOLTAGE_PARAMETERS_V2; 2282 2283 // used by both SetVoltageTable v1.3 and v1.4 2284 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2285 { 2286 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2287 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2288 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2289 }SET_VOLTAGE_PARAMETERS_V1_3; 2290 2291 //ucVoltageType 2292 #define VOLTAGE_TYPE_VDDC 1 2293 #define VOLTAGE_TYPE_MVDDC 2 2294 #define VOLTAGE_TYPE_MVDDQ 3 2295 #define VOLTAGE_TYPE_VDDCI 4 2296 #define VOLTAGE_TYPE_VDDGFX 5 2297 #define VOLTAGE_TYPE_PCC 6 2298 2299 #define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2300 #define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2301 #define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2302 #define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2303 #define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2304 #define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2305 #define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2306 #define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2307 #define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2308 #define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2309 2310 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2311 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2312 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2313 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2314 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2315 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2316 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2317 2318 // define vitual voltage id in usVoltageLevel 2319 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2320 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2321 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2322 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2323 #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2324 #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2325 #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2326 #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2327 2328 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2329 { 2330 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2331 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2332 }SET_VOLTAGE_PS_ALLOCATION; 2333 2334 // New Added from SI for GetVoltageInfoTable, input parameter structure 2335 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2336 { 2337 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2338 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2339 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2340 ULONG ulReserved; 2341 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2342 2343 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2344 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2345 { 2346 ULONG ulVotlageGpioState; 2347 ULONG ulVoltageGPioMask; 2348 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2349 2350 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2351 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2352 { 2353 USHORT usVoltageLevel; 2354 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2355 ULONG ulReseved; 2356 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2357 2358 // GetVoltageInfo v1.1 ucVoltageMode 2359 #define ATOM_GET_VOLTAGE_VID 0x00 2360 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2361 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2362 #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2363 2364 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2365 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2366 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2367 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2368 2369 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2370 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2371 2372 2373 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2374 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2375 { 2376 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2377 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2378 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2379 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2380 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2381 2382 // New in GetVoltageInfo v1.2 ucVoltageMode 2383 #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2384 2385 // New Added from CI Hawaii for EVV feature 2386 typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2387 { 2388 USHORT usVoltageLevel; // real voltage level in unit of mv 2389 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2390 USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2391 USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2392 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2393 2394 /****************************************************************************/ 2395 // Structures used by TVEncoderControlTable 2396 /****************************************************************************/ 2397 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2398 { 2399 USHORT usPixelClock; // in 10KHz; for bios convenient 2400 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2401 UCHAR ucAction; // 0: turn off encoder 2402 // 1: setup and turn on encoder 2403 }TV_ENCODER_CONTROL_PARAMETERS; 2404 2405 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2406 { 2407 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2408 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2409 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2410 2411 //==============================Data Table Portion==================================== 2412 2413 2414 /****************************************************************************/ 2415 // Structure used in Data.mtb 2416 /****************************************************************************/ 2417 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2418 { 2419 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2420 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2421 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2422 USHORT StandardVESA_Timing; // Only used by Bios 2423 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2424 USHORT PaletteData; // Only used by BIOS 2425 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2426 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2427 USHORT AnalogTV_Info; // Shared by various SW components,latest version 1.1 2428 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2429 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2430 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2431 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2432 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2433 USHORT ComponentVideoInfo; // Shared by various SW components,latest version 2.1 will be used from R600 2434 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2435 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2436 USHORT SaveRestoreInfo; // Only used by Bios 2437 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2438 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2439 USHORT XTMDS_Info; // Will be obsolete from R600 2440 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2441 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2442 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2443 USHORT MC_InitParameter; // Only used by command table 2444 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2445 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2446 USHORT TV_VideoMode; // Only used by command table 2447 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2448 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2449 USHORT IntegratedSystemInfo; // Shared by various SW components 2450 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2451 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2452 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2453 USHORT ServiceInfo; 2454 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2455 2456 typedef struct _ATOM_MASTER_DATA_TABLE 2457 { 2458 ATOM_COMMON_TABLE_HEADER sHeader; 2459 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2460 }ATOM_MASTER_DATA_TABLE; 2461 2462 // For backward compatible 2463 #define LVDS_Info LCD_Info 2464 #define DAC_Info PaletteData 2465 #define TMDS_Info DIGTransmitterInfo 2466 #define CompassionateData GPUVirtualizationInfo 2467 2468 /****************************************************************************/ 2469 // Structure used in MultimediaCapabilityInfoTable 2470 /****************************************************************************/ 2471 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2472 { 2473 ATOM_COMMON_TABLE_HEADER sHeader; 2474 ULONG ulSignature; // HW info table signature string "$ATI" 2475 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2476 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2477 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2478 UCHAR ucHostPortInfo; // Provides host port configuration information 2479 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2480 2481 2482 /****************************************************************************/ 2483 // Structure used in MultimediaConfigInfoTable 2484 /****************************************************************************/ 2485 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2486 { 2487 ATOM_COMMON_TABLE_HEADER sHeader; 2488 ULONG ulSignature; // MM info table signature sting "$MMT" 2489 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2490 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2491 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2492 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2493 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2494 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2495 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2496 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2497 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2498 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2499 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2500 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2501 }ATOM_MULTIMEDIA_CONFIG_INFO; 2502 2503 2504 /****************************************************************************/ 2505 // Structures used in FirmwareInfoTable 2506 /****************************************************************************/ 2507 2508 // usBIOSCapability Defintion: 2509 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2510 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2511 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2512 // Others: Reserved 2513 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2514 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2515 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2516 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2517 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2518 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2519 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2520 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2521 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2522 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2523 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2524 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2525 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2526 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2527 2528 2529 #ifndef _H2INC 2530 2531 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2532 typedef struct _ATOM_FIRMWARE_CAPABILITY 2533 { 2534 #if ATOM_BIG_ENDIAN 2535 USHORT Reserved:1; 2536 USHORT SCL2Redefined:1; 2537 USHORT PostWithoutModeSet:1; 2538 USHORT HyperMemory_Size:4; 2539 USHORT HyperMemory_Support:1; 2540 USHORT PPMode_Assigned:1; 2541 USHORT WMI_SUPPORT:1; 2542 USHORT GPUControlsBL:1; 2543 USHORT EngineClockSS_Support:1; 2544 USHORT MemoryClockSS_Support:1; 2545 USHORT ExtendedDesktopSupport:1; 2546 USHORT DualCRTC_Support:1; 2547 USHORT FirmwarePosted:1; 2548 #else 2549 USHORT FirmwarePosted:1; 2550 USHORT DualCRTC_Support:1; 2551 USHORT ExtendedDesktopSupport:1; 2552 USHORT MemoryClockSS_Support:1; 2553 USHORT EngineClockSS_Support:1; 2554 USHORT GPUControlsBL:1; 2555 USHORT WMI_SUPPORT:1; 2556 USHORT PPMode_Assigned:1; 2557 USHORT HyperMemory_Support:1; 2558 USHORT HyperMemory_Size:4; 2559 USHORT PostWithoutModeSet:1; 2560 USHORT SCL2Redefined:1; 2561 USHORT Reserved:1; 2562 #endif 2563 }ATOM_FIRMWARE_CAPABILITY; 2564 2565 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2566 { 2567 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2568 USHORT susAccess; 2569 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2570 2571 #else 2572 2573 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2574 { 2575 USHORT susAccess; 2576 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2577 2578 #endif 2579 2580 typedef struct _ATOM_FIRMWARE_INFO 2581 { 2582 ATOM_COMMON_TABLE_HEADER sHeader; 2583 ULONG ulFirmwareRevision; 2584 ULONG ulDefaultEngineClock; //In 10Khz unit 2585 ULONG ulDefaultMemoryClock; //In 10Khz unit 2586 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2587 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2588 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2589 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2590 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2591 ULONG ulASICMaxEngineClock; //In 10Khz unit 2592 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2593 UCHAR ucASICMaxTemperature; 2594 UCHAR ucPadding[3]; //Don't use them 2595 ULONG aulReservedForBIOS[3]; //Don't use them 2596 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2597 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2598 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2599 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2600 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2601 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2602 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2603 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2604 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2605 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2606 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2607 USHORT usReferenceClock; //In 10Khz unit 2608 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2609 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2610 UCHAR ucDesign_ID; //Indicate what is the board design 2611 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2612 }ATOM_FIRMWARE_INFO; 2613 2614 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2615 { 2616 ATOM_COMMON_TABLE_HEADER sHeader; 2617 ULONG ulFirmwareRevision; 2618 ULONG ulDefaultEngineClock; //In 10Khz unit 2619 ULONG ulDefaultMemoryClock; //In 10Khz unit 2620 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2621 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2622 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2623 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2624 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2625 ULONG ulASICMaxEngineClock; //In 10Khz unit 2626 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2627 UCHAR ucASICMaxTemperature; 2628 UCHAR ucMinAllowedBL_Level; 2629 UCHAR ucPadding[2]; //Don't use them 2630 ULONG aulReservedForBIOS[2]; //Don't use them 2631 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2632 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2633 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2634 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2635 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2636 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2637 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2638 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2639 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2640 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2641 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2642 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2643 USHORT usReferenceClock; //In 10Khz unit 2644 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2645 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2646 UCHAR ucDesign_ID; //Indicate what is the board design 2647 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2648 }ATOM_FIRMWARE_INFO_V1_2; 2649 2650 typedef struct _ATOM_FIRMWARE_INFO_V1_3 2651 { 2652 ATOM_COMMON_TABLE_HEADER sHeader; 2653 ULONG ulFirmwareRevision; 2654 ULONG ulDefaultEngineClock; //In 10Khz unit 2655 ULONG ulDefaultMemoryClock; //In 10Khz unit 2656 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2657 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2658 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2659 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2660 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2661 ULONG ulASICMaxEngineClock; //In 10Khz unit 2662 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2663 UCHAR ucASICMaxTemperature; 2664 UCHAR ucMinAllowedBL_Level; 2665 UCHAR ucPadding[2]; //Don't use them 2666 ULONG aulReservedForBIOS; //Don't use them 2667 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2668 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2669 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2670 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2671 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2672 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2673 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2674 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2675 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2676 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2677 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2678 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2679 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2680 USHORT usReferenceClock; //In 10Khz unit 2681 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2682 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2683 UCHAR ucDesign_ID; //Indicate what is the board design 2684 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2685 }ATOM_FIRMWARE_INFO_V1_3; 2686 2687 typedef struct _ATOM_FIRMWARE_INFO_V1_4 2688 { 2689 ATOM_COMMON_TABLE_HEADER sHeader; 2690 ULONG ulFirmwareRevision; 2691 ULONG ulDefaultEngineClock; //In 10Khz unit 2692 ULONG ulDefaultMemoryClock; //In 10Khz unit 2693 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2694 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2695 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2696 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2697 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2698 ULONG ulASICMaxEngineClock; //In 10Khz unit 2699 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2700 UCHAR ucASICMaxTemperature; 2701 UCHAR ucMinAllowedBL_Level; 2702 USHORT usBootUpVDDCVoltage; //In MV unit 2703 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2704 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2705 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 2706 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2707 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2708 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2709 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2710 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2711 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2712 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2713 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2714 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2715 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2716 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2717 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2718 USHORT usReferenceClock; //In 10Khz unit 2719 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2720 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2721 UCHAR ucDesign_ID; //Indicate what is the board design 2722 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2723 }ATOM_FIRMWARE_INFO_V1_4; 2724 2725 //the structure below to be used from Cypress 2726 typedef struct _ATOM_FIRMWARE_INFO_V2_1 2727 { 2728 ATOM_COMMON_TABLE_HEADER sHeader; 2729 ULONG ulFirmwareRevision; 2730 ULONG ulDefaultEngineClock; //In 10Khz unit 2731 ULONG ulDefaultMemoryClock; //In 10Khz unit 2732 ULONG ulReserved1; 2733 ULONG ulReserved2; 2734 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2735 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2736 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2737 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 2738 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 2739 UCHAR ucReserved1; //Was ucASICMaxTemperature; 2740 UCHAR ucMinAllowedBL_Level; 2741 USHORT usBootUpVDDCVoltage; //In MV unit 2742 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2743 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2744 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2745 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2746 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2747 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2748 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2749 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2750 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2751 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2752 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2753 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2754 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2755 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 2756 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2757 USHORT usCoreReferenceClock; //In 10Khz unit 2758 USHORT usMemoryReferenceClock; //In 10Khz unit 2759 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2760 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2761 UCHAR ucReserved4[3]; 2762 2763 }ATOM_FIRMWARE_INFO_V2_1; 2764 2765 //the structure below to be used from NI 2766 //ucTableFormatRevision=2 2767 //ucTableContentRevision=2 2768 2769 typedef struct _PRODUCT_BRANDING 2770 { 2771 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 2772 UCHAR ucReserved:2; // Bit[3:2] Reserved 2773 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 2774 }PRODUCT_BRANDING; 2775 2776 typedef struct _ATOM_FIRMWARE_INFO_V2_2 2777 { 2778 ATOM_COMMON_TABLE_HEADER sHeader; 2779 ULONG ulFirmwareRevision; 2780 ULONG ulDefaultEngineClock; //In 10Khz unit 2781 ULONG ulDefaultMemoryClock; //In 10Khz unit 2782 ULONG ulSPLL_OutputFreq; //In 10Khz unit 2783 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 2784 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 2785 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 2786 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2787 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 2788 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 2789 UCHAR ucReserved3; //Was ucASICMaxTemperature; 2790 UCHAR ucMinAllowedBL_Level; 2791 USHORT usBootUpVDDCVoltage; //In MV unit 2792 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 2793 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 2794 ULONG ulReserved4; //Was ulAsicMaximumVoltage 2795 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 2796 UCHAR ucRemoteDisplayConfig; 2797 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 2798 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 2799 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 2800 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 2801 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2802 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2803 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2804 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2805 USHORT usCoreReferenceClock; //In 10Khz unit 2806 USHORT usMemoryReferenceClock; //In 10Khz unit 2807 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 2808 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2809 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 2810 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 2811 UCHAR ucReserved9; 2812 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 2813 USHORT usBootUpVDDGFXVoltage; //In unit of mv; 2814 ULONG ulReserved10[3]; // New added comparing to previous version 2815 }ATOM_FIRMWARE_INFO_V2_2; 2816 2817 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 2818 2819 2820 // definition of ucRemoteDisplayConfig 2821 #define REMOTE_DISPLAY_DISABLE 0x00 2822 #define REMOTE_DISPLAY_ENABLE 0x01 2823 2824 /****************************************************************************/ 2825 // Structures used in IntegratedSystemInfoTable 2826 /****************************************************************************/ 2827 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 2828 #define IGP_CAP_FLAG_AC_CARD 0x4 2829 #define IGP_CAP_FLAG_SDVO_CARD 0x8 2830 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 2831 2832 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 2833 { 2834 ATOM_COMMON_TABLE_HEADER sHeader; 2835 ULONG ulBootUpEngineClock; //in 10kHz unit 2836 ULONG ulBootUpMemoryClock; //in 10kHz unit 2837 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 2838 ULONG ulMinSystemMemoryClock; //in 10kHz unit 2839 UCHAR ucNumberOfCyclesInPeriodHi; 2840 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 2841 USHORT usReserved1; 2842 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 2843 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 2844 ULONG ulReserved[2]; 2845 2846 USHORT usFSBClock; //In MHz unit 2847 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 2848 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 2849 //Bit[4]==1: P/2 mode, ==0: P/1 mode 2850 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 2851 USHORT usK8MemoryClock; //in MHz unit 2852 USHORT usK8SyncStartDelay; //in 0.01 us unit 2853 USHORT usK8DataReturnTime; //in 0.01 us unit 2854 UCHAR ucMaxNBVoltage; 2855 UCHAR ucMinNBVoltage; 2856 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 2857 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 2858 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 2859 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 2860 UCHAR ucMaxNBVoltageHigh; 2861 UCHAR ucMinNBVoltageHigh; 2862 }ATOM_INTEGRATED_SYSTEM_INFO; 2863 2864 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 2865 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 2866 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 2867 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2868 For AMD IGP,for now this can be 0 2869 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 2870 For AMD IGP,for now this can be 0 2871 2872 usFSBClock: For Intel IGP,it's FSB Freq 2873 For AMD IGP,it's HT Link Speed 2874 2875 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 2876 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2877 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 2878 2879 VC:Voltage Control 2880 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2881 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2882 2883 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 2884 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 2885 2886 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 2887 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 2888 2889 2890 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 2891 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 2892 */ 2893 2894 2895 /* 2896 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 2897 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 2898 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 2899 2900 SW components can access the IGP system infor structure in the same way as before 2901 */ 2902 2903 2904 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 2905 { 2906 ATOM_COMMON_TABLE_HEADER sHeader; 2907 ULONG ulBootUpEngineClock; //in 10kHz unit 2908 ULONG ulReserved1[2]; //must be 0x0 for the reserved 2909 ULONG ulBootUpUMAClock; //in 10kHz unit 2910 ULONG ulBootUpSidePortClock; //in 10kHz unit 2911 ULONG ulMinSidePortClock; //in 10kHz unit 2912 ULONG ulReserved2[6]; //must be 0x0 for the reserved 2913 ULONG ulSystemConfig; //see explanation below 2914 ULONG ulBootUpReqDisplayVector; 2915 ULONG ulOtherDisplayMisc; 2916 ULONG ulDDISlot1Config; 2917 ULONG ulDDISlot2Config; 2918 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 2919 UCHAR ucUMAChannelNumber; 2920 UCHAR ucDockingPinBit; 2921 UCHAR ucDockingPinPolarity; 2922 ULONG ulDockingPinCFGInfo; 2923 ULONG ulCPUCapInfo; 2924 USHORT usNumberOfCyclesInPeriod; 2925 USHORT usMaxNBVoltage; 2926 USHORT usMinNBVoltage; 2927 USHORT usBootUpNBVoltage; 2928 ULONG ulHTLinkFreq; //in 10Khz 2929 USHORT usMinHTLinkWidth; 2930 USHORT usMaxHTLinkWidth; 2931 USHORT usUMASyncStartDelay; 2932 USHORT usUMADataReturnTime; 2933 USHORT usLinkStatusZeroTime; 2934 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 2935 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 2936 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 2937 USHORT usMaxUpStreamHTLinkWidth; 2938 USHORT usMaxDownStreamHTLinkWidth; 2939 USHORT usMinUpStreamHTLinkWidth; 2940 USHORT usMinDownStreamHTLinkWidth; 2941 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 2942 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 2943 ULONG ulReserved3[96]; //must be 0x0 2944 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 2945 2946 /* 2947 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 2948 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 2949 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 2950 2951 ulSystemConfig: 2952 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 2953 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 2954 =0: system boots up at driver control state. Power state depends on PowerPlay table. 2955 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 2956 Bit[3]=1: Only one power state(Performance) will be supported. 2957 =0: Multiple power states supported from PowerPlay table. 2958 Bit[4]=1: CLMC is supported and enabled on current system. 2959 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 2960 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 2961 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 2962 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 2963 =0: Voltage settings is determined by powerplay table. 2964 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 2965 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 2966 Bit[8]=1: CDLF is supported and enabled on current system. 2967 =0: CDLF is not supported or enabled on current system. 2968 Bit[9]=1: DLL Shut Down feature is enabled on current system. 2969 =0: DLL Shut Down feature is not enabled or supported on current system. 2970 2971 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 2972 2973 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 2974 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 2975 2976 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 2977 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 2978 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 2979 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 2980 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 2981 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 2982 2983 [15:8] - Lane configuration attribute; 2984 [23:16]- Connector type, possible value: 2985 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 2986 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 2987 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 2988 CONNECTOR_OBJECT_ID_DISPLAYPORT 2989 CONNECTOR_OBJECT_ID_eDP 2990 [31:24]- Reserved 2991 2992 ulDDISlot2Config: Same as Slot1. 2993 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 2994 For IGP, Hypermemory is the only memory type showed in CCC. 2995 2996 ucUMAChannelNumber: how many channels for the UMA; 2997 2998 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 2999 ucDockingPinBit: which bit in this register to read the pin status; 3000 ucDockingPinPolarity:Polarity of the pin when docked; 3001 3002 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3003 3004 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3005 3006 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3007 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3008 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3009 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3010 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3011 3012 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3013 3014 3015 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3016 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3017 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3018 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3019 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3020 3021 usUMASyncStartDelay: Memory access latency, required for watermark calculation 3022 usUMADataReturnTime: Memory access latency, required for watermark calculation 3023 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3024 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3025 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3026 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3027 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3028 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3029 3030 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3031 This must be less than or equal to ulHTLinkFreq(bootup frequency). 3032 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3033 This must be less than or equal to ulHighVoltageHTLinkFreq. 3034 3035 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3036 usMaxDownStreamHTLinkWidth: same as above. 3037 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3038 usMinDownStreamHTLinkWidth: same as above. 3039 */ 3040 3041 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3042 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3043 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3044 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3045 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3046 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3047 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3048 3049 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3050 3051 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3052 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3053 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3054 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3055 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3056 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3057 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3058 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3059 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3060 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3061 3062 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3063 3064 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3065 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3066 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3067 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3068 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3069 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3070 3071 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3072 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3073 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3074 3075 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3076 3077 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3078 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3079 { 3080 ATOM_COMMON_TABLE_HEADER sHeader; 3081 ULONG ulBootUpEngineClock; //in 10kHz unit 3082 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3083 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3084 ULONG ulBootUpUMAClock; //in 10kHz unit 3085 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3086 ULONG ulBootUpReqDisplayVector; 3087 ULONG ulOtherDisplayMisc; 3088 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3089 ULONG ulSystemConfig; //TBD 3090 ULONG ulCPUCapInfo; //TBD 3091 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3092 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3093 USHORT usBootUpNBVoltage; //boot up NB voltage 3094 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3095 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3096 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3097 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3098 ULONG ulDDISlot2Config; 3099 ULONG ulDDISlot3Config; 3100 ULONG ulDDISlot4Config; 3101 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3102 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3103 UCHAR ucUMAChannelNumber; 3104 USHORT usReserved; 3105 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3106 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3107 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3108 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3109 ULONG ulReserved6[61]; //must be 0x0 3110 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 3111 3112 3113 3114 /****************************************************************************/ 3115 // Structure used in GPUVirtualizationInfoTable 3116 /****************************************************************************/ 3117 typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3118 { 3119 ATOM_COMMON_TABLE_HEADER sHeader; 3120 ULONG ulMCUcodeRomStartAddr; 3121 ULONG ulMCUcodeLength; 3122 ULONG ulSMCUcodeRomStartAddr; 3123 ULONG ulSMCUcodeLength; 3124 ULONG ulRLCVUcodeRomStartAddr; 3125 ULONG ulRLCVUcodeLength; 3126 ULONG ulTOCUcodeStartAddr; 3127 ULONG ulTOCUcodeLength; 3128 ULONG ulSMCPatchTableStartAddr; 3129 ULONG ulSmcPatchTableLength; 3130 ULONG ulSystemFlag; 3131 }ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3132 3133 3134 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3135 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3136 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3137 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3138 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3139 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3140 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3141 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3142 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3143 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3144 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3145 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3146 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3147 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3148 3149 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3150 #define ASIC_INT_DAC1_ENCODER_ID 0x00 3151 #define ASIC_INT_TV_ENCODER_ID 0x02 3152 #define ASIC_INT_DIG1_ENCODER_ID 0x03 3153 #define ASIC_INT_DAC2_ENCODER_ID 0x04 3154 #define ASIC_EXT_TV_ENCODER_ID 0x06 3155 #define ASIC_INT_DVO_ENCODER_ID 0x07 3156 #define ASIC_INT_DIG2_ENCODER_ID 0x09 3157 #define ASIC_EXT_DIG_ENCODER_ID 0x05 3158 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 3159 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 3160 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 3161 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 3162 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 3163 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 3164 3165 //define Encoder attribute 3166 #define ATOM_ANALOG_ENCODER 0 3167 #define ATOM_DIGITAL_ENCODER 1 3168 #define ATOM_DP_ENCODER 2 3169 3170 #define ATOM_ENCODER_ENUM_MASK 0x70 3171 #define ATOM_ENCODER_ENUM_ID1 0x00 3172 #define ATOM_ENCODER_ENUM_ID2 0x10 3173 #define ATOM_ENCODER_ENUM_ID3 0x20 3174 #define ATOM_ENCODER_ENUM_ID4 0x30 3175 #define ATOM_ENCODER_ENUM_ID5 0x40 3176 #define ATOM_ENCODER_ENUM_ID6 0x50 3177 3178 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3179 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3180 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3181 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3182 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3183 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3184 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3185 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3186 #define ATOM_DEVICE_CV_INDEX 0x00000008 3187 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3188 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3189 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3190 3191 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3192 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3193 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3194 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3195 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3196 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3197 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3198 3199 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3200 3201 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3202 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3203 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3204 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3205 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3206 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3207 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3208 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3209 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3210 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3211 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3212 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3213 3214 3215 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3216 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3217 #define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3218 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3219 3220 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3221 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3222 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3223 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3224 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3225 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3226 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3227 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3228 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3229 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3230 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3231 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3232 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3233 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3234 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3235 3236 3237 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3238 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3239 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3240 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3241 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3242 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3243 3244 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3245 3246 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3247 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3248 3249 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3250 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3251 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3252 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3253 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3254 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3255 3256 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3257 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3258 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3259 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3260 3261 // usDeviceSupport: 3262 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3263 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3264 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3265 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3266 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3267 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3268 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3269 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3270 // Bit 8 = 0 - no CV support= 1- CV is supported 3271 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3272 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3273 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3274 // 3275 // 3276 3277 /****************************************************************************/ 3278 // Structure used in MclkSS_InfoTable 3279 /****************************************************************************/ 3280 // ucI2C_ConfigID 3281 // [7:0] - I2C LINE Associate ID 3282 // = 0 - no I2C 3283 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3284 // = 0, [6:0]=SW assisted I2C ID 3285 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3286 // = 2, HW engine for Multimedia use 3287 // = 3-7 Reserved for future I2C engines 3288 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3289 3290 typedef struct _ATOM_I2C_ID_CONFIG 3291 { 3292 #if ATOM_BIG_ENDIAN 3293 UCHAR bfHW_Capable:1; 3294 UCHAR bfHW_EngineID:3; 3295 UCHAR bfI2C_LineMux:4; 3296 #else 3297 UCHAR bfI2C_LineMux:4; 3298 UCHAR bfHW_EngineID:3; 3299 UCHAR bfHW_Capable:1; 3300 #endif 3301 }ATOM_I2C_ID_CONFIG; 3302 3303 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3304 { 3305 ATOM_I2C_ID_CONFIG sbfAccess; 3306 UCHAR ucAccess; 3307 }ATOM_I2C_ID_CONFIG_ACCESS; 3308 3309 3310 /****************************************************************************/ 3311 // Structure used in GPIO_I2C_InfoTable 3312 /****************************************************************************/ 3313 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3314 { 3315 USHORT usClkMaskRegisterIndex; 3316 USHORT usClkEnRegisterIndex; 3317 USHORT usClkY_RegisterIndex; 3318 USHORT usClkA_RegisterIndex; 3319 USHORT usDataMaskRegisterIndex; 3320 USHORT usDataEnRegisterIndex; 3321 USHORT usDataY_RegisterIndex; 3322 USHORT usDataA_RegisterIndex; 3323 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3324 UCHAR ucClkMaskShift; 3325 UCHAR ucClkEnShift; 3326 UCHAR ucClkY_Shift; 3327 UCHAR ucClkA_Shift; 3328 UCHAR ucDataMaskShift; 3329 UCHAR ucDataEnShift; 3330 UCHAR ucDataY_Shift; 3331 UCHAR ucDataA_Shift; 3332 UCHAR ucReserved1; 3333 UCHAR ucReserved2; 3334 }ATOM_GPIO_I2C_ASSIGMENT; 3335 3336 typedef struct _ATOM_GPIO_I2C_INFO 3337 { 3338 ATOM_COMMON_TABLE_HEADER sHeader; 3339 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3340 }ATOM_GPIO_I2C_INFO; 3341 3342 /****************************************************************************/ 3343 // Common Structure used in other structures 3344 /****************************************************************************/ 3345 3346 #ifndef _H2INC 3347 3348 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3349 typedef struct _ATOM_MODE_MISC_INFO 3350 { 3351 #if ATOM_BIG_ENDIAN 3352 USHORT Reserved:6; 3353 USHORT RGB888:1; 3354 USHORT DoubleClock:1; 3355 USHORT Interlace:1; 3356 USHORT CompositeSync:1; 3357 USHORT V_ReplicationBy2:1; 3358 USHORT H_ReplicationBy2:1; 3359 USHORT VerticalCutOff:1; 3360 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3361 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3362 USHORT HorizontalCutOff:1; 3363 #else 3364 USHORT HorizontalCutOff:1; 3365 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3366 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3367 USHORT VerticalCutOff:1; 3368 USHORT H_ReplicationBy2:1; 3369 USHORT V_ReplicationBy2:1; 3370 USHORT CompositeSync:1; 3371 USHORT Interlace:1; 3372 USHORT DoubleClock:1; 3373 USHORT RGB888:1; 3374 USHORT Reserved:6; 3375 #endif 3376 }ATOM_MODE_MISC_INFO; 3377 3378 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3379 { 3380 ATOM_MODE_MISC_INFO sbfAccess; 3381 USHORT usAccess; 3382 }ATOM_MODE_MISC_INFO_ACCESS; 3383 3384 #else 3385 3386 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3387 { 3388 USHORT usAccess; 3389 }ATOM_MODE_MISC_INFO_ACCESS; 3390 3391 #endif 3392 3393 // usModeMiscInfo- 3394 #define ATOM_H_CUTOFF 0x01 3395 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3396 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3397 #define ATOM_V_CUTOFF 0x08 3398 #define ATOM_H_REPLICATIONBY2 0x10 3399 #define ATOM_V_REPLICATIONBY2 0x20 3400 #define ATOM_COMPOSITESYNC 0x40 3401 #define ATOM_INTERLACE 0x80 3402 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3403 #define ATOM_RGB888_MODE 0x200 3404 3405 //usRefreshRate- 3406 #define ATOM_REFRESH_43 43 3407 #define ATOM_REFRESH_47 47 3408 #define ATOM_REFRESH_56 56 3409 #define ATOM_REFRESH_60 60 3410 #define ATOM_REFRESH_65 65 3411 #define ATOM_REFRESH_70 70 3412 #define ATOM_REFRESH_72 72 3413 #define ATOM_REFRESH_75 75 3414 #define ATOM_REFRESH_85 85 3415 3416 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3417 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3418 // 3419 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3420 // = EDID_HA + EDID_HBL 3421 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3422 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3423 // = EDID_HA + EDID_HSO 3424 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3425 // VESA_BORDER = EDID_BORDER 3426 3427 3428 /****************************************************************************/ 3429 // Structure used in SetCRTC_UsingDTDTimingTable 3430 /****************************************************************************/ 3431 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3432 { 3433 USHORT usH_Size; 3434 USHORT usH_Blanking_Time; 3435 USHORT usV_Size; 3436 USHORT usV_Blanking_Time; 3437 USHORT usH_SyncOffset; 3438 USHORT usH_SyncWidth; 3439 USHORT usV_SyncOffset; 3440 USHORT usV_SyncWidth; 3441 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3442 UCHAR ucH_Border; // From DFP EDID 3443 UCHAR ucV_Border; 3444 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3445 UCHAR ucPadding[3]; 3446 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3447 3448 /****************************************************************************/ 3449 // Structure used in SetCRTC_TimingTable 3450 /****************************************************************************/ 3451 typedef struct _SET_CRTC_TIMING_PARAMETERS 3452 { 3453 USHORT usH_Total; // horizontal total 3454 USHORT usH_Disp; // horizontal display 3455 USHORT usH_SyncStart; // horozontal Sync start 3456 USHORT usH_SyncWidth; // horizontal Sync width 3457 USHORT usV_Total; // vertical total 3458 USHORT usV_Disp; // vertical display 3459 USHORT usV_SyncStart; // vertical Sync start 3460 USHORT usV_SyncWidth; // vertical Sync width 3461 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3462 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3463 UCHAR ucOverscanRight; // right 3464 UCHAR ucOverscanLeft; // left 3465 UCHAR ucOverscanBottom; // bottom 3466 UCHAR ucOverscanTop; // top 3467 UCHAR ucReserved; 3468 }SET_CRTC_TIMING_PARAMETERS; 3469 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3470 3471 3472 /****************************************************************************/ 3473 // Structure used in StandardVESA_TimingTable 3474 // AnalogTV_InfoTable 3475 // ComponentVideoInfoTable 3476 /****************************************************************************/ 3477 typedef struct _ATOM_MODE_TIMING 3478 { 3479 USHORT usCRTC_H_Total; 3480 USHORT usCRTC_H_Disp; 3481 USHORT usCRTC_H_SyncStart; 3482 USHORT usCRTC_H_SyncWidth; 3483 USHORT usCRTC_V_Total; 3484 USHORT usCRTC_V_Disp; 3485 USHORT usCRTC_V_SyncStart; 3486 USHORT usCRTC_V_SyncWidth; 3487 USHORT usPixelClock; //in 10Khz unit 3488 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3489 USHORT usCRTC_OverscanRight; 3490 USHORT usCRTC_OverscanLeft; 3491 USHORT usCRTC_OverscanBottom; 3492 USHORT usCRTC_OverscanTop; 3493 USHORT usReserve; 3494 UCHAR ucInternalModeNumber; 3495 UCHAR ucRefreshRate; 3496 }ATOM_MODE_TIMING; 3497 3498 typedef struct _ATOM_DTD_FORMAT 3499 { 3500 USHORT usPixClk; 3501 USHORT usHActive; 3502 USHORT usHBlanking_Time; 3503 USHORT usVActive; 3504 USHORT usVBlanking_Time; 3505 USHORT usHSyncOffset; 3506 USHORT usHSyncWidth; 3507 USHORT usVSyncOffset; 3508 USHORT usVSyncWidth; 3509 USHORT usImageHSize; 3510 USHORT usImageVSize; 3511 UCHAR ucHBorder; 3512 UCHAR ucVBorder; 3513 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3514 UCHAR ucInternalModeNumber; 3515 UCHAR ucRefreshRate; 3516 }ATOM_DTD_FORMAT; 3517 3518 /****************************************************************************/ 3519 // Structure used in LVDS_InfoTable 3520 // * Need a document to describe this table 3521 /****************************************************************************/ 3522 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3523 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3524 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3525 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3526 #define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3527 3528 //ucTableFormatRevision=1 3529 //ucTableContentRevision=1 3530 typedef struct _ATOM_LVDS_INFO 3531 { 3532 ATOM_COMMON_TABLE_HEADER sHeader; 3533 ATOM_DTD_FORMAT sLCDTiming; 3534 USHORT usModePatchTableOffset; 3535 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3536 USHORT usOffDelayInMs; 3537 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3538 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3539 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3540 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3541 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3542 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3543 UCHAR ucPanelDefaultRefreshRate; 3544 UCHAR ucPanelIdentification; 3545 UCHAR ucSS_Id; 3546 }ATOM_LVDS_INFO; 3547 3548 //ucTableFormatRevision=1 3549 //ucTableContentRevision=2 3550 typedef struct _ATOM_LVDS_INFO_V12 3551 { 3552 ATOM_COMMON_TABLE_HEADER sHeader; 3553 ATOM_DTD_FORMAT sLCDTiming; 3554 USHORT usExtInfoTableOffset; 3555 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3556 USHORT usOffDelayInMs; 3557 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3558 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3559 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3560 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3561 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3562 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3563 UCHAR ucPanelDefaultRefreshRate; 3564 UCHAR ucPanelIdentification; 3565 UCHAR ucSS_Id; 3566 USHORT usLCDVenderID; 3567 USHORT usLCDProductID; 3568 UCHAR ucLCDPanel_SpecialHandlingCap; 3569 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3570 UCHAR ucReserved[2]; 3571 }ATOM_LVDS_INFO_V12; 3572 3573 //Definitions for ucLCDPanel_SpecialHandlingCap: 3574 3575 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3576 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3577 #define LCDPANEL_CAP_READ_EDID 0x1 3578 3579 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3580 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3581 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3582 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3583 3584 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3585 #define LCDPANEL_CAP_eDP 0x4 3586 3587 3588 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3589 //Bit 6 5 4 3590 // 0 0 0 - Color bit depth is undefined 3591 // 0 0 1 - 6 Bits per Primary Color 3592 // 0 1 0 - 8 Bits per Primary Color 3593 // 0 1 1 - 10 Bits per Primary Color 3594 // 1 0 0 - 12 Bits per Primary Color 3595 // 1 0 1 - 14 Bits per Primary Color 3596 // 1 1 0 - 16 Bits per Primary Color 3597 // 1 1 1 - Reserved 3598 3599 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3600 3601 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3602 #define PANEL_RANDOM_DITHER 0x80 3603 #define PANEL_RANDOM_DITHER_MASK 0x80 3604 3605 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3606 3607 3608 typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3609 { 3610 UCHAR ucSupportedRefreshRate; 3611 UCHAR ucMinRefreshRateForDRR; 3612 }ATOM_LCD_REFRESH_RATE_SUPPORT; 3613 3614 /****************************************************************************/ 3615 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3616 // ASIC Families: NI 3617 // ucTableFormatRevision=1 3618 // ucTableContentRevision=3 3619 /****************************************************************************/ 3620 typedef struct _ATOM_LCD_INFO_V13 3621 { 3622 ATOM_COMMON_TABLE_HEADER sHeader; 3623 ATOM_DTD_FORMAT sLCDTiming; 3624 USHORT usExtInfoTableOffset; 3625 union 3626 { 3627 USHORT usSupportedRefreshRate; 3628 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 3629 }; 3630 ULONG ulReserved0; 3631 UCHAR ucLCD_Misc; // Reorganized in V13 3632 // Bit0: {=0:single, =1:dual}, 3633 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 3634 // Bit3:2: {Grey level} 3635 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 3636 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 3637 UCHAR ucPanelDefaultRefreshRate; 3638 UCHAR ucPanelIdentification; 3639 UCHAR ucSS_Id; 3640 USHORT usLCDVenderID; 3641 USHORT usLCDProductID; 3642 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 3643 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 3644 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 3645 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 3646 // Bit7-3: Reserved 3647 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3648 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 3649 3650 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 3651 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 3652 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 3653 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 3654 3655 UCHAR ucOffDelay_in4Ms; 3656 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 3657 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 3658 UCHAR ucReserved1; 3659 3660 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 3661 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 3662 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 3663 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 3664 3665 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 3666 UCHAR uceDPToLVDSRxId; 3667 UCHAR ucLcdReservd; 3668 ULONG ulReserved[2]; 3669 }ATOM_LCD_INFO_V13; 3670 3671 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 3672 3673 //Definitions for ucLCD_Misc 3674 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 3675 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 3676 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 3677 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 3678 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 3679 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 3680 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 3681 3682 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3683 //Bit 6 5 4 3684 // 0 0 0 - Color bit depth is undefined 3685 // 0 0 1 - 6 Bits per Primary Color 3686 // 0 1 0 - 8 Bits per Primary Color 3687 // 0 1 1 - 10 Bits per Primary Color 3688 // 1 0 0 - 12 Bits per Primary Color 3689 // 1 0 1 - 14 Bits per Primary Color 3690 // 1 1 0 - 16 Bits per Primary Color 3691 // 1 1 1 - Reserved 3692 3693 //Definitions for ucLCDPanel_SpecialHandlingCap: 3694 3695 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3696 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3697 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 3698 3699 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3700 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3701 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3702 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 3703 3704 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3705 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 3706 3707 //uceDPToLVDSRxId 3708 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 3709 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 3710 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 3711 3712 typedef struct _ATOM_PATCH_RECORD_MODE 3713 { 3714 UCHAR ucRecordType; 3715 USHORT usHDisp; 3716 USHORT usVDisp; 3717 }ATOM_PATCH_RECORD_MODE; 3718 3719 typedef struct _ATOM_LCD_RTS_RECORD 3720 { 3721 UCHAR ucRecordType; 3722 UCHAR ucRTSValue; 3723 }ATOM_LCD_RTS_RECORD; 3724 3725 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 3726 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 3727 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 3728 { 3729 UCHAR ucRecordType; 3730 USHORT usLCDCap; 3731 }ATOM_LCD_MODE_CONTROL_CAP; 3732 3733 #define LCD_MODE_CAP_BL_OFF 1 3734 #define LCD_MODE_CAP_CRTC_OFF 2 3735 #define LCD_MODE_CAP_PANEL_OFF 4 3736 3737 3738 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 3739 { 3740 UCHAR ucRecordType; 3741 UCHAR ucFakeEDIDLength; // = 128 means EDID lenght is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 3742 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 3743 } ATOM_FAKE_EDID_PATCH_RECORD; 3744 3745 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 3746 { 3747 UCHAR ucRecordType; 3748 USHORT usHSize; 3749 USHORT usVSize; 3750 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 3751 3752 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 3753 #define LCD_RTS_RECORD_TYPE 2 3754 #define LCD_CAP_RECORD_TYPE 3 3755 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 3756 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 3757 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 3758 #define ATOM_RECORD_END_TYPE 0xFF 3759 3760 /****************************Spread Spectrum Info Table Definitions **********************/ 3761 3762 //ucTableFormatRevision=1 3763 //ucTableContentRevision=2 3764 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 3765 { 3766 USHORT usSpreadSpectrumPercentage; 3767 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 3768 UCHAR ucSS_Step; 3769 UCHAR ucSS_Delay; 3770 UCHAR ucSS_Id; 3771 UCHAR ucRecommendedRef_Div; 3772 UCHAR ucSS_Range; //it was reserved for V11 3773 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 3774 3775 #define ATOM_MAX_SS_ENTRY 16 3776 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 3777 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 3778 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 3779 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 3780 3781 3782 3783 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 3784 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 3785 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 3786 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 3787 #define ATOM_INTERNAL_SS_MASK 0x00000000 3788 #define ATOM_EXTERNAL_SS_MASK 0x00000002 3789 #define EXEC_SS_STEP_SIZE_SHIFT 2 3790 #define EXEC_SS_DELAY_SHIFT 4 3791 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 3792 3793 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 3794 { 3795 ATOM_COMMON_TABLE_HEADER sHeader; 3796 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 3797 }ATOM_SPREAD_SPECTRUM_INFO; 3798 3799 3800 /****************************************************************************/ 3801 // Structure used in AnalogTV_InfoTable (Top level) 3802 /****************************************************************************/ 3803 //ucTVBootUpDefaultStd definiton: 3804 3805 //ATOM_TV_NTSC 1 3806 //ATOM_TV_NTSCJ 2 3807 //ATOM_TV_PAL 3 3808 //ATOM_TV_PALM 4 3809 //ATOM_TV_PALCN 5 3810 //ATOM_TV_PALN 6 3811 //ATOM_TV_PAL60 7 3812 //ATOM_TV_SECAM 8 3813 3814 //ucTVSuppportedStd definition: 3815 #define NTSC_SUPPORT 0x1 3816 #define NTSCJ_SUPPORT 0x2 3817 3818 #define PAL_SUPPORT 0x4 3819 #define PALM_SUPPORT 0x8 3820 #define PALCN_SUPPORT 0x10 3821 #define PALN_SUPPORT 0x20 3822 #define PAL60_SUPPORT 0x40 3823 #define SECAM_SUPPORT 0x80 3824 3825 #define MAX_SUPPORTED_TV_TIMING 2 3826 3827 typedef struct _ATOM_ANALOG_TV_INFO 3828 { 3829 ATOM_COMMON_TABLE_HEADER sHeader; 3830 UCHAR ucTV_SuppportedStandard; 3831 UCHAR ucTV_BootUpDefaultStandard; 3832 UCHAR ucExt_TV_ASIC_ID; 3833 UCHAR ucExt_TV_ASIC_SlaveAddr; 3834 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 3835 }ATOM_ANALOG_TV_INFO; 3836 3837 typedef struct _ATOM_DPCD_INFO 3838 { 3839 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 3840 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 3841 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 3842 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 3843 }ATOM_DPCD_INFO; 3844 3845 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 3846 3847 /**************************************************************************/ 3848 // VRAM usage and their defintions 3849 3850 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 3851 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 3852 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 3853 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 3854 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 3855 3856 // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 3857 //#ifndef VESA_MEMORY_IN_64K_BLOCK 3858 //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 3859 //#endif 3860 3861 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 3862 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 3863 #define ATOM_HWICON_INFOTABLE_SIZE 32 3864 #define MAX_DTD_MODE_IN_VRAM 6 3865 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 3866 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 3867 //20 bytes for Encoder Type and DPCD in STD EDID area 3868 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 3869 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 3870 3871 #define ATOM_HWICON1_SURFACE_ADDR 0 3872 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3873 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 3874 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 3875 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3876 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3877 3878 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3879 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3880 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3881 3882 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3883 3884 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3885 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3886 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3887 3888 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3889 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3890 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3891 3892 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3893 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3894 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3895 3896 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3897 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3898 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3899 3900 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3901 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3902 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3903 3904 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3905 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3906 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3907 3908 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3909 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3910 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3911 3912 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3913 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3914 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3915 3916 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3917 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 3918 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 3919 3920 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 3921 3922 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 3923 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 3924 3925 //The size below is in Kb! 3926 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 3927 3928 #define ATOM_VRAM_RESERVE_V2_SIZE 32 3929 3930 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 3931 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 3932 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 3933 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 3934 3935 /***********************************************************************************/ 3936 // Structure used in VRAM_UsageByFirmwareTable 3937 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 3938 // at running time. 3939 // note2: From RV770, the memory is more than 32bit addressable, so we will change 3940 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 3941 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 3942 // (in offset to start of memory address) is KB aligned instead of byte aligend. 3943 // Note3: 3944 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 3945 constant across VGA or non VGA adapter, 3946 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 3947 3948 If (ulStartAddrUsedByFirmware!=0) 3949 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 3950 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 3951 else //Non VGA case 3952 if (FB_Size<=2Gb) 3953 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 3954 else 3955 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 3956 3957 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 3958 3959 /***********************************************************************************/ 3960 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 3961 3962 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 3963 { 3964 ULONG ulStartAddrUsedByFirmware; 3965 USHORT usFirmwareUseInKb; 3966 USHORT usReserved; 3967 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 3968 3969 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 3970 { 3971 ATOM_COMMON_TABLE_HEADER sHeader; 3972 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3973 }ATOM_VRAM_USAGE_BY_FIRMWARE; 3974 3975 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 3976 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 3977 { 3978 ULONG ulStartAddrUsedByFirmware; 3979 USHORT usFirmwareUseInKb; 3980 USHORT usFBUsedByDrvInKb; 3981 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 3982 3983 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 3984 { 3985 ATOM_COMMON_TABLE_HEADER sHeader; 3986 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 3987 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 3988 3989 /****************************************************************************/ 3990 // Structure used in GPIO_Pin_LUTTable 3991 /****************************************************************************/ 3992 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 3993 { 3994 USHORT usGpioPin_AIndex; 3995 UCHAR ucGpioPinBitShift; 3996 UCHAR ucGPIO_ID; 3997 }ATOM_GPIO_PIN_ASSIGNMENT; 3998 3999 //ucGPIO_ID pre-define id for multiple usage 4000 // GPIO use to control PCIE_VDDC in certain SLT board 4001 #define PCIE_VDDC_CONTROL_GPIO_PINID 56 4002 4003 //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC swithing feature is enable 4004 #define PP_AC_DC_SWITCH_GPIO_PINID 60 4005 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4006 #define VDDC_VRHOT_GPIO_PINID 61 4007 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4008 #define VDDC_PCC_GPIO_PINID 62 4009 // Only used on certain SLT/PA board to allow utility to cut Efuse. 4010 #define EFUSE_CUT_ENABLE_GPIO_PINID 63 4011 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4012 #define DRAM_SELF_REFRESH_GPIO_PINID 64 4013 // Thermal interrupt output->system thermal chip GPIO pin 4014 #define THERMAL_INT_OUTPUT_GPIO_PINID 65 4015 4016 4017 typedef struct _ATOM_GPIO_PIN_LUT 4018 { 4019 ATOM_COMMON_TABLE_HEADER sHeader; 4020 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 4021 }ATOM_GPIO_PIN_LUT; 4022 4023 /****************************************************************************/ 4024 // Structure used in ComponentVideoInfoTable 4025 /****************************************************************************/ 4026 #define GPIO_PIN_ACTIVE_HIGH 0x1 4027 #define MAX_SUPPORTED_CV_STANDARDS 5 4028 4029 // definitions for ATOM_D_INFO.ucSettings 4030 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4031 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4032 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4033 4034 typedef struct _ATOM_GPIO_INFO 4035 { 4036 USHORT usAOffset; 4037 UCHAR ucSettings; 4038 UCHAR ucReserved; 4039 }ATOM_GPIO_INFO; 4040 4041 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4042 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4043 4044 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4045 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4046 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4047 4048 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4049 //Line 3 out put 5V. 4050 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4051 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4052 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4053 4054 //Line 3 out put 2.2V 4055 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4056 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4057 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4058 4059 //Line 3 out put 0V 4060 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4061 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4062 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4063 4064 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4065 4066 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4067 4068 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4069 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4070 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4071 4072 4073 typedef struct _ATOM_COMPONENT_VIDEO_INFO 4074 { 4075 ATOM_COMMON_TABLE_HEADER sHeader; 4076 USHORT usMask_PinRegisterIndex; 4077 USHORT usEN_PinRegisterIndex; 4078 USHORT usY_PinRegisterIndex; 4079 USHORT usA_PinRegisterIndex; 4080 UCHAR ucBitShift; 4081 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4082 ATOM_DTD_FORMAT sReserved; // must be zeroed out 4083 UCHAR ucMiscInfo; 4084 UCHAR uc480i; 4085 UCHAR uc480p; 4086 UCHAR uc720p; 4087 UCHAR uc1080i; 4088 UCHAR ucLetterBoxMode; 4089 UCHAR ucReserved[3]; 4090 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4091 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4092 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4093 }ATOM_COMPONENT_VIDEO_INFO; 4094 4095 //ucTableFormatRevision=2 4096 //ucTableContentRevision=1 4097 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4098 { 4099 ATOM_COMMON_TABLE_HEADER sHeader; 4100 UCHAR ucMiscInfo; 4101 UCHAR uc480i; 4102 UCHAR uc480p; 4103 UCHAR uc720p; 4104 UCHAR uc1080i; 4105 UCHAR ucReserved; 4106 UCHAR ucLetterBoxMode; 4107 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4108 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4109 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4110 }ATOM_COMPONENT_VIDEO_INFO_V21; 4111 4112 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4113 4114 /****************************************************************************/ 4115 // Structure used in object_InfoTable 4116 /****************************************************************************/ 4117 typedef struct _ATOM_OBJECT_HEADER 4118 { 4119 ATOM_COMMON_TABLE_HEADER sHeader; 4120 USHORT usDeviceSupport; 4121 USHORT usConnectorObjectTableOffset; 4122 USHORT usRouterObjectTableOffset; 4123 USHORT usEncoderObjectTableOffset; 4124 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4125 USHORT usDisplayPathTableOffset; 4126 }ATOM_OBJECT_HEADER; 4127 4128 typedef struct _ATOM_OBJECT_HEADER_V3 4129 { 4130 ATOM_COMMON_TABLE_HEADER sHeader; 4131 USHORT usDeviceSupport; 4132 USHORT usConnectorObjectTableOffset; 4133 USHORT usRouterObjectTableOffset; 4134 USHORT usEncoderObjectTableOffset; 4135 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4136 USHORT usDisplayPathTableOffset; 4137 USHORT usMiscObjectTableOffset; 4138 }ATOM_OBJECT_HEADER_V3; 4139 4140 4141 typedef struct _ATOM_DISPLAY_OBJECT_PATH 4142 { 4143 USHORT usDeviceTag; //supported device 4144 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4145 USHORT usConnObjectId; //Connector Object ID 4146 USHORT usGPUObjectId; //GPU ID 4147 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4148 }ATOM_DISPLAY_OBJECT_PATH; 4149 4150 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4151 { 4152 USHORT usDeviceTag; //supported device 4153 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4154 USHORT usConnObjectId; //Connector Object ID 4155 USHORT usGPUObjectId; //GPU ID 4156 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4157 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4158 4159 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4160 { 4161 UCHAR ucNumOfDispPath; 4162 UCHAR ucVersion; 4163 UCHAR ucPadding[2]; 4164 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4165 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 4166 4167 typedef struct _ATOM_OBJECT //each object has this structure 4168 { 4169 USHORT usObjectID; 4170 USHORT usSrcDstTableOffset; 4171 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4172 USHORT usReserved; 4173 }ATOM_OBJECT; 4174 4175 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4176 { 4177 UCHAR ucNumberOfObjects; 4178 UCHAR ucPadding[3]; 4179 ATOM_OBJECT asObjects[1]; 4180 }ATOM_OBJECT_TABLE; 4181 4182 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4183 { 4184 UCHAR ucNumberOfSrc; 4185 USHORT usSrcObjectID[1]; 4186 UCHAR ucNumberOfDst; 4187 USHORT usDstObjectID[1]; 4188 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4189 4190 4191 //Two definitions below are for OPM on MXM module designs 4192 4193 #define EXT_HPDPIN_LUTINDEX_0 0 4194 #define EXT_HPDPIN_LUTINDEX_1 1 4195 #define EXT_HPDPIN_LUTINDEX_2 2 4196 #define EXT_HPDPIN_LUTINDEX_3 3 4197 #define EXT_HPDPIN_LUTINDEX_4 4 4198 #define EXT_HPDPIN_LUTINDEX_5 5 4199 #define EXT_HPDPIN_LUTINDEX_6 6 4200 #define EXT_HPDPIN_LUTINDEX_7 7 4201 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4202 4203 #define EXT_AUXDDC_LUTINDEX_0 0 4204 #define EXT_AUXDDC_LUTINDEX_1 1 4205 #define EXT_AUXDDC_LUTINDEX_2 2 4206 #define EXT_AUXDDC_LUTINDEX_3 3 4207 #define EXT_AUXDDC_LUTINDEX_4 4 4208 #define EXT_AUXDDC_LUTINDEX_5 5 4209 #define EXT_AUXDDC_LUTINDEX_6 6 4210 #define EXT_AUXDDC_LUTINDEX_7 7 4211 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4212 4213 //ucChannelMapping are defined as following 4214 //for DP connector, eDP, DP to VGA/LVDS 4215 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4216 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4217 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4218 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4219 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4220 { 4221 #if ATOM_BIG_ENDIAN 4222 UCHAR ucDP_Lane3_Source:2; 4223 UCHAR ucDP_Lane2_Source:2; 4224 UCHAR ucDP_Lane1_Source:2; 4225 UCHAR ucDP_Lane0_Source:2; 4226 #else 4227 UCHAR ucDP_Lane0_Source:2; 4228 UCHAR ucDP_Lane1_Source:2; 4229 UCHAR ucDP_Lane2_Source:2; 4230 UCHAR ucDP_Lane3_Source:2; 4231 #endif 4232 }ATOM_DP_CONN_CHANNEL_MAPPING; 4233 4234 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4235 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4236 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4237 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4238 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4239 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4240 { 4241 #if ATOM_BIG_ENDIAN 4242 UCHAR ucDVI_CLK_Source:2; 4243 UCHAR ucDVI_DATA0_Source:2; 4244 UCHAR ucDVI_DATA1_Source:2; 4245 UCHAR ucDVI_DATA2_Source:2; 4246 #else 4247 UCHAR ucDVI_DATA2_Source:2; 4248 UCHAR ucDVI_DATA1_Source:2; 4249 UCHAR ucDVI_DATA0_Source:2; 4250 UCHAR ucDVI_CLK_Source:2; 4251 #endif 4252 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4253 4254 typedef struct _EXT_DISPLAY_PATH 4255 { 4256 USHORT usDeviceTag; //A bit vector to show what devices are supported 4257 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4258 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4259 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4260 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4261 USHORT usExtEncoderObjId; //external encoder object id 4262 union{ 4263 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4264 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4265 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4266 }; 4267 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4268 USHORT usCaps; 4269 USHORT usReserved; 4270 }EXT_DISPLAY_PATH; 4271 4272 #define NUMBER_OF_UCHAR_FOR_GUID 16 4273 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4274 4275 //usCaps 4276 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x01 4277 #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x02 4278 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 0x04 4279 #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT 0x08 4280 4281 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4282 { 4283 ATOM_COMMON_TABLE_HEADER sHeader; 4284 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4285 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4286 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4287 UCHAR uc3DStereoPinId; // use for eDP panel 4288 UCHAR ucRemoteDisplayConfig; 4289 UCHAR uceDPToLVDSRxId; 4290 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4291 UCHAR Reserved[3]; // for potential expansion 4292 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4293 4294 //Related definitions, all records are differnt but they have a commond header 4295 typedef struct _ATOM_COMMON_RECORD_HEADER 4296 { 4297 UCHAR ucRecordType; //An emun to indicate the record type 4298 UCHAR ucRecordSize; //The size of the whole record in byte 4299 }ATOM_COMMON_RECORD_HEADER; 4300 4301 4302 #define ATOM_I2C_RECORD_TYPE 1 4303 #define ATOM_HPD_INT_RECORD_TYPE 2 4304 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4305 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4306 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4307 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4308 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4309 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4310 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4311 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4312 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4313 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4314 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4315 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4316 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4317 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4318 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4319 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4320 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4321 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4322 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4323 4324 4325 //Must be updated when new record type is added,equal to that record definition! 4326 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_ENCODER_CAP_RECORD_TYPE 4327 4328 typedef struct _ATOM_I2C_RECORD 4329 { 4330 ATOM_COMMON_RECORD_HEADER sheader; 4331 ATOM_I2C_ID_CONFIG sucI2cId; 4332 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4333 }ATOM_I2C_RECORD; 4334 4335 typedef struct _ATOM_HPD_INT_RECORD 4336 { 4337 ATOM_COMMON_RECORD_HEADER sheader; 4338 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4339 UCHAR ucPlugged_PinState; 4340 }ATOM_HPD_INT_RECORD; 4341 4342 4343 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4344 { 4345 ATOM_COMMON_RECORD_HEADER sheader; 4346 UCHAR ucProtectionFlag; 4347 UCHAR ucReserved; 4348 }ATOM_OUTPUT_PROTECTION_RECORD; 4349 4350 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4351 { 4352 ULONG ulACPIDeviceEnum; //Reserved for now 4353 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4354 USHORT usPadding; 4355 }ATOM_CONNECTOR_DEVICE_TAG; 4356 4357 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4358 { 4359 ATOM_COMMON_RECORD_HEADER sheader; 4360 UCHAR ucNumberOfDevice; 4361 UCHAR ucReserved; 4362 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4363 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4364 4365 4366 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4367 { 4368 ATOM_COMMON_RECORD_HEADER sheader; 4369 UCHAR ucConfigGPIOID; 4370 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4371 UCHAR ucFlowinGPIPID; 4372 UCHAR ucExtInGPIPID; 4373 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4374 4375 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4376 { 4377 ATOM_COMMON_RECORD_HEADER sheader; 4378 UCHAR ucCTL1GPIO_ID; 4379 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4380 UCHAR ucCTL2GPIO_ID; 4381 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4382 UCHAR ucCTL3GPIO_ID; 4383 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4384 UCHAR ucCTLFPGA_IN_ID; 4385 UCHAR ucPadding[3]; 4386 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4387 4388 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4389 { 4390 ATOM_COMMON_RECORD_HEADER sheader; 4391 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4392 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4393 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4394 4395 typedef struct _ATOM_JTAG_RECORD 4396 { 4397 ATOM_COMMON_RECORD_HEADER sheader; 4398 UCHAR ucTMSGPIO_ID; 4399 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4400 UCHAR ucTCKGPIO_ID; 4401 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4402 UCHAR ucTDOGPIO_ID; 4403 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4404 UCHAR ucTDIGPIO_ID; 4405 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4406 UCHAR ucPadding[2]; 4407 }ATOM_JTAG_RECORD; 4408 4409 4410 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4411 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4412 { 4413 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4414 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4415 }ATOM_GPIO_PIN_CONTROL_PAIR; 4416 4417 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4418 { 4419 ATOM_COMMON_RECORD_HEADER sheader; 4420 UCHAR ucFlags; // Future expnadibility 4421 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4422 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4423 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4424 4425 //Definitions for GPIO pin state 4426 #define GPIO_PIN_TYPE_INPUT 0x00 4427 #define GPIO_PIN_TYPE_OUTPUT 0x10 4428 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4429 4430 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4431 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4432 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4433 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4434 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4435 4436 // Indexes to GPIO array in GLSync record 4437 // GLSync record is for Frame Lock/Gen Lock feature. 4438 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4439 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4440 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4441 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4442 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4443 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4444 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4445 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4446 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4447 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4448 4449 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4450 { 4451 ATOM_COMMON_RECORD_HEADER sheader; 4452 ULONG ulStrengthControl; // DVOA strength control for CF 4453 UCHAR ucPadding[2]; 4454 }ATOM_ENCODER_DVO_CF_RECORD; 4455 4456 // Bit maps for ATOM_ENCODER_CAP_RECORD.ucEncoderCap 4457 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder 4458 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4459 #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4460 4461 typedef struct _ATOM_ENCODER_CAP_RECORD 4462 { 4463 ATOM_COMMON_RECORD_HEADER sheader; 4464 union { 4465 USHORT usEncoderCap; 4466 struct { 4467 #if ATOM_BIG_ENDIAN 4468 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4469 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4470 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4471 #else 4472 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4473 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4474 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4475 #endif 4476 }; 4477 }; 4478 }ATOM_ENCODER_CAP_RECORD; 4479 4480 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4481 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4482 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4483 4484 typedef struct _ATOM_CONNECTOR_CF_RECORD 4485 { 4486 ATOM_COMMON_RECORD_HEADER sheader; 4487 USHORT usMaxPixClk; 4488 UCHAR ucFlowCntlGpioId; 4489 UCHAR ucSwapCntlGpioId; 4490 UCHAR ucConnectedDvoBundle; 4491 UCHAR ucPadding; 4492 }ATOM_CONNECTOR_CF_RECORD; 4493 4494 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4495 { 4496 ATOM_COMMON_RECORD_HEADER sheader; 4497 ATOM_DTD_FORMAT asTiming; 4498 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4499 4500 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4501 { 4502 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4503 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4504 UCHAR ucReserved; 4505 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4506 4507 4508 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4509 { 4510 ATOM_COMMON_RECORD_HEADER sheader; 4511 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4512 UCHAR ucMuxControlPin; 4513 UCHAR ucMuxState[2]; //for alligment purpose 4514 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4515 4516 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4517 { 4518 ATOM_COMMON_RECORD_HEADER sheader; 4519 UCHAR ucMuxType; 4520 UCHAR ucMuxControlPin; 4521 UCHAR ucMuxState[2]; //for alligment purpose 4522 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4523 4524 // define ucMuxType 4525 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4526 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4527 4528 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4529 { 4530 ATOM_COMMON_RECORD_HEADER sheader; 4531 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4532 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4533 4534 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4535 { 4536 ATOM_COMMON_RECORD_HEADER sheader; 4537 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4538 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4539 4540 typedef struct _ATOM_OBJECT_LINK_RECORD 4541 { 4542 ATOM_COMMON_RECORD_HEADER sheader; 4543 USHORT usObjectID; //could be connector, encorder or other object in object.h 4544 }ATOM_OBJECT_LINK_RECORD; 4545 4546 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4547 { 4548 ATOM_COMMON_RECORD_HEADER sheader; 4549 USHORT usReserved; 4550 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4551 4552 typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4553 { 4554 USHORT usConnectorObjectId; 4555 UCHAR ucConnectorType; 4556 UCHAR ucPosition; 4557 }ATOM_CONNECTOR_LAYOUT_INFO; 4558 4559 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4560 #define CONNECTOR_TYPE_DVI_D 1 4561 #define CONNECTOR_TYPE_DVI_I 2 4562 #define CONNECTOR_TYPE_VGA 3 4563 #define CONNECTOR_TYPE_HDMI 4 4564 #define CONNECTOR_TYPE_DISPLAY_PORT 5 4565 #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4566 4567 typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4568 { 4569 ATOM_COMMON_RECORD_HEADER sheader; 4570 UCHAR ucLength; 4571 UCHAR ucWidth; 4572 UCHAR ucConnNum; 4573 UCHAR ucReserved; 4574 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4575 }ATOM_BRACKET_LAYOUT_RECORD; 4576 4577 4578 /****************************************************************************/ 4579 // Structure used in XXXX 4580 /****************************************************************************/ 4581 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4582 { 4583 USHORT usVDDCBaseLevel; //In number of 50mv unit 4584 USHORT usReserved; //For possible extension table offset 4585 UCHAR ucNumOfVoltageEntries; 4586 UCHAR ucBytesPerVoltageEntry; 4587 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 4588 UCHAR ucDefaultVoltageEntry; 4589 UCHAR ucVoltageControlI2cLine; 4590 UCHAR ucVoltageControlAddress; 4591 UCHAR ucVoltageControlOffset; 4592 }ATOM_VOLTAGE_INFO_HEADER; 4593 4594 typedef struct _ATOM_VOLTAGE_INFO 4595 { 4596 ATOM_COMMON_TABLE_HEADER sHeader; 4597 ATOM_VOLTAGE_INFO_HEADER viHeader; 4598 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 4599 }ATOM_VOLTAGE_INFO; 4600 4601 4602 typedef struct _ATOM_VOLTAGE_FORMULA 4603 { 4604 USHORT usVoltageBaseLevel; // In number of 1mv unit 4605 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 4606 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4607 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 4608 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 4609 UCHAR ucReserved; 4610 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 4611 }ATOM_VOLTAGE_FORMULA; 4612 4613 typedef struct _VOLTAGE_LUT_ENTRY 4614 { 4615 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 4616 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4617 }VOLTAGE_LUT_ENTRY; 4618 4619 typedef struct _ATOM_VOLTAGE_FORMULA_V2 4620 { 4621 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 4622 UCHAR ucReserved[3]; 4623 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 4624 }ATOM_VOLTAGE_FORMULA_V2; 4625 4626 typedef struct _ATOM_VOLTAGE_CONTROL 4627 { 4628 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 4629 UCHAR ucVoltageControlI2cLine; 4630 UCHAR ucVoltageControlAddress; 4631 UCHAR ucVoltageControlOffset; 4632 USHORT usGpioPin_AIndex; //GPIO_PAD register index 4633 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 4634 UCHAR ucReserved; 4635 }ATOM_VOLTAGE_CONTROL; 4636 4637 // Define ucVoltageControlId 4638 #define VOLTAGE_CONTROLLED_BY_HW 0x00 4639 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 4640 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 4641 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 4642 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 4643 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 4644 #define VOLTAGE_CONTROL_ID_DS4402 0x04 4645 #define VOLTAGE_CONTROL_ID_UP6266 0x05 4646 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 4647 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 4648 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 4649 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 4650 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 4651 #define VOLTAGE_CONTROL_ID_CHL8214 0x0B 4652 #define VOLTAGE_CONTROL_ID_UP1801 0x0C 4653 #define VOLTAGE_CONTROL_ID_ST6788A 0x0D 4654 #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 4655 #define VOLTAGE_CONTROL_ID_AD527x 0x0F 4656 #define VOLTAGE_CONTROL_ID_NCP81022 0x10 4657 #define VOLTAGE_CONTROL_ID_LTC2635 0x11 4658 #define VOLTAGE_CONTROL_ID_NCP4208 0x12 4659 #define VOLTAGE_CONTROL_ID_IR35xx 0x13 4660 #define VOLTAGE_CONTROL_ID_RT9403 0x14 4661 4662 #define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 4663 4664 typedef struct _ATOM_VOLTAGE_OBJECT 4665 { 4666 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4667 UCHAR ucSize; //Size of Object 4668 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4669 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 4670 }ATOM_VOLTAGE_OBJECT; 4671 4672 typedef struct _ATOM_VOLTAGE_OBJECT_V2 4673 { 4674 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4675 UCHAR ucSize; //Size of Object 4676 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 4677 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 4678 }ATOM_VOLTAGE_OBJECT_V2; 4679 4680 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 4681 { 4682 ATOM_COMMON_TABLE_HEADER sHeader; 4683 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 4684 }ATOM_VOLTAGE_OBJECT_INFO; 4685 4686 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 4687 { 4688 ATOM_COMMON_TABLE_HEADER sHeader; 4689 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 4690 }ATOM_VOLTAGE_OBJECT_INFO_V2; 4691 4692 typedef struct _ATOM_LEAKID_VOLTAGE 4693 { 4694 UCHAR ucLeakageId; 4695 UCHAR ucReserved; 4696 USHORT usVoltage; 4697 }ATOM_LEAKID_VOLTAGE; 4698 4699 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 4700 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 4701 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 4702 USHORT usSize; //Size of Object 4703 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 4704 4705 // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 4706 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4707 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 4708 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 4709 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 4710 #define VOLTAGE_OBJ_EVV 8 4711 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4712 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4713 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4714 4715 typedef struct _VOLTAGE_LUT_ENTRY_V2 4716 { 4717 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 4718 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 4719 }VOLTAGE_LUT_ENTRY_V2; 4720 4721 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 4722 { 4723 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 4724 USHORT usVoltageId; 4725 USHORT usLeakageId; // The corresponding Voltage Value, in mV 4726 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 4727 4728 4729 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 4730 { 4731 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 4732 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 4733 UCHAR ucVoltageControlI2cLine; 4734 UCHAR ucVoltageControlAddress; 4735 UCHAR ucVoltageControlOffset; 4736 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 4737 UCHAR ulReserved[3]; 4738 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 4739 }ATOM_I2C_VOLTAGE_OBJECT_V3; 4740 4741 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 4742 #define VOLTAGE_DATA_ONE_BYTE 0 4743 #define VOLTAGE_DATA_TWO_BYTE 1 4744 4745 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 4746 { 4747 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 4748 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 4749 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 4750 UCHAR ucPhaseDelay; // phase delay in unit of micro second 4751 UCHAR ucReserved; 4752 ULONG ulGpioMaskVal; // GPIO Mask value 4753 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 4754 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 4755 4756 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 4757 { 4758 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 4759 UCHAR ucLeakageCntlId; // default is 0 4760 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 4761 UCHAR ucReserved[2]; 4762 ULONG ulMaxVoltageLevel; 4763 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 4764 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 4765 4766 4767 typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 4768 { 4769 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 4770 // 14:7 PSI0_VID 4771 // 6 PSI0_EN 4772 // 5 PSI1 4773 // 4:2 load line slope trim. 4774 // 1:0 offset trim, 4775 USHORT usLoadLine_PSI; 4776 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 4777 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 4778 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 4779 ULONG ulReserved; 4780 }ATOM_SVID2_VOLTAGE_OBJECT_V3; 4781 4782 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 4783 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 4784 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 4785 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 4786 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 4787 }ATOM_VOLTAGE_OBJECT_V3; 4788 4789 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 4790 { 4791 ATOM_COMMON_TABLE_HEADER sHeader; 4792 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 4793 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 4794 4795 4796 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 4797 { 4798 UCHAR ucProfileId; 4799 UCHAR ucReserved; 4800 USHORT usSize; 4801 USHORT usEfuseSpareStartAddr; 4802 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 4803 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 4804 }ATOM_ASIC_PROFILE_VOLTAGE; 4805 4806 //ucProfileId 4807 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 4808 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 4809 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 4810 4811 typedef struct _ATOM_ASIC_PROFILING_INFO 4812 { 4813 ATOM_COMMON_TABLE_HEADER asHeader; 4814 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 4815 }ATOM_ASIC_PROFILING_INFO; 4816 4817 typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 4818 { 4819 ATOM_COMMON_TABLE_HEADER asHeader; 4820 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 4821 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 4822 4823 UCHAR ucElbVDDC_Num; 4824 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 4825 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4826 4827 UCHAR ucElbVDDCI_Num; 4828 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 4829 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 4830 }ATOM_ASIC_PROFILING_INFO_V2_1; 4831 4832 4833 //Here is parameter to convert Efuse value to Measure value 4834 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 4835 typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 4836 { 4837 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 4838 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 4839 UCHAR ucEfuseLength; // Efuse bits length, 4840 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 4841 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 4842 }EFUSE_LOGISTIC_FUNC_PARAM; 4843 4844 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 4845 typedef struct _EFUSE_LINEAR_FUNC_PARAM 4846 { 4847 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 4848 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 4849 UCHAR ucEfuseLength; // Efuse bits length, 4850 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 4851 ULONG ulEfuseMin; // Min 4852 }EFUSE_LINEAR_FUNC_PARAM; 4853 4854 4855 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 4856 { 4857 ATOM_COMMON_TABLE_HEADER asHeader; 4858 ULONG ulEvvDerateTdp; 4859 ULONG ulEvvDerateTdc; 4860 ULONG ulBoardCoreTemp; 4861 ULONG ulMaxVddc; 4862 ULONG ulMinVddc; 4863 ULONG ulLoadLineSlop; 4864 ULONG ulLeakageTemp; 4865 ULONG ulLeakageVoltage; 4866 EFUSE_LINEAR_FUNC_PARAM sCACm; 4867 EFUSE_LINEAR_FUNC_PARAM sCACb; 4868 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4869 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4870 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4871 USHORT usLkgEuseIndex; 4872 UCHAR ucLkgEfuseBitLSB; 4873 UCHAR ucLkgEfuseLength; 4874 ULONG ulLkgEncodeLn_MaxDivMin; 4875 ULONG ulLkgEncodeMax; 4876 ULONG ulLkgEncodeMin; 4877 ULONG ulEfuseLogisticAlpha; 4878 USHORT usPowerDpm0; 4879 USHORT usCurrentDpm0; 4880 USHORT usPowerDpm1; 4881 USHORT usCurrentDpm1; 4882 USHORT usPowerDpm2; 4883 USHORT usCurrentDpm2; 4884 USHORT usPowerDpm3; 4885 USHORT usCurrentDpm3; 4886 USHORT usPowerDpm4; 4887 USHORT usCurrentDpm4; 4888 USHORT usPowerDpm5; 4889 USHORT usCurrentDpm5; 4890 USHORT usPowerDpm6; 4891 USHORT usCurrentDpm6; 4892 USHORT usPowerDpm7; 4893 USHORT usCurrentDpm7; 4894 }ATOM_ASIC_PROFILING_INFO_V3_1; 4895 4896 4897 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 4898 { 4899 ATOM_COMMON_TABLE_HEADER asHeader; 4900 ULONG ulEvvLkgFactor; 4901 ULONG ulBoardCoreTemp; 4902 ULONG ulMaxVddc; 4903 ULONG ulMinVddc; 4904 ULONG ulLoadLineSlop; 4905 ULONG ulLeakageTemp; 4906 ULONG ulLeakageVoltage; 4907 EFUSE_LINEAR_FUNC_PARAM sCACm; 4908 EFUSE_LINEAR_FUNC_PARAM sCACb; 4909 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4910 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4911 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4912 USHORT usLkgEuseIndex; 4913 UCHAR ucLkgEfuseBitLSB; 4914 UCHAR ucLkgEfuseLength; 4915 ULONG ulLkgEncodeLn_MaxDivMin; 4916 ULONG ulLkgEncodeMax; 4917 ULONG ulLkgEncodeMin; 4918 ULONG ulEfuseLogisticAlpha; 4919 USHORT usPowerDpm0; 4920 USHORT usPowerDpm1; 4921 USHORT usPowerDpm2; 4922 USHORT usPowerDpm3; 4923 USHORT usPowerDpm4; 4924 USHORT usPowerDpm5; 4925 USHORT usPowerDpm6; 4926 USHORT usPowerDpm7; 4927 ULONG ulTdpDerateDPM0; 4928 ULONG ulTdpDerateDPM1; 4929 ULONG ulTdpDerateDPM2; 4930 ULONG ulTdpDerateDPM3; 4931 ULONG ulTdpDerateDPM4; 4932 ULONG ulTdpDerateDPM5; 4933 ULONG ulTdpDerateDPM6; 4934 ULONG ulTdpDerateDPM7; 4935 }ATOM_ASIC_PROFILING_INFO_V3_2; 4936 4937 4938 // for Tonga/Fiji speed EVV algorithm 4939 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 4940 { 4941 ATOM_COMMON_TABLE_HEADER asHeader; 4942 ULONG ulEvvLkgFactor; 4943 ULONG ulBoardCoreTemp; 4944 ULONG ulMaxVddc; 4945 ULONG ulMinVddc; 4946 ULONG ulLoadLineSlop; 4947 ULONG ulLeakageTemp; 4948 ULONG ulLeakageVoltage; 4949 EFUSE_LINEAR_FUNC_PARAM sCACm; 4950 EFUSE_LINEAR_FUNC_PARAM sCACb; 4951 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 4952 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 4953 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 4954 USHORT usLkgEuseIndex; 4955 UCHAR ucLkgEfuseBitLSB; 4956 UCHAR ucLkgEfuseLength; 4957 ULONG ulLkgEncodeLn_MaxDivMin; 4958 ULONG ulLkgEncodeMax; 4959 ULONG ulLkgEncodeMin; 4960 ULONG ulEfuseLogisticAlpha; 4961 USHORT usPowerDpm0; 4962 USHORT usPowerDpm1; 4963 USHORT usPowerDpm2; 4964 USHORT usPowerDpm3; 4965 USHORT usPowerDpm4; 4966 USHORT usPowerDpm5; 4967 USHORT usPowerDpm6; 4968 USHORT usPowerDpm7; 4969 ULONG ulTdpDerateDPM0; 4970 ULONG ulTdpDerateDPM1; 4971 ULONG ulTdpDerateDPM2; 4972 ULONG ulTdpDerateDPM3; 4973 ULONG ulTdpDerateDPM4; 4974 ULONG ulTdpDerateDPM5; 4975 ULONG ulTdpDerateDPM6; 4976 ULONG ulTdpDerateDPM7; 4977 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 4978 ULONG ulRoAlpha; 4979 ULONG ulRoBeta; 4980 ULONG ulRoGamma; 4981 ULONG ulRoEpsilon; 4982 ULONG ulATermRo; 4983 ULONG ulBTermRo; 4984 ULONG ulCTermRo; 4985 ULONG ulSclkMargin; 4986 ULONG ulFmaxPercent; 4987 ULONG ulCRPercent; 4988 ULONG ulSFmaxPercent; 4989 ULONG ulSCRPercent; 4990 ULONG ulSDCMargine; 4991 }ATOM_ASIC_PROFILING_INFO_V3_3; 4992 4993 typedef struct _ATOM_POWER_SOURCE_OBJECT 4994 { 4995 UCHAR ucPwrSrcId; // Power source 4996 UCHAR ucPwrSensorType; // GPIO, I2C or none 4997 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 4998 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 4999 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5000 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5001 UCHAR ucPwrSensActiveState; // high active or low active 5002 UCHAR ucReserve[3]; // reserve 5003 USHORT usSensPwr; // in unit of watt 5004 }ATOM_POWER_SOURCE_OBJECT; 5005 5006 typedef struct _ATOM_POWER_SOURCE_INFO 5007 { 5008 ATOM_COMMON_TABLE_HEADER asHeader; 5009 UCHAR asPwrbehave[16]; 5010 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5011 }ATOM_POWER_SOURCE_INFO; 5012 5013 5014 //Define ucPwrSrcId 5015 #define POWERSOURCE_PCIE_ID1 0x00 5016 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5017 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5018 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5019 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5020 5021 //define ucPwrSensorId 5022 #define POWER_SENSOR_ALWAYS 0x00 5023 #define POWER_SENSOR_GPIO 0x01 5024 #define POWER_SENSOR_I2C 0x02 5025 5026 typedef struct _ATOM_CLK_VOLT_CAPABILITY 5027 { 5028 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5029 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5030 }ATOM_CLK_VOLT_CAPABILITY; 5031 5032 5033 typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5034 { 5035 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5036 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5037 }ATOM_CLK_VOLT_CAPABILITY_V2; 5038 5039 typedef struct _ATOM_AVAILABLE_SCLK_LIST 5040 { 5041 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5042 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5043 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5044 }ATOM_AVAILABLE_SCLK_LIST; 5045 5046 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5047 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5048 5049 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 5050 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5051 { 5052 ATOM_COMMON_TABLE_HEADER sHeader; 5053 ULONG ulBootUpEngineClock; 5054 ULONG ulDentistVCOFreq; 5055 ULONG ulBootUpUMAClock; 5056 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5057 ULONG ulBootUpReqDisplayVector; 5058 ULONG ulOtherDisplayMisc; 5059 ULONG ulGPUCapInfo; 5060 ULONG ulSB_MMIO_Base_Addr; 5061 USHORT usRequestedPWMFreqInHz; 5062 UCHAR ucHtcTmpLmt; 5063 UCHAR ucHtcHystLmt; 5064 ULONG ulMinEngineClock; 5065 ULONG ulSystemConfig; 5066 ULONG ulCPUCapInfo; 5067 USHORT usNBP0Voltage; 5068 USHORT usNBP1Voltage; 5069 USHORT usBootUpNBVoltage; 5070 USHORT usExtDispConnInfoOffset; 5071 USHORT usPanelRefreshRateRange; 5072 UCHAR ucMemoryType; 5073 UCHAR ucUMAChannelNumber; 5074 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5075 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5076 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5077 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5078 ULONG ulGMCRestoreResetTime; 5079 ULONG ulMinimumNClk; 5080 ULONG ulIdleNClk; 5081 ULONG ulDDR_DLL_PowerUpTime; 5082 ULONG ulDDR_PLL_PowerUpTime; 5083 USHORT usPCIEClkSSPercentage; 5084 USHORT usPCIEClkSSType; 5085 USHORT usLvdsSSPercentage; 5086 USHORT usLvdsSSpreadRateIn10Hz; 5087 USHORT usHDMISSPercentage; 5088 USHORT usHDMISSpreadRateIn10Hz; 5089 USHORT usDVISSPercentage; 5090 USHORT usDVISSpreadRateIn10Hz; 5091 ULONG SclkDpmBoostMargin; 5092 ULONG SclkDpmThrottleMargin; 5093 USHORT SclkDpmTdpLimitPG; 5094 USHORT SclkDpmTdpLimitBoost; 5095 ULONG ulBoostEngineCLock; 5096 UCHAR ulBoostVid_2bit; 5097 UCHAR EnableBoost; 5098 USHORT GnbTdpLimit; 5099 USHORT usMaxLVDSPclkFreqInSingleLink; 5100 UCHAR ucLvdsMisc; 5101 UCHAR ucLVDSReserved; 5102 ULONG ulReserved3[15]; 5103 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5104 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 5105 5106 // ulGPUCapInfo 5107 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5108 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5109 5110 //ucLVDSMisc: 5111 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5112 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5113 #define SYS_INFO_LVDSMISC__888_BPC 0x04 5114 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5115 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5116 // new since Trinity 5117 #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5118 5119 // not used any more 5120 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5121 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5122 5123 /********************************************************************************************************************** 5124 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5125 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5126 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5127 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5128 sDISPCLK_Voltage: Report Display clock voltage requirement. 5129 5130 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5131 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5132 ATOM_DEVICE_CRT2_SUPPORT 0x0010 5133 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5134 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5135 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5136 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5137 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5138 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5139 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5140 ulOtherDisplayMisc: Other display related flags, not defined yet. 5141 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5142 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5143 bit[3]=0: Enable HW AUX mode detection logic 5144 =1: Disable HW AUX mode dettion logic 5145 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5146 5147 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5148 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5149 5150 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5151 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5152 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5153 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5154 and enabling VariBri under the driver environment from PP table is optional. 5155 5156 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5157 that BL control from GPU is expected. 5158 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5159 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5160 it's per platform 5161 and enabling VariBri under the driver environment from PP table is optional. 5162 5163 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5164 Threshold on value to enter HTC_active state. 5165 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5166 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5167 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5168 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5169 =1: PCIE Power Gating Enabled 5170 Bit[1]=0: DDR-DLL shut-down feature disabled. 5171 1: DDR-DLL shut-down feature enabled. 5172 Bit[2]=0: DDR-PLL Power down feature disabled. 5173 1: DDR-PLL Power down feature enabled. 5174 ulCPUCapInfo: TBD 5175 usNBP0Voltage: VID for voltage on NB P0 State 5176 usNBP1Voltage: VID for voltage on NB P1 State 5177 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5178 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5179 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5180 to indicate a range. 5181 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5182 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5183 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5184 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5185 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5186 ucUMAChannelNumber: System memory channel numbers. 5187 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5188 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5189 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5190 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5191 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5192 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5193 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5194 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5195 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5196 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5197 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5198 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5199 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5200 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5201 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5202 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5203 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5204 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5205 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5206 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5207 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5208 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5209 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5210 **********************************************************************************************************************/ 5211 5212 // this Table is used for Liano/Ontario APU 5213 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5214 { 5215 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5216 ULONG ulPowerplayTable[128]; 5217 }ATOM_FUSION_SYSTEM_INFO_V1; 5218 5219 5220 typedef struct _ATOM_TDP_CONFIG_BITS 5221 { 5222 #if ATOM_BIG_ENDIAN 5223 ULONG uReserved:2; 5224 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5225 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5226 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5227 #else 5228 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5229 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5230 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5231 ULONG uReserved:2; 5232 #endif 5233 }ATOM_TDP_CONFIG_BITS; 5234 5235 typedef union _ATOM_TDP_CONFIG 5236 { 5237 ATOM_TDP_CONFIG_BITS TDP_config; 5238 ULONG TDP_config_all; 5239 }ATOM_TDP_CONFIG; 5240 5241 /********************************************************************************************************************** 5242 ATOM_FUSION_SYSTEM_INFO_V1 Description 5243 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5244 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5245 **********************************************************************************************************************/ 5246 5247 // this IntegrateSystemInfoTable is used for Trinity APU 5248 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5249 { 5250 ATOM_COMMON_TABLE_HEADER sHeader; 5251 ULONG ulBootUpEngineClock; 5252 ULONG ulDentistVCOFreq; 5253 ULONG ulBootUpUMAClock; 5254 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5255 ULONG ulBootUpReqDisplayVector; 5256 ULONG ulOtherDisplayMisc; 5257 ULONG ulGPUCapInfo; 5258 ULONG ulSB_MMIO_Base_Addr; 5259 USHORT usRequestedPWMFreqInHz; 5260 UCHAR ucHtcTmpLmt; 5261 UCHAR ucHtcHystLmt; 5262 ULONG ulMinEngineClock; 5263 ULONG ulSystemConfig; 5264 ULONG ulCPUCapInfo; 5265 USHORT usNBP0Voltage; 5266 USHORT usNBP1Voltage; 5267 USHORT usBootUpNBVoltage; 5268 USHORT usExtDispConnInfoOffset; 5269 USHORT usPanelRefreshRateRange; 5270 UCHAR ucMemoryType; 5271 UCHAR ucUMAChannelNumber; 5272 UCHAR strVBIOSMsg[40]; 5273 ATOM_TDP_CONFIG asTdpConfig; 5274 ULONG ulReserved[19]; 5275 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5276 ULONG ulGMCRestoreResetTime; 5277 ULONG ulMinimumNClk; 5278 ULONG ulIdleNClk; 5279 ULONG ulDDR_DLL_PowerUpTime; 5280 ULONG ulDDR_PLL_PowerUpTime; 5281 USHORT usPCIEClkSSPercentage; 5282 USHORT usPCIEClkSSType; 5283 USHORT usLvdsSSPercentage; 5284 USHORT usLvdsSSpreadRateIn10Hz; 5285 USHORT usHDMISSPercentage; 5286 USHORT usHDMISSpreadRateIn10Hz; 5287 USHORT usDVISSPercentage; 5288 USHORT usDVISSpreadRateIn10Hz; 5289 ULONG SclkDpmBoostMargin; 5290 ULONG SclkDpmThrottleMargin; 5291 USHORT SclkDpmTdpLimitPG; 5292 USHORT SclkDpmTdpLimitBoost; 5293 ULONG ulBoostEngineCLock; 5294 UCHAR ulBoostVid_2bit; 5295 UCHAR EnableBoost; 5296 USHORT GnbTdpLimit; 5297 USHORT usMaxLVDSPclkFreqInSingleLink; 5298 UCHAR ucLvdsMisc; 5299 UCHAR ucTravisLVDSVolAdjust; 5300 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5301 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5302 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5303 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5304 UCHAR ucLVDSOffToOnDelay_in4Ms; 5305 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5306 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5307 UCHAR ucMinAllowedBL_Level; 5308 ULONG ulLCDBitDepthControlVal; 5309 ULONG ulNbpStateMemclkFreq[4]; 5310 USHORT usNBP2Voltage; 5311 USHORT usNBP3Voltage; 5312 ULONG ulNbpStateNClkFreq[4]; 5313 UCHAR ucNBDPMEnable; 5314 UCHAR ucReserved[3]; 5315 UCHAR ucDPMState0VclkFid; 5316 UCHAR ucDPMState0DclkFid; 5317 UCHAR ucDPMState1VclkFid; 5318 UCHAR ucDPMState1DclkFid; 5319 UCHAR ucDPMState2VclkFid; 5320 UCHAR ucDPMState2DclkFid; 5321 UCHAR ucDPMState3VclkFid; 5322 UCHAR ucDPMState3DclkFid; 5323 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5324 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5325 5326 // ulOtherDisplayMisc 5327 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5328 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5329 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5330 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5331 5332 // ulGPUCapInfo 5333 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5334 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 5335 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 5336 #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 5337 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 5338 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 5339 5340 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 5341 #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 5342 5343 /********************************************************************************************************************** 5344 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 5345 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5346 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5347 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5348 sDISPCLK_Voltage: Report Display clock voltage requirement. 5349 5350 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5351 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5352 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5353 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5354 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5355 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5356 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5357 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5358 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5359 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5360 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5361 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5362 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5363 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5364 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5365 bit[3]=0: VBIOS fast boot is disable 5366 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5367 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5368 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5369 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 5370 =1: DP mode use single PLL mode 5371 bit[3]=0: Enable AUX HW mode detection logic 5372 =1: Disable AUX HW mode detection logic 5373 5374 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5375 5376 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5377 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5378 5379 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5380 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5381 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5382 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5383 and enabling VariBri under the driver environment from PP table is optional. 5384 5385 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5386 that BL control from GPU is expected. 5387 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5388 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5389 it's per platform 5390 and enabling VariBri under the driver environment from PP table is optional. 5391 5392 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5393 Threshold on value to enter HTC_active state. 5394 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5395 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5396 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5397 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5398 =1: PCIE Power Gating Enabled 5399 Bit[1]=0: DDR-DLL shut-down feature disabled. 5400 1: DDR-DLL shut-down feature enabled. 5401 Bit[2]=0: DDR-PLL Power down feature disabled. 5402 1: DDR-PLL Power down feature enabled. 5403 ulCPUCapInfo: TBD 5404 usNBP0Voltage: VID for voltage on NB P0 State 5405 usNBP1Voltage: VID for voltage on NB P1 State 5406 usNBP2Voltage: VID for voltage on NB P2 State 5407 usNBP3Voltage: VID for voltage on NB P3 State 5408 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5409 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5410 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5411 to indicate a range. 5412 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5413 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5414 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5415 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5416 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5417 ucUMAChannelNumber: System memory channel numbers. 5418 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5419 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5420 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5421 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5422 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5423 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5424 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5425 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5426 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5427 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5428 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5429 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5430 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5431 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5432 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5433 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5434 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5435 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5436 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5437 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5438 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5439 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5440 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5441 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5442 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5443 value to program Travis register LVDS_CTRL_4 5444 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5445 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5446 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5447 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5448 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5449 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5450 5451 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5452 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5453 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5454 5455 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5456 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5457 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5458 5459 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5460 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5461 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5462 5463 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5464 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5465 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5466 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5467 5468 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5469 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5470 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5471 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5472 5473 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5474 5475 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 5476 5477 **********************************************************************************************************************/ 5478 5479 // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 5480 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 5481 { 5482 ATOM_COMMON_TABLE_HEADER sHeader; 5483 ULONG ulBootUpEngineClock; 5484 ULONG ulDentistVCOFreq; 5485 ULONG ulBootUpUMAClock; 5486 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5487 ULONG ulBootUpReqDisplayVector; 5488 ULONG ulVBIOSMisc; 5489 ULONG ulGPUCapInfo; 5490 ULONG ulDISP_CLK2Freq; 5491 USHORT usRequestedPWMFreqInHz; 5492 UCHAR ucHtcTmpLmt; 5493 UCHAR ucHtcHystLmt; 5494 ULONG ulReserved2; 5495 ULONG ulSystemConfig; 5496 ULONG ulCPUCapInfo; 5497 ULONG ulReserved3; 5498 USHORT usGPUReservedSysMemSize; 5499 USHORT usExtDispConnInfoOffset; 5500 USHORT usPanelRefreshRateRange; 5501 UCHAR ucMemoryType; 5502 UCHAR ucUMAChannelNumber; 5503 UCHAR strVBIOSMsg[40]; 5504 ATOM_TDP_CONFIG asTdpConfig; 5505 ULONG ulReserved[19]; 5506 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5507 ULONG ulGMCRestoreResetTime; 5508 ULONG ulReserved4; 5509 ULONG ulIdleNClk; 5510 ULONG ulDDR_DLL_PowerUpTime; 5511 ULONG ulDDR_PLL_PowerUpTime; 5512 USHORT usPCIEClkSSPercentage; 5513 USHORT usPCIEClkSSType; 5514 USHORT usLvdsSSPercentage; 5515 USHORT usLvdsSSpreadRateIn10Hz; 5516 USHORT usHDMISSPercentage; 5517 USHORT usHDMISSpreadRateIn10Hz; 5518 USHORT usDVISSPercentage; 5519 USHORT usDVISSpreadRateIn10Hz; 5520 ULONG ulGPUReservedSysMemBaseAddrLo; 5521 ULONG ulGPUReservedSysMemBaseAddrHi; 5522 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 5523 ULONG ulReserved5; 5524 USHORT usMaxLVDSPclkFreqInSingleLink; 5525 UCHAR ucLvdsMisc; 5526 UCHAR ucTravisLVDSVolAdjust; 5527 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5528 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5529 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5530 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5531 UCHAR ucLVDSOffToOnDelay_in4Ms; 5532 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5533 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5534 UCHAR ucMinAllowedBL_Level; 5535 ULONG ulLCDBitDepthControlVal; 5536 ULONG ulNbpStateMemclkFreq[4]; 5537 ULONG ulPSPVersion; 5538 ULONG ulNbpStateNClkFreq[4]; 5539 USHORT usNBPStateVoltage[4]; 5540 USHORT usBootUpNBVoltage; 5541 USHORT usReserved2; 5542 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5543 }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 5544 5545 /********************************************************************************************************************** 5546 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 5547 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5548 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5549 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5550 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 5551 5552 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 5553 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5554 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5555 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5556 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5557 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5558 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5559 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5560 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5561 5562 ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 5563 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 5564 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 5565 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 5566 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 5567 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 5568 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 5569 bit[3]=0: VBIOS fast boot is disable 5570 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 5571 5572 ulGPUCapInfo: bit[0~2]= Reserved 5573 bit[3]=0: Enable AUX HW mode detection logic 5574 =1: Disable AUX HW mode detection logic 5575 bit[4]=0: Disable DFS bypass feature 5576 =1: Enable DFS bypass feature 5577 5578 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5579 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5580 5581 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5582 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5583 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5584 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5585 and enabling VariBri under the driver environment from PP table is optional. 5586 5587 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5588 that BL control from GPU is expected. 5589 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5590 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5591 it's per platform 5592 and enabling VariBri under the driver environment from PP table is optional. 5593 5594 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 5595 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5596 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5597 5598 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5599 =1: PCIE Power Gating Enabled 5600 Bit[1]=0: DDR-DLL shut-down feature disabled. 5601 1: DDR-DLL shut-down feature enabled. 5602 Bit[2]=0: DDR-PLL Power down feature disabled. 5603 1: DDR-PLL Power down feature enabled. 5604 Bit[3]=0: GNB DPM is disabled 5605 =1: GNB DPM is enabled 5606 ulCPUCapInfo: TBD 5607 5608 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5609 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5610 to indicate a range. 5611 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5612 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5613 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5614 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5615 5616 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 5617 ucUMAChannelNumber: System memory channel numbers. 5618 5619 strVBIOSMsg[40]: VBIOS boot up customized message string 5620 5621 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5622 5623 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5624 ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 5625 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5626 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5627 5628 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 5629 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5630 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5631 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5632 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5633 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5634 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5635 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5636 5637 usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 5638 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 5639 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 5640 5641 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5642 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5643 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5644 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5645 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5646 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5647 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 5648 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 5649 value to program Travis register LVDS_CTRL_4 5650 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 5651 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 5652 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5653 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5654 ucLVDSPwrOnDEtoVARY_BL_in4Ms: 5655 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 5656 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 5657 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5658 ucLVDSPwrOffVARY_BLtoDE_in4Ms: 5659 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 5660 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5661 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5662 ucLVDSPwrOffDEtoDIGON_in4Ms: 5663 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 5664 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 5665 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5666 ucLVDSOffToOnDelay_in4Ms: 5667 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 5668 =0 means to use VBIOS default delay which is 125 ( 500ms ). 5669 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5670 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 5671 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 5672 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5673 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5674 5675 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 5676 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 5677 =0 means to use VBIOS default delay which is 0 ( 0ms ). 5678 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 5679 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 5680 5681 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 5682 5683 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 5684 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 5685 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 5686 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 5687 sExtDispConnInfo: Display connector information table provided to VBIOS 5688 5689 **********************************************************************************************************************/ 5690 5691 // this Table is used for Kaveri/Kabini APU 5692 typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 5693 { 5694 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 5695 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 5696 }ATOM_FUSION_SYSTEM_INFO_V2; 5697 5698 5699 typedef struct _ATOM_I2C_REG_INFO 5700 { 5701 UCHAR ucI2cRegIndex; 5702 UCHAR ucI2cRegVal; 5703 }ATOM_I2C_REG_INFO; 5704 5705 // this IntegrateSystemInfoTable is used for Carrizo 5706 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 5707 { 5708 ATOM_COMMON_TABLE_HEADER sHeader; 5709 ULONG ulBootUpEngineClock; 5710 ULONG ulDentistVCOFreq; 5711 ULONG ulBootUpUMAClock; 5712 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 5713 ULONG ulBootUpReqDisplayVector; 5714 ULONG ulVBIOSMisc; 5715 ULONG ulGPUCapInfo; 5716 ULONG ulDISP_CLK2Freq; 5717 USHORT usRequestedPWMFreqInHz; 5718 UCHAR ucHtcTmpLmt; 5719 UCHAR ucHtcHystLmt; 5720 ULONG ulReserved2; 5721 ULONG ulSystemConfig; 5722 ULONG ulCPUCapInfo; 5723 ULONG ulReserved3; 5724 USHORT usGPUReservedSysMemSize; 5725 USHORT usExtDispConnInfoOffset; 5726 USHORT usPanelRefreshRateRange; 5727 UCHAR ucMemoryType; 5728 UCHAR ucUMAChannelNumber; 5729 UCHAR strVBIOSMsg[40]; 5730 ATOM_TDP_CONFIG asTdpConfig; 5731 UCHAR ucExtHDMIReDrvSlvAddr; 5732 UCHAR ucExtHDMIReDrvRegNum; 5733 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 5734 ULONG ulReserved[2]; 5735 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 5736 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 5737 ULONG ulGMCRestoreResetTime; 5738 ULONG ulReserved4; 5739 ULONG ulIdleNClk; 5740 ULONG ulDDR_DLL_PowerUpTime; 5741 ULONG ulDDR_PLL_PowerUpTime; 5742 USHORT usPCIEClkSSPercentage; 5743 USHORT usPCIEClkSSType; 5744 USHORT usLvdsSSPercentage; 5745 USHORT usLvdsSSpreadRateIn10Hz; 5746 USHORT usHDMISSPercentage; 5747 USHORT usHDMISSpreadRateIn10Hz; 5748 USHORT usDVISSPercentage; 5749 USHORT usDVISSpreadRateIn10Hz; 5750 ULONG ulGPUReservedSysMemBaseAddrLo; 5751 ULONG ulGPUReservedSysMemBaseAddrHi; 5752 ULONG ulReserved5[3]; 5753 USHORT usMaxLVDSPclkFreqInSingleLink; 5754 UCHAR ucLvdsMisc; 5755 UCHAR ucTravisLVDSVolAdjust; 5756 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5757 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5758 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5759 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5760 UCHAR ucLVDSOffToOnDelay_in4Ms; 5761 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5762 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5763 UCHAR ucMinAllowedBL_Level; 5764 ULONG ulLCDBitDepthControlVal; 5765 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 5766 ULONG ulPSPVersion; 5767 ULONG ulNbpStateNClkFreq[4]; 5768 USHORT usNBPStateVoltage[4]; 5769 USHORT usBootUpNBVoltage; 5770 UCHAR ucEDPv1_4VSMode; 5771 UCHAR ucReserved2; 5772 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5773 }ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 5774 5775 5776 // definition for ucEDPv1_4VSMode 5777 #define EDP_VS_LEGACY_MODE 0 5778 #define EDP_VS_LOW_VDIFF_MODE 1 5779 #define EDP_VS_HIGH_VDIFF_MODE 2 5780 #define EDP_VS_STRETCH_MODE 3 5781 #define EDP_VS_SINGLE_VDIFF_MODE 4 5782 #define EDP_VS_VARIABLE_PREM_MODE 5 5783 5784 5785 // this IntegrateSystemInfoTable is used for Carrizo 5786 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 5787 { 5788 ATOM_COMMON_TABLE_HEADER sHeader; 5789 ULONG ulBootUpEngineClock; 5790 ULONG ulDentistVCOFreq; 5791 ULONG ulBootUpUMAClock; 5792 ULONG ulReserved0[8]; 5793 ULONG ulBootUpReqDisplayVector; 5794 ULONG ulVBIOSMisc; 5795 ULONG ulGPUCapInfo; 5796 ULONG ulReserved1; 5797 USHORT usRequestedPWMFreqInHz; 5798 UCHAR ucHtcTmpLmt; 5799 UCHAR ucHtcHystLmt; 5800 ULONG ulReserved2; 5801 ULONG ulSystemConfig; 5802 ULONG ulCPUCapInfo; 5803 ULONG ulReserved3; 5804 USHORT usGPUReservedSysMemSize; 5805 USHORT usExtDispConnInfoOffset; 5806 USHORT usPanelRefreshRateRange; 5807 UCHAR ucMemoryType; 5808 UCHAR ucUMAChannelNumber; 5809 UCHAR strVBIOSMsg[40]; 5810 ATOM_TDP_CONFIG asTdpConfig; 5811 ULONG ulReserved[7]; 5812 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 5813 ULONG ulReserved6[10]; 5814 ULONG ulGMCRestoreResetTime; 5815 ULONG ulReserved4; 5816 ULONG ulIdleNClk; 5817 ULONG ulDDR_DLL_PowerUpTime; 5818 ULONG ulDDR_PLL_PowerUpTime; 5819 USHORT usPCIEClkSSPercentage; 5820 USHORT usPCIEClkSSType; 5821 USHORT usLvdsSSPercentage; 5822 USHORT usLvdsSSpreadRateIn10Hz; 5823 USHORT usHDMISSPercentage; 5824 USHORT usHDMISSpreadRateIn10Hz; 5825 USHORT usDVISSPercentage; 5826 USHORT usDVISSpreadRateIn10Hz; 5827 ULONG ulGPUReservedSysMemBaseAddrLo; 5828 ULONG ulGPUReservedSysMemBaseAddrHi; 5829 ULONG ulReserved5[3]; 5830 USHORT usMaxLVDSPclkFreqInSingleLink; 5831 UCHAR ucLvdsMisc; 5832 UCHAR ucTravisLVDSVolAdjust; 5833 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5834 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5835 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5836 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5837 UCHAR ucLVDSOffToOnDelay_in4Ms; 5838 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5839 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5840 UCHAR ucMinAllowedBL_Level; 5841 ULONG ulLCDBitDepthControlVal; 5842 ULONG ulNbpStateMemclkFreq[2]; 5843 ULONG ulReserved7[2]; 5844 ULONG ulPSPVersion; 5845 ULONG ulNbpStateNClkFreq[4]; 5846 USHORT usNBPStateVoltage[4]; 5847 USHORT usBootUpNBVoltage; 5848 UCHAR ucEDPv1_4VSMode; 5849 UCHAR ucReserved2; 5850 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5851 }ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 5852 5853 /**************************************************************************/ 5854 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 5855 //Memory SS Info Table 5856 //Define Memory Clock SS chip ID 5857 #define ICS91719 1 5858 #define ICS91720 2 5859 5860 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 5861 typedef struct _ATOM_I2C_DATA_RECORD 5862 { 5863 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 5864 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 5865 }ATOM_I2C_DATA_RECORD; 5866 5867 5868 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 5869 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 5870 { 5871 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 5872 UCHAR ucSSChipID; //SS chip being used 5873 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 5874 UCHAR ucNumOfI2CDataRecords; //number of data block 5875 ATOM_I2C_DATA_RECORD asI2CData[1]; 5876 }ATOM_I2C_DEVICE_SETUP_INFO; 5877 5878 //========================================================================================== 5879 typedef struct _ATOM_ASIC_MVDD_INFO 5880 { 5881 ATOM_COMMON_TABLE_HEADER sHeader; 5882 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 5883 }ATOM_ASIC_MVDD_INFO; 5884 5885 //========================================================================================== 5886 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 5887 5888 //========================================================================================== 5889 /**************************************************************************/ 5890 5891 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 5892 { 5893 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 5894 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5895 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 5896 UCHAR ucClockIndication; //Indicate which clock source needs SS 5897 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 5898 UCHAR ucReserved[2]; 5899 }ATOM_ASIC_SS_ASSIGNMENT; 5900 5901 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 5902 //SS is not required or enabled if a match is not found. 5903 #define ASIC_INTERNAL_MEMORY_SS 1 5904 #define ASIC_INTERNAL_ENGINE_SS 2 5905 #define ASIC_INTERNAL_UVD_SS 3 5906 #define ASIC_INTERNAL_SS_ON_TMDS 4 5907 #define ASIC_INTERNAL_SS_ON_HDMI 5 5908 #define ASIC_INTERNAL_SS_ON_LVDS 6 5909 #define ASIC_INTERNAL_SS_ON_DP 7 5910 #define ASIC_INTERNAL_SS_ON_DCPLL 8 5911 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 5912 #define ASIC_INTERNAL_VCE_SS 10 5913 #define ASIC_INTERNAL_GPUPLL_SS 11 5914 5915 5916 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 5917 { 5918 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5919 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5920 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 5921 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5922 UCHAR ucClockIndication; //Indicate which clock source needs SS 5923 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5924 UCHAR ucReserved[2]; 5925 }ATOM_ASIC_SS_ASSIGNMENT_V2; 5926 5927 //ucSpreadSpectrumMode 5928 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 5929 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 5930 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 5931 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 5932 //#define ATOM_INTERNAL_SS_MASK 0x00000000 5933 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 5934 5935 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 5936 { 5937 ATOM_COMMON_TABLE_HEADER sHeader; 5938 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 5939 }ATOM_ASIC_INTERNAL_SS_INFO; 5940 5941 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 5942 { 5943 ATOM_COMMON_TABLE_HEADER sHeader; 5944 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 5945 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 5946 5947 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 5948 { 5949 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 5950 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 5951 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 5952 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 5953 UCHAR ucClockIndication; //Indicate which clock source needs SS 5954 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 5955 UCHAR ucReserved[2]; 5956 }ATOM_ASIC_SS_ASSIGNMENT_V3; 5957 5958 //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 5959 #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 5960 #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 5961 #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 5962 5963 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 5964 { 5965 ATOM_COMMON_TABLE_HEADER sHeader; 5966 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 5967 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 5968 5969 5970 //==============================Scratch Pad Definition Portion=============================== 5971 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 5972 #define ATOM_ROM_LOCATION_DEF 1 5973 #define ATOM_TV_STANDARD_DEF 2 5974 #define ATOM_ACTIVE_INFO_DEF 3 5975 #define ATOM_LCD_INFO_DEF 4 5976 #define ATOM_DOS_REQ_INFO_DEF 5 5977 #define ATOM_ACC_CHANGE_INFO_DEF 6 5978 #define ATOM_DOS_MODE_INFO_DEF 7 5979 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 5980 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 5981 #define ATOM_INTERNAL_TIMER_DEF 10 5982 5983 // BIOS_0_SCRATCH Definition 5984 #define ATOM_S0_CRT1_MONO 0x00000001L 5985 #define ATOM_S0_CRT1_COLOR 0x00000002L 5986 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 5987 5988 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 5989 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 5990 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 5991 5992 #define ATOM_S0_CV_A 0x00000010L 5993 #define ATOM_S0_CV_DIN_A 0x00000020L 5994 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 5995 5996 5997 #define ATOM_S0_CRT2_MONO 0x00000100L 5998 #define ATOM_S0_CRT2_COLOR 0x00000200L 5999 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6000 6001 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 6002 #define ATOM_S0_TV1_SVIDEO 0x00000800L 6003 #define ATOM_S0_TV1_SCART 0x00004000L 6004 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6005 6006 #define ATOM_S0_CV 0x00001000L 6007 #define ATOM_S0_CV_DIN 0x00002000L 6008 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6009 6010 #define ATOM_S0_DFP1 0x00010000L 6011 #define ATOM_S0_DFP2 0x00020000L 6012 #define ATOM_S0_LCD1 0x00040000L 6013 #define ATOM_S0_LCD2 0x00080000L 6014 #define ATOM_S0_DFP6 0x00100000L 6015 #define ATOM_S0_DFP3 0x00200000L 6016 #define ATOM_S0_DFP4 0x00400000L 6017 #define ATOM_S0_DFP5 0x00800000L 6018 6019 6020 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6021 6022 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6023 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6024 6025 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6026 #define ATOM_S0_THERMAL_STATE_SHIFT 26 6027 6028 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6029 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6030 6031 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6032 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6033 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6034 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6035 6036 //Byte aligned defintion for BIOS usage 6037 #define ATOM_S0_CRT1_MONOb0 0x01 6038 #define ATOM_S0_CRT1_COLORb0 0x02 6039 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6040 6041 #define ATOM_S0_TV1_COMPOSITEb0 0x04 6042 #define ATOM_S0_TV1_SVIDEOb0 0x08 6043 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6044 6045 #define ATOM_S0_CVb0 0x10 6046 #define ATOM_S0_CV_DINb0 0x20 6047 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6048 6049 #define ATOM_S0_CRT2_MONOb1 0x01 6050 #define ATOM_S0_CRT2_COLORb1 0x02 6051 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6052 6053 #define ATOM_S0_TV1_COMPOSITEb1 0x04 6054 #define ATOM_S0_TV1_SVIDEOb1 0x08 6055 #define ATOM_S0_TV1_SCARTb1 0x40 6056 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6057 6058 #define ATOM_S0_CVb1 0x10 6059 #define ATOM_S0_CV_DINb1 0x20 6060 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6061 6062 #define ATOM_S0_DFP1b2 0x01 6063 #define ATOM_S0_DFP2b2 0x02 6064 #define ATOM_S0_LCD1b2 0x04 6065 #define ATOM_S0_LCD2b2 0x08 6066 #define ATOM_S0_DFP6b2 0x10 6067 #define ATOM_S0_DFP3b2 0x20 6068 #define ATOM_S0_DFP4b2 0x40 6069 #define ATOM_S0_DFP5b2 0x80 6070 6071 6072 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6073 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6074 6075 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6076 #define ATOM_S0_LCD1_SHIFT 18 6077 6078 // BIOS_1_SCRATCH Definition 6079 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6080 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6081 6082 // BIOS_2_SCRATCH Definition 6083 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6084 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6085 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6086 6087 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6088 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6089 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6090 6091 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6092 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6093 6094 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6095 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6096 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6097 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6098 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6099 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6100 6101 6102 //Byte aligned defintion for BIOS usage 6103 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6104 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6105 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6106 6107 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6108 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6109 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6110 6111 6112 // BIOS_3_SCRATCH Definition 6113 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 6114 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 6115 #define ATOM_S3_TV1_ACTIVE 0x00000004L 6116 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 6117 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 6118 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 6119 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 6120 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 6121 #define ATOM_S3_CV_ACTIVE 0x00000100L 6122 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 6123 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 6124 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 6125 6126 6127 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6128 6129 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6130 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6131 6132 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6133 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6134 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6135 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6136 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6137 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6138 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6139 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6140 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6141 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6142 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6143 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6144 6145 6146 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6147 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6148 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 6149 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6150 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6151 6152 6153 6154 //Byte aligned defintion for BIOS usage 6155 #define ATOM_S3_CRT1_ACTIVEb0 0x01 6156 #define ATOM_S3_LCD1_ACTIVEb0 0x02 6157 #define ATOM_S3_TV1_ACTIVEb0 0x04 6158 #define ATOM_S3_DFP1_ACTIVEb0 0x08 6159 #define ATOM_S3_CRT2_ACTIVEb0 0x10 6160 #define ATOM_S3_LCD2_ACTIVEb0 0x20 6161 #define ATOM_S3_DFP6_ACTIVEb0 0x40 6162 #define ATOM_S3_DFP2_ACTIVEb0 0x80 6163 #define ATOM_S3_CV_ACTIVEb1 0x01 6164 #define ATOM_S3_DFP3_ACTIVEb1 0x02 6165 #define ATOM_S3_DFP4_ACTIVEb1 0x04 6166 #define ATOM_S3_DFP5_ACTIVEb1 0x08 6167 6168 6169 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6170 6171 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6172 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6173 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6174 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6175 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6176 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6177 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6178 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6179 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6180 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6181 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6182 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6183 6184 6185 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6186 6187 6188 // BIOS_4_SCRATCH Definition 6189 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6190 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6191 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 6192 6193 //Byte aligned defintion for BIOS usage 6194 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6195 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6196 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6197 6198 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6199 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 6200 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 6201 #define ATOM_S5_DOS_REQ_TV1b0 0x04 6202 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 6203 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 6204 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 6205 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 6206 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 6207 #define ATOM_S5_DOS_REQ_CVb1 0x01 6208 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 6209 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 6210 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 6211 6212 6213 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6214 6215 #define ATOM_S5_DOS_REQ_CRT1 0x0001 6216 #define ATOM_S5_DOS_REQ_LCD1 0x0002 6217 #define ATOM_S5_DOS_REQ_TV1 0x0004 6218 #define ATOM_S5_DOS_REQ_DFP1 0x0008 6219 #define ATOM_S5_DOS_REQ_CRT2 0x0010 6220 #define ATOM_S5_DOS_REQ_LCD2 0x0020 6221 #define ATOM_S5_DOS_REQ_DFP6 0x0040 6222 #define ATOM_S5_DOS_REQ_DFP2 0x0080 6223 #define ATOM_S5_DOS_REQ_CV 0x0100 6224 #define ATOM_S5_DOS_REQ_DFP3 0x0200 6225 #define ATOM_S5_DOS_REQ_DFP4 0x0400 6226 #define ATOM_S5_DOS_REQ_DFP5 0x0800 6227 6228 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6229 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6230 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6231 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6232 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6233 (ATOM_S5_DOS_FORCE_CVb3<<8)) 6234 // BIOS_6_SCRATCH Definition 6235 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 6236 #define ATOM_S6_SCALER_CHANGE 0x00000002L 6237 #define ATOM_S6_LID_CHANGE 0x00000004L 6238 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 6239 #define ATOM_S6_ACC_MODE 0x00000010L 6240 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6241 #define ATOM_S6_LID_STATE 0x00000040L 6242 #define ATOM_S6_DOCK_STATE 0x00000080L 6243 #define ATOM_S6_CRITICAL_STATE 0x00000100L 6244 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6245 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6246 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6247 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6248 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6249 6250 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6251 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6252 6253 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6254 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6255 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 6256 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6257 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6258 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 6259 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 6260 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 6261 #define ATOM_S6_ACC_REQ_CV 0x01000000L 6262 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 6263 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 6264 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 6265 6266 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 6267 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 6268 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 6269 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 6270 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 6271 6272 //Byte aligned defintion for BIOS usage 6273 #define ATOM_S6_DEVICE_CHANGEb0 0x01 6274 #define ATOM_S6_SCALER_CHANGEb0 0x02 6275 #define ATOM_S6_LID_CHANGEb0 0x04 6276 #define ATOM_S6_DOCKING_CHANGEb0 0x08 6277 #define ATOM_S6_ACC_MODEb0 0x10 6278 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 6279 #define ATOM_S6_LID_STATEb0 0x40 6280 #define ATOM_S6_DOCK_STATEb0 0x80 6281 #define ATOM_S6_CRITICAL_STATEb1 0x01 6282 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 6283 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 6284 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 6285 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 6286 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 6287 6288 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 6289 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 6290 #define ATOM_S6_ACC_REQ_TV1b2 0x04 6291 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 6292 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 6293 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 6294 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 6295 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 6296 #define ATOM_S6_ACC_REQ_CVb3 0x01 6297 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 6298 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 6299 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 6300 6301 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 6302 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 6303 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 6304 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 6305 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 6306 6307 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 6308 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 6309 #define ATOM_S6_LID_CHANGE_SHIFT 2 6310 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 6311 #define ATOM_S6_ACC_MODE_SHIFT 4 6312 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 6313 #define ATOM_S6_LID_STATE_SHIFT 6 6314 #define ATOM_S6_DOCK_STATE_SHIFT 7 6315 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 6316 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 6317 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 6318 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 6319 #define ATOM_S6_REQ_SCALER_SHIFT 12 6320 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 6321 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 6322 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 6323 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 6324 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 6325 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 6326 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 6327 6328 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 6329 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 6330 #define ATOM_S7_DOS_MODE_VGAb0 0x00 6331 #define ATOM_S7_DOS_MODE_VESAb0 0x01 6332 #define ATOM_S7_DOS_MODE_EXTb0 0x02 6333 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 6334 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 6335 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 6336 #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 6337 #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 6338 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 6339 6340 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 6341 6342 // BIOS_8_SCRATCH Definition 6343 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 6344 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 6345 6346 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 6347 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 6348 6349 // BIOS_9_SCRATCH Definition 6350 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 6351 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 6352 #endif 6353 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 6354 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 6355 #endif 6356 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 6357 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 6358 #endif 6359 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 6360 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 6361 #endif 6362 6363 6364 #define ATOM_FLAG_SET 0x20 6365 #define ATOM_FLAG_CLEAR 0 6366 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 6367 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 6368 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 6369 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 6370 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 6371 6372 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 6373 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 6374 6375 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 6376 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 6377 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 6378 6379 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 6380 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 6381 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 6382 6383 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 6384 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 6385 6386 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 6387 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 6388 6389 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 6390 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 6391 6392 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 6393 6394 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 6395 6396 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 6397 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 6398 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 6399 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 6400 6401 /****************************************************************************/ 6402 //Portion II: Definitinos only used in Driver 6403 /****************************************************************************/ 6404 6405 // Macros used by driver 6406 6407 #ifdef __cplusplus 6408 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 6409 6410 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 6411 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 6412 #else // not __cplusplus 6413 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 6414 6415 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 6416 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 6417 #endif // __cplusplus 6418 6419 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 6420 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 6421 6422 /****************************************************************************/ 6423 //Portion III: Definitinos only used in VBIOS 6424 /****************************************************************************/ 6425 #define ATOM_DAC_SRC 0x80 6426 #define ATOM_SRC_DAC1 0 6427 #define ATOM_SRC_DAC2 0x80 6428 6429 6430 6431 typedef struct _MEMORY_PLLINIT_PARAMETERS 6432 { 6433 ULONG ulTargetMemoryClock; //In 10Khz unit 6434 UCHAR ucAction; //not define yet 6435 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 6436 UCHAR ucFbDiv; //FB value 6437 UCHAR ucPostDiv; //Post div 6438 }MEMORY_PLLINIT_PARAMETERS; 6439 6440 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 6441 6442 6443 #define GPIO_PIN_WRITE 0x01 6444 #define GPIO_PIN_READ 0x00 6445 6446 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 6447 { 6448 UCHAR ucGPIO_ID; //return value, read from GPIO pins 6449 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 6450 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 6451 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 6452 }GPIO_PIN_CONTROL_PARAMETERS; 6453 6454 typedef struct _ENABLE_SCALER_PARAMETERS 6455 { 6456 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 6457 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 6458 UCHAR ucTVStandard; // 6459 UCHAR ucPadding[1]; 6460 }ENABLE_SCALER_PARAMETERS; 6461 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 6462 6463 //ucEnable: 6464 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 6465 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 6466 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 6467 #define SCALER_ENABLE_MULTITAP_MODE 3 6468 6469 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 6470 { 6471 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 6472 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 6473 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 6474 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 6475 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6476 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 6477 6478 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 6479 { 6480 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 6481 ENABLE_CRTC_PARAMETERS sReserved; 6482 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 6483 6484 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 6485 { 6486 USHORT usHight; // Image Hight 6487 USHORT usWidth; // Image Width 6488 UCHAR ucSurface; // Surface 1 or 2 6489 UCHAR ucPadding[3]; 6490 }ENABLE_GRAPH_SURFACE_PARAMETERS; 6491 6492 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 6493 { 6494 USHORT usHight; // Image Hight 6495 USHORT usWidth; // Image Width 6496 UCHAR ucSurface; // Surface 1 or 2 6497 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6498 UCHAR ucPadding[2]; 6499 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 6500 6501 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 6502 { 6503 USHORT usHight; // Image Hight 6504 USHORT usWidth; // Image Width 6505 UCHAR ucSurface; // Surface 1 or 2 6506 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6507 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 6508 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 6509 6510 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 6511 { 6512 USHORT usHight; // Image Hight 6513 USHORT usWidth; // Image Width 6514 USHORT usGraphPitch; 6515 UCHAR ucColorDepth; 6516 UCHAR ucPixelFormat; 6517 UCHAR ucSurface; // Surface 1 or 2 6518 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 6519 UCHAR ucModeType; 6520 UCHAR ucReserved; 6521 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 6522 6523 // ucEnable 6524 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 6525 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 6526 6527 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 6528 { 6529 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 6530 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 6531 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 6532 6533 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 6534 { 6535 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 6536 USHORT usMemorySize; //8Kb blocks aligned 6537 }MEMORY_CLEAN_UP_PARAMETERS; 6538 6539 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 6540 6541 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 6542 { 6543 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6544 USHORT usY_Size; 6545 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 6546 6547 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 6548 { 6549 union{ 6550 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 6551 USHORT usSurface; 6552 }; 6553 USHORT usY_Size; 6554 USHORT usDispXStart; 6555 USHORT usDispYStart; 6556 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 6557 6558 6559 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 6560 { 6561 UCHAR ucLutId; 6562 UCHAR ucAction; 6563 USHORT usLutStartIndex; 6564 USHORT usLutLength; 6565 USHORT usLutOffsetInVram; 6566 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 6567 6568 // ucAction: 6569 #define PALETTE_DATA_AUTO_FILL 1 6570 #define PALETTE_DATA_READ 2 6571 #define PALETTE_DATA_WRITE 3 6572 6573 6574 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 6575 { 6576 UCHAR ucInterruptId; 6577 UCHAR ucServiceId; 6578 UCHAR ucStatus; 6579 UCHAR ucReserved; 6580 }INTERRUPT_SERVICE_PARAMETER_V2; 6581 6582 // ucInterruptId 6583 #define HDP1_INTERRUPT_ID 1 6584 #define HDP2_INTERRUPT_ID 2 6585 #define HDP3_INTERRUPT_ID 3 6586 #define HDP4_INTERRUPT_ID 4 6587 #define HDP5_INTERRUPT_ID 5 6588 #define HDP6_INTERRUPT_ID 6 6589 #define SW_INTERRUPT_ID 11 6590 6591 // ucAction 6592 #define INTERRUPT_SERVICE_GEN_SW_INT 1 6593 #define INTERRUPT_SERVICE_GET_STATUS 2 6594 6595 // ucStatus 6596 #define INTERRUPT_STATUS__INT_TRIGGER 1 6597 #define INTERRUPT_STATUS__HPD_HIGH 2 6598 6599 typedef struct _EFUSE_INPUT_PARAMETER 6600 { 6601 USHORT usEfuseIndex; 6602 UCHAR ucBitShift; 6603 UCHAR ucBitLength; 6604 }EFUSE_INPUT_PARAMETER; 6605 6606 // ReadEfuseValue command table input/output parameter 6607 typedef union _READ_EFUSE_VALUE_PARAMETER 6608 { 6609 EFUSE_INPUT_PARAMETER sEfuse; 6610 ULONG ulEfuseValue; 6611 }READ_EFUSE_VALUE_PARAMETER; 6612 6613 typedef struct _INDIRECT_IO_ACCESS 6614 { 6615 ATOM_COMMON_TABLE_HEADER sHeader; 6616 UCHAR IOAccessSequence[256]; 6617 } INDIRECT_IO_ACCESS; 6618 6619 #define INDIRECT_READ 0x00 6620 #define INDIRECT_WRITE 0x80 6621 6622 #define INDIRECT_IO_MM 0 6623 #define INDIRECT_IO_PLL 1 6624 #define INDIRECT_IO_MC 2 6625 #define INDIRECT_IO_PCIE 3 6626 #define INDIRECT_IO_PCIEP 4 6627 #define INDIRECT_IO_NBMISC 5 6628 #define INDIRECT_IO_SMU 5 6629 6630 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 6631 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 6632 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 6633 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 6634 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 6635 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 6636 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 6637 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 6638 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 6639 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 6640 #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 6641 #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 6642 6643 6644 typedef struct _ATOM_OEM_INFO 6645 { 6646 ATOM_COMMON_TABLE_HEADER sHeader; 6647 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 6648 }ATOM_OEM_INFO; 6649 6650 typedef struct _ATOM_TV_MODE 6651 { 6652 UCHAR ucVMode_Num; //Video mode number 6653 UCHAR ucTV_Mode_Num; //Internal TV mode number 6654 }ATOM_TV_MODE; 6655 6656 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 6657 { 6658 ATOM_COMMON_TABLE_HEADER sHeader; 6659 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 6660 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 6661 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 6662 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6663 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 6664 }ATOM_BIOS_INT_TVSTD_MODE; 6665 6666 6667 typedef struct _ATOM_TV_MODE_SCALER_PTR 6668 { 6669 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 6670 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 6671 UCHAR ucTV_Mode_Num; 6672 }ATOM_TV_MODE_SCALER_PTR; 6673 6674 typedef struct _ATOM_STANDARD_VESA_TIMING 6675 { 6676 ATOM_COMMON_TABLE_HEADER sHeader; 6677 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 6678 }ATOM_STANDARD_VESA_TIMING; 6679 6680 6681 typedef struct _ATOM_STD_FORMAT 6682 { 6683 USHORT usSTD_HDisp; 6684 USHORT usSTD_VDisp; 6685 USHORT usSTD_RefreshRate; 6686 USHORT usReserved; 6687 }ATOM_STD_FORMAT; 6688 6689 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 6690 { 6691 USHORT usVESA_ModeNumber; 6692 USHORT usExtendedModeNumber; 6693 }ATOM_VESA_TO_EXTENDED_MODE; 6694 6695 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 6696 { 6697 ATOM_COMMON_TABLE_HEADER sHeader; 6698 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 6699 }ATOM_VESA_TO_INTENAL_MODE_LUT; 6700 6701 /*************** ATOM Memory Related Data Structure ***********************/ 6702 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 6703 UCHAR ucMemoryType; 6704 UCHAR ucMemoryVendor; 6705 UCHAR ucAdjMCId; 6706 UCHAR ucDynClkId; 6707 ULONG ulDllResetClkRange; 6708 }ATOM_MEMORY_VENDOR_BLOCK; 6709 6710 6711 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 6712 #if ATOM_BIG_ENDIAN 6713 ULONG ucMemBlkId:8; 6714 ULONG ulMemClockRange:24; 6715 #else 6716 ULONG ulMemClockRange:24; 6717 ULONG ucMemBlkId:8; 6718 #endif 6719 }ATOM_MEMORY_SETTING_ID_CONFIG; 6720 6721 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 6722 { 6723 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 6724 ULONG ulAccess; 6725 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 6726 6727 6728 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 6729 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 6730 ULONG aulMemData[1]; 6731 }ATOM_MEMORY_SETTING_DATA_BLOCK; 6732 6733 6734 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 6735 USHORT usRegIndex; // MC register index 6736 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 6737 }ATOM_INIT_REG_INDEX_FORMAT; 6738 6739 6740 typedef struct _ATOM_INIT_REG_BLOCK{ 6741 USHORT usRegIndexTblSize; //size of asRegIndexBuf 6742 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 6743 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 6744 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 6745 }ATOM_INIT_REG_BLOCK; 6746 6747 #define END_OF_REG_INDEX_BLOCK 0x0ffff 6748 #define END_OF_REG_DATA_BLOCK 0x00000000 6749 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 6750 #define CLOCK_RANGE_HIGHEST 0x00ffffff 6751 6752 #define VALUE_DWORD SIZEOF ULONG 6753 #define VALUE_SAME_AS_ABOVE 0 6754 #define VALUE_MASK_DWORD 0x84 6755 6756 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 6757 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 6758 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 6759 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 6760 #define ACCESS_PLACEHOLDER 0x80 6761 6762 6763 typedef struct _ATOM_MC_INIT_PARAM_TABLE 6764 { 6765 ATOM_COMMON_TABLE_HEADER sHeader; 6766 USHORT usAdjustARB_SEQDataOffset; 6767 USHORT usMCInitMemTypeTblOffset; 6768 USHORT usMCInitCommonTblOffset; 6769 USHORT usMCInitPowerDownTblOffset; 6770 ULONG ulARB_SEQDataBuf[32]; 6771 ATOM_INIT_REG_BLOCK asMCInitMemType; 6772 ATOM_INIT_REG_BLOCK asMCInitCommon; 6773 }ATOM_MC_INIT_PARAM_TABLE; 6774 6775 6776 typedef struct _ATOM_REG_INIT_SETTING 6777 { 6778 USHORT usRegIndex; 6779 ULONG ulRegValue; 6780 }ATOM_REG_INIT_SETTING; 6781 6782 typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 6783 { 6784 ATOM_COMMON_TABLE_HEADER sHeader; 6785 ULONG ulMCUcodeVersion; 6786 ULONG ulMCUcodeRomStartAddr; 6787 ULONG ulMCUcodeLength; 6788 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 6789 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 6790 }ATOM_MC_INIT_PARAM_TABLE_V2_1; 6791 6792 6793 #define _4Mx16 0x2 6794 #define _4Mx32 0x3 6795 #define _8Mx16 0x12 6796 #define _8Mx32 0x13 6797 #define _8Mx128 0x15 6798 #define _16Mx16 0x22 6799 #define _16Mx32 0x23 6800 #define _16Mx128 0x25 6801 #define _32Mx16 0x32 6802 #define _32Mx32 0x33 6803 #define _32Mx128 0x35 6804 #define _64Mx32 0x43 6805 #define _64Mx8 0x41 6806 #define _64Mx16 0x42 6807 #define _128Mx8 0x51 6808 #define _128Mx16 0x52 6809 #define _128Mx32 0x53 6810 #define _256Mx8 0x61 6811 #define _256Mx16 0x62 6812 #define _512Mx8 0x71 6813 6814 6815 #define SAMSUNG 0x1 6816 #define INFINEON 0x2 6817 #define ELPIDA 0x3 6818 #define ETRON 0x4 6819 #define NANYA 0x5 6820 #define HYNIX 0x6 6821 #define MOSEL 0x7 6822 #define WINBOND 0x8 6823 #define ESMT 0x9 6824 #define MICRON 0xF 6825 6826 #define QIMONDA INFINEON 6827 #define PROMOS MOSEL 6828 #define KRETON INFINEON 6829 #define ELIXIR NANYA 6830 #define MEZZA ELPIDA 6831 6832 6833 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 6834 6835 #define UCODE_ROM_START_ADDRESS 0x1b800 6836 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 6837 6838 //uCode block header for reference 6839 6840 typedef struct _MCuCodeHeader 6841 { 6842 ULONG ulSignature; 6843 UCHAR ucRevision; 6844 UCHAR ucChecksum; 6845 UCHAR ucReserved1; 6846 UCHAR ucReserved2; 6847 USHORT usParametersLength; 6848 USHORT usUCodeLength; 6849 USHORT usReserved1; 6850 USHORT usReserved2; 6851 } MCuCodeHeader; 6852 6853 ////////////////////////////////////////////////////////////////////////////////// 6854 6855 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 6856 6857 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 6858 typedef struct _ATOM_VRAM_MODULE_V1 6859 { 6860 ULONG ulReserved; 6861 USHORT usEMRSValue; 6862 USHORT usMRSValue; 6863 USHORT usReserved; 6864 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6865 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 6866 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 6867 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6868 UCHAR ucRow; // Number of Row,in power of 2; 6869 UCHAR ucColumn; // Number of Column,in power of 2; 6870 UCHAR ucBank; // Nunber of Bank; 6871 UCHAR ucRank; // Number of Rank, in power of 2 6872 UCHAR ucChannelNum; // Number of channel; 6873 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6874 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6875 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6876 UCHAR ucReserved[2]; 6877 }ATOM_VRAM_MODULE_V1; 6878 6879 6880 typedef struct _ATOM_VRAM_MODULE_V2 6881 { 6882 ULONG ulReserved; 6883 ULONG ulFlags; // To enable/disable functionalities based on memory type 6884 ULONG ulEngineClock; // Override of default engine clock for particular memory type 6885 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 6886 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 6887 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 6888 USHORT usEMRSValue; 6889 USHORT usMRSValue; 6890 USHORT usReserved; 6891 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 6892 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 6893 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 6894 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 6895 UCHAR ucRow; // Number of Row,in power of 2; 6896 UCHAR ucColumn; // Number of Column,in power of 2; 6897 UCHAR ucBank; // Nunber of Bank; 6898 UCHAR ucRank; // Number of Rank, in power of 2 6899 UCHAR ucChannelNum; // Number of channel; 6900 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 6901 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 6902 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 6903 UCHAR ucRefreshRateFactor; 6904 UCHAR ucReserved[3]; 6905 }ATOM_VRAM_MODULE_V2; 6906 6907 6908 typedef struct _ATOM_MEMORY_TIMING_FORMAT 6909 { 6910 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6911 union{ 6912 USHORT usMRS; // mode register 6913 USHORT usDDR3_MR0; 6914 }; 6915 union{ 6916 USHORT usEMRS; // extended mode register 6917 USHORT usDDR3_MR1; 6918 }; 6919 UCHAR ucCL; // CAS latency 6920 UCHAR ucWL; // WRITE Latency 6921 UCHAR uctRAS; // tRAS 6922 UCHAR uctRC; // tRC 6923 UCHAR uctRFC; // tRFC 6924 UCHAR uctRCDR; // tRCDR 6925 UCHAR uctRCDW; // tRCDW 6926 UCHAR uctRP; // tRP 6927 UCHAR uctRRD; // tRRD 6928 UCHAR uctWR; // tWR 6929 UCHAR uctWTR; // tWTR 6930 UCHAR uctPDIX; // tPDIX 6931 UCHAR uctFAW; // tFAW 6932 UCHAR uctAOND; // tAOND 6933 union 6934 { 6935 struct { 6936 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6937 UCHAR ucReserved; 6938 }; 6939 USHORT usDDR3_MR2; 6940 }; 6941 }ATOM_MEMORY_TIMING_FORMAT; 6942 6943 6944 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 6945 { 6946 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6947 USHORT usMRS; // mode register 6948 USHORT usEMRS; // extended mode register 6949 UCHAR ucCL; // CAS latency 6950 UCHAR ucWL; // WRITE Latency 6951 UCHAR uctRAS; // tRAS 6952 UCHAR uctRC; // tRC 6953 UCHAR uctRFC; // tRFC 6954 UCHAR uctRCDR; // tRCDR 6955 UCHAR uctRCDW; // tRCDW 6956 UCHAR uctRP; // tRP 6957 UCHAR uctRRD; // tRRD 6958 UCHAR uctWR; // tWR 6959 UCHAR uctWTR; // tWTR 6960 UCHAR uctPDIX; // tPDIX 6961 UCHAR uctFAW; // tFAW 6962 UCHAR uctAOND; // tAOND 6963 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 6964 ////////////////////////////////////GDDR parameters/////////////////////////////////// 6965 UCHAR uctCCDL; // 6966 UCHAR uctCRCRL; // 6967 UCHAR uctCRCWL; // 6968 UCHAR uctCKE; // 6969 UCHAR uctCKRSE; // 6970 UCHAR uctCKRSX; // 6971 UCHAR uctFAW32; // 6972 UCHAR ucMR5lo; // 6973 UCHAR ucMR5hi; // 6974 UCHAR ucTerminator; 6975 }ATOM_MEMORY_TIMING_FORMAT_V1; 6976 6977 6978 6979 6980 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 6981 { 6982 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 6983 USHORT usMRS; // mode register 6984 USHORT usEMRS; // extended mode register 6985 UCHAR ucCL; // CAS latency 6986 UCHAR ucWL; // WRITE Latency 6987 UCHAR uctRAS; // tRAS 6988 UCHAR uctRC; // tRC 6989 UCHAR uctRFC; // tRFC 6990 UCHAR uctRCDR; // tRCDR 6991 UCHAR uctRCDW; // tRCDW 6992 UCHAR uctRP; // tRP 6993 UCHAR uctRRD; // tRRD 6994 UCHAR uctWR; // tWR 6995 UCHAR uctWTR; // tWTR 6996 UCHAR uctPDIX; // tPDIX 6997 UCHAR uctFAW; // tFAW 6998 UCHAR uctAOND; // tAOND 6999 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7000 ////////////////////////////////////GDDR parameters/////////////////////////////////// 7001 UCHAR uctCCDL; // 7002 UCHAR uctCRCRL; // 7003 UCHAR uctCRCWL; // 7004 UCHAR uctCKE; // 7005 UCHAR uctCKRSE; // 7006 UCHAR uctCKRSX; // 7007 UCHAR uctFAW32; // 7008 UCHAR ucMR4lo; // 7009 UCHAR ucMR4hi; // 7010 UCHAR ucMR5lo; // 7011 UCHAR ucMR5hi; // 7012 UCHAR ucTerminator; 7013 UCHAR ucReserved; 7014 }ATOM_MEMORY_TIMING_FORMAT_V2; 7015 7016 7017 typedef struct _ATOM_MEMORY_FORMAT 7018 { 7019 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7020 union{ 7021 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7022 USHORT usDDR3_Reserved; // Not used for DDR3 memory 7023 }; 7024 union{ 7025 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7026 USHORT usDDR3_MR3; // Used for DDR3 memory 7027 }; 7028 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7029 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7030 UCHAR ucRow; // Number of Row,in power of 2; 7031 UCHAR ucColumn; // Number of Column,in power of 2; 7032 UCHAR ucBank; // Nunber of Bank; 7033 UCHAR ucRank; // Number of Rank, in power of 2 7034 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7035 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7036 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7037 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7038 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7039 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7040 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7041 }ATOM_MEMORY_FORMAT; 7042 7043 7044 typedef struct _ATOM_VRAM_MODULE_V3 7045 { 7046 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7047 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7048 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7049 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7050 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7051 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7052 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7053 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7054 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7055 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7056 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7057 }ATOM_VRAM_MODULE_V3; 7058 7059 7060 //ATOM_VRAM_MODULE_V3.ucNPL_RT 7061 #define NPL_RT_MASK 0x0f 7062 #define BATTERY_ODT_MASK 0xc0 7063 7064 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7065 7066 typedef struct _ATOM_VRAM_MODULE_V4 7067 { 7068 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7069 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7070 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7071 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7072 USHORT usReserved; 7073 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7074 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7075 UCHAR ucChannelNum; // Number of channels present in this module config 7076 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7077 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7078 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7079 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7080 UCHAR ucVREFI; // board dependent parameter 7081 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7082 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7083 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7084 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7085 UCHAR ucReserved[3]; 7086 7087 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7088 union{ 7089 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7090 USHORT usDDR3_Reserved; 7091 }; 7092 union{ 7093 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7094 USHORT usDDR3_MR3; // Used for DDR3 memory 7095 }; 7096 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7097 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7098 UCHAR ucReserved2[2]; 7099 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7100 }ATOM_VRAM_MODULE_V4; 7101 7102 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7103 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7104 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7105 #define VRAM_MODULE_V4_MISC_BL8 0x4 7106 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7107 7108 typedef struct _ATOM_VRAM_MODULE_V5 7109 { 7110 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7111 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7112 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7113 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7114 USHORT usReserved; 7115 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7116 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7117 UCHAR ucChannelNum; // Number of channels present in this module config 7118 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7119 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7120 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7121 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7122 UCHAR ucVREFI; // board dependent parameter 7123 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7124 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7125 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7126 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7127 UCHAR ucReserved[3]; 7128 7129 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7130 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7131 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7132 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7133 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7134 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7135 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7136 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7137 }ATOM_VRAM_MODULE_V5; 7138 7139 7140 typedef struct _ATOM_VRAM_MODULE_V6 7141 { 7142 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7143 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7144 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7145 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7146 USHORT usReserved; 7147 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7148 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7149 UCHAR ucChannelNum; // Number of channels present in this module config 7150 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7151 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7152 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7153 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7154 UCHAR ucVREFI; // board dependent parameter 7155 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7156 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7157 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7158 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7159 UCHAR ucReserved[3]; 7160 7161 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7162 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7163 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7164 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7165 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7166 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7167 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7168 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7169 }ATOM_VRAM_MODULE_V6; 7170 7171 typedef struct _ATOM_VRAM_MODULE_V7 7172 { 7173 // Design Specific Values 7174 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7175 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7176 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7177 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7178 UCHAR ucExtMemoryID; // Current memory module ID 7179 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7180 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7181 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7182 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7183 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7184 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7185 UCHAR ucVREFI; // Not used. 7186 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7187 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7188 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7189 USHORT usSEQSettingOffset; 7190 UCHAR ucReserved; 7191 // Memory Module specific values 7192 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7193 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7194 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7195 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7196 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7197 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7198 char strMemPNString[20]; // part number end with '0'. 7199 }ATOM_VRAM_MODULE_V7; 7200 7201 7202 typedef struct _ATOM_VRAM_MODULE_V8 7203 { 7204 // Design Specific Values 7205 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7206 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7207 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7208 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7209 UCHAR ucExtMemoryID; // Current memory module ID 7210 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7211 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7212 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7213 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7214 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7215 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7216 UCHAR ucVREFI; // Not used. 7217 USHORT usReserved; // Not used 7218 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7219 UCHAR ucMcTunningSetId; // MC phy registers set per. 7220 UCHAR ucRowNum; 7221 // Memory Module specific values 7222 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7223 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7224 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7225 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7226 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7227 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7228 7229 ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7230 ULONG ulBankMapCfg; 7231 ULONG ulReserved; 7232 char strMemPNString[20]; // part number end with '0'. 7233 }ATOM_VRAM_MODULE_V8; 7234 7235 7236 typedef struct _ATOM_VRAM_INFO_V2 7237 { 7238 ATOM_COMMON_TABLE_HEADER sHeader; 7239 UCHAR ucNumOfVRAMModule; 7240 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7241 }ATOM_VRAM_INFO_V2; 7242 7243 typedef struct _ATOM_VRAM_INFO_V3 7244 { 7245 ATOM_COMMON_TABLE_HEADER sHeader; 7246 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7247 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7248 USHORT usRerseved; 7249 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7250 UCHAR ucNumOfVRAMModule; 7251 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7252 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7253 7254 }ATOM_VRAM_INFO_V3; 7255 7256 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 7257 7258 typedef struct _ATOM_VRAM_INFO_V4 7259 { 7260 ATOM_COMMON_TABLE_HEADER sHeader; 7261 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7262 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7263 USHORT usRerseved; 7264 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 7265 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 7266 UCHAR ucReservde[4]; 7267 UCHAR ucNumOfVRAMModule; 7268 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7269 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7270 }ATOM_VRAM_INFO_V4; 7271 7272 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 7273 { 7274 ATOM_COMMON_TABLE_HEADER sHeader; 7275 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7276 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7277 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 7278 USHORT usReserved[3]; 7279 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 7280 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 7281 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 7282 UCHAR ucReserved; 7283 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7284 }ATOM_VRAM_INFO_HEADER_V2_1; 7285 7286 typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 7287 { 7288 ATOM_COMMON_TABLE_HEADER sHeader; 7289 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7290 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7291 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 7292 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 7293 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 7294 USHORT usReserved1; 7295 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 7296 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 7297 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 7298 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 7299 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7300 }ATOM_VRAM_INFO_HEADER_V2_2; 7301 7302 7303 typedef struct _ATOM_DRAM_DATA_REMAP 7304 { 7305 UCHAR ucByteRemapCh0; 7306 UCHAR ucByteRemapCh1; 7307 ULONG ulByte0BitRemapCh0; 7308 ULONG ulByte1BitRemapCh0; 7309 ULONG ulByte2BitRemapCh0; 7310 ULONG ulByte3BitRemapCh0; 7311 ULONG ulByte0BitRemapCh1; 7312 ULONG ulByte1BitRemapCh1; 7313 ULONG ulByte2BitRemapCh1; 7314 ULONG ulByte3BitRemapCh1; 7315 }ATOM_DRAM_DATA_REMAP; 7316 7317 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 7318 { 7319 ATOM_COMMON_TABLE_HEADER sHeader; 7320 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7321 }ATOM_VRAM_GPIO_DETECTION_INFO; 7322 7323 7324 typedef struct _ATOM_MEMORY_TRAINING_INFO 7325 { 7326 ATOM_COMMON_TABLE_HEADER sHeader; 7327 UCHAR ucTrainingLoop; 7328 UCHAR ucReserved[3]; 7329 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 7330 }ATOM_MEMORY_TRAINING_INFO; 7331 7332 7333 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 7334 { 7335 UCHAR ucControl; 7336 UCHAR ucData; 7337 UCHAR ucSatus; 7338 UCHAR ucTemp; 7339 } SW_I2C_CNTL_DATA_PARAMETERS; 7340 7341 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 7342 7343 typedef struct _SW_I2C_IO_DATA_PARAMETERS 7344 { 7345 USHORT GPIO_Info; 7346 UCHAR ucAct; 7347 UCHAR ucData; 7348 } SW_I2C_IO_DATA_PARAMETERS; 7349 7350 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 7351 7352 /****************************SW I2C CNTL DEFINITIONS**********************/ 7353 #define SW_I2C_IO_RESET 0 7354 #define SW_I2C_IO_GET 1 7355 #define SW_I2C_IO_DRIVE 2 7356 #define SW_I2C_IO_SET 3 7357 #define SW_I2C_IO_START 4 7358 7359 #define SW_I2C_IO_CLOCK 0 7360 #define SW_I2C_IO_DATA 0x80 7361 7362 #define SW_I2C_IO_ZERO 0 7363 #define SW_I2C_IO_ONE 0x100 7364 7365 #define SW_I2C_CNTL_READ 0 7366 #define SW_I2C_CNTL_WRITE 1 7367 #define SW_I2C_CNTL_START 2 7368 #define SW_I2C_CNTL_STOP 3 7369 #define SW_I2C_CNTL_OPEN 4 7370 #define SW_I2C_CNTL_CLOSE 5 7371 #define SW_I2C_CNTL_WRITE1BIT 6 7372 7373 //==============================VESA definition Portion=============================== 7374 #define VESA_OEM_PRODUCT_REV '01.00' 7375 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 7376 #define VESA_MODE_WIN_ATTRIBUTE 7 7377 #define VESA_WIN_SIZE 64 7378 7379 typedef struct _PTR_32_BIT_STRUCTURE 7380 { 7381 USHORT Offset16; 7382 USHORT Segment16; 7383 } PTR_32_BIT_STRUCTURE; 7384 7385 typedef union _PTR_32_BIT_UNION 7386 { 7387 PTR_32_BIT_STRUCTURE SegmentOffset; 7388 ULONG Ptr32_Bit; 7389 } PTR_32_BIT_UNION; 7390 7391 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 7392 { 7393 UCHAR VbeSignature[4]; 7394 USHORT VbeVersion; 7395 PTR_32_BIT_UNION OemStringPtr; 7396 UCHAR Capabilities[4]; 7397 PTR_32_BIT_UNION VideoModePtr; 7398 USHORT TotalMemory; 7399 } VBE_1_2_INFO_BLOCK_UPDATABLE; 7400 7401 7402 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 7403 { 7404 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 7405 USHORT OemSoftRev; 7406 PTR_32_BIT_UNION OemVendorNamePtr; 7407 PTR_32_BIT_UNION OemProductNamePtr; 7408 PTR_32_BIT_UNION OemProductRevPtr; 7409 } VBE_2_0_INFO_BLOCK_UPDATABLE; 7410 7411 typedef union _VBE_VERSION_UNION 7412 { 7413 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 7414 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 7415 } VBE_VERSION_UNION; 7416 7417 typedef struct _VBE_INFO_BLOCK 7418 { 7419 VBE_VERSION_UNION UpdatableVBE_Info; 7420 UCHAR Reserved[222]; 7421 UCHAR OemData[256]; 7422 } VBE_INFO_BLOCK; 7423 7424 typedef struct _VBE_FP_INFO 7425 { 7426 USHORT HSize; 7427 USHORT VSize; 7428 USHORT FPType; 7429 UCHAR RedBPP; 7430 UCHAR GreenBPP; 7431 UCHAR BlueBPP; 7432 UCHAR ReservedBPP; 7433 ULONG RsvdOffScrnMemSize; 7434 ULONG RsvdOffScrnMEmPtr; 7435 UCHAR Reserved[14]; 7436 } VBE_FP_INFO; 7437 7438 typedef struct _VESA_MODE_INFO_BLOCK 7439 { 7440 // Mandatory information for all VBE revisions 7441 USHORT ModeAttributes; // dw ? ; mode attributes 7442 UCHAR WinAAttributes; // db ? ; window A attributes 7443 UCHAR WinBAttributes; // db ? ; window B attributes 7444 USHORT WinGranularity; // dw ? ; window granularity 7445 USHORT WinSize; // dw ? ; window size 7446 USHORT WinASegment; // dw ? ; window A start segment 7447 USHORT WinBSegment; // dw ? ; window B start segment 7448 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 7449 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 7450 7451 //; Mandatory information for VBE 1.2 and above 7452 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 7453 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 7454 UCHAR XCharSize; // db ? ; character cell width in pixels 7455 UCHAR YCharSize; // db ? ; character cell height in pixels 7456 UCHAR NumberOfPlanes; // db ? ; number of memory planes 7457 UCHAR BitsPerPixel; // db ? ; bits per pixel 7458 UCHAR NumberOfBanks; // db ? ; number of banks 7459 UCHAR MemoryModel; // db ? ; memory model type 7460 UCHAR BankSize; // db ? ; bank size in KB 7461 UCHAR NumberOfImagePages;// db ? ; number of images 7462 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 7463 7464 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 7465 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 7466 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 7467 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 7468 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 7469 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 7470 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 7471 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 7472 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 7473 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 7474 7475 //; Mandatory information for VBE 2.0 and above 7476 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 7477 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 7478 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 7479 7480 //; Mandatory information for VBE 3.0 and above 7481 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 7482 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 7483 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 7484 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 7485 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 7486 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 7487 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 7488 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 7489 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 7490 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 7491 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 7492 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 7493 UCHAR Reserved; // db 190 dup (0) 7494 } VESA_MODE_INFO_BLOCK; 7495 7496 // BIOS function CALLS 7497 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 7498 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 7499 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 7500 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 7501 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 7502 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 7503 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 7504 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 7505 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 7506 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 7507 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 7508 7509 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 7510 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 7511 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 7512 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 7513 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 7514 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 7515 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 7516 7517 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 7518 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 7519 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 7520 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 7521 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 7522 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 7523 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 7524 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 7525 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 7526 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 7527 7528 7529 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 7530 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 7531 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 7532 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 7533 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 7534 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 7535 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 7536 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 7537 7538 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 7539 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 7540 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 7541 7542 // structure used for VBIOS only 7543 7544 //DispOutInfoTable 7545 typedef struct _ASIC_TRANSMITTER_INFO 7546 { 7547 USHORT usTransmitterObjId; 7548 USHORT usSupportDevice; 7549 UCHAR ucTransmitterCmdTblId; 7550 UCHAR ucConfig; 7551 UCHAR ucEncoderID; //available 1st encoder ( default ) 7552 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 7553 UCHAR uc2ndEncoderID; 7554 UCHAR ucReserved; 7555 }ASIC_TRANSMITTER_INFO; 7556 7557 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 7558 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 7559 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 7560 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 7561 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 7562 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 7563 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 7564 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 7565 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 7566 7567 typedef struct _ASIC_ENCODER_INFO 7568 { 7569 UCHAR ucEncoderID; 7570 UCHAR ucEncoderConfig; 7571 USHORT usEncoderCmdTblId; 7572 }ASIC_ENCODER_INFO; 7573 7574 typedef struct _ATOM_DISP_OUT_INFO 7575 { 7576 ATOM_COMMON_TABLE_HEADER sHeader; 7577 USHORT ptrTransmitterInfo; 7578 USHORT ptrEncoderInfo; 7579 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7580 ASIC_ENCODER_INFO asEncoderInfo[1]; 7581 }ATOM_DISP_OUT_INFO; 7582 7583 7584 typedef struct _ATOM_DISP_OUT_INFO_V2 7585 { 7586 ATOM_COMMON_TABLE_HEADER sHeader; 7587 USHORT ptrTransmitterInfo; 7588 USHORT ptrEncoderInfo; 7589 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7590 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 7591 ASIC_ENCODER_INFO asEncoderInfo[1]; 7592 }ATOM_DISP_OUT_INFO_V2; 7593 7594 7595 typedef struct _ATOM_DISP_CLOCK_ID { 7596 UCHAR ucPpllId; 7597 UCHAR ucPpllAttribute; 7598 }ATOM_DISP_CLOCK_ID; 7599 7600 // ucPpllAttribute 7601 #define CLOCK_SOURCE_SHAREABLE 0x01 7602 #define CLOCK_SOURCE_DP_MODE 0x02 7603 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 7604 7605 //DispOutInfoTable 7606 typedef struct _ASIC_TRANSMITTER_INFO_V2 7607 { 7608 USHORT usTransmitterObjId; 7609 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 7610 UCHAR ucTransmitterCmdTblId; 7611 UCHAR ucConfig; 7612 UCHAR ucEncoderID; // available 1st encoder ( default ) 7613 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 7614 UCHAR uc2ndEncoderID; 7615 UCHAR ucReserved; 7616 }ASIC_TRANSMITTER_INFO_V2; 7617 7618 typedef struct _ATOM_DISP_OUT_INFO_V3 7619 { 7620 ATOM_COMMON_TABLE_HEADER sHeader; 7621 USHORT ptrTransmitterInfo; 7622 USHORT ptrEncoderInfo; 7623 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 7624 USHORT usReserved; 7625 UCHAR ucDCERevision; 7626 UCHAR ucMaxDispEngineNum; 7627 UCHAR ucMaxActiveDispEngineNum; 7628 UCHAR ucMaxPPLLNum; 7629 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 7630 UCHAR ucDispCaps; 7631 UCHAR ucReserved[2]; 7632 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 7633 }ATOM_DISP_OUT_INFO_V3; 7634 7635 //ucDispCaps 7636 #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 7637 #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 7638 7639 typedef enum CORE_REF_CLK_SOURCE{ 7640 CLOCK_SRC_XTALIN=0, 7641 CLOCK_SRC_XO_IN=1, 7642 CLOCK_SRC_XO_IN2=2, 7643 }CORE_REF_CLK_SOURCE; 7644 7645 // DispDevicePriorityInfo 7646 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 7647 { 7648 ATOM_COMMON_TABLE_HEADER sHeader; 7649 USHORT asDevicePriority[16]; 7650 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 7651 7652 //ProcessAuxChannelTransactionTable 7653 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7654 { 7655 USHORT lpAuxRequest; 7656 USHORT lpDataOut; 7657 UCHAR ucChannelID; 7658 union 7659 { 7660 UCHAR ucReplyStatus; 7661 UCHAR ucDelay; 7662 }; 7663 UCHAR ucDataOutLen; 7664 UCHAR ucReserved; 7665 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 7666 7667 //ProcessAuxChannelTransactionTable 7668 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 7669 { 7670 USHORT lpAuxRequest; 7671 USHORT lpDataOut; 7672 UCHAR ucChannelID; 7673 union 7674 { 7675 UCHAR ucReplyStatus; 7676 UCHAR ucDelay; 7677 }; 7678 UCHAR ucDataOutLen; 7679 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 7680 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 7681 7682 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 7683 7684 //GetSinkType 7685 7686 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 7687 { 7688 USHORT ucLinkClock; 7689 union 7690 { 7691 UCHAR ucConfig; // for DP training command 7692 UCHAR ucI2cId; // use for GET_SINK_TYPE command 7693 }; 7694 UCHAR ucAction; 7695 UCHAR ucStatus; 7696 UCHAR ucLaneNum; 7697 UCHAR ucReserved[2]; 7698 }DP_ENCODER_SERVICE_PARAMETERS; 7699 7700 // ucAction 7701 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 7702 7703 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 7704 7705 7706 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 7707 { 7708 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7709 UCHAR ucAuxId; 7710 UCHAR ucAction; 7711 UCHAR ucSinkType; // Iput and Output parameters. 7712 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 7713 UCHAR ucReserved[2]; 7714 }DP_ENCODER_SERVICE_PARAMETERS_V2; 7715 7716 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 7717 { 7718 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 7719 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 7720 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 7721 7722 // ucAction 7723 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 7724 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 7725 7726 7727 // DP_TRAINING_TABLE 7728 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 7729 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 7730 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 7731 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 7732 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 7733 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 7734 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 7735 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 7736 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 7737 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 7738 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 7739 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 7740 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 7741 7742 7743 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7744 { 7745 UCHAR ucI2CSpeed; 7746 union 7747 { 7748 UCHAR ucRegIndex; 7749 UCHAR ucStatus; 7750 }; 7751 USHORT lpI2CDataOut; 7752 UCHAR ucFlag; 7753 UCHAR ucTransBytes; 7754 UCHAR ucSlaveAddr; 7755 UCHAR ucLineNumber; 7756 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 7757 7758 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 7759 7760 //ucFlag 7761 #define HW_I2C_WRITE 1 7762 #define HW_I2C_READ 0 7763 #define I2C_2BYTE_ADDR 0x02 7764 7765 /****************************************************************************/ 7766 // Structures used by HW_Misc_OperationTable 7767 /****************************************************************************/ 7768 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 7769 { 7770 UCHAR ucCmd; // Input: To tell which action to take 7771 UCHAR ucReserved[3]; 7772 ULONG ulReserved; 7773 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 7774 7775 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 7776 { 7777 UCHAR ucReturnCode; // Output: Return value base on action was taken 7778 UCHAR ucReserved[3]; 7779 ULONG ulReserved; 7780 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 7781 7782 // Actions code 7783 #define ATOM_GET_SDI_SUPPORT 0xF0 7784 7785 // Return code 7786 #define ATOM_UNKNOWN_CMD 0 7787 #define ATOM_FEATURE_NOT_SUPPORTED 1 7788 #define ATOM_FEATURE_SUPPORTED 2 7789 7790 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 7791 { 7792 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 7793 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 7794 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 7795 7796 /****************************************************************************/ 7797 7798 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 7799 { 7800 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 7801 UCHAR ucReserved[3]; 7802 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 7803 7804 #define HWBLKINST_INSTANCE_MASK 0x07 7805 #define HWBLKINST_HWBLK_MASK 0xF0 7806 #define HWBLKINST_HWBLK_SHIFT 0x04 7807 7808 //ucHWBlock 7809 #define SELECT_DISP_ENGINE 0 7810 #define SELECT_DISP_PLL 1 7811 #define SELECT_DCIO_UNIPHY_LINK0 2 7812 #define SELECT_DCIO_UNIPHY_LINK1 3 7813 #define SELECT_DCIO_IMPCAL 4 7814 #define SELECT_DCIO_DIG 6 7815 #define SELECT_CRTC_PIXEL_RATE 7 7816 #define SELECT_VGA_BLK 8 7817 7818 // DIGTransmitterInfoTable structure used to program UNIPHY settings 7819 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 7820 ATOM_COMMON_TABLE_HEADER sHeader; 7821 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7822 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7823 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7824 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7825 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7826 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 7827 7828 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 7829 ATOM_COMMON_TABLE_HEADER sHeader; 7830 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7831 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7832 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7833 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7834 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7835 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7836 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7837 }DIG_TRANSMITTER_INFO_HEADER_V3_2; 7838 7839 7840 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 7841 ATOM_COMMON_TABLE_HEADER sHeader; 7842 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 7843 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 7844 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 7845 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 7846 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 7847 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 7848 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 7849 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 7850 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7851 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7852 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 7853 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 7854 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 7855 }DIG_TRANSMITTER_INFO_HEADER_V3_3; 7856 7857 7858 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 7859 USHORT usRegisterIndex; 7860 UCHAR ucStartBit; 7861 UCHAR ucEndBit; 7862 }CLOCK_CONDITION_REGESTER_INFO; 7863 7864 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 7865 USHORT usMaxClockFreq; 7866 UCHAR ucEncodeMode; 7867 UCHAR ucPhySel; 7868 ULONG ulAnalogSetting[1]; 7869 }CLOCK_CONDITION_SETTING_ENTRY; 7870 7871 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 7872 USHORT usEntrySize; 7873 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 7874 }CLOCK_CONDITION_SETTING_INFO; 7875 7876 typedef struct _PHY_CONDITION_REG_VAL{ 7877 ULONG ulCondition; 7878 ULONG ulRegVal; 7879 }PHY_CONDITION_REG_VAL; 7880 7881 typedef struct _PHY_CONDITION_REG_VAL_V2{ 7882 ULONG ulCondition; 7883 UCHAR ucCondition2; 7884 ULONG ulRegVal; 7885 }PHY_CONDITION_REG_VAL_V2; 7886 7887 typedef struct _PHY_CONDITION_REG_INFO{ 7888 USHORT usRegIndex; 7889 USHORT usSize; 7890 PHY_CONDITION_REG_VAL asRegVal[1]; 7891 }PHY_CONDITION_REG_INFO; 7892 7893 typedef struct _PHY_CONDITION_REG_INFO_V2{ 7894 USHORT usRegIndex; 7895 USHORT usSize; 7896 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 7897 }PHY_CONDITION_REG_INFO_V2; 7898 7899 typedef struct _PHY_ANALOG_SETTING_INFO{ 7900 UCHAR ucEncodeMode; 7901 UCHAR ucPhySel; 7902 USHORT usSize; 7903 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 7904 }PHY_ANALOG_SETTING_INFO; 7905 7906 typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 7907 UCHAR ucEncodeMode; 7908 UCHAR ucPhySel; 7909 USHORT usSize; 7910 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 7911 }PHY_ANALOG_SETTING_INFO_V2; 7912 7913 7914 typedef struct _GFX_HAVESTING_PARAMETERS { 7915 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 7916 UCHAR ucReserved; //reserved 7917 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 7918 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 7919 } GFX_HAVESTING_PARAMETERS; 7920 7921 //ucGfxBlkId 7922 #define GFX_HARVESTING_CU_ID 0 7923 #define GFX_HARVESTING_RB_ID 1 7924 #define GFX_HARVESTING_PRIM_ID 2 7925 7926 7927 typedef struct _VBIOS_ROM_HEADER{ 7928 UCHAR PciRomSignature[2]; 7929 UCHAR ucPciRomSizeIn512bytes; 7930 UCHAR ucJumpCoreMainInitBIOS; 7931 USHORT usLabelCoreMainInitBIOS; 7932 UCHAR PciReservedSpace[18]; 7933 USHORT usPciDataStructureOffset; 7934 UCHAR Rsvd1d_1a[4]; 7935 char strIbm[3]; 7936 UCHAR CheckSum[14]; 7937 UCHAR ucBiosMsgNumber; 7938 char str761295520[16]; 7939 USHORT usLabelCoreVPOSTNoMode; 7940 USHORT usSpecialPostOffset; 7941 UCHAR ucSpeicalPostImageSizeIn512Bytes; 7942 UCHAR Rsved47_45[3]; 7943 USHORT usROM_HeaderInformationTableOffset; 7944 UCHAR Rsved4f_4a[6]; 7945 char strBuildTimeStamp[20]; 7946 UCHAR ucJumpCoreXFuncFarHandler; 7947 USHORT usCoreXFuncFarHandlerOffset; 7948 UCHAR ucRsved67; 7949 UCHAR ucJumpCoreVFuncFarHandler; 7950 USHORT usCoreVFuncFarHandlerOffset; 7951 UCHAR Rsved6d_6b[3]; 7952 USHORT usATOM_BIOS_MESSAGE_Offset; 7953 }VBIOS_ROM_HEADER; 7954 7955 /****************************************************************************/ 7956 //Portion VI: Definitinos for vbios MC scratch registers that driver used 7957 /****************************************************************************/ 7958 7959 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 7960 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 7961 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 7962 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 7963 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 7964 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 7965 #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 7966 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 7967 7968 #define ATOM_MEM_TYPE_DDR_STRING "DDR" 7969 #define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 7970 #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 7971 #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 7972 #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 7973 #define ATOM_MEM_TYPE_HBM_STRING "HBM" 7974 #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 7975 7976 /****************************************************************************/ 7977 //Portion VII: Definitinos being oboselete 7978 /****************************************************************************/ 7979 7980 //========================================================================================== 7981 //Remove the definitions below when driver is ready! 7982 typedef struct _ATOM_DAC_INFO 7983 { 7984 ATOM_COMMON_TABLE_HEADER sHeader; 7985 USHORT usMaxFrequency; // in 10kHz unit 7986 USHORT usReserved; 7987 }ATOM_DAC_INFO; 7988 7989 7990 typedef struct _COMPASSIONATE_DATA 7991 { 7992 ATOM_COMMON_TABLE_HEADER sHeader; 7993 7994 //============================== DAC1 portion 7995 UCHAR ucDAC1_BG_Adjustment; 7996 UCHAR ucDAC1_DAC_Adjustment; 7997 USHORT usDAC1_FORCE_Data; 7998 //============================== DAC2 portion 7999 UCHAR ucDAC2_CRT2_BG_Adjustment; 8000 UCHAR ucDAC2_CRT2_DAC_Adjustment; 8001 USHORT usDAC2_CRT2_FORCE_Data; 8002 USHORT usDAC2_CRT2_MUX_RegisterIndex; 8003 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8004 UCHAR ucDAC2_NTSC_BG_Adjustment; 8005 UCHAR ucDAC2_NTSC_DAC_Adjustment; 8006 USHORT usDAC2_TV1_FORCE_Data; 8007 USHORT usDAC2_TV1_MUX_RegisterIndex; 8008 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8009 UCHAR ucDAC2_CV_BG_Adjustment; 8010 UCHAR ucDAC2_CV_DAC_Adjustment; 8011 USHORT usDAC2_CV_FORCE_Data; 8012 USHORT usDAC2_CV_MUX_RegisterIndex; 8013 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8014 UCHAR ucDAC2_PAL_BG_Adjustment; 8015 UCHAR ucDAC2_PAL_DAC_Adjustment; 8016 USHORT usDAC2_TV2_FORCE_Data; 8017 }COMPASSIONATE_DATA; 8018 8019 /****************************Supported Device Info Table Definitions**********************/ 8020 // ucConnectInfo: 8021 // [7:4] - connector type 8022 // = 1 - VGA connector 8023 // = 2 - DVI-I 8024 // = 3 - DVI-D 8025 // = 4 - DVI-A 8026 // = 5 - SVIDEO 8027 // = 6 - COMPOSITE 8028 // = 7 - LVDS 8029 // = 8 - DIGITAL LINK 8030 // = 9 - SCART 8031 // = 0xA - HDMI_type A 8032 // = 0xB - HDMI_type B 8033 // = 0xE - Special case1 (DVI+DIN) 8034 // Others=TBD 8035 // [3:0] - DAC Associated 8036 // = 0 - no DAC 8037 // = 1 - DACA 8038 // = 2 - DACB 8039 // = 3 - External DAC 8040 // Others=TBD 8041 // 8042 8043 typedef struct _ATOM_CONNECTOR_INFO 8044 { 8045 #if ATOM_BIG_ENDIAN 8046 UCHAR bfConnectorType:4; 8047 UCHAR bfAssociatedDAC:4; 8048 #else 8049 UCHAR bfAssociatedDAC:4; 8050 UCHAR bfConnectorType:4; 8051 #endif 8052 }ATOM_CONNECTOR_INFO; 8053 8054 typedef union _ATOM_CONNECTOR_INFO_ACCESS 8055 { 8056 ATOM_CONNECTOR_INFO sbfAccess; 8057 UCHAR ucAccess; 8058 }ATOM_CONNECTOR_INFO_ACCESS; 8059 8060 typedef struct _ATOM_CONNECTOR_INFO_I2C 8061 { 8062 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8063 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8064 }ATOM_CONNECTOR_INFO_I2C; 8065 8066 8067 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8068 { 8069 ATOM_COMMON_TABLE_HEADER sHeader; 8070 USHORT usDeviceSupport; 8071 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8072 }ATOM_SUPPORTED_DEVICES_INFO; 8073 8074 #define NO_INT_SRC_MAPPED 0xFF 8075 8076 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8077 { 8078 UCHAR ucIntSrcBitmap; 8079 }ATOM_CONNECTOR_INC_SRC_BITMAP; 8080 8081 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8082 { 8083 ATOM_COMMON_TABLE_HEADER sHeader; 8084 USHORT usDeviceSupport; 8085 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8086 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8087 }ATOM_SUPPORTED_DEVICES_INFO_2; 8088 8089 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8090 { 8091 ATOM_COMMON_TABLE_HEADER sHeader; 8092 USHORT usDeviceSupport; 8093 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8094 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8095 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 8096 8097 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8098 8099 8100 8101 typedef struct _ATOM_MISC_CONTROL_INFO 8102 { 8103 USHORT usFrequency; 8104 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8105 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8106 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8107 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8108 }ATOM_MISC_CONTROL_INFO; 8109 8110 8111 #define ATOM_MAX_MISC_INFO 4 8112 8113 typedef struct _ATOM_TMDS_INFO 8114 { 8115 ATOM_COMMON_TABLE_HEADER sHeader; 8116 USHORT usMaxFrequency; // in 10Khz 8117 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8118 }ATOM_TMDS_INFO; 8119 8120 8121 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8122 { 8123 UCHAR ucTVStandard; //Same as TV standards defined above, 8124 UCHAR ucPadding[1]; 8125 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 8126 8127 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8128 { 8129 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8130 UCHAR ucPadding[1]; 8131 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8132 8133 typedef union _ATOM_ENCODER_ATTRIBUTE 8134 { 8135 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8136 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8137 }ATOM_ENCODER_ATTRIBUTE; 8138 8139 8140 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8141 { 8142 USHORT usPixelClock; 8143 USHORT usEncoderID; 8144 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8145 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8146 ATOM_ENCODER_ATTRIBUTE usDevAttr; 8147 }DVO_ENCODER_CONTROL_PARAMETERS; 8148 8149 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8150 { 8151 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8152 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8153 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 8154 8155 8156 #define ATOM_XTMDS_ASIC_SI164_ID 1 8157 #define ATOM_XTMDS_ASIC_SI178_ID 2 8158 #define ATOM_XTMDS_ASIC_TFP513_ID 3 8159 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8160 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8161 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 8162 8163 8164 typedef struct _ATOM_XTMDS_INFO 8165 { 8166 ATOM_COMMON_TABLE_HEADER sHeader; 8167 USHORT usSingleLinkMaxFrequency; 8168 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8169 UCHAR ucXtransimitterID; 8170 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8171 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8172 // due to design. This ID is used to alert driver that the sequence is not "standard"! 8173 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8174 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8175 }ATOM_XTMDS_INFO; 8176 8177 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8178 { 8179 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8180 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8181 UCHAR ucPadding[2]; 8182 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8183 8184 /****************************Legacy Power Play Table Definitions **********************/ 8185 8186 //Definitions for ulPowerPlayMiscInfo 8187 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8188 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8189 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8190 8191 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8192 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8193 8194 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8195 8196 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8197 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8198 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8199 8200 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8201 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8202 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8203 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8204 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8205 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8206 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8207 8208 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8209 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8210 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8211 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8212 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8213 8214 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8215 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8216 8217 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8218 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8219 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8220 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8221 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8222 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8223 8224 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8225 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8226 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8227 8228 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8229 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8230 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8231 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8232 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8233 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8234 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8235 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8236 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8237 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8238 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8239 8240 //ucTableFormatRevision=1 8241 //ucTableContentRevision=1 8242 typedef struct _ATOM_POWERMODE_INFO 8243 { 8244 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8245 ULONG ulReserved1; // must set to 0 8246 ULONG ulReserved2; // must set to 0 8247 USHORT usEngineClock; 8248 USHORT usMemoryClock; 8249 UCHAR ucVoltageDropIndex; // index to GPIO table 8250 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8251 UCHAR ucMinTemperature; 8252 UCHAR ucMaxTemperature; 8253 UCHAR ucNumPciELanes; // number of PCIE lanes 8254 }ATOM_POWERMODE_INFO; 8255 8256 //ucTableFormatRevision=2 8257 //ucTableContentRevision=1 8258 typedef struct _ATOM_POWERMODE_INFO_V2 8259 { 8260 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8261 ULONG ulMiscInfo2; 8262 ULONG ulEngineClock; 8263 ULONG ulMemoryClock; 8264 UCHAR ucVoltageDropIndex; // index to GPIO table 8265 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8266 UCHAR ucMinTemperature; 8267 UCHAR ucMaxTemperature; 8268 UCHAR ucNumPciELanes; // number of PCIE lanes 8269 }ATOM_POWERMODE_INFO_V2; 8270 8271 //ucTableFormatRevision=2 8272 //ucTableContentRevision=2 8273 typedef struct _ATOM_POWERMODE_INFO_V3 8274 { 8275 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8276 ULONG ulMiscInfo2; 8277 ULONG ulEngineClock; 8278 ULONG ulMemoryClock; 8279 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 8280 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8281 UCHAR ucMinTemperature; 8282 UCHAR ucMaxTemperature; 8283 UCHAR ucNumPciELanes; // number of PCIE lanes 8284 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 8285 }ATOM_POWERMODE_INFO_V3; 8286 8287 8288 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 8289 8290 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 8291 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 8292 8293 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 8294 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 8295 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 8296 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 8297 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 8298 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 8299 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 8300 8301 8302 typedef struct _ATOM_POWERPLAY_INFO 8303 { 8304 ATOM_COMMON_TABLE_HEADER sHeader; 8305 UCHAR ucOverdriveThermalController; 8306 UCHAR ucOverdriveI2cLine; 8307 UCHAR ucOverdriveIntBitmap; 8308 UCHAR ucOverdriveControllerAddress; 8309 UCHAR ucSizeOfPowerModeEntry; 8310 UCHAR ucNumOfPowerModeEntries; 8311 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8312 }ATOM_POWERPLAY_INFO; 8313 8314 typedef struct _ATOM_POWERPLAY_INFO_V2 8315 { 8316 ATOM_COMMON_TABLE_HEADER sHeader; 8317 UCHAR ucOverdriveThermalController; 8318 UCHAR ucOverdriveI2cLine; 8319 UCHAR ucOverdriveIntBitmap; 8320 UCHAR ucOverdriveControllerAddress; 8321 UCHAR ucSizeOfPowerModeEntry; 8322 UCHAR ucNumOfPowerModeEntries; 8323 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8324 }ATOM_POWERPLAY_INFO_V2; 8325 8326 typedef struct _ATOM_POWERPLAY_INFO_V3 8327 { 8328 ATOM_COMMON_TABLE_HEADER sHeader; 8329 UCHAR ucOverdriveThermalController; 8330 UCHAR ucOverdriveI2cLine; 8331 UCHAR ucOverdriveIntBitmap; 8332 UCHAR ucOverdriveControllerAddress; 8333 UCHAR ucSizeOfPowerModeEntry; 8334 UCHAR ucNumOfPowerModeEntries; 8335 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 8336 }ATOM_POWERPLAY_INFO_V3; 8337 8338 8339 8340 /**************************************************************************/ 8341 8342 8343 // Following definitions are for compatiblity issue in different SW components. 8344 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 8345 #define Object_Info Object_Header 8346 #define AdjustARB_SEQ MC_InitParameter 8347 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 8348 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 8349 #define ASIC_MVDDQ_Info MemoryTrainingInfo 8350 #define SS_Info PPLL_SS_Info 8351 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 8352 #define DispDevicePriorityInfo SaveRestoreInfo 8353 #define DispOutInfo TV_VideoMode 8354 8355 8356 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 8357 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 8358 8359 //New device naming, remove them when both DAL/VBIOS is ready 8360 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 8361 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 8362 8363 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 8364 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 8365 8366 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 8367 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 8368 8369 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 8370 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 8371 8372 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 8373 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 8374 8375 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 8376 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 8377 8378 #define ATOM_S0_DFP1I ATOM_S0_DFP1 8379 #define ATOM_S0_DFP1X ATOM_S0_DFP2 8380 8381 #define ATOM_S0_DFP2I 0x00200000L 8382 #define ATOM_S0_DFP2Ib2 0x20 8383 8384 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 8385 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 8386 8387 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 8388 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 8389 8390 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 8391 8392 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 8393 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 8394 8395 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 8396 8397 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 8398 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 8399 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 8400 8401 8402 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 8403 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 8404 8405 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 8406 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 8407 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 8408 8409 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 8410 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 8411 8412 #define TMDS1XEncoderControl DVOEncoderControl 8413 #define DFP1XOutputControl DVOOutputControl 8414 8415 #define ExternalDFPOutputControl DFP1XOutputControl 8416 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 8417 8418 #define DFP1IOutputControl TMDSAOutputControl 8419 #define DFP2IOutputControl LVTMAOutputControl 8420 8421 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 8422 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 8423 8424 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 8425 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 8426 8427 #define ucDac1Standard ucDacStandard 8428 #define ucDac2Standard ucDacStandard 8429 8430 #define TMDS1EncoderControl TMDSAEncoderControl 8431 #define TMDS2EncoderControl LVTMAEncoderControl 8432 8433 #define DFP1OutputControl TMDSAOutputControl 8434 #define DFP2OutputControl LVTMAOutputControl 8435 #define CRT1OutputControl DAC1OutputControl 8436 #define CRT2OutputControl DAC2OutputControl 8437 8438 //These two lines will be removed for sure in a few days, will follow up with Michael V. 8439 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 8440 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 8441 8442 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 8443 #define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8444 #define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8445 #define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8446 #define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 8447 8448 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 8449 #define ATOM_DEVICE_TV2_INDEX 0x00000006 8450 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 8451 #define ATOM_S0_TV2 0x00100000L 8452 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 8453 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 8454 8455 /*********************************************************************************/ 8456 8457 #pragma pack() // BIOS data must use byte aligment 8458 8459 #pragma pack(1) 8460 8461 typedef struct _ATOM_HOLE_INFO 8462 { 8463 USHORT usOffset; // offset of the hole ( from the start of the binary ) 8464 USHORT usLength; // length of the hole ( in bytes ) 8465 }ATOM_HOLE_INFO; 8466 8467 typedef struct _ATOM_SERVICE_DESCRIPTION 8468 { 8469 UCHAR ucRevision; // Holes set revision 8470 UCHAR ucAlgorithm; // Hash algorithm 8471 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 8472 UCHAR ucReserved; 8473 USHORT usSigOffset; // Signature offset ( from the start of the binary ) 8474 USHORT usSigLength; // Signature length 8475 }ATOM_SERVICE_DESCRIPTION; 8476 8477 8478 typedef struct _ATOM_SERVICE_INFO 8479 { 8480 ATOM_COMMON_TABLE_HEADER asHeader; 8481 ATOM_SERVICE_DESCRIPTION asDescr; 8482 UCHAR ucholesNo; // number of holes that follow 8483 ATOM_HOLE_INFO holes[1]; // array of hole descriptions 8484 }ATOM_SERVICE_INFO; 8485 8486 8487 8488 #pragma pack() // BIOS data must use byte aligment 8489 8490 // 8491 // AMD ACPI Table 8492 // 8493 #pragma pack(1) 8494 8495 typedef struct { 8496 ULONG Signature; 8497 ULONG TableLength; //Length 8498 UCHAR Revision; 8499 UCHAR Checksum; 8500 UCHAR OemId[6]; 8501 UCHAR OemTableId[8]; //UINT64 OemTableId; 8502 ULONG OemRevision; 8503 ULONG CreatorId; 8504 ULONG CreatorRevision; 8505 } AMD_ACPI_DESCRIPTION_HEADER; 8506 /* 8507 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 8508 typedef struct { 8509 UINT32 Signature; //0x0 8510 UINT32 Length; //0x4 8511 UINT8 Revision; //0x8 8512 UINT8 Checksum; //0x9 8513 UINT8 OemId[6]; //0xA 8514 UINT64 OemTableId; //0x10 8515 UINT32 OemRevision; //0x18 8516 UINT32 CreatorId; //0x1C 8517 UINT32 CreatorRevision; //0x20 8518 }EFI_ACPI_DESCRIPTION_HEADER; 8519 */ 8520 typedef struct { 8521 AMD_ACPI_DESCRIPTION_HEADER SHeader; 8522 UCHAR TableUUID[16]; //0x24 8523 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 8524 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 8525 ULONG Reserved[4]; //0x3C 8526 }UEFI_ACPI_VFCT; 8527 8528 typedef struct { 8529 ULONG PCIBus; //0x4C 8530 ULONG PCIDevice; //0x50 8531 ULONG PCIFunction; //0x54 8532 USHORT VendorID; //0x58 8533 USHORT DeviceID; //0x5A 8534 USHORT SSVID; //0x5C 8535 USHORT SSID; //0x5E 8536 ULONG Revision; //0x60 8537 ULONG ImageLength; //0x64 8538 }VFCT_IMAGE_HEADER; 8539 8540 8541 typedef struct { 8542 VFCT_IMAGE_HEADER VbiosHeader; 8543 UCHAR VbiosContent[1]; 8544 }GOP_VBIOS_CONTENT; 8545 8546 typedef struct { 8547 VFCT_IMAGE_HEADER Lib1Header; 8548 UCHAR Lib1Content[1]; 8549 }GOP_LIB1_CONTENT; 8550 8551 #pragma pack() 8552 8553 8554 #endif /* _ATOMBIOS_H */ 8555 8556 #include "pptable.h" 8557 8558
Indexes created Tue Oct 14 21:09:58 GMT 2025