atombios.h revision 1.3
1 /* $NetBSD: atombios.h,v 1.3 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2006-2007 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 */ 24 25 26 /****************************************************************************/ 27 /*Portion I: Definitions shared between VBIOS and Driver */ 28 /****************************************************************************/ 29 30 #ifndef _ATOMBIOS_H 31 #define _ATOMBIOS_H 32 33 #define ATOM_VERSION_MAJOR 0x00020000 34 #define ATOM_VERSION_MINOR 0x00000002 35 36 #define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR) 37 38 /* Endianness should be specified before inclusion, 39 * default to little endian 40 */ 41 #ifndef ATOM_BIG_ENDIAN 42 #error Endian not specified 43 #endif 44 45 #ifdef _H2INC 46 #ifndef ULONG 47 typedef unsigned long ULONG; 48 #endif 49 50 #ifndef UCHAR 51 typedef unsigned char UCHAR; 52 #endif 53 54 #ifndef USHORT 55 typedef unsigned short USHORT; 56 #endif 57 #endif 58 59 #define ATOM_DAC_A 0 60 #define ATOM_DAC_B 1 61 #define ATOM_EXT_DAC 2 62 63 #define ATOM_CRTC1 0 64 #define ATOM_CRTC2 1 65 #define ATOM_CRTC3 2 66 #define ATOM_CRTC4 3 67 #define ATOM_CRTC5 4 68 #define ATOM_CRTC6 5 69 70 #define ATOM_UNDERLAY_PIPE0 16 71 #define ATOM_UNDERLAY_PIPE1 17 72 73 #define ATOM_CRTC_INVALID 0xFF 74 75 #define ATOM_DIGA 0 76 #define ATOM_DIGB 1 77 78 #define ATOM_PPLL1 0 79 #define ATOM_PPLL2 1 80 #define ATOM_DCPLL 2 81 #define ATOM_PPLL0 2 82 #define ATOM_PPLL3 3 83 84 #define ATOM_PHY_PLL0 4 85 #define ATOM_PHY_PLL1 5 86 87 #define ATOM_EXT_PLL1 8 88 #define ATOM_GCK_DFS 8 89 #define ATOM_EXT_PLL2 9 90 #define ATOM_FCH_CLK 9 91 #define ATOM_EXT_CLOCK 10 92 #define ATOM_DP_DTO 11 93 94 #define ATOM_COMBOPHY_PLL0 20 95 #define ATOM_COMBOPHY_PLL1 21 96 #define ATOM_COMBOPHY_PLL2 22 97 #define ATOM_COMBOPHY_PLL3 23 98 #define ATOM_COMBOPHY_PLL4 24 99 #define ATOM_COMBOPHY_PLL5 25 100 101 #define ATOM_PPLL_INVALID 0xFF 102 103 #define ENCODER_REFCLK_SRC_P1PLL 0 104 #define ENCODER_REFCLK_SRC_P2PLL 1 105 #define ENCODER_REFCLK_SRC_DCPLL 2 106 #define ENCODER_REFCLK_SRC_EXTCLK 3 107 #define ENCODER_REFCLK_SRC_INVALID 0xFF 108 109 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication 110 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication 111 #define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode 112 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios 113 114 #define ATOM_DISABLE 0 115 #define ATOM_ENABLE 1 116 #define ATOM_LCD_BLOFF (ATOM_DISABLE+2) 117 #define ATOM_LCD_BLON (ATOM_ENABLE+2) 118 #define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3) 119 #define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5) 120 #define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5) 121 #define ATOM_ENCODER_INIT (ATOM_DISABLE+7) 122 #define ATOM_INIT (ATOM_DISABLE+7) 123 #define ATOM_GET_STATUS (ATOM_DISABLE+8) 124 125 #define ATOM_BLANKING 1 126 #define ATOM_BLANKING_OFF 0 127 128 129 #define ATOM_CRT1 0 130 #define ATOM_CRT2 1 131 132 #define ATOM_TV_NTSC 1 133 #define ATOM_TV_NTSCJ 2 134 #define ATOM_TV_PAL 3 135 #define ATOM_TV_PALM 4 136 #define ATOM_TV_PALCN 5 137 #define ATOM_TV_PALN 6 138 #define ATOM_TV_PAL60 7 139 #define ATOM_TV_SECAM 8 140 #define ATOM_TV_CV 16 141 142 #define ATOM_DAC1_PS2 1 143 #define ATOM_DAC1_CV 2 144 #define ATOM_DAC1_NTSC 3 145 #define ATOM_DAC1_PAL 4 146 147 #define ATOM_DAC2_PS2 ATOM_DAC1_PS2 148 #define ATOM_DAC2_CV ATOM_DAC1_CV 149 #define ATOM_DAC2_NTSC ATOM_DAC1_NTSC 150 #define ATOM_DAC2_PAL ATOM_DAC1_PAL 151 152 #define ATOM_PM_ON 0 153 #define ATOM_PM_STANDBY 1 154 #define ATOM_PM_SUSPEND 2 155 #define ATOM_PM_OFF 3 156 157 // For ATOM_LVDS_INFO_V12 158 // Bit0:{=0:single, =1:dual}, 159 // Bit1 {=0:666RGB, =1:888RGB}, 160 // Bit2:3:{Grey level} 161 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 162 #define ATOM_PANEL_MISC_DUAL 0x00000001 163 #define ATOM_PANEL_MISC_888RGB 0x00000002 164 #define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C 165 #define ATOM_PANEL_MISC_FPDI 0x00000010 166 #define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2 167 #define ATOM_PANEL_MISC_SPATIAL 0x00000020 168 #define ATOM_PANEL_MISC_TEMPORAL 0x00000040 169 #define ATOM_PANEL_MISC_API_ENABLED 0x00000080 170 171 #define MEMTYPE_DDR1 "DDR1" 172 #define MEMTYPE_DDR2 "DDR2" 173 #define MEMTYPE_DDR3 "DDR3" 174 #define MEMTYPE_DDR4 "DDR4" 175 176 #define ASIC_BUS_TYPE_PCI "PCI" 177 #define ASIC_BUS_TYPE_AGP "AGP" 178 #define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS" 179 180 //Maximum size of that FireGL flag string 181 #define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support 182 #define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING ) 183 184 #define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop 185 #define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 186 187 #define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support 188 #define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING ) 189 190 #define HW_ASSISTED_I2C_STATUS_FAILURE 2 191 #define HW_ASSISTED_I2C_STATUS_SUCCESS 1 192 193 #pragma pack(1) // BIOS data must use byte alignment 194 195 // Define offset to location of ROM header. 196 #define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L 197 #define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L 198 199 #define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94 200 #define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0! 201 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f 202 #define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e 203 204 /****************************************************************************/ 205 // Common header for all tables (Data table, Command table). 206 // Every table pointed _ATOM_MASTER_DATA_TABLE has this common header. 207 // And the pointer actually points to this header. 208 /****************************************************************************/ 209 210 typedef struct _ATOM_COMMON_TABLE_HEADER 211 { 212 USHORT usStructureSize; 213 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible 214 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware 215 //Image can't be updated, while Driver needs to carry the new table! 216 }ATOM_COMMON_TABLE_HEADER; 217 218 /****************************************************************************/ 219 // Structure stores the ROM header. 220 /****************************************************************************/ 221 typedef struct _ATOM_ROM_HEADER 222 { 223 ATOM_COMMON_TABLE_HEADER sHeader; 224 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 225 //atombios should init it as "ATOM", don't change the position 226 USHORT usBiosRuntimeSegmentAddress; 227 USHORT usProtectedModeInfoOffset; 228 USHORT usConfigFilenameOffset; 229 USHORT usCRC_BlockOffset; 230 USHORT usBIOS_BootupMessageOffset; 231 USHORT usInt10Offset; 232 USHORT usPciBusDevInitCode; 233 USHORT usIoBaseAddress; 234 USHORT usSubsystemVendorID; 235 USHORT usSubsystemID; 236 USHORT usPCI_InfoOffset; 237 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 238 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 239 UCHAR ucExtendedFunctionCode; 240 UCHAR ucReserved; 241 }ATOM_ROM_HEADER; 242 243 244 typedef struct _ATOM_ROM_HEADER_V2_1 245 { 246 ATOM_COMMON_TABLE_HEADER sHeader; 247 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios, 248 //atombios should init it as "ATOM", don't change the position 249 USHORT usBiosRuntimeSegmentAddress; 250 USHORT usProtectedModeInfoOffset; 251 USHORT usConfigFilenameOffset; 252 USHORT usCRC_BlockOffset; 253 USHORT usBIOS_BootupMessageOffset; 254 USHORT usInt10Offset; 255 USHORT usPciBusDevInitCode; 256 USHORT usIoBaseAddress; 257 USHORT usSubsystemVendorID; 258 USHORT usSubsystemID; 259 USHORT usPCI_InfoOffset; 260 USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position 261 USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position 262 UCHAR ucExtendedFunctionCode; 263 UCHAR ucReserved; 264 ULONG ulPSPDirTableOffset; 265 }ATOM_ROM_HEADER_V2_1; 266 267 268 //==============================Command Table Portion==================================== 269 270 271 /****************************************************************************/ 272 // Structures used in Command.mtb 273 /****************************************************************************/ 274 typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{ 275 USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1 276 USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON 277 USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 278 USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios 279 USHORT DIGxEncoderControl; //Only used by Bios 280 USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 281 USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1 282 USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed 283 USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2 284 USHORT GPIOPinControl; //Atomic Table, only used by Bios 285 USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1 286 USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1 287 USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2 288 USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 289 USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 290 USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 291 USHORT MemoryPLLInit; //Atomic Table, used only by Bios 292 USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes. 293 USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 294 USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios 295 USHORT SetUniphyInstance; //Atomic Table, only used by Bios 296 USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2 297 USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3 298 USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1 299 USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 300 USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1 301 USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 302 USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead 303 USHORT GetConditionalGoldenSetting; //Only used by Bios 304 USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1 305 USHORT PatchMCSetting; //only used by BIOS 306 USHORT MC_SEQ_Control; //only used by BIOS 307 USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting 308 USHORT EnableScaler; //Atomic Table, used only by Bios 309 USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 310 USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1 311 USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1 312 USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1 313 USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios 314 USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1 315 USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1 316 USHORT GetSMUClockInfo; //Atomic Table, used only by Bios 317 USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1 318 USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios 319 USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios 320 USHORT LUT_AutoFill; //Atomic Table, only used by Bios 321 USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK 322 USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1 323 USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1 324 USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1 325 USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1 326 USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 327 USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios 328 USHORT MemoryCleanUp; //Atomic Table, only used by Bios 329 USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios 330 USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components 331 USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components 332 USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init 333 USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1 334 USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 335 USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock 336 USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock 337 USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios 338 USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 339 USHORT MemoryTraining; //Atomic Table, used only by Bios 340 USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2 341 USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 342 USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1 343 USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1 344 USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1 345 USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C" 346 USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init 347 USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock 348 USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender 349 USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 350 USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1 351 USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 352 USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1 353 USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios 354 USHORT DPEncoderService; //Function Table,only used by Bios 355 USHORT GetVoltageInfo; //Function Table,only used by Bios since SI 356 }ATOM_MASTER_LIST_OF_COMMAND_TABLES; 357 358 // For backward compatible 359 #define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction 360 #define DPTranslatorControl DIG2EncoderControl 361 #define UNIPHYTransmitterControl DIG1TransmitterControl 362 #define LVTMATransmitterControl DIG2TransmitterControl 363 #define SetCRTC_DPM_State GetConditionalGoldenSetting 364 #define ASIC_StaticPwrMgtStatusChange SetUniphyInstance 365 #define HPDInterruptService ReadHWAssistedI2CStatus 366 #define EnableVGA_Access GetSCLKOverMCLKRatio 367 #define EnableYUV GetDispObjectInfo 368 #define DynamicClockGating EnableDispPowerGating 369 #define SetupHWAssistedI2CStatus ComputeMemoryClockParam 370 #define DAC2OutputControl ReadEfuseValue 371 372 #define TMDSAEncoderControl PatchMCSetting 373 #define LVDSEncoderControl MC_SEQ_Control 374 #define LCD1OutputControl HW_Misc_Operation 375 #define TV1OutputControl Gfx_Harvesting 376 #define TVEncoderControl SMC_Init 377 #define EnableHW_IconCursor SetDCEClock 378 #define SetCRTC_Replication GetSMUClockInfo 379 380 #define MemoryRefreshConversion Gfx_Init 381 382 typedef struct _ATOM_MASTER_COMMAND_TABLE 383 { 384 ATOM_COMMON_TABLE_HEADER sHeader; 385 ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables; 386 }ATOM_MASTER_COMMAND_TABLE; 387 388 /****************************************************************************/ 389 // Structures used in every command table 390 /****************************************************************************/ 391 typedef struct _ATOM_TABLE_ATTRIBUTE 392 { 393 #if ATOM_BIG_ENDIAN 394 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 395 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 396 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 397 #else 398 USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 399 USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 400 USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag 401 #endif 402 }ATOM_TABLE_ATTRIBUTE; 403 404 /****************************************************************************/ 405 // Common header for all command tables. 406 // Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 407 // And the pointer actually points to this header. 408 /****************************************************************************/ 409 typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER 410 { 411 ATOM_COMMON_TABLE_HEADER CommonHeader; 412 ATOM_TABLE_ATTRIBUTE TableAttribute; 413 }ATOM_COMMON_ROM_COMMAND_TABLE_HEADER; 414 415 /****************************************************************************/ 416 // Structures used by ComputeMemoryEnginePLLTable 417 /****************************************************************************/ 418 419 #define COMPUTE_MEMORY_PLL_PARAM 1 420 #define COMPUTE_ENGINE_PLL_PARAM 2 421 #define ADJUST_MC_SETTING_PARAM 3 422 423 /****************************************************************************/ 424 // Structures used by AdjustMemoryControllerTable 425 /****************************************************************************/ 426 typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ 427 { 428 #if ATOM_BIG_ENDIAN 429 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 430 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 431 ULONG ulClockFreq:24; 432 #else 433 ULONG ulClockFreq:24; 434 ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0] 435 ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block 436 #endif 437 }ATOM_ADJUST_MEMORY_CLOCK_FREQ; 438 #define POINTER_RETURN_FLAG 0x80 439 440 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 441 { 442 ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div 443 UCHAR ucAction; //0:reserved //1:Memory //2:Engine 444 UCHAR ucReserved; //may expand to return larger Fbdiv later 445 UCHAR ucFbDiv; //return value 446 UCHAR ucPostDiv; //return value 447 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS; 448 449 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 450 { 451 ULONG ulClock; //When return, [23:0] return real clock 452 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register 453 USHORT usFbDiv; //return Feedback value to be written to register 454 UCHAR ucPostDiv; //return post div to be written to register 455 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2; 456 457 #define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS 458 459 #define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value 460 #define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 461 #define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 462 #define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 463 #define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 464 #define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 465 #define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK 466 467 #define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa) 468 #define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition 469 #define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change 470 #define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup 471 #define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL 472 #define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path 473 #define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 474 #define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only 475 #define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only 476 477 typedef struct _ATOM_COMPUTE_CLOCK_FREQ 478 { 479 #if ATOM_BIG_ENDIAN 480 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 481 ULONG ulClockFreq:24; // in unit of 10kHz 482 #else 483 ULONG ulClockFreq:24; // in unit of 10kHz 484 ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM 485 #endif 486 }ATOM_COMPUTE_CLOCK_FREQ; 487 488 typedef struct _ATOM_S_MPLL_FB_DIVIDER 489 { 490 USHORT usFbDivFrac; 491 USHORT usFbDiv; 492 }ATOM_S_MPLL_FB_DIVIDER; 493 494 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 495 { 496 union 497 { 498 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 499 ULONG ulClockParams; //ULONG access for BE 500 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 501 }; 502 UCHAR ucRefDiv; //Output Parameter 503 UCHAR ucPostDiv; //Output Parameter 504 UCHAR ucCntlFlag; //Output Parameter 505 UCHAR ucReserved; 506 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3; 507 508 // ucCntlFlag 509 #define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1 510 #define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2 511 #define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4 512 #define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8 513 514 515 // V4 are only used for APU which PLL outside GPU 516 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 517 { 518 #if ATOM_BIG_ENDIAN 519 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 520 ULONG ulClock:24; //Input= target clock, output = actual clock 521 #else 522 ULONG ulClock:24; //Input= target clock, output = actual clock 523 ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly 524 #endif 525 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4; 526 527 typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 528 { 529 union 530 { 531 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 532 ULONG ulClockParams; //ULONG access for BE 533 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter 534 }; 535 UCHAR ucRefDiv; //Output Parameter 536 UCHAR ucPostDiv; //Output Parameter 537 union 538 { 539 UCHAR ucCntlFlag; //Output Flags 540 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode 541 }; 542 UCHAR ucReserved; 543 }COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5; 544 545 546 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 547 { 548 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 549 ULONG ulReserved[2]; 550 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6; 551 552 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 553 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 554 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 555 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 556 557 558 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 559 { 560 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 561 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider 562 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider 563 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider 564 UCHAR ucPllCntlFlag; //Output Flags: control flag 565 UCHAR ucReserved; 566 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6; 567 568 //ucPllCntlFlag 569 #define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 570 571 typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 572 { 573 ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter 574 ULONG ulReserved[5]; 575 }COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7; 576 577 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 578 #define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f 579 #define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00 580 #define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01 581 582 typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 583 { 584 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider 585 USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 586 USHORT usSclk_fcw_int; //integer divider of fcwc 587 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv 588 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved 589 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 ) 590 UCHAR ucSscEnable; 591 USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable 592 USHORT usSsc_fcw1_int; //fcw1_int when SSC enable 593 USHORT usReserved; 594 USHORT usPcc_fcw_int; 595 USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable 596 USHORT usPcc_fcw_slew_frac; 597 }COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7; 598 599 // ucInputFlag 600 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode 601 602 // use for ComputeMemoryClockParamTable 603 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 604 { 605 union 606 { 607 ULONG ulClock; 608 ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS) 609 }; 610 UCHAR ucDllSpeed; //Output 611 UCHAR ucPostDiv; //Output 612 union{ 613 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode 614 UCHAR ucPllCntlFlag; //Output: 615 }; 616 UCHAR ucBWCntl; 617 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1; 618 619 // definition of ucInputFlag 620 #define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01 621 // definition of ucPllCntlFlag 622 #define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03 623 #define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04 624 #define MPLL_CNTL_FLAG_QDR_ENABLE 0x08 625 #define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10 626 627 //MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL 628 #define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04 629 630 // use for ComputeMemoryClockParamTable 631 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 632 { 633 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 634 ULONG ulReserved; 635 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2; 636 637 typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3 638 { 639 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; 640 USHORT usMclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536 641 USHORT usMclk_fcw_int; //integer divider of fcwc 642 }COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_3; 643 644 //Input parameter of DynamicMemorySettingsTable 645 //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM 646 typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER 647 { 648 ATOM_COMPUTE_CLOCK_FREQ ulClock; 649 ULONG ulReserved[2]; 650 }DYNAMICE_MEMORY_SETTINGS_PARAMETER; 651 652 //Input parameter of DynamicMemorySettingsTable 653 //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM 654 typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER 655 { 656 ATOM_COMPUTE_CLOCK_FREQ ulClock; 657 ULONG ulMemoryClock; 658 ULONG ulReserved; 659 }DYNAMICE_ENGINE_SETTINGS_PARAMETER; 660 661 //Input parameter of DynamicMemorySettingsTable ver2.1 and above 662 //when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM 663 typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER 664 { 665 ATOM_COMPUTE_CLOCK_FREQ ulClock; 666 UCHAR ucMclkDPMState; 667 UCHAR ucReserved[3]; 668 ULONG ulReserved; 669 }DYNAMICE_MC_DPM_SETTINGS_PARAMETER; 670 671 //ucMclkDPMState 672 #define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0 673 #define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1 674 #define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2 675 676 typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 677 { 678 DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg; 679 DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg; 680 DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg; 681 }DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1; 682 683 684 /****************************************************************************/ 685 // Structures used by SetEngineClockTable 686 /****************************************************************************/ 687 typedef struct _SET_ENGINE_CLOCK_PARAMETERS 688 { 689 ULONG ulTargetEngineClock; //In 10Khz unit 690 }SET_ENGINE_CLOCK_PARAMETERS; 691 692 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION 693 { 694 ULONG ulTargetEngineClock; //In 10Khz unit 695 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 696 }SET_ENGINE_CLOCK_PS_ALLOCATION; 697 698 typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2 699 { 700 ULONG ulTargetEngineClock; //In 10Khz unit 701 COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved; 702 }SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2; 703 704 705 /****************************************************************************/ 706 // Structures used by SetMemoryClockTable 707 /****************************************************************************/ 708 typedef struct _SET_MEMORY_CLOCK_PARAMETERS 709 { 710 ULONG ulTargetMemoryClock; //In 10Khz unit 711 }SET_MEMORY_CLOCK_PARAMETERS; 712 713 typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION 714 { 715 ULONG ulTargetMemoryClock; //In 10Khz unit 716 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved; 717 }SET_MEMORY_CLOCK_PS_ALLOCATION; 718 719 /****************************************************************************/ 720 // Structures used by ASIC_Init.ctb 721 /****************************************************************************/ 722 typedef struct _ASIC_INIT_PARAMETERS 723 { 724 ULONG ulDefaultEngineClock; //In 10Khz unit 725 ULONG ulDefaultMemoryClock; //In 10Khz unit 726 }ASIC_INIT_PARAMETERS; 727 728 typedef struct _ASIC_INIT_PS_ALLOCATION 729 { 730 ASIC_INIT_PARAMETERS sASICInitClocks; 731 SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure 732 }ASIC_INIT_PS_ALLOCATION; 733 734 typedef struct _ASIC_INIT_CLOCK_PARAMETERS 735 { 736 ULONG ulClkFreqIn10Khz:24; 737 ULONG ucClkFlag:8; 738 }ASIC_INIT_CLOCK_PARAMETERS; 739 740 typedef struct _ASIC_INIT_PARAMETERS_V1_2 741 { 742 ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit 743 ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit 744 }ASIC_INIT_PARAMETERS_V1_2; 745 746 typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2 747 { 748 ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks; 749 ULONG ulReserved[8]; 750 }ASIC_INIT_PS_ALLOCATION_V1_2; 751 752 /****************************************************************************/ 753 // Structure used by DynamicClockGatingTable.ctb 754 /****************************************************************************/ 755 typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS 756 { 757 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 758 UCHAR ucPadding[3]; 759 }DYNAMIC_CLOCK_GATING_PARAMETERS; 760 #define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS 761 762 /****************************************************************************/ 763 // Structure used by EnableDispPowerGatingTable.ctb 764 /****************************************************************************/ 765 typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 766 { 767 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 768 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 769 UCHAR ucPadding[2]; 770 }ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1; 771 772 typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION 773 { 774 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ... 775 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT 776 UCHAR ucPadding[2]; 777 ULONG ulReserved[4]; 778 }ENABLE_DISP_POWER_GATING_PS_ALLOCATION; 779 780 /****************************************************************************/ 781 // Structure used by EnableASIC_StaticPwrMgtTable.ctb 782 /****************************************************************************/ 783 typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 784 { 785 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 786 UCHAR ucPadding[3]; 787 }ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS; 788 #define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS 789 790 /****************************************************************************/ 791 // Structures used by DAC_LoadDetectionTable.ctb 792 /****************************************************************************/ 793 typedef struct _DAC_LOAD_DETECTION_PARAMETERS 794 { 795 USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT} 796 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC} 797 UCHAR ucMisc; //Valid only when table revision =1.3 and above 798 }DAC_LOAD_DETECTION_PARAMETERS; 799 800 // DAC_LOAD_DETECTION_PARAMETERS.ucMisc 801 #define DAC_LOAD_MISC_YPrPb 0x01 802 803 typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION 804 { 805 DAC_LOAD_DETECTION_PARAMETERS sDacload; 806 ULONG Reserved[2];// Don't set this one, allocation for EXT DAC 807 }DAC_LOAD_DETECTION_PS_ALLOCATION; 808 809 /****************************************************************************/ 810 // Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb 811 /****************************************************************************/ 812 typedef struct _DAC_ENCODER_CONTROL_PARAMETERS 813 { 814 USHORT usPixelClock; // in 10KHz; for bios convenient 815 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0) 816 UCHAR ucAction; // 0: turn off encoder 817 // 1: setup and turn on encoder 818 // 7: ATOM_ENCODER_INIT Initialize DAC 819 }DAC_ENCODER_CONTROL_PARAMETERS; 820 821 #define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS 822 823 /****************************************************************************/ 824 // Structures used by DIG1EncoderControlTable 825 // DIG2EncoderControlTable 826 // ExternalEncoderControlTable 827 /****************************************************************************/ 828 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS 829 { 830 USHORT usPixelClock; // in 10KHz; for bios convenient 831 UCHAR ucConfig; 832 // [2] Link Select: 833 // =0: PHY linkA if bfLane<3 834 // =1: PHY linkB if bfLanes<3 835 // =0: PHY linkA+B if bfLanes=3 836 // [3] Transmitter Sel 837 // =0: UNIPHY or PCIEPHY 838 // =1: LVTMA 839 UCHAR ucAction; // =0: turn off encoder 840 // =1: turn on encoder 841 UCHAR ucEncoderMode; 842 // =0: DP encoder 843 // =1: LVDS encoder 844 // =2: DVI encoder 845 // =3: HDMI encoder 846 // =4: SDVO encoder 847 UCHAR ucLaneNum; // how many lanes to enable 848 UCHAR ucReserved[2]; 849 }DIG_ENCODER_CONTROL_PARAMETERS; 850 #define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS 851 #define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS 852 853 //ucConfig 854 #define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01 855 #define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00 856 #define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01 857 #define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02 858 #define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04 859 #define ATOM_ENCODER_CONFIG_LINKA 0x00 860 #define ATOM_ENCODER_CONFIG_LINKB 0x04 861 #define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA 862 #define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB 863 #define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08 864 #define ATOM_ENCODER_CONFIG_UNIPHY 0x00 865 #define ATOM_ENCODER_CONFIG_LVTMA 0x08 866 #define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00 867 #define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08 868 #define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0 869 // ucAction 870 // ATOM_ENABLE: Enable Encoder 871 // ATOM_DISABLE: Disable Encoder 872 873 //ucEncoderMode 874 #define ATOM_ENCODER_MODE_DP 0 875 #define ATOM_ENCODER_MODE_LVDS 1 876 #define ATOM_ENCODER_MODE_DVI 2 877 #define ATOM_ENCODER_MODE_HDMI 3 878 #define ATOM_ENCODER_MODE_SDVO 4 879 #define ATOM_ENCODER_MODE_DP_AUDIO 5 880 #define ATOM_ENCODER_MODE_TV 13 881 #define ATOM_ENCODER_MODE_CV 14 882 #define ATOM_ENCODER_MODE_CRT 15 883 #define ATOM_ENCODER_MODE_DVO 16 884 #define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2 885 #define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2 886 887 888 typedef struct _ATOM_DIG_ENCODER_CONFIG_V2 889 { 890 #if ATOM_BIG_ENDIAN 891 UCHAR ucReserved1:2; 892 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 893 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 894 UCHAR ucReserved:1; 895 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 896 #else 897 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 898 UCHAR ucReserved:1; 899 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F 900 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF 901 UCHAR ucReserved1:2; 902 #endif 903 }ATOM_DIG_ENCODER_CONFIG_V2; 904 905 906 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2 907 { 908 USHORT usPixelClock; // in 10KHz; for bios convenient 909 ATOM_DIG_ENCODER_CONFIG_V2 acConfig; 910 UCHAR ucAction; 911 UCHAR ucEncoderMode; 912 // =0: DP encoder 913 // =1: LVDS encoder 914 // =2: DVI encoder 915 // =3: HDMI encoder 916 // =4: SDVO encoder 917 UCHAR ucLaneNum; // how many lanes to enable 918 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 919 UCHAR ucReserved; 920 }DIG_ENCODER_CONTROL_PARAMETERS_V2; 921 922 //ucConfig 923 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01 924 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00 925 #define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01 926 #define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04 927 #define ATOM_ENCODER_CONFIG_V2_LINKA 0x00 928 #define ATOM_ENCODER_CONFIG_V2_LINKB 0x04 929 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18 930 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00 931 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08 932 #define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10 933 934 // ucAction: 935 // ATOM_DISABLE 936 // ATOM_ENABLE 937 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08 938 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09 939 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a 940 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13 941 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b 942 #define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c 943 #define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d 944 #define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e 945 #define ATOM_ENCODER_CMD_SETUP 0x0f 946 #define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10 947 948 // New Command for DIGxEncoderControlTable v1.5 949 #define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14 950 #define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP 951 #define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table 952 #define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table 953 954 // ucStatus 955 #define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10 956 #define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00 957 958 //ucTableFormatRevision=1 959 //ucTableContentRevision=3 960 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 961 typedef struct _ATOM_DIG_ENCODER_CONFIG_V3 962 { 963 #if ATOM_BIG_ENDIAN 964 UCHAR ucReserved1:1; 965 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 966 UCHAR ucReserved:3; 967 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 968 #else 969 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz 970 UCHAR ucReserved:3; 971 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 972 UCHAR ucReserved1:1; 973 #endif 974 }ATOM_DIG_ENCODER_CONFIG_V3; 975 976 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 977 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 978 #define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 979 #define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70 980 #define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00 981 #define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10 982 #define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20 983 #define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30 984 #define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40 985 #define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50 986 987 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3 988 { 989 USHORT usPixelClock; // in 10KHz; for bios convenient 990 ATOM_DIG_ENCODER_CONFIG_V3 acConfig; 991 UCHAR ucAction; 992 union{ 993 UCHAR ucEncoderMode; 994 // =0: DP encoder 995 // =1: LVDS encoder 996 // =2: DVI encoder 997 // =3: HDMI encoder 998 // =4: SDVO encoder 999 // =5: DP audio 1000 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1001 // =0: external DP 1002 // =0x1: internal DP2 1003 // =0x11: internal DP1 for NutMeg/Travis DP translator 1004 }; 1005 UCHAR ucLaneNum; // how many lanes to enable 1006 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1007 UCHAR ucReserved; 1008 }DIG_ENCODER_CONTROL_PARAMETERS_V3; 1009 1010 //ucTableFormatRevision=1 1011 //ucTableContentRevision=4 1012 // start from NI 1013 // Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver 1014 typedef struct _ATOM_DIG_ENCODER_CONFIG_V4 1015 { 1016 #if ATOM_BIG_ENDIAN 1017 UCHAR ucReserved1:1; 1018 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1019 UCHAR ucReserved:2; 1020 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1021 #else 1022 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version 1023 UCHAR ucReserved:2; 1024 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F) 1025 UCHAR ucReserved1:1; 1026 #endif 1027 }ATOM_DIG_ENCODER_CONFIG_V4; 1028 1029 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03 1030 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00 1031 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01 1032 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02 1033 #define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03 1034 #define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70 1035 #define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00 1036 #define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10 1037 #define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20 1038 #define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30 1039 #define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40 1040 #define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50 1041 #define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60 1042 1043 typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4 1044 { 1045 USHORT usPixelClock; // in 10KHz; for bios convenient 1046 union{ 1047 ATOM_DIG_ENCODER_CONFIG_V4 acConfig; 1048 UCHAR ucConfig; 1049 }; 1050 UCHAR ucAction; 1051 union{ 1052 UCHAR ucEncoderMode; 1053 // =0: DP encoder 1054 // =1: LVDS encoder 1055 // =2: DVI encoder 1056 // =3: HDMI encoder 1057 // =4: SDVO encoder 1058 // =5: DP audio 1059 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE 1060 // =0: external DP 1061 // =0x1: internal DP2 1062 // =0x11: internal DP1 for NutMeg/Travis DP translator 1063 }; 1064 UCHAR ucLaneNum; // how many lanes to enable 1065 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP 1066 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version 1067 }DIG_ENCODER_CONTROL_PARAMETERS_V4; 1068 1069 // define ucBitPerColor: 1070 #define PANEL_BPC_UNDEFINE 0x00 1071 #define PANEL_6BIT_PER_COLOR 0x01 1072 #define PANEL_8BIT_PER_COLOR 0x02 1073 #define PANEL_10BIT_PER_COLOR 0x03 1074 #define PANEL_12BIT_PER_COLOR 0x04 1075 #define PANEL_16BIT_PER_COLOR 0x05 1076 1077 //define ucPanelMode 1078 #define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00 1079 #define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01 1080 #define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11 1081 1082 1083 typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5 1084 { 1085 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1086 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP 1087 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1088 UCHAR ucLaneNum; // Lane number 1089 ULONG ulPixelClock; // Pixel Clock in 10Khz 1090 UCHAR ucBitPerColor; 1091 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 1092 UCHAR ucReserved[2]; 1093 }ENCODER_STREAM_SETUP_PARAMETERS_V5; 1094 1095 typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5 1096 { 1097 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1098 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP 1099 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1100 UCHAR ucLaneNum; // Lane number 1101 ULONG ulSymClock; // Symbol Clock in 10Khz 1102 UCHAR ucHPDSel; 1103 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1104 UCHAR ucReserved[2]; 1105 }ENCODER_LINK_SETUP_PARAMETERS_V5; 1106 1107 typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5 1108 { 1109 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1110 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP 1111 UCHAR ucPanelMode; // =0: external DP 1112 // =0x1: internal DP2 1113 // =0x11: internal DP1 NutMeg/Travis DP Translator 1114 UCHAR ucReserved; 1115 ULONG ulReserved[2]; 1116 }DP_PANEL_MODE_SETUP_PARAMETERS_V5; 1117 1118 typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5 1119 { 1120 UCHAR ucDigId; // 0~6 map to DIG0~DIG6 1121 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters 1122 UCHAR ucReserved[2]; 1123 ULONG ulReserved[2]; 1124 }ENCODER_GENERIC_CMD_PARAMETERS_V5; 1125 1126 //ucDigId 1127 #define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00 1128 #define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01 1129 #define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02 1130 #define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03 1131 #define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04 1132 #define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05 1133 #define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06 1134 1135 1136 typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5 1137 { 1138 ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam; 1139 ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam; 1140 ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam; 1141 DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam; 1142 }DIG_ENCODER_CONTROL_PARAMETERS_V5; 1143 1144 1145 /****************************************************************************/ 1146 // Structures used by UNIPHYTransmitterControlTable 1147 // LVTMATransmitterControlTable 1148 // DVOOutputControlTable 1149 /****************************************************************************/ 1150 typedef struct _ATOM_DP_VS_MODE 1151 { 1152 UCHAR ucLaneSel; 1153 UCHAR ucLaneSet; 1154 }ATOM_DP_VS_MODE; 1155 1156 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS 1157 { 1158 union 1159 { 1160 USHORT usPixelClock; // in 10KHz; for bios convenient 1161 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1162 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1163 }; 1164 UCHAR ucConfig; 1165 // [0]=0: 4 lane Link, 1166 // =1: 8 lane Link ( Dual Links TMDS ) 1167 // [1]=0: InCoherent mode 1168 // =1: Coherent Mode 1169 // [2] Link Select: 1170 // =0: PHY linkA if bfLane<3 1171 // =1: PHY linkB if bfLanes<3 1172 // =0: PHY linkA+B if bfLanes=3 1173 // [5:4]PCIE lane Sel 1174 // =0: lane 0~3 or 0~7 1175 // =1: lane 4~7 1176 // =2: lane 8~11 or 8~15 1177 // =3: lane 12~15 1178 UCHAR ucAction; // =0: turn off encoder 1179 // =1: turn on encoder 1180 UCHAR ucReserved[4]; 1181 }DIG_TRANSMITTER_CONTROL_PARAMETERS; 1182 1183 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS 1184 1185 //ucInitInfo 1186 #define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff 1187 1188 //ucConfig 1189 #define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01 1190 #define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02 1191 #define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04 1192 #define ATOM_TRANSMITTER_CONFIG_LINKA 0x00 1193 #define ATOM_TRANSMITTER_CONFIG_LINKB 0x04 1194 #define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00 1195 #define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04 1196 1197 #define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1198 #define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1199 #define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE 1200 1201 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30 1202 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00 1203 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20 1204 #define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30 1205 #define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0 1206 #define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00 1207 #define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00 1208 #define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40 1209 #define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80 1210 #define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80 1211 #define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0 1212 1213 //ucAction 1214 #define ATOM_TRANSMITTER_ACTION_DISABLE 0 1215 #define ATOM_TRANSMITTER_ACTION_ENABLE 1 1216 #define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2 1217 #define ATOM_TRANSMITTER_ACTION_LCD_BLON 3 1218 #define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4 1219 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5 1220 #define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6 1221 #define ATOM_TRANSMITTER_ACTION_INIT 7 1222 #define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8 1223 #define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9 1224 #define ATOM_TRANSMITTER_ACTION_SETUP 10 1225 #define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11 1226 #define ATOM_TRANSMITTER_ACTION_POWER_ON 12 1227 #define ATOM_TRANSMITTER_ACTION_POWER_OFF 13 1228 1229 // Following are used for DigTransmitterControlTable ver1.2 1230 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2 1231 { 1232 #if ATOM_BIG_ENDIAN 1233 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1234 // =1 Dig Transmitter 2 ( Uniphy CD ) 1235 // =2 Dig Transmitter 3 ( Uniphy EF ) 1236 UCHAR ucReserved:1; 1237 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1238 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1239 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1240 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1241 1242 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1244 #else 1245 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1246 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1247 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1248 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1249 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 ) 1250 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector 1251 UCHAR ucReserved:1; 1252 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1253 // =1 Dig Transmitter 2 ( Uniphy CD ) 1254 // =2 Dig Transmitter 3 ( Uniphy EF ) 1255 #endif 1256 }ATOM_DIG_TRANSMITTER_CONFIG_V2; 1257 1258 //ucConfig 1259 //Bit0 1260 #define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01 1261 1262 //Bit1 1263 #define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02 1264 1265 //Bit2 1266 #define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04 1267 #define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00 1268 #define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04 1269 1270 // Bit3 1271 #define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08 1272 #define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1273 #define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP 1274 1275 // Bit4 1276 #define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10 1277 1278 // Bit7:6 1279 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0 1280 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB 1281 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD 1282 #define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF 1283 1284 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 1285 { 1286 union 1287 { 1288 USHORT usPixelClock; // in 10KHz; for bios convenient 1289 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1290 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1291 }; 1292 ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig; 1293 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1294 UCHAR ucReserved[4]; 1295 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V2; 1296 1297 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3 1298 { 1299 #if ATOM_BIG_ENDIAN 1300 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1301 // =1 Dig Transmitter 2 ( Uniphy CD ) 1302 // =2 Dig Transmitter 3 ( Uniphy EF ) 1303 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1304 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1305 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1306 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1307 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1309 #else 1310 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1311 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1312 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1313 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1314 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1315 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 1316 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1317 // =1 Dig Transmitter 2 ( Uniphy CD ) 1318 // =2 Dig Transmitter 3 ( Uniphy EF ) 1319 #endif 1320 }ATOM_DIG_TRANSMITTER_CONFIG_V3; 1321 1322 1323 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 1324 { 1325 union 1326 { 1327 USHORT usPixelClock; // in 10KHz; for bios convenient 1328 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1329 ATOM_DP_VS_MODE asMode; // DP Voltage swing mode 1330 }; 1331 ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig; 1332 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1333 UCHAR ucLaneNum; 1334 UCHAR ucReserved[3]; 1335 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V3; 1336 1337 //ucConfig 1338 //Bit0 1339 #define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01 1340 1341 //Bit1 1342 #define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02 1343 1344 //Bit2 1345 #define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04 1346 #define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00 1347 #define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04 1348 1349 // Bit3 1350 #define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08 1351 #define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00 1352 #define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08 1353 1354 // Bit5:4 1355 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30 1356 #define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00 1357 #define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10 1358 #define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20 1359 1360 // Bit7:6 1361 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0 1362 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB 1363 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD 1364 #define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF 1365 1366 1367 /****************************************************************************/ 1368 // Structures used by UNIPHYTransmitterControlTable V1.4 1369 // ASIC Families: NI 1370 // ucTableFormatRevision=1 1371 // ucTableContentRevision=4 1372 /****************************************************************************/ 1373 typedef struct _ATOM_DP_VS_MODE_V4 1374 { 1375 UCHAR ucLaneSel; 1376 union 1377 { 1378 UCHAR ucLaneSet; 1379 struct { 1380 #if ATOM_BIG_ENDIAN 1381 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1382 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1384 #else 1385 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level 1386 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level 1387 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4 1388 #endif 1389 }; 1390 }; 1391 }ATOM_DP_VS_MODE_V4; 1392 1393 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4 1394 { 1395 #if ATOM_BIG_ENDIAN 1396 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1397 // =1 Dig Transmitter 2 ( Uniphy CD ) 1398 // =2 Dig Transmitter 3 ( Uniphy EF ) 1399 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1400 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1401 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1402 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1403 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1405 #else 1406 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector 1407 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode ) 1408 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E 1409 // =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F 1410 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F 1411 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New 1412 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB ) 1413 // =1 Dig Transmitter 2 ( Uniphy CD ) 1414 // =2 Dig Transmitter 3 ( Uniphy EF ) 1415 #endif 1416 }ATOM_DIG_TRANSMITTER_CONFIG_V4; 1417 1418 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 1419 { 1420 union 1421 { 1422 USHORT usPixelClock; // in 10KHz; for bios convenient 1423 USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h 1424 ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version 1425 }; 1426 union 1427 { 1428 ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig; 1429 UCHAR ucConfig; 1430 }; 1431 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX 1432 UCHAR ucLaneNum; 1433 UCHAR ucReserved[3]; 1434 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V4; 1435 1436 //ucConfig 1437 //Bit0 1438 #define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01 1439 //Bit1 1440 #define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02 1441 //Bit2 1442 #define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04 1443 #define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00 1444 #define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04 1445 // Bit3 1446 #define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08 1447 #define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00 1448 #define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08 1449 // Bit5:4 1450 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30 1451 #define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00 1452 #define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10 1453 #define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4 1454 #define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3 1455 // Bit7:6 1456 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0 1457 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB 1458 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD 1459 #define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF 1460 1461 1462 typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5 1463 { 1464 #if ATOM_BIG_ENDIAN 1465 UCHAR ucReservd1:1; 1466 UCHAR ucHPDSel:3; 1467 UCHAR ucPhyClkSrcId:2; 1468 UCHAR ucCoherentMode:1; 1469 UCHAR ucReserved:1; 1470 #else 1471 UCHAR ucReserved:1; 1472 UCHAR ucCoherentMode:1; 1473 UCHAR ucPhyClkSrcId:2; 1474 UCHAR ucHPDSel:3; 1475 UCHAR ucReservd1:1; 1476 #endif 1477 }ATOM_DIG_TRANSMITTER_CONFIG_V5; 1478 1479 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1480 { 1481 USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio 1482 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1483 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1484 UCHAR ucLaneNum; // indicate lane number 1-8 1485 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1486 UCHAR ucDigMode; // indicate DIG mode 1487 union{ 1488 ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1489 UCHAR ucConfig; 1490 }; 1491 UCHAR ucDigEncoderSel; // indicate DIG front end encoder 1492 UCHAR ucDPLaneSet; 1493 UCHAR ucReserved; 1494 UCHAR ucReserved1; 1495 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5; 1496 1497 //ucPhyId 1498 #define ATOM_PHY_ID_UNIPHYA 0 1499 #define ATOM_PHY_ID_UNIPHYB 1 1500 #define ATOM_PHY_ID_UNIPHYC 2 1501 #define ATOM_PHY_ID_UNIPHYD 3 1502 #define ATOM_PHY_ID_UNIPHYE 4 1503 #define ATOM_PHY_ID_UNIPHYF 5 1504 #define ATOM_PHY_ID_UNIPHYG 6 1505 1506 // ucDigEncoderSel 1507 #define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01 1508 #define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02 1509 #define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04 1510 #define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08 1511 #define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10 1512 #define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20 1513 #define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40 1514 1515 // ucDigMode 1516 #define ATOM_TRANSMITTER_DIGMODE_V5_DP 0 1517 #define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1 1518 #define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2 1519 #define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3 1520 #define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4 1521 #define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5 1522 1523 // ucDPLaneSet 1524 #define DP_LANE_SET__0DB_0_4V 0x00 1525 #define DP_LANE_SET__0DB_0_6V 0x01 1526 #define DP_LANE_SET__0DB_0_8V 0x02 1527 #define DP_LANE_SET__0DB_1_2V 0x03 1528 #define DP_LANE_SET__3_5DB_0_4V 0x08 1529 #define DP_LANE_SET__3_5DB_0_6V 0x09 1530 #define DP_LANE_SET__3_5DB_0_8V 0x0a 1531 #define DP_LANE_SET__6DB_0_4V 0x10 1532 #define DP_LANE_SET__6DB_0_6V 0x11 1533 #define DP_LANE_SET__9_5DB_0_4V 0x18 1534 1535 // ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig; 1536 // Bit1 1537 #define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02 1538 1539 // Bit3:2 1540 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c 1541 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02 1542 1543 #define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00 1544 #define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04 1545 #define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08 1546 #define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c 1547 // Bit6:4 1548 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70 1549 #define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04 1550 1551 #define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00 1552 #define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10 1553 #define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20 1554 #define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30 1555 #define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40 1556 #define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50 1557 #define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60 1558 1559 #define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 1560 1561 typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6 1562 { 1563 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 1564 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx 1565 union 1566 { 1567 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 1568 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 1569 }; 1570 UCHAR ucLaneNum; // Lane number 1571 ULONG ulSymClock; // Symbol Clock in 10Khz 1572 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 1573 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 1574 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h 1575 UCHAR ucReserved; 1576 ULONG ulReserved; 1577 }DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6; 1578 1579 1580 // ucDigEncoderSel 1581 #define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01 1582 #define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02 1583 #define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04 1584 #define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08 1585 #define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10 1586 #define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20 1587 #define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40 1588 1589 // ucDigMode 1590 #define ATOM_TRANSMITTER_DIGMODE_V6_DP 0 1591 #define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2 1592 #define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3 1593 #define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5 1594 1595 //ucHPDSel 1596 #define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00 1597 #define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01 1598 #define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02 1599 #define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03 1600 #define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04 1601 #define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05 1602 #define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06 1603 1604 1605 /****************************************************************************/ 1606 // Structures used by ExternalEncoderControlTable V1.3 1607 // ASIC Families: Evergreen, Llano, NI 1608 // ucTableFormatRevision=1 1609 // ucTableContentRevision=3 1610 /****************************************************************************/ 1611 1612 typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 1613 { 1614 union{ 1615 USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 1616 USHORT usConnectorId; // connector id, valid when ucAction = INIT 1617 }; 1618 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 1619 UCHAR ucAction; // 1620 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 1621 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 1622 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 1623 UCHAR ucReserved; 1624 }EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3; 1625 1626 // ucAction 1627 #define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00 1628 #define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01 1629 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07 1630 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f 1631 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10 1632 #define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11 1633 #define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12 1634 #define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14 1635 1636 // ucConfig 1637 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03 1638 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00 1639 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01 1640 #define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02 1641 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70 1642 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00 1643 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10 1644 #define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20 1645 1646 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 1647 { 1648 EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder; 1649 ULONG ulReserved[2]; 1650 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3; 1651 1652 1653 /****************************************************************************/ 1654 // Structures used by DAC1OuputControlTable 1655 // DAC2OuputControlTable 1656 // LVTMAOutputControlTable (Before DEC30) 1657 // TMDSAOutputControlTable (Before DEC30) 1658 /****************************************************************************/ 1659 typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1660 { 1661 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE 1662 // When the display is LCD, in addition to above: 1663 // ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START|| 1664 // ATOM_LCD_SELFTEST_STOP 1665 1666 UCHAR aucPadding[3]; // padding to DWORD aligned 1667 }DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS; 1668 1669 #define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1670 1671 1672 #define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1673 #define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1674 1675 #define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1676 #define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1677 1678 #define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1679 #define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1680 1681 #define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1682 #define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1683 1684 #define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1685 #define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1686 1687 #define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1688 #define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1689 1690 #define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1691 #define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION 1692 1693 #define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS 1694 #define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION 1695 #define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS 1696 1697 1698 typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2 1699 { 1700 // Possible value of ucAction 1701 // ATOM_TRANSMITTER_ACTION_LCD_BLON 1702 // ATOM_TRANSMITTER_ACTION_LCD_BLOFF 1703 // ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 1704 // ATOM_TRANSMITTER_ACTION_POWER_ON 1705 // ATOM_TRANSMITTER_ACTION_POWER_OFF 1706 UCHAR ucAction; 1707 UCHAR ucBriLevel; 1708 USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz 1709 }LVTMA_OUTPUT_CONTROL_PARAMETERS_V2; 1710 1711 1712 1713 /****************************************************************************/ 1714 // Structures used by BlankCRTCTable 1715 /****************************************************************************/ 1716 typedef struct _BLANK_CRTC_PARAMETERS 1717 { 1718 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1719 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF 1720 USHORT usBlackColorRCr; 1721 USHORT usBlackColorGY; 1722 USHORT usBlackColorBCb; 1723 }BLANK_CRTC_PARAMETERS; 1724 #define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS 1725 1726 /****************************************************************************/ 1727 // Structures used by EnableCRTCTable 1728 // EnableCRTCMemReqTable 1729 // UpdateCRTC_DoubleBufferRegistersTable 1730 /****************************************************************************/ 1731 typedef struct _ENABLE_CRTC_PARAMETERS 1732 { 1733 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1734 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 1735 UCHAR ucPadding[2]; 1736 }ENABLE_CRTC_PARAMETERS; 1737 #define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS 1738 1739 /****************************************************************************/ 1740 // Structures used by SetCRTC_OverScanTable 1741 /****************************************************************************/ 1742 typedef struct _SET_CRTC_OVERSCAN_PARAMETERS 1743 { 1744 USHORT usOverscanRight; // right 1745 USHORT usOverscanLeft; // left 1746 USHORT usOverscanBottom; // bottom 1747 USHORT usOverscanTop; // top 1748 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1749 UCHAR ucPadding[3]; 1750 }SET_CRTC_OVERSCAN_PARAMETERS; 1751 #define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS 1752 1753 /****************************************************************************/ 1754 // Structures used by SetCRTC_ReplicationTable 1755 /****************************************************************************/ 1756 typedef struct _SET_CRTC_REPLICATION_PARAMETERS 1757 { 1758 UCHAR ucH_Replication; // horizontal replication 1759 UCHAR ucV_Replication; // vertical replication 1760 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1761 UCHAR ucPadding; 1762 }SET_CRTC_REPLICATION_PARAMETERS; 1763 #define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS 1764 1765 /****************************************************************************/ 1766 // Structures used by SelectCRTC_SourceTable 1767 /****************************************************************************/ 1768 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS 1769 { 1770 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1771 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|.... 1772 UCHAR ucPadding[2]; 1773 }SELECT_CRTC_SOURCE_PARAMETERS; 1774 #define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS 1775 1776 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2 1777 { 1778 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1779 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1780 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1781 UCHAR ucPadding; 1782 }SELECT_CRTC_SOURCE_PARAMETERS_V2; 1783 1784 //ucEncoderID 1785 //#define ASIC_INT_DAC1_ENCODER_ID 0x00 1786 //#define ASIC_INT_TV_ENCODER_ID 0x02 1787 //#define ASIC_INT_DIG1_ENCODER_ID 0x03 1788 //#define ASIC_INT_DAC2_ENCODER_ID 0x04 1789 //#define ASIC_EXT_TV_ENCODER_ID 0x06 1790 //#define ASIC_INT_DVO_ENCODER_ID 0x07 1791 //#define ASIC_INT_DIG2_ENCODER_ID 0x09 1792 //#define ASIC_EXT_DIG_ENCODER_ID 0x05 1793 1794 //ucEncodeMode 1795 //#define ATOM_ENCODER_MODE_DP 0 1796 //#define ATOM_ENCODER_MODE_LVDS 1 1797 //#define ATOM_ENCODER_MODE_DVI 2 1798 //#define ATOM_ENCODER_MODE_HDMI 3 1799 //#define ATOM_ENCODER_MODE_SDVO 4 1800 //#define ATOM_ENCODER_MODE_TV 13 1801 //#define ATOM_ENCODER_MODE_CV 14 1802 //#define ATOM_ENCODER_MODE_CRT 15 1803 1804 1805 typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3 1806 { 1807 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 1808 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO 1809 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO 1810 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR 1811 }SELECT_CRTC_SOURCE_PARAMETERS_V3; 1812 1813 1814 /****************************************************************************/ 1815 // Structures used by SetPixelClockTable 1816 // GetPixelClockTable 1817 /****************************************************************************/ 1818 //Major revision=1., Minor revision=1 1819 typedef struct _PIXEL_CLOCK_PARAMETERS 1820 { 1821 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1822 // 0 means disable PPLL 1823 USHORT usRefDiv; // Reference divider 1824 USHORT usFbDiv; // feedback divider 1825 UCHAR ucPostDiv; // post divider 1826 UCHAR ucFracFbDiv; // fractional feedback divider 1827 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1828 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1829 UCHAR ucCRTC; // Which CRTC uses this Ppll 1830 UCHAR ucPadding; 1831 }PIXEL_CLOCK_PARAMETERS; 1832 1833 //Major revision=1., Minor revision=2, add ucMiscIfno 1834 //ucMiscInfo: 1835 #define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1 1836 #define MISC_DEVICE_INDEX_MASK 0xF0 1837 #define MISC_DEVICE_INDEX_SHIFT 4 1838 1839 typedef struct _PIXEL_CLOCK_PARAMETERS_V2 1840 { 1841 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1842 // 0 means disable PPLL 1843 USHORT usRefDiv; // Reference divider 1844 USHORT usFbDiv; // feedback divider 1845 UCHAR ucPostDiv; // post divider 1846 UCHAR ucFracFbDiv; // fractional feedback divider 1847 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1848 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER 1849 UCHAR ucCRTC; // Which CRTC uses this Ppll 1850 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog 1851 }PIXEL_CLOCK_PARAMETERS_V2; 1852 1853 //Major revision=1., Minor revision=3, structure/definition change 1854 //ucEncoderMode: 1855 //ATOM_ENCODER_MODE_DP 1856 //ATOM_ENOCDER_MODE_LVDS 1857 //ATOM_ENOCDER_MODE_DVI 1858 //ATOM_ENOCDER_MODE_HDMI 1859 //ATOM_ENOCDER_MODE_SDVO 1860 //ATOM_ENCODER_MODE_TV 13 1861 //ATOM_ENCODER_MODE_CV 14 1862 //ATOM_ENCODER_MODE_CRT 15 1863 1864 //ucDVOConfig 1865 //#define DVO_ENCODER_CONFIG_RATE_SEL 0x01 1866 //#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 1867 //#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 1868 //#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 1869 //#define DVO_ENCODER_CONFIG_LOW12BIT 0x00 1870 //#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 1871 //#define DVO_ENCODER_CONFIG_24BIT 0x08 1872 1873 //ucMiscInfo: also changed, see below 1874 #define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01 1875 #define PIXEL_CLOCK_MISC_VGA_MODE 0x02 1876 #define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04 1877 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00 1878 #define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04 1879 #define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08 1880 #define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10 1881 // V1.4 for RoadRunner 1882 #define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10 1883 #define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20 1884 1885 1886 typedef struct _PIXEL_CLOCK_PARAMETERS_V3 1887 { 1888 USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div) 1889 // 0 means disable PPLL. For VGA PPLL,make sure this value is not 0. 1890 USHORT usRefDiv; // Reference divider 1891 USHORT usFbDiv; // feedback divider 1892 UCHAR ucPostDiv; // post divider 1893 UCHAR ucFracFbDiv; // fractional feedback divider 1894 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2 1895 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h 1896 union 1897 { 1898 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/ 1899 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit 1900 }; 1901 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel 1902 // bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source 1903 // bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider 1904 }PIXEL_CLOCK_PARAMETERS_V3; 1905 1906 #define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2 1907 #define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST 1908 1909 1910 typedef struct _PIXEL_CLOCK_PARAMETERS_V5 1911 { 1912 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 1913 // drive the pixel clock. not used for DCPLL case. 1914 union{ 1915 UCHAR ucReserved; 1916 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed. 1917 }; 1918 USHORT usPixelClock; // target the pixel clock to drive the CRTC timing 1919 // 0 means disable PPLL/DCPLL. 1920 USHORT usFbDiv; // feedback divider integer part. 1921 UCHAR ucPostDiv; // post divider. 1922 UCHAR ucRefDiv; // Reference divider 1923 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1924 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1925 // indicate which graphic encoder will be used. 1926 UCHAR ucEncoderMode; // Encoder mode: 1927 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1928 // bit[1]= when VGA timing is used. 1929 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1930 // bit[4]= RefClock source for PPLL. 1931 // =0: XTLAIN( default mode ) 1932 // =1: other external clock source, which is pre-defined 1933 // by VBIOS depend on the feature required. 1934 // bit[7:5]: reserved. 1935 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1936 1937 }PIXEL_CLOCK_PARAMETERS_V5; 1938 1939 #define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01 1940 #define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02 1941 #define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c 1942 #define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00 1943 #define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04 1944 #define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08 1945 #define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10 1946 1947 typedef struct _CRTC_PIXEL_CLOCK_FREQ 1948 { 1949 #if ATOM_BIG_ENDIAN 1950 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1951 // drive the pixel clock. not used for DCPLL case. 1952 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1953 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1954 #else 1955 ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing. 1956 // 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version. 1957 ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to 1958 // drive the pixel clock. not used for DCPLL case. 1959 #endif 1960 }CRTC_PIXEL_CLOCK_FREQ; 1961 1962 typedef struct _PIXEL_CLOCK_PARAMETERS_V6 1963 { 1964 union{ 1965 CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency 1966 ULONG ulDispEngClkFreq; // dispclk frequency 1967 }; 1968 USHORT usFbDiv; // feedback divider integer part. 1969 UCHAR ucPostDiv; // post divider. 1970 UCHAR ucRefDiv; // Reference divider 1971 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL 1972 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 1973 // indicate which graphic encoder will be used. 1974 UCHAR ucEncoderMode; // Encoder mode: 1975 UCHAR ucMiscInfo; // bit[0]= Force program PPLL 1976 // bit[1]= when VGA timing is used. 1977 // bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp 1978 // bit[4]= RefClock source for PPLL. 1979 // =0: XTLAIN( default mode ) 1980 // =1: other external clock source, which is pre-defined 1981 // by VBIOS depend on the feature required. 1982 // bit[7:5]: reserved. 1983 ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 ) 1984 1985 }PIXEL_CLOCK_PARAMETERS_V6; 1986 1987 #define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01 1988 #define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02 1989 #define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c 1990 #define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00 1991 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04 1992 #define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1) 1993 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08 1994 #define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4) 1995 #define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c 1996 #define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10 1997 #define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40 1998 #define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40 1999 2000 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2 2001 { 2002 PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput; 2003 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2; 2004 2005 typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2 2006 { 2007 UCHAR ucStatus; 2008 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock 2009 UCHAR ucReserved[2]; 2010 }GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2; 2011 2012 typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3 2013 { 2014 PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput; 2015 }GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3; 2016 2017 typedef struct _PIXEL_CLOCK_PARAMETERS_V7 2018 { 2019 ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2020 2021 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2022 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h, 2023 // indicate which graphic encoder will be used. 2024 UCHAR ucEncoderMode; // Encoder mode: 2025 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk 2026 // bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk ) 2027 // bit[5:4]= RefClock source for PPLL. 2028 // =0: XTLAIN( default mode ) 2029 // =1: pcie 2030 // =2: GENLK 2031 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to 2032 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp 2033 UCHAR ucReserved[2]; 2034 ULONG ulReserved; 2035 }PIXEL_CLOCK_PARAMETERS_V7; 2036 2037 //ucMiscInfo 2038 #define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01 2039 #define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02 2040 #define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04 2041 #define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08 2042 #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30 2043 #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00 2044 #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10 2045 #define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20 2046 2047 //ucDeepColorRatio 2048 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2049 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2050 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2051 #define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2052 2053 // SetDCEClockTable input parameter for DCE11.1 2054 typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1 2055 { 2056 ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz. 2057 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS 2058 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1 2059 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1 2060 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1 2061 }SET_DCE_CLOCK_PARAMETERS_V1_1; 2062 2063 2064 typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 2065 { 2066 SET_DCE_CLOCK_PARAMETERS_V1_1 asParam; 2067 ULONG ulReserved[2]; 2068 }SET_DCE_CLOCK_PS_ALLOCATION_V1_1; 2069 2070 //SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag 2071 #define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01 2072 #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 2073 #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 2074 2075 // SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above 2076 typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 2077 { 2078 ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2079 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2080 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2081 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2082 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2083 }SET_DCE_CLOCK_PARAMETERS_V2_1; 2084 2085 //ucDCEClkType 2086 #define DCE_CLOCK_TYPE_DISPCLK 0 2087 #define DCE_CLOCK_TYPE_DPREFCLK 1 2088 #define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable 2089 2090 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 2091 #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03 2092 #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00 2093 #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01 2094 #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02 2095 #define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03 2096 2097 //ucDCEClkFlag when ucDCEClkType == PIXCLK 2098 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03 2099 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2100 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2101 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2102 #define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2103 #define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04 2104 2105 typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1 2106 { 2107 SET_DCE_CLOCK_PARAMETERS_V2_1 asParam; 2108 ULONG ulReserved[2]; 2109 }SET_DCE_CLOCK_PS_ALLOCATION_V2_1; 2110 2111 2112 2113 /****************************************************************************/ 2114 // Structures used by AdjustDisplayPllTable 2115 /****************************************************************************/ 2116 typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS 2117 { 2118 USHORT usPixelClock; 2119 UCHAR ucTransmitterID; 2120 UCHAR ucEncodeMode; 2121 union 2122 { 2123 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit 2124 UCHAR ucConfig; //if none DVO, not defined yet 2125 }; 2126 UCHAR ucReserved[3]; 2127 }ADJUST_DISPLAY_PLL_PARAMETERS; 2128 2129 #define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10 2130 #define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS 2131 2132 typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 2133 { 2134 USHORT usPixelClock; // target pixel clock 2135 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h 2136 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI 2137 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX 2138 UCHAR ucExtTransmitterID; // external encoder id. 2139 UCHAR ucReserved[2]; 2140 }ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3; 2141 2142 // usDispPllConfig v1.2 for RoadRunner 2143 #define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO 2144 #define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO 2145 #define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO 2146 #define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO 2147 #define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO 2148 #define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO 2149 #define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO 2150 #define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS 2151 #define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI 2152 #define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS 2153 2154 2155 typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 2156 { 2157 ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc 2158 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given ) 2159 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider 2160 UCHAR ucReserved[2]; 2161 }ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3; 2162 2163 typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 2164 { 2165 union 2166 { 2167 ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput; 2168 ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput; 2169 }; 2170 } ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3; 2171 2172 /****************************************************************************/ 2173 // Structures used by EnableYUVTable 2174 /****************************************************************************/ 2175 typedef struct _ENABLE_YUV_PARAMETERS 2176 { 2177 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB) 2178 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format 2179 UCHAR ucPadding[2]; 2180 }ENABLE_YUV_PARAMETERS; 2181 #define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS 2182 2183 /****************************************************************************/ 2184 // Structures used by GetMemoryClockTable 2185 /****************************************************************************/ 2186 typedef struct _GET_MEMORY_CLOCK_PARAMETERS 2187 { 2188 ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit 2189 } GET_MEMORY_CLOCK_PARAMETERS; 2190 #define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS 2191 2192 /****************************************************************************/ 2193 // Structures used by GetEngineClockTable 2194 /****************************************************************************/ 2195 typedef struct _GET_ENGINE_CLOCK_PARAMETERS 2196 { 2197 ULONG ulReturnEngineClock; // current engine speed in 10KHz unit 2198 } GET_ENGINE_CLOCK_PARAMETERS; 2199 #define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS 2200 2201 /****************************************************************************/ 2202 // Following Structures and constant may be obsolete 2203 /****************************************************************************/ 2204 //Maxium 8 bytes,the data read in will be placed in the parameter space. 2205 //Read operaion successeful when the paramter space is non-zero, otherwise read operation failed 2206 typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2207 { 2208 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2209 USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID 2210 USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status 2211 //WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte 2212 UCHAR ucSlaveAddr; //Read from which slave 2213 UCHAR ucLineNumber; //Read from which HW assisted line 2214 }READ_EDID_FROM_HW_I2C_DATA_PARAMETERS; 2215 #define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS 2216 2217 2218 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0 2219 #define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1 2220 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2 2221 #define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3 2222 #define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4 2223 2224 typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2225 { 2226 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2227 USHORT usByteOffset; //Write to which byte 2228 //Upper portion of usByteOffset is Format of data 2229 //1bytePS+offsetPS 2230 //2bytesPS+offsetPS 2231 //blockID+offsetPS 2232 //blockID+offsetID 2233 //blockID+counterID+offsetID 2234 UCHAR ucData; //PS data1 2235 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2 2236 UCHAR ucSlaveAddr; //Write to which slave 2237 UCHAR ucLineNumber; //Write from which HW assisted line 2238 }WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS; 2239 2240 #define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2241 2242 typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS 2243 { 2244 USHORT usPrescale; //Ratio between Engine clock and I2C clock 2245 UCHAR ucSlaveAddr; //Write to which slave 2246 UCHAR ucLineNumber; //Write from which HW assisted line 2247 }SET_UP_HW_I2C_DATA_PARAMETERS; 2248 2249 /**************************************************************************/ 2250 #define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 2251 2252 2253 /****************************************************************************/ 2254 // Structures used by PowerConnectorDetectionTable 2255 /****************************************************************************/ 2256 typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS 2257 { 2258 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2259 UCHAR ucPwrBehaviorId; 2260 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2261 }POWER_CONNECTOR_DETECTION_PARAMETERS; 2262 2263 typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION 2264 { 2265 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected 2266 UCHAR ucReserved; 2267 USHORT usPwrBudget; //how much power currently boot to in unit of watt 2268 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2269 }POWER_CONNECTOR_DETECTION_PS_ALLOCATION; 2270 2271 2272 /****************************LVDS SS Command Table Definitions**********************/ 2273 2274 /****************************************************************************/ 2275 // Structures used by EnableSpreadSpectrumOnPPLLTable 2276 /****************************************************************************/ 2277 typedef struct _ENABLE_LVDS_SS_PARAMETERS 2278 { 2279 USHORT usSpreadSpectrumPercentage; 2280 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2281 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY 2282 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2283 UCHAR ucPadding[3]; 2284 }ENABLE_LVDS_SS_PARAMETERS; 2285 2286 //ucTableFormatRevision=1,ucTableContentRevision=2 2287 typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2 2288 { 2289 USHORT usSpreadSpectrumPercentage; 2290 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2291 UCHAR ucSpreadSpectrumStep; // 2292 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE 2293 UCHAR ucSpreadSpectrumDelay; 2294 UCHAR ucSpreadSpectrumRange; 2295 UCHAR ucPadding; 2296 }ENABLE_LVDS_SS_PARAMETERS_V2; 2297 2298 //This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS. 2299 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL 2300 { 2301 USHORT usSpreadSpectrumPercentage; 2302 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD 2303 UCHAR ucSpreadSpectrumStep; // 2304 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2305 UCHAR ucSpreadSpectrumDelay; 2306 UCHAR ucSpreadSpectrumRange; 2307 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2 2308 }ENABLE_SPREAD_SPECTRUM_ON_PPLL; 2309 2310 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 2311 { 2312 USHORT usSpreadSpectrumPercentage; 2313 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2314 // Bit[1]: 1-Ext. 0-Int. 2315 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2316 // Bits[7:4] reserved 2317 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2318 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2319 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2320 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2; 2321 2322 #define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00 2323 #define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01 2324 #define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02 2325 #define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c 2326 #define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00 2327 #define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04 2328 #define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08 2329 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF 2330 #define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0 2331 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00 2332 #define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8 2333 2334 // Used by DCE5.0 2335 typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 2336 { 2337 USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0 2338 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread. 2339 // Bit[1]: 1-Ext. 0-Int. 2340 // Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL 2341 // Bits[7:4] reserved 2342 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 2343 USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8] 2344 USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC 2345 }ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3; 2346 2347 2348 #define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00 2349 #define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01 2350 #define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02 2351 #define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c 2352 #define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00 2353 #define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04 2354 #define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08 2355 #define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL 2356 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF 2357 #define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0 2358 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00 2359 #define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8 2360 2361 #define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL 2362 2363 typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION 2364 { 2365 PIXEL_CLOCK_PARAMETERS sPCLKInput; 2366 ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion 2367 }SET_PIXEL_CLOCK_PS_ALLOCATION; 2368 2369 2370 2371 #define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION 2372 2373 /****************************************************************************/ 2374 // Structures used by ### 2375 /****************************************************************************/ 2376 typedef struct _MEMORY_TRAINING_PARAMETERS 2377 { 2378 ULONG ulTargetMemoryClock; //In 10Khz unit 2379 }MEMORY_TRAINING_PARAMETERS; 2380 #define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS 2381 2382 2383 typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2 2384 { 2385 USHORT usMemTrainingMode; 2386 USHORT usReserved; 2387 }MEMORY_TRAINING_PARAMETERS_V1_2; 2388 2389 //usMemTrainingMode 2390 #define NORMAL_MEMORY_TRAINING_MODE 0 2391 #define ENTER_DRAM_SELFREFRESH_MODE 1 2392 #define EXIT_DRAM_SELFRESH_MODE 2 2393 2394 /****************************LVDS and other encoder command table definitions **********************/ 2395 2396 2397 /****************************************************************************/ 2398 // Structures used by LVDSEncoderControlTable (Before DEC30) 2399 // LVTMAEncoderControlTable (Before DEC30) 2400 // TMDSAEncoderControlTable (Before DEC30) 2401 /****************************************************************************/ 2402 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS 2403 { 2404 USHORT usPixelClock; // in 10KHz; for bios convenient 2405 UCHAR ucMisc; // bit0=0: Enable single link 2406 // =1: Enable dual link 2407 // Bit1=0: 666RGB 2408 // =1: 888RGB 2409 UCHAR ucAction; // 0: turn off encoder 2410 // 1: setup and turn on encoder 2411 }LVDS_ENCODER_CONTROL_PARAMETERS; 2412 2413 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS 2414 2415 #define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS 2416 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS 2417 2418 #define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS 2419 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS 2420 2421 //ucTableFormatRevision=1,ucTableContentRevision=2 2422 typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2 2423 { 2424 USHORT usPixelClock; // in 10KHz; for bios convenient 2425 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below 2426 UCHAR ucAction; // 0: turn off encoder 2427 // 1: setup and turn on encoder 2428 UCHAR ucTruncate; // bit0=0: Disable truncate 2429 // =1: Enable truncate 2430 // bit4=0: 666RGB 2431 // =1: 888RGB 2432 UCHAR ucSpatial; // bit0=0: Disable spatial dithering 2433 // =1: Enable spatial dithering 2434 // bit4=0: 666RGB 2435 // =1: 888RGB 2436 UCHAR ucTemporal; // bit0=0: Disable temporal dithering 2437 // =1: Enable temporal dithering 2438 // bit4=0: 666RGB 2439 // =1: 888RGB 2440 // bit5=0: Gray level 2 2441 // =1: Gray level 4 2442 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E 2443 // =1: 25FRC_SEL pattern F 2444 // bit6:5=0: 50FRC_SEL pattern A 2445 // =1: 50FRC_SEL pattern B 2446 // =2: 50FRC_SEL pattern C 2447 // =3: 50FRC_SEL pattern D 2448 // bit7=0: 75FRC_SEL pattern E 2449 // =1: 75FRC_SEL pattern F 2450 }LVDS_ENCODER_CONTROL_PARAMETERS_V2; 2451 2452 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2453 2454 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2455 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2456 2457 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2 2458 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2 2459 2460 2461 #define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2462 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2463 2464 #define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2465 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3 2466 2467 #define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3 2468 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3 2469 2470 /****************************************************************************/ 2471 // Structures used by ### 2472 /****************************************************************************/ 2473 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS 2474 { 2475 UCHAR ucEnable; // Enable or Disable External TMDS encoder 2476 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB} 2477 UCHAR ucPadding[2]; 2478 }ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS; 2479 2480 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION 2481 { 2482 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder; 2483 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2484 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION; 2485 2486 #define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2 2487 typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2 2488 { 2489 ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder; 2490 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 2491 }ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2; 2492 2493 typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION 2494 { 2495 DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder; 2496 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2497 }EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION; 2498 2499 /****************************************************************************/ 2500 // Structures used by DVOEncoderControlTable 2501 /****************************************************************************/ 2502 //ucTableFormatRevision=1,ucTableContentRevision=3 2503 //ucDVOConfig: 2504 #define DVO_ENCODER_CONFIG_RATE_SEL 0x01 2505 #define DVO_ENCODER_CONFIG_DDR_SPEED 0x00 2506 #define DVO_ENCODER_CONFIG_SDR_SPEED 0x01 2507 #define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c 2508 #define DVO_ENCODER_CONFIG_LOW12BIT 0x00 2509 #define DVO_ENCODER_CONFIG_UPPER12BIT 0x04 2510 #define DVO_ENCODER_CONFIG_24BIT 0x08 2511 2512 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3 2513 { 2514 USHORT usPixelClock; 2515 UCHAR ucDVOConfig; 2516 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2517 UCHAR ucReseved[4]; 2518 }DVO_ENCODER_CONTROL_PARAMETERS_V3; 2519 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3 2520 2521 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2522 { 2523 USHORT usPixelClock; 2524 UCHAR ucDVOConfig; 2525 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 2526 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR 2527 UCHAR ucReseved[3]; 2528 }DVO_ENCODER_CONTROL_PARAMETERS_V1_4; 2529 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4 2530 2531 2532 //ucTableFormatRevision=1 2533 //ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for 2534 // bit1=0: non-coherent mode 2535 // =1: coherent mode 2536 2537 //========================================================================================== 2538 //Only change is here next time when changing encoder parameter definitions again! 2539 #define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2540 #define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST 2541 2542 #define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2543 #define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST 2544 2545 #define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3 2546 #define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST 2547 2548 #define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS 2549 #define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION 2550 2551 //========================================================================================== 2552 #define PANEL_ENCODER_MISC_DUAL 0x01 2553 #define PANEL_ENCODER_MISC_COHERENT 0x02 2554 #define PANEL_ENCODER_MISC_TMDS_LINKB 0x04 2555 #define PANEL_ENCODER_MISC_HDMI_TYPE 0x08 2556 2557 #define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE 2558 #define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE 2559 #define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1) 2560 2561 #define PANEL_ENCODER_TRUNCATE_EN 0x01 2562 #define PANEL_ENCODER_TRUNCATE_DEPTH 0x10 2563 #define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01 2564 #define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10 2565 #define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01 2566 #define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10 2567 #define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20 2568 #define PANEL_ENCODER_25FRC_MASK 0x10 2569 #define PANEL_ENCODER_25FRC_E 0x00 2570 #define PANEL_ENCODER_25FRC_F 0x10 2571 #define PANEL_ENCODER_50FRC_MASK 0x60 2572 #define PANEL_ENCODER_50FRC_A 0x00 2573 #define PANEL_ENCODER_50FRC_B 0x20 2574 #define PANEL_ENCODER_50FRC_C 0x40 2575 #define PANEL_ENCODER_50FRC_D 0x60 2576 #define PANEL_ENCODER_75FRC_MASK 0x80 2577 #define PANEL_ENCODER_75FRC_E 0x00 2578 #define PANEL_ENCODER_75FRC_F 0x80 2579 2580 /****************************************************************************/ 2581 // Structures used by SetVoltageTable 2582 /****************************************************************************/ 2583 #define SET_VOLTAGE_TYPE_ASIC_VDDC 1 2584 #define SET_VOLTAGE_TYPE_ASIC_MVDDC 2 2585 #define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3 2586 #define SET_VOLTAGE_TYPE_ASIC_VDDCI 4 2587 #define SET_VOLTAGE_INIT_MODE 5 2588 #define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic 2589 2590 #define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1 2591 #define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2 2592 #define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4 2593 2594 #define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0 2595 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1 2596 #define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2 2597 2598 typedef struct _SET_VOLTAGE_PARAMETERS 2599 { 2600 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2601 UCHAR ucVoltageMode; // To set all, to set source A or source B or ... 2602 UCHAR ucVoltageIndex; // An index to tell which voltage level 2603 UCHAR ucReserved; 2604 }SET_VOLTAGE_PARAMETERS; 2605 2606 typedef struct _SET_VOLTAGE_PARAMETERS_V2 2607 { 2608 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ 2609 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode 2610 USHORT usVoltageLevel; // real voltage level 2611 }SET_VOLTAGE_PARAMETERS_V2; 2612 2613 // used by both SetVoltageTable v1.3 and v1.4 2614 typedef struct _SET_VOLTAGE_PARAMETERS_V1_3 2615 { 2616 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2617 UCHAR ucVoltageMode; // Indicate action: Set voltage level 2618 USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) 2619 }SET_VOLTAGE_PARAMETERS_V1_3; 2620 2621 //ucVoltageType 2622 #define VOLTAGE_TYPE_VDDC 1 2623 #define VOLTAGE_TYPE_MVDDC 2 2624 #define VOLTAGE_TYPE_MVDDQ 3 2625 #define VOLTAGE_TYPE_VDDCI 4 2626 #define VOLTAGE_TYPE_VDDGFX 5 2627 #define VOLTAGE_TYPE_PCC 6 2628 #define VOLTAGE_TYPE_MVPP 7 2629 #define VOLTAGE_TYPE_LEDDPM 8 2630 #define VOLTAGE_TYPE_PCC_MVDD 9 2631 #define VOLTAGE_TYPE_PCIE_VDDC 10 2632 #define VOLTAGE_TYPE_PCIE_VDDR 11 2633 2634 #define VOLTAGE_TYPE_GENERIC_I2C_1 0x11 2635 #define VOLTAGE_TYPE_GENERIC_I2C_2 0x12 2636 #define VOLTAGE_TYPE_GENERIC_I2C_3 0x13 2637 #define VOLTAGE_TYPE_GENERIC_I2C_4 0x14 2638 #define VOLTAGE_TYPE_GENERIC_I2C_5 0x15 2639 #define VOLTAGE_TYPE_GENERIC_I2C_6 0x16 2640 #define VOLTAGE_TYPE_GENERIC_I2C_7 0x17 2641 #define VOLTAGE_TYPE_GENERIC_I2C_8 0x18 2642 #define VOLTAGE_TYPE_GENERIC_I2C_9 0x19 2643 #define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A 2644 2645 //SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode 2646 #define ATOM_SET_VOLTAGE 0 //Set voltage Level 2647 #define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator 2648 #define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator 2649 #define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3 2650 #define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4 2651 #define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4 2652 2653 // define vitual voltage id in usVoltageLevel 2654 #define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01 2655 #define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02 2656 #define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03 2657 #define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04 2658 #define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05 2659 #define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06 2660 #define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07 2661 #define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08 2662 2663 typedef struct _SET_VOLTAGE_PS_ALLOCATION 2664 { 2665 SET_VOLTAGE_PARAMETERS sASICSetVoltage; 2666 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; 2667 }SET_VOLTAGE_PS_ALLOCATION; 2668 2669 // New Added from SI for GetVoltageInfoTable, input parameter structure 2670 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1 2671 { 2672 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2673 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2674 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2675 ULONG ulReserved; 2676 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1; 2677 2678 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID 2679 typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2680 { 2681 ULONG ulVotlageGpioState; 2682 ULONG ulVoltageGPioMask; 2683 }GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2684 2685 // New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID 2686 typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1 2687 { 2688 USHORT usVoltageLevel; 2689 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2690 ULONG ulReseved; 2691 }GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1; 2692 2693 // GetVoltageInfo v1.1 ucVoltageMode 2694 #define ATOM_GET_VOLTAGE_VID 0x00 2695 #define ATOM_GET_VOTLAGE_INIT_SEQ 0x03 2696 #define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04 2697 #define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info 2698 2699 // for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state 2700 #define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10 2701 // for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state 2702 #define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11 2703 2704 #define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12 2705 #define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13 2706 2707 2708 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2709 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 2710 { 2711 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2712 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2713 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2714 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2715 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2; 2716 2717 // New in GetVoltageInfo v1.2 ucVoltageMode 2718 #define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09 2719 2720 // New Added from CI Hawaii for EVV feature 2721 typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 2722 { 2723 USHORT usVoltageLevel; // real voltage level in unit of mv 2724 USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator 2725 USHORT usTDP_Current; // TDP_Current in unit of 0.01A 2726 USHORT usTDP_Power; // TDP_Current in unit of 0.1W 2727 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2; 2728 2729 2730 // New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure 2731 typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 2732 { 2733 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI 2734 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info 2735 USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id 2736 ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table 2737 ULONG ulReserved[3]; 2738 }GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3; 2739 2740 // New Added from CI Hawaii for EVV feature 2741 typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3 2742 { 2743 ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv 2744 ULONG ulReserved[4]; 2745 }GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3; 2746 2747 2748 /****************************************************************************/ 2749 // Structures used by GetSMUClockInfo 2750 /****************************************************************************/ 2751 typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1 2752 { 2753 ULONG ulDfsPllOutputFreq:24; 2754 ULONG ucDfsDivider:8; 2755 }GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1; 2756 2757 typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1 2758 { 2759 ULONG ulDfsOutputFreq; 2760 }GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1; 2761 2762 /****************************************************************************/ 2763 // Structures used by TVEncoderControlTable 2764 /****************************************************************************/ 2765 typedef struct _TV_ENCODER_CONTROL_PARAMETERS 2766 { 2767 USHORT usPixelClock; // in 10KHz; for bios convenient 2768 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..." 2769 UCHAR ucAction; // 0: turn off encoder 2770 // 1: setup and turn on encoder 2771 }TV_ENCODER_CONTROL_PARAMETERS; 2772 2773 typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION 2774 { 2775 TV_ENCODER_CONTROL_PARAMETERS sTVEncoder; 2776 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one 2777 }TV_ENCODER_CONTROL_PS_ALLOCATION; 2778 2779 //==============================Data Table Portion==================================== 2780 2781 2782 /****************************************************************************/ 2783 // Structure used in Data.mtb 2784 /****************************************************************************/ 2785 typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES 2786 { 2787 USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position! 2788 USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios 2789 USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios 2790 USHORT StandardVESA_Timing; // Only used by Bios 2791 USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4 2792 USHORT PaletteData; // Only used by BIOS 2793 USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info 2794 USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1 2795 USHORT SMU_Info; // Shared by various SW components,latest version 1.1 2796 USHORT SupportedDevicesInfo; // Will be obsolete from R600 2797 USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600 2798 USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600 2799 USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1 2800 USHORT VESA_ToInternalModeLUT; // Only used by Bios 2801 USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600 2802 USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600 2803 USHORT GPUVirtualizationInfo; // Will be obsolete from R600 2804 USHORT SaveRestoreInfo; // Only used by Bios 2805 USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info 2806 USHORT OemInfo; // Defined and used by external SW, should be obsolete soon 2807 USHORT XTMDS_Info; // Will be obsolete from R600 2808 USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used 2809 USHORT Object_Header; // Shared by various SW components,latest version 1.1 2810 USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!! 2811 USHORT MC_InitParameter; // Only used by command table 2812 USHORT ASIC_VDDC_Info; // Will be obsolete from R600 2813 USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info" 2814 USHORT TV_VideoMode; // Only used by command table 2815 USHORT VRAM_Info; // Only used by command table, latest version 1.3 2816 USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1 2817 USHORT IntegratedSystemInfo; // Shared by various SW components 2818 USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600 2819 USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1 2820 USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1 2821 USHORT ServiceInfo; 2822 }ATOM_MASTER_LIST_OF_DATA_TABLES; 2823 2824 typedef struct _ATOM_MASTER_DATA_TABLE 2825 { 2826 ATOM_COMMON_TABLE_HEADER sHeader; 2827 ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables; 2828 }ATOM_MASTER_DATA_TABLE; 2829 2830 // For backward compatible 2831 #define LVDS_Info LCD_Info 2832 #define DAC_Info PaletteData 2833 #define TMDS_Info DIGTransmitterInfo 2834 #define CompassionateData GPUVirtualizationInfo 2835 #define AnalogTV_Info SMU_Info 2836 #define ComponentVideoInfo GFX_Info 2837 2838 /****************************************************************************/ 2839 // Structure used in MultimediaCapabilityInfoTable 2840 /****************************************************************************/ 2841 typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO 2842 { 2843 ATOM_COMMON_TABLE_HEADER sHeader; 2844 ULONG ulSignature; // HW info table signature string "$ATI" 2845 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc) 2846 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7) 2847 UCHAR ucVideoPortInfo; // Provides the video port capabilities 2848 UCHAR ucHostPortInfo; // Provides host port configuration information 2849 }ATOM_MULTIMEDIA_CAPABILITY_INFO; 2850 2851 2852 /****************************************************************************/ 2853 // Structure used in MultimediaConfigInfoTable 2854 /****************************************************************************/ 2855 typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO 2856 { 2857 ATOM_COMMON_TABLE_HEADER sHeader; 2858 ULONG ulSignature; // MM info table signature sting "$MMT" 2859 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5) 2860 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5) 2861 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting 2862 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7) 2863 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6) 2864 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4) 2865 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3) 2866 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2867 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2868 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2869 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2870 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6) 2871 }ATOM_MULTIMEDIA_CONFIG_INFO; 2872 2873 2874 /****************************************************************************/ 2875 // Structures used in FirmwareInfoTable 2876 /****************************************************************************/ 2877 2878 // usBIOSCapability Defintion: 2879 // Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted; 2880 // Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported; 2881 // Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported; 2882 // Others: Reserved 2883 #define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001 2884 #define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002 2885 #define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004 2886 #define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable. 2887 #define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable. 2888 #define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020 2889 #define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040 2890 #define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080 2891 #define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100 2892 #define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00 2893 #define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000 2894 #define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000 2895 #define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip 2896 #define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip 2897 2898 2899 #ifndef _H2INC 2900 2901 //Please don't add or expand this bitfield structure below, this one will retire soon.! 2902 typedef struct _ATOM_FIRMWARE_CAPABILITY 2903 { 2904 #if ATOM_BIG_ENDIAN 2905 USHORT Reserved:1; 2906 USHORT SCL2Redefined:1; 2907 USHORT PostWithoutModeSet:1; 2908 USHORT HyperMemory_Size:4; 2909 USHORT HyperMemory_Support:1; 2910 USHORT PPMode_Assigned:1; 2911 USHORT WMI_SUPPORT:1; 2912 USHORT GPUControlsBL:1; 2913 USHORT EngineClockSS_Support:1; 2914 USHORT MemoryClockSS_Support:1; 2915 USHORT ExtendedDesktopSupport:1; 2916 USHORT DualCRTC_Support:1; 2917 USHORT FirmwarePosted:1; 2918 #else 2919 USHORT FirmwarePosted:1; 2920 USHORT DualCRTC_Support:1; 2921 USHORT ExtendedDesktopSupport:1; 2922 USHORT MemoryClockSS_Support:1; 2923 USHORT EngineClockSS_Support:1; 2924 USHORT GPUControlsBL:1; 2925 USHORT WMI_SUPPORT:1; 2926 USHORT PPMode_Assigned:1; 2927 USHORT HyperMemory_Support:1; 2928 USHORT HyperMemory_Size:4; 2929 USHORT PostWithoutModeSet:1; 2930 USHORT SCL2Redefined:1; 2931 USHORT Reserved:1; 2932 #endif 2933 }ATOM_FIRMWARE_CAPABILITY; 2934 2935 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2936 { 2937 ATOM_FIRMWARE_CAPABILITY sbfAccess; 2938 USHORT susAccess; 2939 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2940 2941 #else 2942 2943 typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS 2944 { 2945 USHORT susAccess; 2946 }ATOM_FIRMWARE_CAPABILITY_ACCESS; 2947 2948 #endif 2949 2950 typedef struct _ATOM_FIRMWARE_INFO 2951 { 2952 ATOM_COMMON_TABLE_HEADER sHeader; 2953 ULONG ulFirmwareRevision; 2954 ULONG ulDefaultEngineClock; //In 10Khz unit 2955 ULONG ulDefaultMemoryClock; //In 10Khz unit 2956 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2957 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2958 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2959 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2960 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2961 ULONG ulASICMaxEngineClock; //In 10Khz unit 2962 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2963 UCHAR ucASICMaxTemperature; 2964 UCHAR ucPadding[3]; //Don't use them 2965 ULONG aulReservedForBIOS[3]; //Don't use them 2966 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 2967 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 2968 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 2969 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 2970 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 2971 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 2972 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 2973 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 2974 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 2975 USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!! 2976 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 2977 USHORT usReferenceClock; //In 10Khz unit 2978 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 2979 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 2980 UCHAR ucDesign_ID; //Indicate what is the board design 2981 UCHAR ucMemoryModule_ID; //Indicate what is the board design 2982 }ATOM_FIRMWARE_INFO; 2983 2984 typedef struct _ATOM_FIRMWARE_INFO_V1_2 2985 { 2986 ATOM_COMMON_TABLE_HEADER sHeader; 2987 ULONG ulFirmwareRevision; 2988 ULONG ulDefaultEngineClock; //In 10Khz unit 2989 ULONG ulDefaultMemoryClock; //In 10Khz unit 2990 ULONG ulDriverTargetEngineClock; //In 10Khz unit 2991 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 2992 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 2993 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 2994 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 2995 ULONG ulASICMaxEngineClock; //In 10Khz unit 2996 ULONG ulASICMaxMemoryClock; //In 10Khz unit 2997 UCHAR ucASICMaxTemperature; 2998 UCHAR ucMinAllowedBL_Level; 2999 UCHAR ucPadding[2]; //Don't use them 3000 ULONG aulReservedForBIOS[2]; //Don't use them 3001 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3002 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3003 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3004 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3005 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3006 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3007 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3008 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3009 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3010 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3011 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3012 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3013 USHORT usReferenceClock; //In 10Khz unit 3014 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3015 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3016 UCHAR ucDesign_ID; //Indicate what is the board design 3017 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3018 }ATOM_FIRMWARE_INFO_V1_2; 3019 3020 typedef struct _ATOM_FIRMWARE_INFO_V1_3 3021 { 3022 ATOM_COMMON_TABLE_HEADER sHeader; 3023 ULONG ulFirmwareRevision; 3024 ULONG ulDefaultEngineClock; //In 10Khz unit 3025 ULONG ulDefaultMemoryClock; //In 10Khz unit 3026 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3027 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3028 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3029 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3030 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3031 ULONG ulASICMaxEngineClock; //In 10Khz unit 3032 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3033 UCHAR ucASICMaxTemperature; 3034 UCHAR ucMinAllowedBL_Level; 3035 UCHAR ucPadding[2]; //Don't use them 3036 ULONG aulReservedForBIOS; //Don't use them 3037 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3038 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3039 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3040 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3041 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3042 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3043 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3044 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3045 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3046 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3047 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3048 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3049 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3050 USHORT usReferenceClock; //In 10Khz unit 3051 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3052 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3053 UCHAR ucDesign_ID; //Indicate what is the board design 3054 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3055 }ATOM_FIRMWARE_INFO_V1_3; 3056 3057 typedef struct _ATOM_FIRMWARE_INFO_V1_4 3058 { 3059 ATOM_COMMON_TABLE_HEADER sHeader; 3060 ULONG ulFirmwareRevision; 3061 ULONG ulDefaultEngineClock; //In 10Khz unit 3062 ULONG ulDefaultMemoryClock; //In 10Khz unit 3063 ULONG ulDriverTargetEngineClock; //In 10Khz unit 3064 ULONG ulDriverTargetMemoryClock; //In 10Khz unit 3065 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3066 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3067 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3068 ULONG ulASICMaxEngineClock; //In 10Khz unit 3069 ULONG ulASICMaxMemoryClock; //In 10Khz unit 3070 UCHAR ucASICMaxTemperature; 3071 UCHAR ucMinAllowedBL_Level; 3072 USHORT usBootUpVDDCVoltage; //In MV unit 3073 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3074 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3075 ULONG ul3DAccelerationEngineClock;//In 10Khz unit 3076 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3077 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3078 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3079 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3080 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3081 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3082 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3083 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3084 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3085 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3086 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3087 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3088 USHORT usReferenceClock; //In 10Khz unit 3089 USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit 3090 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit 3091 UCHAR ucDesign_ID; //Indicate what is the board design 3092 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3093 }ATOM_FIRMWARE_INFO_V1_4; 3094 3095 //the structure below to be used from Cypress 3096 typedef struct _ATOM_FIRMWARE_INFO_V2_1 3097 { 3098 ATOM_COMMON_TABLE_HEADER sHeader; 3099 ULONG ulFirmwareRevision; 3100 ULONG ulDefaultEngineClock; //In 10Khz unit 3101 ULONG ulDefaultMemoryClock; //In 10Khz unit 3102 ULONG ulReserved1; 3103 ULONG ulReserved2; 3104 ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit 3105 ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit 3106 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3107 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock 3108 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit 3109 UCHAR ucReserved1; //Was ucASICMaxTemperature; 3110 UCHAR ucMinAllowedBL_Level; 3111 USHORT usBootUpVDDCVoltage; //In MV unit 3112 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3113 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3114 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3115 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3116 USHORT usMinEngineClockPLL_Input; //In 10Khz unit 3117 USHORT usMaxEngineClockPLL_Input; //In 10Khz unit 3118 USHORT usMinEngineClockPLL_Output; //In 10Khz unit 3119 USHORT usMinMemoryClockPLL_Input; //In 10Khz unit 3120 USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit 3121 USHORT usMinMemoryClockPLL_Output; //In 10Khz unit 3122 USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk 3123 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3124 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3125 USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output 3126 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3127 USHORT usCoreReferenceClock; //In 10Khz unit 3128 USHORT usMemoryReferenceClock; //In 10Khz unit 3129 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3130 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3131 UCHAR ucReserved4[3]; 3132 3133 }ATOM_FIRMWARE_INFO_V2_1; 3134 3135 //the structure below to be used from NI 3136 //ucTableFormatRevision=2 3137 //ucTableContentRevision=2 3138 3139 typedef struct _PRODUCT_BRANDING 3140 { 3141 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level 3142 UCHAR ucReserved:2; // Bit[3:2] Reserved 3143 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID 3144 }PRODUCT_BRANDING; 3145 3146 typedef struct _ATOM_FIRMWARE_INFO_V2_2 3147 { 3148 ATOM_COMMON_TABLE_HEADER sHeader; 3149 ULONG ulFirmwareRevision; 3150 ULONG ulDefaultEngineClock; //In 10Khz unit 3151 ULONG ulDefaultMemoryClock; //In 10Khz unit 3152 ULONG ulSPLL_OutputFreq; //In 10Khz unit 3153 ULONG ulGPUPLL_OutputFreq; //In 10Khz unit 3154 ULONG ulReserved1; //Was ulMaxEngineClockPLL_Output; //In 10Khz unit* 3155 ULONG ulReserved2; //Was ulMaxMemoryClockPLL_Output; //In 10Khz unit* 3156 ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit 3157 ULONG ulBinaryAlteredInfo; //Was ulASICMaxEngineClock ? 3158 ULONG ulDefaultDispEngineClkFreq; //In 10Khz unit. This is the frequency before DCDTO, corresponding to usBootUpVDDCVoltage. 3159 UCHAR ucReserved3; //Was ucASICMaxTemperature; 3160 UCHAR ucMinAllowedBL_Level; 3161 USHORT usBootUpVDDCVoltage; //In MV unit 3162 USHORT usLcdMinPixelClockPLL_Output; // In MHz unit 3163 USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit 3164 ULONG ulReserved4; //Was ulAsicMaximumVoltage 3165 ULONG ulMinPixelClockPLL_Output; //In 10Khz unit 3166 UCHAR ucRemoteDisplayConfig; 3167 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input 3168 ULONG ulReserved6; //Was usMinEngineClockPLL_Output and usMinMemoryClockPLL_Input 3169 ULONG ulReserved7; //Was usMaxMemoryClockPLL_Input and usMinMemoryClockPLL_Output 3170 USHORT usReserved11; //Was usMaxPixelClock; //In 10Khz unit, Max. Pclk used only for DAC 3171 USHORT usMinPixelClockPLL_Input; //In 10Khz unit 3172 USHORT usMaxPixelClockPLL_Input; //In 10Khz unit 3173 USHORT usBootUpVDDCIVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3174 ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability; 3175 USHORT usCoreReferenceClock; //In 10Khz unit 3176 USHORT usMemoryReferenceClock; //In 10Khz unit 3177 USHORT usUniphyDPModeExtClkFreq; //In 10Khz unit, if it is 0, In DP Mode Uniphy Input clock from internal PPLL, otherwise Input clock from external Spread clock 3178 UCHAR ucMemoryModule_ID; //Indicate what is the board design 3179 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION] 3180 PRODUCT_BRANDING ucProductBranding; // Bit[7:4]ucBRANDING_ID: Branding ID, Bit[3:2]ucReserved: Reserved, Bit[1:0]ucEMBEDDED_CAP: Embedded feature level. 3181 UCHAR ucReserved9; 3182 USHORT usBootUpMVDDCVoltage; //In unit of mv; Was usMinPixelClockPLL_Output; 3183 USHORT usBootUpVDDGFXVoltage; //In unit of mv; 3184 ULONG ulReserved10[3]; // New added comparing to previous version 3185 }ATOM_FIRMWARE_INFO_V2_2; 3186 3187 #define ATOM_FIRMWARE_INFO_LAST ATOM_FIRMWARE_INFO_V2_2 3188 3189 3190 // definition of ucRemoteDisplayConfig 3191 #define REMOTE_DISPLAY_DISABLE 0x00 3192 #define REMOTE_DISPLAY_ENABLE 0x01 3193 3194 /****************************************************************************/ 3195 // Structures used in IntegratedSystemInfoTable 3196 /****************************************************************************/ 3197 #define IGP_CAP_FLAG_DYNAMIC_CLOCK_EN 0x2 3198 #define IGP_CAP_FLAG_AC_CARD 0x4 3199 #define IGP_CAP_FLAG_SDVO_CARD 0x8 3200 #define IGP_CAP_FLAG_POSTDIV_BY_2_MODE 0x10 3201 3202 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO 3203 { 3204 ATOM_COMMON_TABLE_HEADER sHeader; 3205 ULONG ulBootUpEngineClock; //in 10kHz unit 3206 ULONG ulBootUpMemoryClock; //in 10kHz unit 3207 ULONG ulMaxSystemMemoryClock; //in 10kHz unit 3208 ULONG ulMinSystemMemoryClock; //in 10kHz unit 3209 UCHAR ucNumberOfCyclesInPeriodHi; 3210 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID. 3211 USHORT usReserved1; 3212 USHORT usInterNBVoltageLow; //An intermidiate PMW value to set the voltage 3213 USHORT usInterNBVoltageHigh; //Another intermidiate PMW value to set the voltage 3214 ULONG ulReserved[2]; 3215 3216 USHORT usFSBClock; //In MHz unit 3217 USHORT usCapabilityFlag; //Bit0=1 indicates the fake HDMI support,Bit1=0/1 for Dynamic clocking dis/enable 3218 //Bit[3:2]== 0:No PCIE card, 1:AC card, 2:SDVO card 3219 //Bit[4]==1: P/2 mode, ==0: P/1 mode 3220 USHORT usPCIENBCfgReg7; //bit[7:0]=MUX_Sel, bit[9:8]=MUX_SEL_LEVEL2, bit[10]=Lane_Reversal 3221 USHORT usK8MemoryClock; //in MHz unit 3222 USHORT usK8SyncStartDelay; //in 0.01 us unit 3223 USHORT usK8DataReturnTime; //in 0.01 us unit 3224 UCHAR ucMaxNBVoltage; 3225 UCHAR ucMinNBVoltage; 3226 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved 3227 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod 3228 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime 3229 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit 3230 UCHAR ucMaxNBVoltageHigh; 3231 UCHAR ucMinNBVoltageHigh; 3232 }ATOM_INTEGRATED_SYSTEM_INFO; 3233 3234 /* Explanation on entries in ATOM_INTEGRATED_SYSTEM_INFO 3235 ulBootUpMemoryClock: For Intel IGP,it's the UMA system memory clock 3236 For AMD IGP,it's 0 if no SidePort memory installed or it's the boot-up SidePort memory clock 3237 ulMaxSystemMemoryClock: For Intel IGP,it's the Max freq from memory SPD if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3238 For AMD IGP,for now this can be 0 3239 ulMinSystemMemoryClock: For Intel IGP,it's 133MHz if memory runs in ASYNC mode or otherwise (SYNC mode) it's 0 3240 For AMD IGP,for now this can be 0 3241 3242 usFSBClock: For Intel IGP,it's FSB Freq 3243 For AMD IGP,it's HT Link Speed 3244 3245 usK8MemoryClock: For AMD IGP only. For RevF CPU, set it to 200 3246 usK8SyncStartDelay: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3247 usK8DataReturnTime: For AMD IGP only. Memory access latency in K8, required for watermark calculation 3248 3249 VC:Voltage Control 3250 ucMaxNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3251 ucMinNBVoltage: Voltage regulator dependent PWM value. Low 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3252 3253 ucNumberOfCyclesInPeriod: Indicate how many cycles when PWM duty is 100%. low 8 bits of the value. 3254 ucNumberOfCyclesInPeriodHi: Indicate how many cycles when PWM duty is 100%. high 8 bits of the value.If the PWM has an inverter,set bit [7]==1,otherwise set it 0 3255 3256 ucMaxNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the max voltage.Set this one to 0xFF if VC without PWM. Set this to 0x0 if no VC at all. 3257 ucMinNBVoltageHigh: Voltage regulator dependent PWM value. High 8 bits of the value for the min voltage.Set this one to 0x00 if VC without PWM or no VC at all. 3258 3259 3260 usInterNBVoltageLow: Voltage regulator dependent PWM value. The value makes the the voltage >=Min NB voltage but <=InterNBVoltageHigh. Set this to 0x0000 if VC without PWM or no VC at all. 3261 usInterNBVoltageHigh: Voltage regulator dependent PWM value. The value makes the the voltage >=InterNBVoltageLow but <=Max NB voltage.Set this to 0x0000 if VC without PWM or no VC at all. 3262 */ 3263 3264 3265 /* 3266 The following IGP table is introduced from RS780, which is supposed to be put by SBIOS in FB before IGP VBIOS starts VPOST; 3267 Then VBIOS will copy the whole structure to its image so all GPU SW components can access this data structure to get whatever they need. 3268 The enough reservation should allow us to never change table revisions. Whenever needed, a GPU SW component can use reserved portion for new data entries. 3269 3270 SW components can access the IGP system infor structure in the same way as before 3271 */ 3272 3273 3274 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 3275 { 3276 ATOM_COMMON_TABLE_HEADER sHeader; 3277 ULONG ulBootUpEngineClock; //in 10kHz unit 3278 ULONG ulReserved1[2]; //must be 0x0 for the reserved 3279 ULONG ulBootUpUMAClock; //in 10kHz unit 3280 ULONG ulBootUpSidePortClock; //in 10kHz unit 3281 ULONG ulMinSidePortClock; //in 10kHz unit 3282 ULONG ulReserved2[6]; //must be 0x0 for the reserved 3283 ULONG ulSystemConfig; //see explanation below 3284 ULONG ulBootUpReqDisplayVector; 3285 ULONG ulOtherDisplayMisc; 3286 ULONG ulDDISlot1Config; 3287 ULONG ulDDISlot2Config; 3288 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3289 UCHAR ucUMAChannelNumber; 3290 UCHAR ucDockingPinBit; 3291 UCHAR ucDockingPinPolarity; 3292 ULONG ulDockingPinCFGInfo; 3293 ULONG ulCPUCapInfo; 3294 USHORT usNumberOfCyclesInPeriod; 3295 USHORT usMaxNBVoltage; 3296 USHORT usMinNBVoltage; 3297 USHORT usBootUpNBVoltage; 3298 ULONG ulHTLinkFreq; //in 10Khz 3299 USHORT usMinHTLinkWidth; 3300 USHORT usMaxHTLinkWidth; 3301 USHORT usUMASyncStartDelay; 3302 USHORT usUMADataReturnTime; 3303 USHORT usLinkStatusZeroTime; 3304 USHORT usDACEfuse; //for storing badgap value (for RS880 only) 3305 ULONG ulHighVoltageHTLinkFreq; // in 10Khz 3306 ULONG ulLowVoltageHTLinkFreq; // in 10Khz 3307 USHORT usMaxUpStreamHTLinkWidth; 3308 USHORT usMaxDownStreamHTLinkWidth; 3309 USHORT usMinUpStreamHTLinkWidth; 3310 USHORT usMinDownStreamHTLinkWidth; 3311 USHORT usFirmwareVersion; //0 means FW is not supported. Otherwise it's the FW version loaded by SBIOS and driver should enable FW. 3312 USHORT usFullT0Time; // Input to calculate minimum HT link change time required by NB P-State. Unit is 0.01us. 3313 ULONG ulReserved3[96]; //must be 0x0 3314 }ATOM_INTEGRATED_SYSTEM_INFO_V2; 3315 3316 /* 3317 ulBootUpEngineClock: Boot-up Engine Clock in 10Khz; 3318 ulBootUpUMAClock: Boot-up UMA Clock in 10Khz; it must be 0x0 when UMA is not present 3319 ulBootUpSidePortClock: Boot-up SidePort Clock in 10Khz; it must be 0x0 when SidePort Memory is not present,this could be equal to or less than maximum supported Sideport memory clock 3320 3321 ulSystemConfig: 3322 Bit[0]=1: PowerExpress mode =0 Non-PowerExpress mode; 3323 Bit[1]=1: system boots up at AMD overdrived state or user customized mode. In this case, driver will just stick to this boot-up mode. No other PowerPlay state 3324 =0: system boots up at driver control state. Power state depends on PowerPlay table. 3325 Bit[2]=1: PWM method is used on NB voltage control. =0: GPIO method is used. 3326 Bit[3]=1: Only one power state(Performance) will be supported. 3327 =0: Multiple power states supported from PowerPlay table. 3328 Bit[4]=1: CLMC is supported and enabled on current system. 3329 =0: CLMC is not supported or enabled on current system. SBIOS need to support HT link/freq change through ATIF interface. 3330 Bit[5]=1: Enable CDLW for all driver control power states. Max HT width is from SBIOS, while Min HT width is determined by display requirement. 3331 =0: CDLW is disabled. If CLMC is enabled case, Min HT width will be set equal to Max HT width. If CLMC disabled case, Max HT width will be applied. 3332 Bit[6]=1: High Voltage requested for all power states. In this case, voltage will be forced at 1.1v and powerplay table voltage drop/throttling request will be ignored. 3333 =0: Voltage settings is determined by powerplay table. 3334 Bit[7]=1: Enable CLMC as hybrid Mode. CDLD and CILR will be disabled in this case and we're using legacy C1E. This is workaround for CPU(Griffin) performance issue. 3335 =0: Enable CLMC as regular mode, CDLD and CILR will be enabled. 3336 Bit[8]=1: CDLF is supported and enabled on current system. 3337 =0: CDLF is not supported or enabled on current system. 3338 Bit[9]=1: DLL Shut Down feature is enabled on current system. 3339 =0: DLL Shut Down feature is not enabled or supported on current system. 3340 3341 ulBootUpReqDisplayVector: This dword is a bit vector indicates what display devices are requested during boot-up. Refer to ATOM_DEVICE_xxx_SUPPORT for the bit vector definitions. 3342 3343 ulOtherDisplayMisc: [15:8]- Bootup LCD Expansion selection; 0-center, 1-full panel size expansion; 3344 [7:0] - BootupTV standard selection; This is a bit vector to indicate what TV standards are supported by the system. Refer to ucTVSuppportedStd definition; 3345 3346 ulDDISlot1Config: Describes the PCIE lane configuration on this DDI PCIE slot (ADD2 card) or connector (Mobile design). 3347 [3:0] - Bit vector to indicate PCIE lane config of the DDI slot/connector on chassis (bit 0=1 lane 3:0; bit 1=1 lane 7:4; bit 2=1 lane 11:8; bit 3=1 lane 15:12) 3348 [7:4] - Bit vector to indicate PCIE lane config of the same DDI slot/connector on docking station (bit 4=1 lane 3:0; bit 5=1 lane 7:4; bit 6=1 lane 11:8; bit 7=1 lane 15:12) 3349 When a DDI connector is not "paired" (meaming two connections mutualexclusive on chassis or docking, only one of them can be connected at one time. 3350 in both chassis and docking, SBIOS has to duplicate the same PCIE lane info from chassis to docking or vice versa. For example: 3351 one DDI connector is only populated in docking with PCIE lane 8-11, but there is no paired connection on chassis, SBIOS has to copy bit 6 to bit 2. 3352 3353 [15:8] - Lane configuration attribute; 3354 [23:16]- Connector type, possible value: 3355 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D 3356 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D 3357 CONNECTOR_OBJECT_ID_HDMI_TYPE_A 3358 CONNECTOR_OBJECT_ID_DISPLAYPORT 3359 CONNECTOR_OBJECT_ID_eDP 3360 [31:24]- Reserved 3361 3362 ulDDISlot2Config: Same as Slot1. 3363 ucMemoryType: SidePort memory type, set it to 0x0 when Sideport memory is not installed. Driver needs this info to change sideport memory clock. Not for display in CCC. 3364 For IGP, Hypermemory is the only memory type showed in CCC. 3365 3366 ucUMAChannelNumber: how many channels for the UMA; 3367 3368 ulDockingPinCFGInfo: [15:0]-Bus/Device/Function # to CFG to read this Docking Pin; [31:16]-reg offset in CFG to read this pin 3369 ucDockingPinBit: which bit in this register to read the pin status; 3370 ucDockingPinPolarity:Polarity of the pin when docked; 3371 3372 ulCPUCapInfo: [7:0]=1:Griffin;[7:0]=2:Greyhound;[7:0]=3:K8, [7:0]=4:Pharaoh, other bits reserved for now and must be 0x0 3373 3374 usNumberOfCyclesInPeriod:Indicate how many cycles when PWM duty is 100%. 3375 3376 usMaxNBVoltage:Max. voltage control value in either PWM or GPIO mode. 3377 usMinNBVoltage:Min. voltage control value in either PWM or GPIO mode. 3378 GPIO mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=0 3379 PWM mode: both usMaxNBVoltage & usMinNBVoltage have a valid value ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE=1 3380 GPU SW don't control mode: usMaxNBVoltage & usMinNBVoltage=0 and no care about ulSystemConfig.SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 3381 3382 usBootUpNBVoltage:Boot-up voltage regulator dependent PWM value. 3383 3384 3385 ulHTLinkFreq: Bootup HT link Frequency in 10Khz. 3386 usMinHTLinkWidth: Bootup minimum HT link width. If CDLW disabled, this is equal to usMaxHTLinkWidth. 3387 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3388 usMaxHTLinkWidth: Bootup maximum HT link width. If CDLW disabled, this is equal to usMinHTLinkWidth. 3389 If CDLW enabled, both upstream and downstream width should be the same during bootup. 3390 3391 usUMASyncStartDelay: Memory access latency, required for watermark calculation 3392 usUMADataReturnTime: Memory access latency, required for watermark calculation 3393 usLinkStatusZeroTime:Memory access latency required for watermark calculation, set this to 0x0 for K8 CPU, set a proper value in 0.01 the unit of us 3394 for Griffin or Greyhound. SBIOS needs to convert to actual time by: 3395 if T0Ttime [5:4]=00b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.1us (0.0 to 1.5us) 3396 if T0Ttime [5:4]=01b, then usLinkStatusZeroTime=T0Ttime [3:0]*0.5us (0.0 to 7.5us) 3397 if T0Ttime [5:4]=10b, then usLinkStatusZeroTime=T0Ttime [3:0]*2.0us (0.0 to 30us) 3398 if T0Ttime [5:4]=11b, and T0Ttime [3:0]=0x0 to 0xa, then usLinkStatusZeroTime=T0Ttime [3:0]*20us (0.0 to 200us) 3399 3400 ulHighVoltageHTLinkFreq: HT link frequency for power state with low voltage. If boot up runs in HT1, this must be 0. 3401 This must be less than or equal to ulHTLinkFreq(bootup frequency). 3402 ulLowVoltageHTLinkFreq: HT link frequency for power state with low voltage or voltage scaling 1.0v~1.1v. If boot up runs in HT1, this must be 0. 3403 This must be less than or equal to ulHighVoltageHTLinkFreq. 3404 3405 usMaxUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMaxHTLinkWidth. Not used for now. 3406 usMaxDownStreamHTLinkWidth: same as above. 3407 usMinUpStreamHTLinkWidth: Asymmetric link width support in the future, to replace usMinHTLinkWidth. Not used for now. 3408 usMinDownStreamHTLinkWidth: same as above. 3409 */ 3410 3411 // ATOM_INTEGRATED_SYSTEM_INFO::ulCPUCapInfo - CPU type definition 3412 #define INTEGRATED_SYSTEM_INFO__UNKNOWN_CPU 0 3413 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GRIFFIN 1 3414 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__GREYHOUND 2 3415 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__K8 3 3416 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__PHARAOH 4 3417 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI 5 3418 3419 #define INTEGRATED_SYSTEM_INFO__AMD_CPU__MAX_CODE INTEGRATED_SYSTEM_INFO__AMD_CPU__OROCHI // this deff reflects max defined CPU code 3420 3421 #define SYSTEM_CONFIG_POWEREXPRESS_ENABLE 0x00000001 3422 #define SYSTEM_CONFIG_RUN_AT_OVERDRIVE_ENGINE 0x00000002 3423 #define SYSTEM_CONFIG_USE_PWM_ON_VOLTAGE 0x00000004 3424 #define SYSTEM_CONFIG_PERFORMANCE_POWERSTATE_ONLY 0x00000008 3425 #define SYSTEM_CONFIG_CLMC_ENABLED 0x00000010 3426 #define SYSTEM_CONFIG_CDLW_ENABLED 0x00000020 3427 #define SYSTEM_CONFIG_HIGH_VOLTAGE_REQUESTED 0x00000040 3428 #define SYSTEM_CONFIG_CLMC_HYBRID_MODE_ENABLED 0x00000080 3429 #define SYSTEM_CONFIG_CDLF_ENABLED 0x00000100 3430 #define SYSTEM_CONFIG_DLL_SHUTDOWN_ENABLED 0x00000200 3431 3432 #define IGP_DDI_SLOT_LANE_CONFIG_MASK 0x000000FF 3433 3434 #define b0IGP_DDI_SLOT_LANE_MAP_MASK 0x0F 3435 #define b0IGP_DDI_SLOT_DOCKING_LANE_MAP_MASK 0xF0 3436 #define b0IGP_DDI_SLOT_CONFIG_LANE_0_3 0x01 3437 #define b0IGP_DDI_SLOT_CONFIG_LANE_4_7 0x02 3438 #define b0IGP_DDI_SLOT_CONFIG_LANE_8_11 0x04 3439 #define b0IGP_DDI_SLOT_CONFIG_LANE_12_15 0x08 3440 3441 #define IGP_DDI_SLOT_ATTRIBUTE_MASK 0x0000FF00 3442 #define IGP_DDI_SLOT_CONFIG_REVERSED 0x00000100 3443 #define b1IGP_DDI_SLOT_CONFIG_REVERSED 0x01 3444 3445 #define IGP_DDI_SLOT_CONNECTOR_TYPE_MASK 0x00FF0000 3446 3447 // IntegratedSystemInfoTable new Rev is V5 after V2, because of the real rev of V2 is v1.4. This rev is used for RR 3448 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 3449 { 3450 ATOM_COMMON_TABLE_HEADER sHeader; 3451 ULONG ulBootUpEngineClock; //in 10kHz unit 3452 ULONG ulDentistVCOFreq; //Dentist VCO clock in 10kHz unit, the source of GPU SCLK, LCLK, UCLK and VCLK. 3453 ULONG ulLClockFreq; //GPU Lclk freq in 10kHz unit, have relationship with NCLK in NorthBridge 3454 ULONG ulBootUpUMAClock; //in 10kHz unit 3455 ULONG ulReserved1[8]; //must be 0x0 for the reserved 3456 ULONG ulBootUpReqDisplayVector; 3457 ULONG ulOtherDisplayMisc; 3458 ULONG ulReserved2[4]; //must be 0x0 for the reserved 3459 ULONG ulSystemConfig; //TBD 3460 ULONG ulCPUCapInfo; //TBD 3461 USHORT usMaxNBVoltage; //high NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3462 USHORT usMinNBVoltage; //low NB voltage, calculated using current VDDNB (D24F2xDC) and VDDNB offset fuse; 3463 USHORT usBootUpNBVoltage; //boot up NB voltage 3464 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD 3465 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD 3466 ULONG ulReserved3[4]; //must be 0x0 for the reserved 3467 ULONG ulDDISlot1Config; //see above ulDDISlot1Config definition 3468 ULONG ulDDISlot2Config; 3469 ULONG ulDDISlot3Config; 3470 ULONG ulDDISlot4Config; 3471 ULONG ulReserved4[4]; //must be 0x0 for the reserved 3472 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved 3473 UCHAR ucUMAChannelNumber; 3474 USHORT usReserved; 3475 ULONG ulReserved5[4]; //must be 0x0 for the reserved 3476 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10];//arrays with values for CSR M3 arbiter for default 3477 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; //arrays with values for CSR M3 arbiter for UVD playback 3478 ULONG ulCSR_M3_ARB_CNTL_FS3D[10];//arrays with values for CSR M3 arbiter for Full Screen 3D applications 3479 ULONG ulReserved6[61]; //must be 0x0 3480 }ATOM_INTEGRATED_SYSTEM_INFO_V5; 3481 3482 3483 3484 /****************************************************************************/ 3485 // Structure used in GPUVirtualizationInfoTable 3486 /****************************************************************************/ 3487 typedef struct _ATOM_GPU_VIRTUALIZATION_INFO_V2_1 3488 { 3489 ATOM_COMMON_TABLE_HEADER sHeader; 3490 ULONG ulMCUcodeRomStartAddr; 3491 ULONG ulMCUcodeLength; 3492 ULONG ulSMCUcodeRomStartAddr; 3493 ULONG ulSMCUcodeLength; 3494 ULONG ulRLCVUcodeRomStartAddr; 3495 ULONG ulRLCVUcodeLength; 3496 ULONG ulTOCUcodeStartAddr; 3497 ULONG ulTOCUcodeLength; 3498 ULONG ulSMCPatchTableStartAddr; 3499 ULONG ulSmcPatchTableLength; 3500 ULONG ulSystemFlag; 3501 }ATOM_GPU_VIRTUALIZATION_INFO_V2_1; 3502 3503 3504 #define ATOM_CRT_INT_ENCODER1_INDEX 0x00000000 3505 #define ATOM_LCD_INT_ENCODER1_INDEX 0x00000001 3506 #define ATOM_TV_INT_ENCODER1_INDEX 0x00000002 3507 #define ATOM_DFP_INT_ENCODER1_INDEX 0x00000003 3508 #define ATOM_CRT_INT_ENCODER2_INDEX 0x00000004 3509 #define ATOM_LCD_EXT_ENCODER1_INDEX 0x00000005 3510 #define ATOM_TV_EXT_ENCODER1_INDEX 0x00000006 3511 #define ATOM_DFP_EXT_ENCODER1_INDEX 0x00000007 3512 #define ATOM_CV_INT_ENCODER1_INDEX 0x00000008 3513 #define ATOM_DFP_INT_ENCODER2_INDEX 0x00000009 3514 #define ATOM_CRT_EXT_ENCODER1_INDEX 0x0000000A 3515 #define ATOM_CV_EXT_ENCODER1_INDEX 0x0000000B 3516 #define ATOM_DFP_INT_ENCODER3_INDEX 0x0000000C 3517 #define ATOM_DFP_INT_ENCODER4_INDEX 0x0000000D 3518 3519 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSelTable 3520 #define ASIC_INT_DAC1_ENCODER_ID 0x00 3521 #define ASIC_INT_TV_ENCODER_ID 0x02 3522 #define ASIC_INT_DIG1_ENCODER_ID 0x03 3523 #define ASIC_INT_DAC2_ENCODER_ID 0x04 3524 #define ASIC_EXT_TV_ENCODER_ID 0x06 3525 #define ASIC_INT_DVO_ENCODER_ID 0x07 3526 #define ASIC_INT_DIG2_ENCODER_ID 0x09 3527 #define ASIC_EXT_DIG_ENCODER_ID 0x05 3528 #define ASIC_EXT_DIG2_ENCODER_ID 0x08 3529 #define ASIC_INT_DIG3_ENCODER_ID 0x0a 3530 #define ASIC_INT_DIG4_ENCODER_ID 0x0b 3531 #define ASIC_INT_DIG5_ENCODER_ID 0x0c 3532 #define ASIC_INT_DIG6_ENCODER_ID 0x0d 3533 #define ASIC_INT_DIG7_ENCODER_ID 0x0e 3534 3535 //define Encoder attribute 3536 #define ATOM_ANALOG_ENCODER 0 3537 #define ATOM_DIGITAL_ENCODER 1 3538 #define ATOM_DP_ENCODER 2 3539 3540 #define ATOM_ENCODER_ENUM_MASK 0x70 3541 #define ATOM_ENCODER_ENUM_ID1 0x00 3542 #define ATOM_ENCODER_ENUM_ID2 0x10 3543 #define ATOM_ENCODER_ENUM_ID3 0x20 3544 #define ATOM_ENCODER_ENUM_ID4 0x30 3545 #define ATOM_ENCODER_ENUM_ID5 0x40 3546 #define ATOM_ENCODER_ENUM_ID6 0x50 3547 3548 #define ATOM_DEVICE_CRT1_INDEX 0x00000000 3549 #define ATOM_DEVICE_LCD1_INDEX 0x00000001 3550 #define ATOM_DEVICE_TV1_INDEX 0x00000002 3551 #define ATOM_DEVICE_DFP1_INDEX 0x00000003 3552 #define ATOM_DEVICE_CRT2_INDEX 0x00000004 3553 #define ATOM_DEVICE_LCD2_INDEX 0x00000005 3554 #define ATOM_DEVICE_DFP6_INDEX 0x00000006 3555 #define ATOM_DEVICE_DFP2_INDEX 0x00000007 3556 #define ATOM_DEVICE_CV_INDEX 0x00000008 3557 #define ATOM_DEVICE_DFP3_INDEX 0x00000009 3558 #define ATOM_DEVICE_DFP4_INDEX 0x0000000A 3559 #define ATOM_DEVICE_DFP5_INDEX 0x0000000B 3560 3561 #define ATOM_DEVICE_RESERVEDC_INDEX 0x0000000C 3562 #define ATOM_DEVICE_RESERVEDD_INDEX 0x0000000D 3563 #define ATOM_DEVICE_RESERVEDE_INDEX 0x0000000E 3564 #define ATOM_DEVICE_RESERVEDF_INDEX 0x0000000F 3565 #define ATOM_MAX_SUPPORTED_DEVICE_INFO (ATOM_DEVICE_DFP3_INDEX+1) 3566 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_2 ATOM_MAX_SUPPORTED_DEVICE_INFO 3567 #define ATOM_MAX_SUPPORTED_DEVICE_INFO_3 (ATOM_DEVICE_DFP5_INDEX + 1 ) 3568 3569 #define ATOM_MAX_SUPPORTED_DEVICE (ATOM_DEVICE_RESERVEDF_INDEX+1) 3570 3571 #define ATOM_DEVICE_CRT1_SUPPORT (0x1L << ATOM_DEVICE_CRT1_INDEX ) 3572 #define ATOM_DEVICE_LCD1_SUPPORT (0x1L << ATOM_DEVICE_LCD1_INDEX ) 3573 #define ATOM_DEVICE_TV1_SUPPORT (0x1L << ATOM_DEVICE_TV1_INDEX ) 3574 #define ATOM_DEVICE_DFP1_SUPPORT (0x1L << ATOM_DEVICE_DFP1_INDEX ) 3575 #define ATOM_DEVICE_CRT2_SUPPORT (0x1L << ATOM_DEVICE_CRT2_INDEX ) 3576 #define ATOM_DEVICE_LCD2_SUPPORT (0x1L << ATOM_DEVICE_LCD2_INDEX ) 3577 #define ATOM_DEVICE_DFP6_SUPPORT (0x1L << ATOM_DEVICE_DFP6_INDEX ) 3578 #define ATOM_DEVICE_DFP2_SUPPORT (0x1L << ATOM_DEVICE_DFP2_INDEX ) 3579 #define ATOM_DEVICE_CV_SUPPORT (0x1L << ATOM_DEVICE_CV_INDEX ) 3580 #define ATOM_DEVICE_DFP3_SUPPORT (0x1L << ATOM_DEVICE_DFP3_INDEX ) 3581 #define ATOM_DEVICE_DFP4_SUPPORT (0x1L << ATOM_DEVICE_DFP4_INDEX ) 3582 #define ATOM_DEVICE_DFP5_SUPPORT (0x1L << ATOM_DEVICE_DFP5_INDEX ) 3583 3584 3585 #define ATOM_DEVICE_CRT_SUPPORT (ATOM_DEVICE_CRT1_SUPPORT | ATOM_DEVICE_CRT2_SUPPORT) 3586 #define ATOM_DEVICE_DFP_SUPPORT (ATOM_DEVICE_DFP1_SUPPORT | ATOM_DEVICE_DFP2_SUPPORT | ATOM_DEVICE_DFP3_SUPPORT | ATOM_DEVICE_DFP4_SUPPORT | ATOM_DEVICE_DFP5_SUPPORT | ATOM_DEVICE_DFP6_SUPPORT) 3587 #define ATOM_DEVICE_TV_SUPPORT ATOM_DEVICE_TV1_SUPPORT 3588 #define ATOM_DEVICE_LCD_SUPPORT (ATOM_DEVICE_LCD1_SUPPORT | ATOM_DEVICE_LCD2_SUPPORT) 3589 3590 #define ATOM_DEVICE_CONNECTOR_TYPE_MASK 0x000000F0 3591 #define ATOM_DEVICE_CONNECTOR_TYPE_SHIFT 0x00000004 3592 #define ATOM_DEVICE_CONNECTOR_VGA 0x00000001 3593 #define ATOM_DEVICE_CONNECTOR_DVI_I 0x00000002 3594 #define ATOM_DEVICE_CONNECTOR_DVI_D 0x00000003 3595 #define ATOM_DEVICE_CONNECTOR_DVI_A 0x00000004 3596 #define ATOM_DEVICE_CONNECTOR_SVIDEO 0x00000005 3597 #define ATOM_DEVICE_CONNECTOR_COMPOSITE 0x00000006 3598 #define ATOM_DEVICE_CONNECTOR_LVDS 0x00000007 3599 #define ATOM_DEVICE_CONNECTOR_DIGI_LINK 0x00000008 3600 #define ATOM_DEVICE_CONNECTOR_SCART 0x00000009 3601 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_A 0x0000000A 3602 #define ATOM_DEVICE_CONNECTOR_HDMI_TYPE_B 0x0000000B 3603 #define ATOM_DEVICE_CONNECTOR_CASE_1 0x0000000E 3604 #define ATOM_DEVICE_CONNECTOR_DISPLAYPORT 0x0000000F 3605 3606 3607 #define ATOM_DEVICE_DAC_INFO_MASK 0x0000000F 3608 #define ATOM_DEVICE_DAC_INFO_SHIFT 0x00000000 3609 #define ATOM_DEVICE_DAC_INFO_NODAC 0x00000000 3610 #define ATOM_DEVICE_DAC_INFO_DACA 0x00000001 3611 #define ATOM_DEVICE_DAC_INFO_DACB 0x00000002 3612 #define ATOM_DEVICE_DAC_INFO_EXDAC 0x00000003 3613 3614 #define ATOM_DEVICE_I2C_ID_NOI2C 0x00000000 3615 3616 #define ATOM_DEVICE_I2C_LINEMUX_MASK 0x0000000F 3617 #define ATOM_DEVICE_I2C_LINEMUX_SHIFT 0x00000000 3618 3619 #define ATOM_DEVICE_I2C_ID_MASK 0x00000070 3620 #define ATOM_DEVICE_I2C_ID_SHIFT 0x00000004 3621 #define ATOM_DEVICE_I2C_ID_IS_FOR_NON_MM_USE 0x00000001 3622 #define ATOM_DEVICE_I2C_ID_IS_FOR_MM_USE 0x00000002 3623 #define ATOM_DEVICE_I2C_ID_IS_FOR_SDVO_USE 0x00000003 //For IGP RS600 3624 #define ATOM_DEVICE_I2C_ID_IS_FOR_DAC_SCL 0x00000004 //For IGP RS690 3625 3626 #define ATOM_DEVICE_I2C_HARDWARE_CAP_MASK 0x00000080 3627 #define ATOM_DEVICE_I2C_HARDWARE_CAP_SHIFT 0x00000007 3628 #define ATOM_DEVICE_USES_SOFTWARE_ASSISTED_I2C 0x00000000 3629 #define ATOM_DEVICE_USES_HARDWARE_ASSISTED_I2C 0x00000001 3630 3631 // usDeviceSupport: 3632 // Bits0 = 0 - no CRT1 support= 1- CRT1 is supported 3633 // Bit 1 = 0 - no LCD1 support= 1- LCD1 is supported 3634 // Bit 2 = 0 - no TV1 support= 1- TV1 is supported 3635 // Bit 3 = 0 - no DFP1 support= 1- DFP1 is supported 3636 // Bit 4 = 0 - no CRT2 support= 1- CRT2 is supported 3637 // Bit 5 = 0 - no LCD2 support= 1- LCD2 is supported 3638 // Bit 6 = 0 - no DFP6 support= 1- DFP6 is supported 3639 // Bit 7 = 0 - no DFP2 support= 1- DFP2 is supported 3640 // Bit 8 = 0 - no CV support= 1- CV is supported 3641 // Bit 9 = 0 - no DFP3 support= 1- DFP3 is supported 3642 // Bit 10= 0 - no DFP4 support= 1- DFP4 is supported 3643 // Bit 11= 0 - no DFP5 support= 1- DFP5 is supported 3644 // 3645 // 3646 3647 /****************************************************************************/ 3648 // Structure used in MclkSS_InfoTable 3649 /****************************************************************************/ 3650 // ucI2C_ConfigID 3651 // [7:0] - I2C LINE Associate ID 3652 // = 0 - no I2C 3653 // [7] - HW_Cap = 1, [6:0]=HW assisted I2C ID(HW line selection) 3654 // = 0, [6:0]=SW assisted I2C ID 3655 // [6-4] - HW_ENGINE_ID = 1, HW engine for NON multimedia use 3656 // = 2, HW engine for Multimedia use 3657 // = 3-7 Reserved for future I2C engines 3658 // [3-0] - I2C_LINE_MUX = A Mux number when it's HW assisted I2C or GPIO ID when it's SW I2C 3659 3660 typedef struct _ATOM_I2C_ID_CONFIG 3661 { 3662 #if ATOM_BIG_ENDIAN 3663 UCHAR bfHW_Capable:1; 3664 UCHAR bfHW_EngineID:3; 3665 UCHAR bfI2C_LineMux:4; 3666 #else 3667 UCHAR bfI2C_LineMux:4; 3668 UCHAR bfHW_EngineID:3; 3669 UCHAR bfHW_Capable:1; 3670 #endif 3671 }ATOM_I2C_ID_CONFIG; 3672 3673 typedef union _ATOM_I2C_ID_CONFIG_ACCESS 3674 { 3675 ATOM_I2C_ID_CONFIG sbfAccess; 3676 UCHAR ucAccess; 3677 }ATOM_I2C_ID_CONFIG_ACCESS; 3678 3679 3680 /****************************************************************************/ 3681 // Structure used in GPIO_I2C_InfoTable 3682 /****************************************************************************/ 3683 typedef struct _ATOM_GPIO_I2C_ASSIGMENT 3684 { 3685 USHORT usClkMaskRegisterIndex; 3686 USHORT usClkEnRegisterIndex; 3687 USHORT usClkY_RegisterIndex; 3688 USHORT usClkA_RegisterIndex; 3689 USHORT usDataMaskRegisterIndex; 3690 USHORT usDataEnRegisterIndex; 3691 USHORT usDataY_RegisterIndex; 3692 USHORT usDataA_RegisterIndex; 3693 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 3694 UCHAR ucClkMaskShift; 3695 UCHAR ucClkEnShift; 3696 UCHAR ucClkY_Shift; 3697 UCHAR ucClkA_Shift; 3698 UCHAR ucDataMaskShift; 3699 UCHAR ucDataEnShift; 3700 UCHAR ucDataY_Shift; 3701 UCHAR ucDataA_Shift; 3702 UCHAR ucReserved1; 3703 UCHAR ucReserved2; 3704 }ATOM_GPIO_I2C_ASSIGMENT; 3705 3706 typedef struct _ATOM_GPIO_I2C_INFO 3707 { 3708 ATOM_COMMON_TABLE_HEADER sHeader; 3709 ATOM_GPIO_I2C_ASSIGMENT asGPIO_Info[ATOM_MAX_SUPPORTED_DEVICE]; 3710 }ATOM_GPIO_I2C_INFO; 3711 3712 /****************************************************************************/ 3713 // Common Structure used in other structures 3714 /****************************************************************************/ 3715 3716 #ifndef _H2INC 3717 3718 //Please don't add or expand this bitfield structure below, this one will retire soon.! 3719 typedef struct _ATOM_MODE_MISC_INFO 3720 { 3721 #if ATOM_BIG_ENDIAN 3722 USHORT Reserved:6; 3723 USHORT RGB888:1; 3724 USHORT DoubleClock:1; 3725 USHORT Interlace:1; 3726 USHORT CompositeSync:1; 3727 USHORT V_ReplicationBy2:1; 3728 USHORT H_ReplicationBy2:1; 3729 USHORT VerticalCutOff:1; 3730 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3731 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3732 USHORT HorizontalCutOff:1; 3733 #else 3734 USHORT HorizontalCutOff:1; 3735 USHORT HSyncPolarity:1; //0=Active High, 1=Active Low 3736 USHORT VSyncPolarity:1; //0=Active High, 1=Active Low 3737 USHORT VerticalCutOff:1; 3738 USHORT H_ReplicationBy2:1; 3739 USHORT V_ReplicationBy2:1; 3740 USHORT CompositeSync:1; 3741 USHORT Interlace:1; 3742 USHORT DoubleClock:1; 3743 USHORT RGB888:1; 3744 USHORT Reserved:6; 3745 #endif 3746 }ATOM_MODE_MISC_INFO; 3747 3748 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3749 { 3750 ATOM_MODE_MISC_INFO sbfAccess; 3751 USHORT usAccess; 3752 }ATOM_MODE_MISC_INFO_ACCESS; 3753 3754 #else 3755 3756 typedef union _ATOM_MODE_MISC_INFO_ACCESS 3757 { 3758 USHORT usAccess; 3759 }ATOM_MODE_MISC_INFO_ACCESS; 3760 3761 #endif 3762 3763 // usModeMiscInfo- 3764 #define ATOM_H_CUTOFF 0x01 3765 #define ATOM_HSYNC_POLARITY 0x02 //0=Active High, 1=Active Low 3766 #define ATOM_VSYNC_POLARITY 0x04 //0=Active High, 1=Active Low 3767 #define ATOM_V_CUTOFF 0x08 3768 #define ATOM_H_REPLICATIONBY2 0x10 3769 #define ATOM_V_REPLICATIONBY2 0x20 3770 #define ATOM_COMPOSITESYNC 0x40 3771 #define ATOM_INTERLACE 0x80 3772 #define ATOM_DOUBLE_CLOCK_MODE 0x100 3773 #define ATOM_RGB888_MODE 0x200 3774 3775 //usRefreshRate- 3776 #define ATOM_REFRESH_43 43 3777 #define ATOM_REFRESH_47 47 3778 #define ATOM_REFRESH_56 56 3779 #define ATOM_REFRESH_60 60 3780 #define ATOM_REFRESH_65 65 3781 #define ATOM_REFRESH_70 70 3782 #define ATOM_REFRESH_72 72 3783 #define ATOM_REFRESH_75 75 3784 #define ATOM_REFRESH_85 85 3785 3786 // ATOM_MODE_TIMING data are exactly the same as VESA timing data. 3787 // Translation from EDID to ATOM_MODE_TIMING, use the following formula. 3788 // 3789 // VESA_HTOTAL = VESA_ACTIVE + 2* VESA_BORDER + VESA_BLANK 3790 // = EDID_HA + EDID_HBL 3791 // VESA_HDISP = VESA_ACTIVE = EDID_HA 3792 // VESA_HSYNC_START = VESA_ACTIVE + VESA_BORDER + VESA_FRONT_PORCH 3793 // = EDID_HA + EDID_HSO 3794 // VESA_HSYNC_WIDTH = VESA_HSYNC_TIME = EDID_HSPW 3795 // VESA_BORDER = EDID_BORDER 3796 3797 3798 /****************************************************************************/ 3799 // Structure used in SetCRTC_UsingDTDTimingTable 3800 /****************************************************************************/ 3801 typedef struct _SET_CRTC_USING_DTD_TIMING_PARAMETERS 3802 { 3803 USHORT usH_Size; 3804 USHORT usH_Blanking_Time; 3805 USHORT usV_Size; 3806 USHORT usV_Blanking_Time; 3807 USHORT usH_SyncOffset; 3808 USHORT usH_SyncWidth; 3809 USHORT usV_SyncOffset; 3810 USHORT usV_SyncWidth; 3811 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3812 UCHAR ucH_Border; // From DFP EDID 3813 UCHAR ucV_Border; 3814 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3815 UCHAR ucPadding[3]; 3816 }SET_CRTC_USING_DTD_TIMING_PARAMETERS; 3817 3818 /****************************************************************************/ 3819 // Structure used in SetCRTC_TimingTable 3820 /****************************************************************************/ 3821 typedef struct _SET_CRTC_TIMING_PARAMETERS 3822 { 3823 USHORT usH_Total; // horizontal total 3824 USHORT usH_Disp; // horizontal display 3825 USHORT usH_SyncStart; // horozontal Sync start 3826 USHORT usH_SyncWidth; // horizontal Sync width 3827 USHORT usV_Total; // vertical total 3828 USHORT usV_Disp; // vertical display 3829 USHORT usV_SyncStart; // vertical Sync start 3830 USHORT usV_SyncWidth; // vertical Sync width 3831 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3832 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2 3833 UCHAR ucOverscanRight; // right 3834 UCHAR ucOverscanLeft; // left 3835 UCHAR ucOverscanBottom; // bottom 3836 UCHAR ucOverscanTop; // top 3837 UCHAR ucReserved; 3838 }SET_CRTC_TIMING_PARAMETERS; 3839 #define SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION SET_CRTC_TIMING_PARAMETERS 3840 3841 3842 /****************************************************************************/ 3843 // Structure used in StandardVESA_TimingTable 3844 // AnalogTV_InfoTable 3845 // ComponentVideoInfoTable 3846 /****************************************************************************/ 3847 typedef struct _ATOM_MODE_TIMING 3848 { 3849 USHORT usCRTC_H_Total; 3850 USHORT usCRTC_H_Disp; 3851 USHORT usCRTC_H_SyncStart; 3852 USHORT usCRTC_H_SyncWidth; 3853 USHORT usCRTC_V_Total; 3854 USHORT usCRTC_V_Disp; 3855 USHORT usCRTC_V_SyncStart; 3856 USHORT usCRTC_V_SyncWidth; 3857 USHORT usPixelClock; //in 10Khz unit 3858 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3859 USHORT usCRTC_OverscanRight; 3860 USHORT usCRTC_OverscanLeft; 3861 USHORT usCRTC_OverscanBottom; 3862 USHORT usCRTC_OverscanTop; 3863 USHORT usReserve; 3864 UCHAR ucInternalModeNumber; 3865 UCHAR ucRefreshRate; 3866 }ATOM_MODE_TIMING; 3867 3868 typedef struct _ATOM_DTD_FORMAT 3869 { 3870 USHORT usPixClk; 3871 USHORT usHActive; 3872 USHORT usHBlanking_Time; 3873 USHORT usVActive; 3874 USHORT usVBlanking_Time; 3875 USHORT usHSyncOffset; 3876 USHORT usHSyncWidth; 3877 USHORT usVSyncOffset; 3878 USHORT usVSyncWidth; 3879 USHORT usImageHSize; 3880 USHORT usImageVSize; 3881 UCHAR ucHBorder; 3882 UCHAR ucVBorder; 3883 ATOM_MODE_MISC_INFO_ACCESS susModeMiscInfo; 3884 UCHAR ucInternalModeNumber; 3885 UCHAR ucRefreshRate; 3886 }ATOM_DTD_FORMAT; 3887 3888 /****************************************************************************/ 3889 // Structure used in LVDS_InfoTable 3890 // * Need a document to describe this table 3891 /****************************************************************************/ 3892 #define SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 3893 #define SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 3894 #define SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 3895 #define SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 3896 #define SUPPORTED_LCD_REFRESHRATE_48Hz 0x0040 3897 3898 //ucTableFormatRevision=1 3899 //ucTableContentRevision=1 3900 typedef struct _ATOM_LVDS_INFO 3901 { 3902 ATOM_COMMON_TABLE_HEADER sHeader; 3903 ATOM_DTD_FORMAT sLCDTiming; 3904 USHORT usModePatchTableOffset; 3905 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3906 USHORT usOffDelayInMs; 3907 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3908 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3909 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3910 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3911 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3912 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3913 UCHAR ucPanelDefaultRefreshRate; 3914 UCHAR ucPanelIdentification; 3915 UCHAR ucSS_Id; 3916 }ATOM_LVDS_INFO; 3917 3918 //ucTableFormatRevision=1 3919 //ucTableContentRevision=2 3920 typedef struct _ATOM_LVDS_INFO_V12 3921 { 3922 ATOM_COMMON_TABLE_HEADER sHeader; 3923 ATOM_DTD_FORMAT sLCDTiming; 3924 USHORT usExtInfoTableOffset; 3925 USHORT usSupportedRefreshRate; //Refer to panel info table in ATOMBIOS extension Spec. 3926 USHORT usOffDelayInMs; 3927 UCHAR ucPowerSequenceDigOntoDEin10Ms; 3928 UCHAR ucPowerSequenceDEtoBLOnin10Ms; 3929 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level} 3930 // Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888} 3931 // Bit5:{=0:Spatial Dithering disabled;1 Spatial Dithering enabled} 3932 // Bit6:{=0:Temporal Dithering disabled;1 Temporal Dithering enabled} 3933 UCHAR ucPanelDefaultRefreshRate; 3934 UCHAR ucPanelIdentification; 3935 UCHAR ucSS_Id; 3936 USHORT usLCDVenderID; 3937 USHORT usLCDProductID; 3938 UCHAR ucLCDPanel_SpecialHandlingCap; 3939 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 3940 UCHAR ucReserved[2]; 3941 }ATOM_LVDS_INFO_V12; 3942 3943 //Definitions for ucLCDPanel_SpecialHandlingCap: 3944 3945 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 3946 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 3947 #define LCDPANEL_CAP_READ_EDID 0x1 3948 3949 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 3950 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 3951 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 3952 #define LCDPANEL_CAP_DRR_SUPPORTED 0x2 3953 3954 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 3955 #define LCDPANEL_CAP_eDP 0x4 3956 3957 3958 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 3959 //Bit 6 5 4 3960 // 0 0 0 - Color bit depth is undefined 3961 // 0 0 1 - 6 Bits per Primary Color 3962 // 0 1 0 - 8 Bits per Primary Color 3963 // 0 1 1 - 10 Bits per Primary Color 3964 // 1 0 0 - 12 Bits per Primary Color 3965 // 1 0 1 - 14 Bits per Primary Color 3966 // 1 1 0 - 16 Bits per Primary Color 3967 // 1 1 1 - Reserved 3968 3969 #define PANEL_COLOR_BIT_DEPTH_MASK 0x70 3970 3971 // Bit7:{=0:Random Dithering disabled;1 Random Dithering enabled} 3972 #define PANEL_RANDOM_DITHER 0x80 3973 #define PANEL_RANDOM_DITHER_MASK 0x80 3974 3975 #define ATOM_LVDS_INFO_LAST ATOM_LVDS_INFO_V12 // no need to change this 3976 3977 3978 typedef struct _ATOM_LCD_REFRESH_RATE_SUPPORT 3979 { 3980 UCHAR ucSupportedRefreshRate; 3981 UCHAR ucMinRefreshRateForDRR; 3982 }ATOM_LCD_REFRESH_RATE_SUPPORT; 3983 3984 /****************************************************************************/ 3985 // Structures used by LCD_InfoTable V1.3 Note: previous version was called ATOM_LVDS_INFO_V12 3986 // ASIC Families: NI 3987 // ucTableFormatRevision=1 3988 // ucTableContentRevision=3 3989 /****************************************************************************/ 3990 typedef struct _ATOM_LCD_INFO_V13 3991 { 3992 ATOM_COMMON_TABLE_HEADER sHeader; 3993 ATOM_DTD_FORMAT sLCDTiming; 3994 USHORT usExtInfoTableOffset; 3995 union 3996 { 3997 USHORT usSupportedRefreshRate; 3998 ATOM_LCD_REFRESH_RATE_SUPPORT sRefreshRateSupport; 3999 }; 4000 ULONG ulReserved0; 4001 UCHAR ucLCD_Misc; // Reorganized in V13 4002 // Bit0: {=0:single, =1:dual}, 4003 // Bit1: {=0:LDI format for RGB888, =1 FPDI format for RGB888} // was {=0:666RGB, =1:888RGB}, 4004 // Bit3:2: {Grey level} 4005 // Bit6:4 Color Bit Depth definition (see below definition in EDID V1.4 @BYTE 14h) 4006 // Bit7 Reserved. was for ATOM_PANEL_MISC_API_ENABLED, still need it? 4007 UCHAR ucPanelDefaultRefreshRate; 4008 UCHAR ucPanelIdentification; 4009 UCHAR ucSS_Id; 4010 USHORT usLCDVenderID; 4011 USHORT usLCDProductID; 4012 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13 4013 // Bit0: Once DAL sees this CAP is set, it will read EDID from LCD on its own 4014 // Bit1: See LCDPANEL_CAP_DRR_SUPPORTED 4015 // Bit2: a quick reference whether an embadded panel (LCD1 ) is LVDS (0) or eDP (1) 4016 // Bit7-3: Reserved 4017 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable 4018 USHORT usBacklightPWM; // Backlight PWM in Hz. New in _V13 4019 4020 UCHAR ucPowerSequenceDIGONtoDE_in4Ms; 4021 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms; 4022 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms; 4023 UCHAR ucPowerSequenceDEtoDIGON_in4Ms; 4024 4025 UCHAR ucOffDelay_in4Ms; 4026 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms; 4027 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms; 4028 UCHAR ucReserved1; 4029 4030 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh 4031 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h 4032 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h 4033 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h 4034 4035 USHORT usMaxPclkFreqInSingleLink; // Max PixelClock frequency in single link mode. 4036 UCHAR uceDPToLVDSRxId; 4037 UCHAR ucLcdReservd; 4038 ULONG ulReserved[2]; 4039 }ATOM_LCD_INFO_V13; 4040 4041 #define ATOM_LCD_INFO_LAST ATOM_LCD_INFO_V13 4042 4043 //Definitions for ucLCD_Misc 4044 #define ATOM_PANEL_MISC_V13_DUAL 0x00000001 4045 #define ATOM_PANEL_MISC_V13_FPDI 0x00000002 4046 #define ATOM_PANEL_MISC_V13_GREY_LEVEL 0x0000000C 4047 #define ATOM_PANEL_MISC_V13_GREY_LEVEL_SHIFT 2 4048 #define ATOM_PANEL_MISC_V13_COLOR_BIT_DEPTH_MASK 0x70 4049 #define ATOM_PANEL_MISC_V13_6BIT_PER_COLOR 0x10 4050 #define ATOM_PANEL_MISC_V13_8BIT_PER_COLOR 0x20 4051 4052 //Color Bit Depth definition in EDID V1.4 @BYTE 14h 4053 //Bit 6 5 4 4054 // 0 0 0 - Color bit depth is undefined 4055 // 0 0 1 - 6 Bits per Primary Color 4056 // 0 1 0 - 8 Bits per Primary Color 4057 // 0 1 1 - 10 Bits per Primary Color 4058 // 1 0 0 - 12 Bits per Primary Color 4059 // 1 0 1 - 14 Bits per Primary Color 4060 // 1 1 0 - 16 Bits per Primary Color 4061 // 1 1 1 - Reserved 4062 4063 //Definitions for ucLCDPanel_SpecialHandlingCap: 4064 4065 //Once DAL sees this CAP is set, it will read EDID from LCD on its own instead of using sLCDTiming in ATOM_LVDS_INFO_V12. 4066 //Other entries in ATOM_LVDS_INFO_V12 are still valid/useful to DAL 4067 #define LCDPANEL_CAP_V13_READ_EDID 0x1 // = LCDPANEL_CAP_READ_EDID no change comparing to previous version 4068 4069 //If a design supports DRR (dynamic refresh rate) on internal panels (LVDS or EDP), this cap is set in ucLCDPanel_SpecialHandlingCap together 4070 //with multiple supported refresh rates@usSupportedRefreshRate. This cap should not be set when only slow refresh rate is supported (static 4071 //refresh rate switch by SW. This is only valid from ATOM_LVDS_INFO_V12 4072 #define LCDPANEL_CAP_V13_DRR_SUPPORTED 0x2 // = LCDPANEL_CAP_DRR_SUPPORTED no change comparing to previous version 4073 4074 //Use this cap bit for a quick reference whether an embadded panel (LCD1 ) is LVDS or eDP. 4075 #define LCDPANEL_CAP_V13_eDP 0x4 // = LCDPANEL_CAP_eDP no change comparing to previous version 4076 4077 //uceDPToLVDSRxId 4078 #define eDP_TO_LVDS_RX_DISABLE 0x00 // no eDP->LVDS translator chip 4079 #define eDP_TO_LVDS_COMMON_ID 0x01 // common eDP->LVDS translator chip without AMD SW init 4080 #define eDP_TO_LVDS_RT_ID 0x02 // RT tansaltor which require AMD SW init 4081 4082 typedef struct _ATOM_PATCH_RECORD_MODE 4083 { 4084 UCHAR ucRecordType; 4085 USHORT usHDisp; 4086 USHORT usVDisp; 4087 }ATOM_PATCH_RECORD_MODE; 4088 4089 typedef struct _ATOM_LCD_RTS_RECORD 4090 { 4091 UCHAR ucRecordType; 4092 UCHAR ucRTSValue; 4093 }ATOM_LCD_RTS_RECORD; 4094 4095 //!! If the record below exits, it shoud always be the first record for easy use in command table!!! 4096 // The record below is only used when LVDS_Info is present. From ATOM_LVDS_INFO_V12, use ucLCDPanel_SpecialHandlingCap instead. 4097 typedef struct _ATOM_LCD_MODE_CONTROL_CAP 4098 { 4099 UCHAR ucRecordType; 4100 USHORT usLCDCap; 4101 }ATOM_LCD_MODE_CONTROL_CAP; 4102 4103 #define LCD_MODE_CAP_BL_OFF 1 4104 #define LCD_MODE_CAP_CRTC_OFF 2 4105 #define LCD_MODE_CAP_PANEL_OFF 4 4106 4107 4108 typedef struct _ATOM_FAKE_EDID_PATCH_RECORD 4109 { 4110 UCHAR ucRecordType; 4111 UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128 4112 UCHAR ucFakeEDIDString[1]; // This actually has ucFakeEdidLength elements. 4113 } ATOM_FAKE_EDID_PATCH_RECORD; 4114 4115 typedef struct _ATOM_PANEL_RESOLUTION_PATCH_RECORD 4116 { 4117 UCHAR ucRecordType; 4118 USHORT usHSize; 4119 USHORT usVSize; 4120 }ATOM_PANEL_RESOLUTION_PATCH_RECORD; 4121 4122 #define LCD_MODE_PATCH_RECORD_MODE_TYPE 1 4123 #define LCD_RTS_RECORD_TYPE 2 4124 #define LCD_CAP_RECORD_TYPE 3 4125 #define LCD_FAKE_EDID_PATCH_RECORD_TYPE 4 4126 #define LCD_PANEL_RESOLUTION_RECORD_TYPE 5 4127 #define LCD_EDID_OFFSET_PATCH_RECORD_TYPE 6 4128 #define ATOM_RECORD_END_TYPE 0xFF 4129 4130 /****************************Spread Spectrum Info Table Definitions **********************/ 4131 4132 //ucTableFormatRevision=1 4133 //ucTableContentRevision=2 4134 typedef struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT 4135 { 4136 USHORT usSpreadSpectrumPercentage; 4137 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD 4138 UCHAR ucSS_Step; 4139 UCHAR ucSS_Delay; 4140 UCHAR ucSS_Id; 4141 UCHAR ucRecommendedRef_Div; 4142 UCHAR ucSS_Range; //it was reserved for V11 4143 }ATOM_SPREAD_SPECTRUM_ASSIGNMENT; 4144 4145 #define ATOM_MAX_SS_ENTRY 16 4146 #define ATOM_DP_SS_ID1 0x0f1 // SS ID for internal DP stream at 2.7Ghz. if ATOM_DP_SS_ID2 does not exist in SS_InfoTable, it is used for internal DP stream at 1.62Ghz as well. 4147 #define ATOM_DP_SS_ID2 0x0f2 // SS ID for internal DP stream at 1.62Ghz, if it exists in SS_InfoTable. 4148 #define ATOM_LVLINK_2700MHz_SS_ID 0x0f3 // SS ID for LV link translator chip at 2.7Ghz 4149 #define ATOM_LVLINK_1620MHz_SS_ID 0x0f4 // SS ID for LV link translator chip at 1.62Ghz 4150 4151 4152 4153 #define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 4154 #define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 4155 #define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 4156 #define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 4157 #define ATOM_INTERNAL_SS_MASK 0x00000000 4158 #define ATOM_EXTERNAL_SS_MASK 0x00000002 4159 #define EXEC_SS_STEP_SIZE_SHIFT 2 4160 #define EXEC_SS_DELAY_SHIFT 4 4161 #define ACTIVEDATA_TO_BLON_DELAY_SHIFT 4 4162 4163 typedef struct _ATOM_SPREAD_SPECTRUM_INFO 4164 { 4165 ATOM_COMMON_TABLE_HEADER sHeader; 4166 ATOM_SPREAD_SPECTRUM_ASSIGNMENT asSS_Info[ATOM_MAX_SS_ENTRY]; 4167 }ATOM_SPREAD_SPECTRUM_INFO; 4168 4169 4170 /****************************************************************************/ 4171 // Structure used in AnalogTV_InfoTable (Top level) 4172 /****************************************************************************/ 4173 //ucTVBootUpDefaultStd definiton: 4174 4175 //ATOM_TV_NTSC 1 4176 //ATOM_TV_NTSCJ 2 4177 //ATOM_TV_PAL 3 4178 //ATOM_TV_PALM 4 4179 //ATOM_TV_PALCN 5 4180 //ATOM_TV_PALN 6 4181 //ATOM_TV_PAL60 7 4182 //ATOM_TV_SECAM 8 4183 4184 //ucTVSuppportedStd definition: 4185 #define NTSC_SUPPORT 0x1 4186 #define NTSCJ_SUPPORT 0x2 4187 4188 #define PAL_SUPPORT 0x4 4189 #define PALM_SUPPORT 0x8 4190 #define PALCN_SUPPORT 0x10 4191 #define PALN_SUPPORT 0x20 4192 #define PAL60_SUPPORT 0x40 4193 #define SECAM_SUPPORT 0x80 4194 4195 #define MAX_SUPPORTED_TV_TIMING 2 4196 4197 typedef struct _ATOM_ANALOG_TV_INFO 4198 { 4199 ATOM_COMMON_TABLE_HEADER sHeader; 4200 UCHAR ucTV_SuppportedStandard; 4201 UCHAR ucTV_BootUpDefaultStandard; 4202 UCHAR ucExt_TV_ASIC_ID; 4203 UCHAR ucExt_TV_ASIC_SlaveAddr; 4204 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_TV_TIMING]; 4205 }ATOM_ANALOG_TV_INFO; 4206 4207 typedef struct _ATOM_DPCD_INFO 4208 { 4209 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1 4210 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane 4211 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP 4212 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec) 4213 }ATOM_DPCD_INFO; 4214 4215 #define ATOM_DPCD_MAX_LANE_MASK 0x1F 4216 4217 /**************************************************************************/ 4218 // VRAM usage and their defintions 4219 4220 // One chunk of VRAM used by Bios are for HWICON surfaces,EDID data. 4221 // Current Mode timing and Dail Timing and/or STD timing data EACH device. They can be broken down as below. 4222 // All the addresses below are the offsets from the frame buffer start.They all MUST be Dword aligned! 4223 // To driver: The physical address of this memory portion=mmFB_START(4K aligned)+ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR 4224 // To Bios: ATOMBIOS_VRAM_USAGE_START_ADDR+ATOM_x_ADDR->MM_INDEX 4225 4226 // Moved VESA_MEMORY_IN_64K_BLOCK definition to "AtomConfig.h" so that it can be redefined in design (SKU). 4227 //#ifndef VESA_MEMORY_IN_64K_BLOCK 4228 //#define VESA_MEMORY_IN_64K_BLOCK 0x100 //256*64K=16Mb (Max. VESA memory is 16Mb!) 4229 //#endif 4230 4231 #define ATOM_EDID_RAW_DATASIZE 256 //In Bytes 4232 #define ATOM_HWICON_SURFACE_SIZE 4096 //In Bytes 4233 #define ATOM_HWICON_INFOTABLE_SIZE 32 4234 #define MAX_DTD_MODE_IN_VRAM 6 4235 #define ATOM_DTD_MODE_SUPPORT_TBL_SIZE (MAX_DTD_MODE_IN_VRAM*28) //28= (SIZEOF ATOM_DTD_FORMAT) 4236 #define ATOM_STD_MODE_SUPPORT_TBL_SIZE 32*8 //32 is a predefined number,8= (SIZEOF ATOM_STD_FORMAT) 4237 //20 bytes for Encoder Type and DPCD in STD EDID area 4238 #define DFP_ENCODER_TYPE_OFFSET (ATOM_EDID_RAW_DATASIZE + ATOM_DTD_MODE_SUPPORT_TBL_SIZE + ATOM_STD_MODE_SUPPORT_TBL_SIZE - 20) 4239 #define ATOM_DP_DPCD_OFFSET (DFP_ENCODER_TYPE_OFFSET + 4 ) 4240 4241 #define ATOM_HWICON1_SURFACE_ADDR 0 4242 #define ATOM_HWICON2_SURFACE_ADDR (ATOM_HWICON1_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4243 #define ATOM_HWICON_INFOTABLE_ADDR (ATOM_HWICON2_SURFACE_ADDR + ATOM_HWICON_SURFACE_SIZE) 4244 #define ATOM_CRT1_EDID_ADDR (ATOM_HWICON_INFOTABLE_ADDR + ATOM_HWICON_INFOTABLE_SIZE) 4245 #define ATOM_CRT1_DTD_MODE_TBL_ADDR (ATOM_CRT1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4246 #define ATOM_CRT1_STD_MODE_TBL_ADDR (ATOM_CRT1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4247 4248 #define ATOM_LCD1_EDID_ADDR (ATOM_CRT1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4249 #define ATOM_LCD1_DTD_MODE_TBL_ADDR (ATOM_LCD1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4250 #define ATOM_LCD1_STD_MODE_TBL_ADDR (ATOM_LCD1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4251 4252 #define ATOM_TV1_DTD_MODE_TBL_ADDR (ATOM_LCD1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4253 4254 #define ATOM_DFP1_EDID_ADDR (ATOM_TV1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4255 #define ATOM_DFP1_DTD_MODE_TBL_ADDR (ATOM_DFP1_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4256 #define ATOM_DFP1_STD_MODE_TBL_ADDR (ATOM_DFP1_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4257 4258 #define ATOM_CRT2_EDID_ADDR (ATOM_DFP1_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4259 #define ATOM_CRT2_DTD_MODE_TBL_ADDR (ATOM_CRT2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4260 #define ATOM_CRT2_STD_MODE_TBL_ADDR (ATOM_CRT2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4261 4262 #define ATOM_LCD2_EDID_ADDR (ATOM_CRT2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4263 #define ATOM_LCD2_DTD_MODE_TBL_ADDR (ATOM_LCD2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4264 #define ATOM_LCD2_STD_MODE_TBL_ADDR (ATOM_LCD2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4265 4266 #define ATOM_DFP6_EDID_ADDR (ATOM_LCD2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4267 #define ATOM_DFP6_DTD_MODE_TBL_ADDR (ATOM_DFP6_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4268 #define ATOM_DFP6_STD_MODE_TBL_ADDR (ATOM_DFP6_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4269 4270 #define ATOM_DFP2_EDID_ADDR (ATOM_DFP6_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4271 #define ATOM_DFP2_DTD_MODE_TBL_ADDR (ATOM_DFP2_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4272 #define ATOM_DFP2_STD_MODE_TBL_ADDR (ATOM_DFP2_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4273 4274 #define ATOM_CV_EDID_ADDR (ATOM_DFP2_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4275 #define ATOM_CV_DTD_MODE_TBL_ADDR (ATOM_CV_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4276 #define ATOM_CV_STD_MODE_TBL_ADDR (ATOM_CV_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4277 4278 #define ATOM_DFP3_EDID_ADDR (ATOM_CV_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4279 #define ATOM_DFP3_DTD_MODE_TBL_ADDR (ATOM_DFP3_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4280 #define ATOM_DFP3_STD_MODE_TBL_ADDR (ATOM_DFP3_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4281 4282 #define ATOM_DFP4_EDID_ADDR (ATOM_DFP3_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4283 #define ATOM_DFP4_DTD_MODE_TBL_ADDR (ATOM_DFP4_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4284 #define ATOM_DFP4_STD_MODE_TBL_ADDR (ATOM_DFP4_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4285 4286 #define ATOM_DFP5_EDID_ADDR (ATOM_DFP4_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4287 #define ATOM_DFP5_DTD_MODE_TBL_ADDR (ATOM_DFP5_EDID_ADDR + ATOM_EDID_RAW_DATASIZE) 4288 #define ATOM_DFP5_STD_MODE_TBL_ADDR (ATOM_DFP5_DTD_MODE_TBL_ADDR + ATOM_DTD_MODE_SUPPORT_TBL_SIZE) 4289 4290 #define ATOM_DP_TRAINING_TBL_ADDR (ATOM_DFP5_STD_MODE_TBL_ADDR + ATOM_STD_MODE_SUPPORT_TBL_SIZE) 4291 4292 #define ATOM_STACK_STORAGE_START (ATOM_DP_TRAINING_TBL_ADDR + 1024) 4293 #define ATOM_STACK_STORAGE_END ATOM_STACK_STORAGE_START + 512 4294 4295 //The size below is in Kb! 4296 #define ATOM_VRAM_RESERVE_SIZE ((((ATOM_STACK_STORAGE_END - ATOM_HWICON1_SURFACE_ADDR)>>10)+4)&0xFFFC) 4297 4298 #define ATOM_VRAM_RESERVE_V2_SIZE 32 4299 4300 #define ATOM_VRAM_OPERATION_FLAGS_MASK 0xC0000000L 4301 #define ATOM_VRAM_OPERATION_FLAGS_SHIFT 30 4302 #define ATOM_VRAM_BLOCK_NEEDS_NO_RESERVATION 0x1 4303 #define ATOM_VRAM_BLOCK_NEEDS_RESERVATION 0x0 4304 #define ATOM_VRAM_BLOCK_SRIOV_MSG_SHARE_RESERVATION 0x2 4305 4306 /***********************************************************************************/ 4307 // Structure used in VRAM_UsageByFirmwareTable 4308 // Note1: This table is filled by SetBiosReservationStartInFB in CoreCommSubs.asm 4309 // at running time. 4310 // note2: From RV770, the memory is more than 32bit addressable, so we will change 4311 // ucTableFormatRevision=1,ucTableContentRevision=4, the strcuture remains 4312 // exactly same as 1.1 and 1.2 (1.3 is never in use), but ulStartAddrUsedByFirmware 4313 // (in offset to start of memory address) is KB aligned instead of byte aligend. 4314 // Note3: 4315 /* If we change usReserved to "usFBUsedbyDrvInKB", then to VBIOS this usFBUsedbyDrvInKB is a predefined, unchanged 4316 constant across VGA or non VGA adapter, 4317 for CAIL, The size of FB access area is known, only thing missing is the Offset of FB Access area, so we can have: 4318 4319 If (ulStartAddrUsedByFirmware!=0) 4320 FBAccessAreaOffset= ulStartAddrUsedByFirmware - usFBUsedbyDrvInKB; 4321 Reserved area has been claimed by VBIOS including this FB access area; CAIL doesn't need to reserve any extra area for this purpose 4322 else //Non VGA case 4323 if (FB_Size<=2Gb) 4324 FBAccessAreaOffset= FB_Size - usFBUsedbyDrvInKB; 4325 else 4326 FBAccessAreaOffset= Aper_Size - usFBUsedbyDrvInKB 4327 4328 CAIL needs to claim an reserved area defined by FBAccessAreaOffset and usFBUsedbyDrvInKB in non VGA case.*/ 4329 4330 /***********************************************************************************/ 4331 #define ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO 1 4332 4333 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO 4334 { 4335 ULONG ulStartAddrUsedByFirmware; 4336 USHORT usFirmwareUseInKb; 4337 USHORT usReserved; 4338 }ATOM_FIRMWARE_VRAM_RESERVE_INFO; 4339 4340 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE 4341 { 4342 ATOM_COMMON_TABLE_HEADER sHeader; 4343 ATOM_FIRMWARE_VRAM_RESERVE_INFO asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4344 }ATOM_VRAM_USAGE_BY_FIRMWARE; 4345 4346 // change verion to 1.5, when allow driver to allocate the vram area for command table access. 4347 typedef struct _ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 4348 { 4349 ULONG ulStartAddrUsedByFirmware; 4350 USHORT usFirmwareUseInKb; 4351 USHORT usFBUsedByDrvInKb; 4352 }ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5; 4353 4354 typedef struct _ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5 4355 { 4356 ATOM_COMMON_TABLE_HEADER sHeader; 4357 ATOM_FIRMWARE_VRAM_RESERVE_INFO_V1_5 asFirmwareVramReserveInfo[ATOM_MAX_FIRMWARE_VRAM_USAGE_INFO]; 4358 }ATOM_VRAM_USAGE_BY_FIRMWARE_V1_5; 4359 4360 /****************************************************************************/ 4361 // Structure used in GPIO_Pin_LUTTable 4362 /****************************************************************************/ 4363 typedef struct _ATOM_GPIO_PIN_ASSIGNMENT 4364 { 4365 USHORT usGpioPin_AIndex; 4366 UCHAR ucGpioPinBitShift; 4367 UCHAR ucGPIO_ID; 4368 }ATOM_GPIO_PIN_ASSIGNMENT; 4369 4370 //ucGPIO_ID pre-define id for multiple usage 4371 // GPIO use to control PCIE_VDDC in certain SLT board 4372 #define PCIE_VDDC_CONTROL_GPIO_PINID 56 4373 4374 //from SMU7.x, if ucGPIO_ID=PP_AC_DC_SWITCH_GPIO_PINID in GPIO_LUTTable, AC/DC switching feature is enable 4375 #define PP_AC_DC_SWITCH_GPIO_PINID 60 4376 //from SMU7.x, if ucGPIO_ID=VDDC_REGULATOR_VRHOT_GPIO_PINID in GPIO_LUTable, VRHot feature is enable 4377 #define VDDC_VRHOT_GPIO_PINID 61 4378 //if ucGPIO_ID=VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled 4379 #define VDDC_PCC_GPIO_PINID 62 4380 // Only used on certain SLT/PA board to allow utility to cut Efuse. 4381 #define EFUSE_CUT_ENABLE_GPIO_PINID 63 4382 // ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= 4383 #define DRAM_SELF_REFRESH_GPIO_PINID 64 4384 // Thermal interrupt output->system thermal chip GPIO pin 4385 #define THERMAL_INT_OUTPUT_GPIO_PINID 65 4386 4387 4388 typedef struct _ATOM_GPIO_PIN_LUT 4389 { 4390 ATOM_COMMON_TABLE_HEADER sHeader; 4391 ATOM_GPIO_PIN_ASSIGNMENT asGPIO_Pin[1]; 4392 }ATOM_GPIO_PIN_LUT; 4393 4394 /****************************************************************************/ 4395 // Structure used in ComponentVideoInfoTable 4396 /****************************************************************************/ 4397 #define GPIO_PIN_ACTIVE_HIGH 0x1 4398 #define MAX_SUPPORTED_CV_STANDARDS 5 4399 4400 // definitions for ATOM_D_INFO.ucSettings 4401 #define ATOM_GPIO_SETTINGS_BITSHIFT_MASK 0x1F // [4:0] 4402 #define ATOM_GPIO_SETTINGS_RESERVED_MASK 0x60 // [6:5] = must be zeroed out 4403 #define ATOM_GPIO_SETTINGS_ACTIVE_MASK 0x80 // [7] 4404 4405 typedef struct _ATOM_GPIO_INFO 4406 { 4407 USHORT usAOffset; 4408 UCHAR ucSettings; 4409 UCHAR ucReserved; 4410 }ATOM_GPIO_INFO; 4411 4412 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucMiscInfo (bit vector) 4413 #define ATOM_CV_RESTRICT_FORMAT_SELECTION 0x2 4414 4415 // definitions for ATOM_COMPONENT_VIDEO_INFO.uc480i/uc480p/uc720p/uc1080i 4416 #define ATOM_GPIO_DEFAULT_MODE_EN 0x80 //[7]; 4417 #define ATOM_GPIO_SETTING_PERMODE_MASK 0x7F //[6:0] 4418 4419 // definitions for ATOM_COMPONENT_VIDEO_INFO.ucLetterBoxMode 4420 //Line 3 out put 5V. 4421 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_A 0x01 //represent gpio 3 state for 16:9 4422 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_B 0x02 //represent gpio 4 state for 16:9 4423 #define ATOM_CV_LINE3_ASPECTRATIO_16_9_GPIO_SHIFT 0x0 4424 4425 //Line 3 out put 2.2V 4426 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_A 0x04 //represent gpio 3 state for 4:3 Letter box 4427 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_B 0x08 //represent gpio 4 state for 4:3 Letter box 4428 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_LETBOX_GPIO_SHIFT 0x2 4429 4430 //Line 3 out put 0V 4431 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_A 0x10 //represent gpio 3 state for 4:3 4432 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_B 0x20 //represent gpio 4 state for 4:3 4433 #define ATOM_CV_LINE3_ASPECTRATIO_4_3_GPIO_SHIFT 0x4 4434 4435 #define ATOM_CV_LINE3_ASPECTRATIO_MASK 0x3F // bit [5:0] 4436 4437 #define ATOM_CV_LINE3_ASPECTRATIO_EXIST 0x80 //bit 7 4438 4439 //GPIO bit index in gpio setting per mode value, also represend the block no. in gpio blocks. 4440 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_A 3 //bit 3 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4441 #define ATOM_GPIO_INDEX_LINE3_ASPECRATIO_GPIO_B 4 //bit 4 in uc480i/uc480p/uc720p/uc1080i, which represend the default gpio bit setting for the mode. 4442 4443 4444 typedef struct _ATOM_COMPONENT_VIDEO_INFO 4445 { 4446 ATOM_COMMON_TABLE_HEADER sHeader; 4447 USHORT usMask_PinRegisterIndex; 4448 USHORT usEN_PinRegisterIndex; 4449 USHORT usY_PinRegisterIndex; 4450 USHORT usA_PinRegisterIndex; 4451 UCHAR ucBitShift; 4452 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low 4453 ATOM_DTD_FORMAT sReserved; // must be zeroed out 4454 UCHAR ucMiscInfo; 4455 UCHAR uc480i; 4456 UCHAR uc480p; 4457 UCHAR uc720p; 4458 UCHAR uc1080i; 4459 UCHAR ucLetterBoxMode; 4460 UCHAR ucReserved[3]; 4461 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4462 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4463 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4464 }ATOM_COMPONENT_VIDEO_INFO; 4465 4466 //ucTableFormatRevision=2 4467 //ucTableContentRevision=1 4468 typedef struct _ATOM_COMPONENT_VIDEO_INFO_V21 4469 { 4470 ATOM_COMMON_TABLE_HEADER sHeader; 4471 UCHAR ucMiscInfo; 4472 UCHAR uc480i; 4473 UCHAR uc480p; 4474 UCHAR uc720p; 4475 UCHAR uc1080i; 4476 UCHAR ucReserved; 4477 UCHAR ucLetterBoxMode; 4478 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector 4479 ATOM_GPIO_INFO aWbGpioStateBlock[MAX_SUPPORTED_CV_STANDARDS]; 4480 ATOM_DTD_FORMAT aModeTimings[MAX_SUPPORTED_CV_STANDARDS]; 4481 }ATOM_COMPONENT_VIDEO_INFO_V21; 4482 4483 #define ATOM_COMPONENT_VIDEO_INFO_LAST ATOM_COMPONENT_VIDEO_INFO_V21 4484 4485 /****************************************************************************/ 4486 // Structure used in object_InfoTable 4487 /****************************************************************************/ 4488 typedef struct _ATOM_OBJECT_HEADER 4489 { 4490 ATOM_COMMON_TABLE_HEADER sHeader; 4491 USHORT usDeviceSupport; 4492 USHORT usConnectorObjectTableOffset; 4493 USHORT usRouterObjectTableOffset; 4494 USHORT usEncoderObjectTableOffset; 4495 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4496 USHORT usDisplayPathTableOffset; 4497 }ATOM_OBJECT_HEADER; 4498 4499 typedef struct _ATOM_OBJECT_HEADER_V3 4500 { 4501 ATOM_COMMON_TABLE_HEADER sHeader; 4502 USHORT usDeviceSupport; 4503 USHORT usConnectorObjectTableOffset; 4504 USHORT usRouterObjectTableOffset; 4505 USHORT usEncoderObjectTableOffset; 4506 USHORT usProtectionObjectTableOffset; //only available when Protection block is independent. 4507 USHORT usDisplayPathTableOffset; 4508 USHORT usMiscObjectTableOffset; 4509 }ATOM_OBJECT_HEADER_V3; 4510 4511 4512 typedef struct _ATOM_DISPLAY_OBJECT_PATH 4513 { 4514 USHORT usDeviceTag; //supported device 4515 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4516 USHORT usConnObjectId; //Connector Object ID 4517 USHORT usGPUObjectId; //GPU ID 4518 USHORT usGraphicObjIds[1]; //1st Encoder Obj source from GPU to last Graphic Obj destinate to connector. 4519 }ATOM_DISPLAY_OBJECT_PATH; 4520 4521 typedef struct _ATOM_DISPLAY_EXTERNAL_OBJECT_PATH 4522 { 4523 USHORT usDeviceTag; //supported device 4524 USHORT usSize; //the size of ATOM_DISPLAY_OBJECT_PATH 4525 USHORT usConnObjectId; //Connector Object ID 4526 USHORT usGPUObjectId; //GPU ID 4527 USHORT usGraphicObjIds[2]; //usGraphicObjIds[0]= GPU internal encoder, usGraphicObjIds[1]= external encoder 4528 }ATOM_DISPLAY_EXTERNAL_OBJECT_PATH; 4529 4530 typedef struct _ATOM_DISPLAY_OBJECT_PATH_TABLE 4531 { 4532 UCHAR ucNumOfDispPath; 4533 UCHAR ucVersion; 4534 UCHAR ucPadding[2]; 4535 ATOM_DISPLAY_OBJECT_PATH asDispPath[1]; 4536 }ATOM_DISPLAY_OBJECT_PATH_TABLE; 4537 4538 typedef struct _ATOM_OBJECT //each object has this structure 4539 { 4540 USHORT usObjectID; 4541 USHORT usSrcDstTableOffset; 4542 USHORT usRecordOffset; //this pointing to a bunch of records defined below 4543 USHORT usReserved; 4544 }ATOM_OBJECT; 4545 4546 typedef struct _ATOM_OBJECT_TABLE //Above 4 object table offset pointing to a bunch of objects all have this structure 4547 { 4548 UCHAR ucNumberOfObjects; 4549 UCHAR ucPadding[3]; 4550 ATOM_OBJECT asObjects[1]; 4551 }ATOM_OBJECT_TABLE; 4552 4553 typedef struct _ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT //usSrcDstTableOffset pointing to this structure 4554 { 4555 UCHAR ucNumberOfSrc; 4556 USHORT usSrcObjectID[1]; 4557 UCHAR ucNumberOfDst; 4558 USHORT usDstObjectID[1]; 4559 }ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT; 4560 4561 4562 //Two definitions below are for OPM on MXM module designs 4563 4564 #define EXT_HPDPIN_LUTINDEX_0 0 4565 #define EXT_HPDPIN_LUTINDEX_1 1 4566 #define EXT_HPDPIN_LUTINDEX_2 2 4567 #define EXT_HPDPIN_LUTINDEX_3 3 4568 #define EXT_HPDPIN_LUTINDEX_4 4 4569 #define EXT_HPDPIN_LUTINDEX_5 5 4570 #define EXT_HPDPIN_LUTINDEX_6 6 4571 #define EXT_HPDPIN_LUTINDEX_7 7 4572 #define MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES (EXT_HPDPIN_LUTINDEX_7+1) 4573 4574 #define EXT_AUXDDC_LUTINDEX_0 0 4575 #define EXT_AUXDDC_LUTINDEX_1 1 4576 #define EXT_AUXDDC_LUTINDEX_2 2 4577 #define EXT_AUXDDC_LUTINDEX_3 3 4578 #define EXT_AUXDDC_LUTINDEX_4 4 4579 #define EXT_AUXDDC_LUTINDEX_5 5 4580 #define EXT_AUXDDC_LUTINDEX_6 6 4581 #define EXT_AUXDDC_LUTINDEX_7 7 4582 #define MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES (EXT_AUXDDC_LUTINDEX_7+1) 4583 4584 //ucChannelMapping are defined as following 4585 //for DP connector, eDP, DP to VGA/LVDS 4586 //Bit[1:0]: Define which pin connect to DP connector DP_Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4587 //Bit[3:2]: Define which pin connect to DP connector DP_Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4588 //Bit[5:4]: Define which pin connect to DP connector DP_Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4589 //Bit[7:6]: Define which pin connect to DP connector DP_Lane3, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4590 typedef struct _ATOM_DP_CONN_CHANNEL_MAPPING 4591 { 4592 #if ATOM_BIG_ENDIAN 4593 UCHAR ucDP_Lane3_Source:2; 4594 UCHAR ucDP_Lane2_Source:2; 4595 UCHAR ucDP_Lane1_Source:2; 4596 UCHAR ucDP_Lane0_Source:2; 4597 #else 4598 UCHAR ucDP_Lane0_Source:2; 4599 UCHAR ucDP_Lane1_Source:2; 4600 UCHAR ucDP_Lane2_Source:2; 4601 UCHAR ucDP_Lane3_Source:2; 4602 #endif 4603 }ATOM_DP_CONN_CHANNEL_MAPPING; 4604 4605 //for DVI/HDMI, in dual link case, both links have to have same mapping. 4606 //Bit[1:0]: Define which pin connect to DVI connector data Lane2, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4607 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4608 //Bit[5:4]: Define which pin connect to DVI connector data Lane0, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4609 //Bit[7:6]: Define which pin connect to DVI connector clock lane, =0: source from GPU pin TX0, =1: from GPU pin TX1, =2: from GPU pin TX2, =3 from GPU pin TX3 4610 typedef struct _ATOM_DVI_CONN_CHANNEL_MAPPING 4611 { 4612 #if ATOM_BIG_ENDIAN 4613 UCHAR ucDVI_CLK_Source:2; 4614 UCHAR ucDVI_DATA0_Source:2; 4615 UCHAR ucDVI_DATA1_Source:2; 4616 UCHAR ucDVI_DATA2_Source:2; 4617 #else 4618 UCHAR ucDVI_DATA2_Source:2; 4619 UCHAR ucDVI_DATA1_Source:2; 4620 UCHAR ucDVI_DATA0_Source:2; 4621 UCHAR ucDVI_CLK_Source:2; 4622 #endif 4623 }ATOM_DVI_CONN_CHANNEL_MAPPING; 4624 4625 typedef struct _EXT_DISPLAY_PATH 4626 { 4627 USHORT usDeviceTag; //A bit vector to show what devices are supported 4628 USHORT usDeviceACPIEnum; //16bit device ACPI id. 4629 USHORT usDeviceConnector; //A physical connector for displays to plug in, using object connector definitions 4630 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT 4631 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT 4632 USHORT usExtEncoderObjId; //external encoder object id 4633 union{ 4634 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping 4635 ATOM_DP_CONN_CHANNEL_MAPPING asDPMapping; 4636 ATOM_DVI_CONN_CHANNEL_MAPPING asDVIMapping; 4637 }; 4638 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 4639 USHORT usCaps; 4640 USHORT usReserved; 4641 }EXT_DISPLAY_PATH; 4642 4643 #define NUMBER_OF_UCHAR_FOR_GUID 16 4644 #define MAX_NUMBER_OF_EXT_DISPLAY_PATH 7 4645 4646 //usCaps 4647 #define EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE 0x0001 4648 #define EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN 0x0002 4649 #define EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK 0x007C 4650 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204 (0x01 << 2 ) //PI redriver chip 4651 #define EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT (0x02 << 2 ) //TI retimer chip 4652 #define EXT_DISPLAY_PATH_CAPS__HDMI20_PARADE_PS175 (0x03 << 2 ) //Parade DP->HDMI recoverter chip 4653 4654 4655 4656 4657 typedef struct _ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO 4658 { 4659 ATOM_COMMON_TABLE_HEADER sHeader; 4660 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string 4661 EXT_DISPLAY_PATH sPath[MAX_NUMBER_OF_EXT_DISPLAY_PATH]; // total of fixed 7 entries. 4662 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0. 4663 UCHAR uc3DStereoPinId; // use for eDP panel 4664 UCHAR ucRemoteDisplayConfig; 4665 UCHAR uceDPToLVDSRxId; 4666 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value 4667 UCHAR Reserved[3]; // for potential expansion 4668 }ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO; 4669 4670 //Related definitions, all records are differnt but they have a commond header 4671 typedef struct _ATOM_COMMON_RECORD_HEADER 4672 { 4673 UCHAR ucRecordType; //An emun to indicate the record type 4674 UCHAR ucRecordSize; //The size of the whole record in byte 4675 }ATOM_COMMON_RECORD_HEADER; 4676 4677 4678 #define ATOM_I2C_RECORD_TYPE 1 4679 #define ATOM_HPD_INT_RECORD_TYPE 2 4680 #define ATOM_OUTPUT_PROTECTION_RECORD_TYPE 3 4681 #define ATOM_CONNECTOR_DEVICE_TAG_RECORD_TYPE 4 4682 #define ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD_TYPE 5 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4683 #define ATOM_ENCODER_FPGA_CONTROL_RECORD_TYPE 6 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4684 #define ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD_TYPE 7 4685 #define ATOM_JTAG_RECORD_TYPE 8 //Obsolete, switch to use GPIO_CNTL_RECORD_TYPE 4686 #define ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE 9 4687 #define ATOM_ENCODER_DVO_CF_RECORD_TYPE 10 4688 #define ATOM_CONNECTOR_CF_RECORD_TYPE 11 4689 #define ATOM_CONNECTOR_HARDCODE_DTD_RECORD_TYPE 12 4690 #define ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 13 4691 #define ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE 14 4692 #define ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE 15 4693 #define ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 16 //This is for the case when connectors are not known to object table 4694 #define ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 17 //This is for the case when connectors are not known to object table 4695 #define ATOM_OBJECT_LINK_RECORD_TYPE 18 //Once this record is present under one object, it indicats the oobject is linked to another obj described by the record 4696 #define ATOM_CONNECTOR_REMOTE_CAP_RECORD_TYPE 19 4697 #define ATOM_ENCODER_CAP_RECORD_TYPE 20 4698 #define ATOM_BRACKET_LAYOUT_RECORD_TYPE 21 4699 #define ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 22 4700 4701 //Must be updated when new record type is added,equal to that record definition! 4702 #define ATOM_MAX_OBJECT_RECORD_NUMBER ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE 4703 4704 typedef struct _ATOM_I2C_RECORD 4705 { 4706 ATOM_COMMON_RECORD_HEADER sheader; 4707 ATOM_I2C_ID_CONFIG sucI2cId; 4708 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC 4709 }ATOM_I2C_RECORD; 4710 4711 typedef struct _ATOM_HPD_INT_RECORD 4712 { 4713 ATOM_COMMON_RECORD_HEADER sheader; 4714 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4715 UCHAR ucPlugged_PinState; 4716 }ATOM_HPD_INT_RECORD; 4717 4718 4719 typedef struct _ATOM_OUTPUT_PROTECTION_RECORD 4720 { 4721 ATOM_COMMON_RECORD_HEADER sheader; 4722 UCHAR ucProtectionFlag; 4723 UCHAR ucReserved; 4724 }ATOM_OUTPUT_PROTECTION_RECORD; 4725 4726 typedef struct _ATOM_CONNECTOR_DEVICE_TAG 4727 { 4728 ULONG ulACPIDeviceEnum; //Reserved for now 4729 USHORT usDeviceID; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT" 4730 USHORT usPadding; 4731 }ATOM_CONNECTOR_DEVICE_TAG; 4732 4733 typedef struct _ATOM_CONNECTOR_DEVICE_TAG_RECORD 4734 { 4735 ATOM_COMMON_RECORD_HEADER sheader; 4736 UCHAR ucNumberOfDevice; 4737 UCHAR ucReserved; 4738 ATOM_CONNECTOR_DEVICE_TAG asDeviceTag[1]; //This Id is same as "ATOM_DEVICE_XXX_SUPPORT", 1 is only for allocation 4739 }ATOM_CONNECTOR_DEVICE_TAG_RECORD; 4740 4741 4742 typedef struct _ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD 4743 { 4744 ATOM_COMMON_RECORD_HEADER sheader; 4745 UCHAR ucConfigGPIOID; 4746 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in 4747 UCHAR ucFlowinGPIPID; 4748 UCHAR ucExtInGPIPID; 4749 }ATOM_CONNECTOR_DVI_EXT_INPUT_RECORD; 4750 4751 typedef struct _ATOM_ENCODER_FPGA_CONTROL_RECORD 4752 { 4753 ATOM_COMMON_RECORD_HEADER sheader; 4754 UCHAR ucCTL1GPIO_ID; 4755 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high 4756 UCHAR ucCTL2GPIO_ID; 4757 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high 4758 UCHAR ucCTL3GPIO_ID; 4759 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high 4760 UCHAR ucCTLFPGA_IN_ID; 4761 UCHAR ucPadding[3]; 4762 }ATOM_ENCODER_FPGA_CONTROL_RECORD; 4763 4764 typedef struct _ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD 4765 { 4766 ATOM_COMMON_RECORD_HEADER sheader; 4767 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info 4768 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected 4769 }ATOM_CONNECTOR_CVTV_SHARE_DIN_RECORD; 4770 4771 typedef struct _ATOM_JTAG_RECORD 4772 { 4773 ATOM_COMMON_RECORD_HEADER sheader; 4774 UCHAR ucTMSGPIO_ID; 4775 UCHAR ucTMSGPIOState; //Set to 1 when it's active high 4776 UCHAR ucTCKGPIO_ID; 4777 UCHAR ucTCKGPIOState; //Set to 1 when it's active high 4778 UCHAR ucTDOGPIO_ID; 4779 UCHAR ucTDOGPIOState; //Set to 1 when it's active high 4780 UCHAR ucTDIGPIO_ID; 4781 UCHAR ucTDIGPIOState; //Set to 1 when it's active high 4782 UCHAR ucPadding[2]; 4783 }ATOM_JTAG_RECORD; 4784 4785 4786 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 4787 typedef struct _ATOM_GPIO_PIN_CONTROL_PAIR 4788 { 4789 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table 4790 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin 4791 }ATOM_GPIO_PIN_CONTROL_PAIR; 4792 4793 typedef struct _ATOM_OBJECT_GPIO_CNTL_RECORD 4794 { 4795 ATOM_COMMON_RECORD_HEADER sheader; 4796 UCHAR ucFlags; // Future expnadibility 4797 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object 4798 ATOM_GPIO_PIN_CONTROL_PAIR asGpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 4799 }ATOM_OBJECT_GPIO_CNTL_RECORD; 4800 4801 //Definitions for GPIO pin state 4802 #define GPIO_PIN_TYPE_INPUT 0x00 4803 #define GPIO_PIN_TYPE_OUTPUT 0x10 4804 #define GPIO_PIN_TYPE_HW_CONTROL 0x20 4805 4806 //For GPIO_PIN_TYPE_OUTPUT the following is defined 4807 #define GPIO_PIN_OUTPUT_STATE_MASK 0x01 4808 #define GPIO_PIN_OUTPUT_STATE_SHIFT 0 4809 #define GPIO_PIN_STATE_ACTIVE_LOW 0x0 4810 #define GPIO_PIN_STATE_ACTIVE_HIGH 0x1 4811 4812 // Indexes to GPIO array in GLSync record 4813 // GLSync record is for Frame Lock/Gen Lock feature. 4814 #define ATOM_GPIO_INDEX_GLSYNC_REFCLK 0 4815 #define ATOM_GPIO_INDEX_GLSYNC_HSYNC 1 4816 #define ATOM_GPIO_INDEX_GLSYNC_VSYNC 2 4817 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ 3 4818 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT 4 4819 #define ATOM_GPIO_INDEX_GLSYNC_INTERRUPT 5 4820 #define ATOM_GPIO_INDEX_GLSYNC_V_RESET 6 4821 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL 7 4822 #define ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL 8 4823 #define ATOM_GPIO_INDEX_GLSYNC_MAX 9 4824 4825 typedef struct _ATOM_ENCODER_DVO_CF_RECORD 4826 { 4827 ATOM_COMMON_RECORD_HEADER sheader; 4828 ULONG ulStrengthControl; // DVOA strength control for CF 4829 UCHAR ucPadding[2]; 4830 }ATOM_ENCODER_DVO_CF_RECORD; 4831 4832 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 4833 #define ATOM_ENCODER_CAP_RECORD_HBR2 0x01 // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 4834 #define ATOM_ENCODER_CAP_RECORD_MST_EN 0x01 // from SI, this bit means DP MST is enable or not. 4835 #define ATOM_ENCODER_CAP_RECORD_HBR2_EN 0x02 // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 4836 #define ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN 0x04 // HDMI2.0 6Gbps enable or not. 4837 #define ATOM_ENCODER_CAP_RECORD_HBR3_EN 0x08 // DP1.3 HBR3 is supported by board. 4838 4839 typedef struct _ATOM_ENCODER_CAP_RECORD 4840 { 4841 ATOM_COMMON_RECORD_HEADER sheader; 4842 union { 4843 USHORT usEncoderCap; 4844 struct { 4845 #if ATOM_BIG_ENDIAN 4846 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4847 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4848 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4849 #else 4850 USHORT usHBR2Cap:1; // Bit0 is for DP1.2 HBR2 capability. 4851 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4852 USHORT usReserved:14; // Bit1-15 may be defined for other capability in future 4853 #endif 4854 }; 4855 }; 4856 }ATOM_ENCODER_CAP_RECORD; 4857 4858 // Used after SI 4859 typedef struct _ATOM_ENCODER_CAP_RECORD_V2 4860 { 4861 ATOM_COMMON_RECORD_HEADER sheader; 4862 union { 4863 USHORT usEncoderCap; 4864 struct { 4865 #if ATOM_BIG_ENDIAN 4866 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4867 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4868 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4869 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4870 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4871 #else 4872 USHORT usMSTEn:1; // Bit0 is for DP1.2 MST enable 4873 USHORT usHBR2En:1; // Bit1 is for DP1.2 HBR2 enable 4874 USHORT usHDMI6GEn:1; // Bit2 is for HDMI6Gbps enable, this bit is used starting from CZ( APU) Ellemere (dGPU) 4875 USHORT usHBR3En:1; // bit3 is for DP1.3 HBR3 enable 4876 USHORT usReserved:12; // Bit4-15 may be defined for other capability in future 4877 #endif 4878 }; 4879 }; 4880 }ATOM_ENCODER_CAP_RECORD_V2; 4881 4882 4883 // value for ATOM_CONNECTOR_CF_RECORD.ucConnectedDvoBundle 4884 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_UPPER12BITBUNDLEA 1 4885 #define ATOM_CONNECTOR_CF_RECORD_CONNECTED_LOWER12BITBUNDLEB 2 4886 4887 typedef struct _ATOM_CONNECTOR_CF_RECORD 4888 { 4889 ATOM_COMMON_RECORD_HEADER sheader; 4890 USHORT usMaxPixClk; 4891 UCHAR ucFlowCntlGpioId; 4892 UCHAR ucSwapCntlGpioId; 4893 UCHAR ucConnectedDvoBundle; 4894 UCHAR ucPadding; 4895 }ATOM_CONNECTOR_CF_RECORD; 4896 4897 typedef struct _ATOM_CONNECTOR_HARDCODE_DTD_RECORD 4898 { 4899 ATOM_COMMON_RECORD_HEADER sheader; 4900 ATOM_DTD_FORMAT asTiming; 4901 }ATOM_CONNECTOR_HARDCODE_DTD_RECORD; 4902 4903 typedef struct _ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD 4904 { 4905 ATOM_COMMON_RECORD_HEADER sheader; //ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD_TYPE 4906 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A 4907 UCHAR ucReserved; 4908 }ATOM_CONNECTOR_PCIE_SUBCONNECTOR_RECORD; 4909 4910 4911 typedef struct _ATOM_ROUTER_DDC_PATH_SELECT_RECORD 4912 { 4913 ATOM_COMMON_RECORD_HEADER sheader; 4914 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state 4915 UCHAR ucMuxControlPin; 4916 UCHAR ucMuxState[2]; //for alligment purpose 4917 }ATOM_ROUTER_DDC_PATH_SELECT_RECORD; 4918 4919 typedef struct _ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD 4920 { 4921 ATOM_COMMON_RECORD_HEADER sheader; 4922 UCHAR ucMuxType; 4923 UCHAR ucMuxControlPin; 4924 UCHAR ucMuxState[2]; //for alligment purpose 4925 }ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD; 4926 4927 // define ucMuxType 4928 #define ATOM_ROUTER_MUX_PIN_STATE_MASK 0x0f 4929 #define ATOM_ROUTER_MUX_PIN_SINGLE_STATE_COMPLEMENT 0x01 4930 4931 typedef struct _ATOM_CONNECTOR_HPDPIN_LUT_RECORD //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 4932 { 4933 ATOM_COMMON_RECORD_HEADER sheader; 4934 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table 4935 }ATOM_CONNECTOR_HPDPIN_LUT_RECORD; 4936 4937 typedef struct _ATOM_CONNECTOR_AUXDDC_LUT_RECORD //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 4938 { 4939 ATOM_COMMON_RECORD_HEADER sheader; 4940 ATOM_I2C_ID_CONFIG ucAUXDDCMap[MAX_NUMBER_OF_EXT_AUXDDC_LUT_ENTRIES]; //An fixed size array which maps external pins to internal DDC ID 4941 }ATOM_CONNECTOR_AUXDDC_LUT_RECORD; 4942 4943 typedef struct _ATOM_OBJECT_LINK_RECORD 4944 { 4945 ATOM_COMMON_RECORD_HEADER sheader; 4946 USHORT usObjectID; //could be connector, encorder or other object in object.h 4947 }ATOM_OBJECT_LINK_RECORD; 4948 4949 typedef struct _ATOM_CONNECTOR_REMOTE_CAP_RECORD 4950 { 4951 ATOM_COMMON_RECORD_HEADER sheader; 4952 USHORT usReserved; 4953 }ATOM_CONNECTOR_REMOTE_CAP_RECORD; 4954 4955 4956 typedef struct _ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD 4957 { 4958 ATOM_COMMON_RECORD_HEADER sheader; 4959 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 4960 UCHAR ucMaxTmdsClkRateIn2_5Mhz; 4961 UCHAR ucReserved; 4962 } ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD; 4963 4964 4965 typedef struct _ATOM_CONNECTOR_LAYOUT_INFO 4966 { 4967 USHORT usConnectorObjectId; 4968 UCHAR ucConnectorType; 4969 UCHAR ucPosition; 4970 }ATOM_CONNECTOR_LAYOUT_INFO; 4971 4972 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 4973 #define CONNECTOR_TYPE_DVI_D 1 4974 #define CONNECTOR_TYPE_DVI_I 2 4975 #define CONNECTOR_TYPE_VGA 3 4976 #define CONNECTOR_TYPE_HDMI 4 4977 #define CONNECTOR_TYPE_DISPLAY_PORT 5 4978 #define CONNECTOR_TYPE_MINI_DISPLAY_PORT 6 4979 4980 typedef struct _ATOM_BRACKET_LAYOUT_RECORD 4981 { 4982 ATOM_COMMON_RECORD_HEADER sheader; 4983 UCHAR ucLength; 4984 UCHAR ucWidth; 4985 UCHAR ucConnNum; 4986 UCHAR ucReserved; 4987 ATOM_CONNECTOR_LAYOUT_INFO asConnInfo[1]; 4988 }ATOM_BRACKET_LAYOUT_RECORD; 4989 4990 4991 /****************************************************************************/ 4992 // Structure used in XXXX 4993 /****************************************************************************/ 4994 typedef struct _ATOM_VOLTAGE_INFO_HEADER 4995 { 4996 USHORT usVDDCBaseLevel; //In number of 50mv unit 4997 USHORT usReserved; //For possible extension table offset 4998 UCHAR ucNumOfVoltageEntries; 4999 UCHAR ucBytesPerVoltageEntry; 5000 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit 5001 UCHAR ucDefaultVoltageEntry; 5002 UCHAR ucVoltageControlI2cLine; 5003 UCHAR ucVoltageControlAddress; 5004 UCHAR ucVoltageControlOffset; 5005 }ATOM_VOLTAGE_INFO_HEADER; 5006 5007 typedef struct _ATOM_VOLTAGE_INFO 5008 { 5009 ATOM_COMMON_TABLE_HEADER sHeader; 5010 ATOM_VOLTAGE_INFO_HEADER viHeader; 5011 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry 5012 }ATOM_VOLTAGE_INFO; 5013 5014 5015 typedef struct _ATOM_VOLTAGE_FORMULA 5016 { 5017 USHORT usVoltageBaseLevel; // In number of 1mv unit 5018 USHORT usVoltageStep; // Indicating in how many mv increament is one step, 1mv unit 5019 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5020 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv 5021 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep 5022 UCHAR ucReserved; 5023 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries 5024 }ATOM_VOLTAGE_FORMULA; 5025 5026 typedef struct _VOLTAGE_LUT_ENTRY 5027 { 5028 USHORT usVoltageCode; // The Voltage ID, either GPIO or I2C code 5029 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5030 }VOLTAGE_LUT_ENTRY; 5031 5032 typedef struct _ATOM_VOLTAGE_FORMULA_V2 5033 { 5034 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage 5035 UCHAR ucReserved[3]; 5036 VOLTAGE_LUT_ENTRY asVIDAdjustEntries[32];// 32 is for allocation, the actual number of entries is in ucNumOfVoltageEntries 5037 }ATOM_VOLTAGE_FORMULA_V2; 5038 5039 typedef struct _ATOM_VOLTAGE_CONTROL 5040 { 5041 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine 5042 UCHAR ucVoltageControlI2cLine; 5043 UCHAR ucVoltageControlAddress; 5044 UCHAR ucVoltageControlOffset; 5045 USHORT usGpioPin_AIndex; //GPIO_PAD register index 5046 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff 5047 UCHAR ucReserved; 5048 }ATOM_VOLTAGE_CONTROL; 5049 5050 // Define ucVoltageControlId 5051 #define VOLTAGE_CONTROLLED_BY_HW 0x00 5052 #define VOLTAGE_CONTROLLED_BY_I2C_MASK 0x7F 5053 #define VOLTAGE_CONTROLLED_BY_GPIO 0x80 5054 #define VOLTAGE_CONTROL_ID_LM64 0x01 //I2C control, used for R5xx Core Voltage 5055 #define VOLTAGE_CONTROL_ID_DAC 0x02 //I2C control, used for R5xx/R6xx MVDDC,MVDDQ or VDDCI 5056 #define VOLTAGE_CONTROL_ID_VT116xM 0x03 //I2C control, used for R6xx Core Voltage 5057 #define VOLTAGE_CONTROL_ID_DS4402 0x04 5058 #define VOLTAGE_CONTROL_ID_UP6266 0x05 5059 #define VOLTAGE_CONTROL_ID_SCORPIO 0x06 5060 #define VOLTAGE_CONTROL_ID_VT1556M 0x07 5061 #define VOLTAGE_CONTROL_ID_CHL822x 0x08 5062 #define VOLTAGE_CONTROL_ID_VT1586M 0x09 5063 #define VOLTAGE_CONTROL_ID_UP1637 0x0A 5064 #define VOLTAGE_CONTROL_ID_CHL8214 0x0B 5065 #define VOLTAGE_CONTROL_ID_UP1801 0x0C 5066 #define VOLTAGE_CONTROL_ID_ST6788A 0x0D 5067 #define VOLTAGE_CONTROL_ID_CHLIR3564SVI2 0x0E 5068 #define VOLTAGE_CONTROL_ID_AD527x 0x0F 5069 #define VOLTAGE_CONTROL_ID_NCP81022 0x10 5070 #define VOLTAGE_CONTROL_ID_LTC2635 0x11 5071 #define VOLTAGE_CONTROL_ID_NCP4208 0x12 5072 #define VOLTAGE_CONTROL_ID_IR35xx 0x13 5073 #define VOLTAGE_CONTROL_ID_RT9403 0x14 5074 5075 #define VOLTAGE_CONTROL_ID_GENERIC_I2C 0x40 5076 5077 typedef struct _ATOM_VOLTAGE_OBJECT 5078 { 5079 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5080 UCHAR ucSize; //Size of Object 5081 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5082 ATOM_VOLTAGE_FORMULA asFormula; //Indicate How to convert real Voltage to VID 5083 }ATOM_VOLTAGE_OBJECT; 5084 5085 typedef struct _ATOM_VOLTAGE_OBJECT_V2 5086 { 5087 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5088 UCHAR ucSize; //Size of Object 5089 ATOM_VOLTAGE_CONTROL asControl; //describ how to control 5090 ATOM_VOLTAGE_FORMULA_V2 asFormula; //Indicate How to convert real Voltage to VID 5091 }ATOM_VOLTAGE_OBJECT_V2; 5092 5093 typedef struct _ATOM_VOLTAGE_OBJECT_INFO 5094 { 5095 ATOM_COMMON_TABLE_HEADER sHeader; 5096 ATOM_VOLTAGE_OBJECT asVoltageObj[3]; //Info for Voltage control 5097 }ATOM_VOLTAGE_OBJECT_INFO; 5098 5099 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V2 5100 { 5101 ATOM_COMMON_TABLE_HEADER sHeader; 5102 ATOM_VOLTAGE_OBJECT_V2 asVoltageObj[3]; //Info for Voltage control 5103 }ATOM_VOLTAGE_OBJECT_INFO_V2; 5104 5105 typedef struct _ATOM_LEAKID_VOLTAGE 5106 { 5107 UCHAR ucLeakageId; 5108 UCHAR ucReserved; 5109 USHORT usVoltage; 5110 }ATOM_LEAKID_VOLTAGE; 5111 5112 typedef struct _ATOM_VOLTAGE_OBJECT_HEADER_V3{ 5113 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI 5114 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase 5115 USHORT usSize; //Size of Object 5116 }ATOM_VOLTAGE_OBJECT_HEADER_V3; 5117 5118 // ATOM_VOLTAGE_OBJECT_HEADER_V3.ucVoltageMode 5119 #define VOLTAGE_OBJ_GPIO_LUT 0 //VOLTAGE and GPIO Lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5120 #define VOLTAGE_OBJ_VR_I2C_INIT_SEQ 3 //VOLTAGE REGULATOR INIT sequece through I2C -> ATOM_I2C_VOLTAGE_OBJECT_V3 5121 #define VOLTAGE_OBJ_PHASE_LUT 4 //Set Vregulator Phase lookup table ->ATOM_GPIO_VOLTAGE_OBJECT_V3 5122 #define VOLTAGE_OBJ_SVID2 7 //Indicate voltage control by SVID2 ->ATOM_SVID2_VOLTAGE_OBJECT_V3 5123 #define VOLTAGE_OBJ_EVV 8 5124 #define VOLTAGE_OBJ_PWRBOOST_LEAKAGE_LUT 0x10 //Powerboost Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5125 #define VOLTAGE_OBJ_HIGH_STATE_LEAKAGE_LUT 0x11 //High voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5126 #define VOLTAGE_OBJ_HIGH1_STATE_LEAKAGE_LUT 0x12 //High1 voltage state Voltage and LeakageId lookup table->ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5127 5128 typedef struct _VOLTAGE_LUT_ENTRY_V2 5129 { 5130 ULONG ulVoltageId; // The Voltage ID which is used to program GPIO register 5131 USHORT usVoltageValue; // The corresponding Voltage Value, in mV 5132 }VOLTAGE_LUT_ENTRY_V2; 5133 5134 typedef struct _LEAKAGE_VOLTAGE_LUT_ENTRY_V2 5135 { 5136 USHORT usVoltageLevel; // The Voltage ID which is used to program GPIO register 5137 USHORT usVoltageId; 5138 USHORT usLeakageId; // The corresponding Voltage Value, in mV 5139 }LEAKAGE_VOLTAGE_LUT_ENTRY_V2; 5140 5141 5142 typedef struct _ATOM_I2C_VOLTAGE_OBJECT_V3 5143 { 5144 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 5145 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id 5146 UCHAR ucVoltageControlI2cLine; 5147 UCHAR ucVoltageControlAddress; 5148 UCHAR ucVoltageControlOffset; 5149 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data 5150 UCHAR ulReserved[3]; 5151 VOLTAGE_LUT_ENTRY asVolI2cLut[1]; // end with 0xff 5152 }ATOM_I2C_VOLTAGE_OBJECT_V3; 5153 5154 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 5155 #define VOLTAGE_DATA_ONE_BYTE 0 5156 #define VOLTAGE_DATA_TWO_BYTE 1 5157 5158 typedef struct _ATOM_GPIO_VOLTAGE_OBJECT_V3 5159 { 5160 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 5161 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode 5162 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table 5163 UCHAR ucPhaseDelay; // phase delay in unit of micro second 5164 UCHAR ucReserved; 5165 ULONG ulGpioMaskVal; // GPIO Mask value 5166 VOLTAGE_LUT_ENTRY_V2 asVolGpioLut[1]; 5167 }ATOM_GPIO_VOLTAGE_OBJECT_V3; 5168 5169 typedef struct _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 5170 { 5171 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = 0x10/0x11/0x12 5172 UCHAR ucLeakageCntlId; // default is 0 5173 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table 5174 UCHAR ucReserved[2]; 5175 ULONG ulMaxVoltageLevel; 5176 LEAKAGE_VOLTAGE_LUT_ENTRY_V2 asLeakageIdLut[1]; 5177 }ATOM_LEAKAGE_VOLTAGE_OBJECT_V3; 5178 5179 5180 typedef struct _ATOM_SVID2_VOLTAGE_OBJECT_V3 5181 { 5182 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5183 // 14:7 PSI0_VID 5184 // 6 PSI0_EN 5185 // 5 PSI1 5186 // 4:2 load line slope trim. 5187 // 1:0 offset trim, 5188 USHORT usLoadLine_PSI; 5189 // GPU GPIO pin Id to SVID2 regulator VRHot pin. possible value 0~31. 0 means GPIO0, 31 means GPIO31 5190 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31 5191 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31 5192 ULONG ulReserved; 5193 }ATOM_SVID2_VOLTAGE_OBJECT_V3; 5194 5195 5196 5197 typedef struct _ATOM_MERGED_VOLTAGE_OBJECT_V3 5198 { 5199 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 5200 UCHAR ucMergedVType; // VDDC/VDCCI/.... 5201 UCHAR ucReserved[3]; 5202 }ATOM_MERGED_VOLTAGE_OBJECT_V3; 5203 5204 5205 typedef struct _ATOM_EVV_DPM_INFO 5206 { 5207 ULONG ulDPMSclk; // DPM state SCLK 5208 USHORT usVAdjOffset; // Adjust Voltage offset in unit of mv 5209 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable 5210 UCHAR ucDPMState; // DPMState0~7 5211 } ATOM_EVV_DPM_INFO; 5212 5213 // ucVoltageMode = VOLTAGE_OBJ_EVV 5214 typedef struct _ATOM_EVV_VOLTAGE_OBJECT_V3 5215 { 5216 ATOM_VOLTAGE_OBJECT_HEADER_V3 sHeader; // voltage mode = VOLTAGE_OBJ_SVID2 5217 ATOM_EVV_DPM_INFO asEvvDpmList[8]; 5218 }ATOM_EVV_VOLTAGE_OBJECT_V3; 5219 5220 5221 typedef union _ATOM_VOLTAGE_OBJECT_V3{ 5222 ATOM_GPIO_VOLTAGE_OBJECT_V3 asGpioVoltageObj; 5223 ATOM_I2C_VOLTAGE_OBJECT_V3 asI2cVoltageObj; 5224 ATOM_LEAKAGE_VOLTAGE_OBJECT_V3 asLeakageObj; 5225 ATOM_SVID2_VOLTAGE_OBJECT_V3 asSVID2Obj; 5226 ATOM_EVV_VOLTAGE_OBJECT_V3 asEvvObj; 5227 }ATOM_VOLTAGE_OBJECT_V3; 5228 5229 typedef struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 5230 { 5231 ATOM_COMMON_TABLE_HEADER sHeader; 5232 ATOM_VOLTAGE_OBJECT_V3 asVoltageObj[3]; //Info for Voltage control 5233 }ATOM_VOLTAGE_OBJECT_INFO_V3_1; 5234 5235 5236 typedef struct _ATOM_ASIC_PROFILE_VOLTAGE 5237 { 5238 UCHAR ucProfileId; 5239 UCHAR ucReserved; 5240 USHORT usSize; 5241 USHORT usEfuseSpareStartAddr; 5242 USHORT usFuseIndex[8]; //from LSB to MSB, Max 8bit,end of 0xffff if less than 8 efuse id, 5243 ATOM_LEAKID_VOLTAGE asLeakVol[2]; //Leakid and relatd voltage 5244 }ATOM_ASIC_PROFILE_VOLTAGE; 5245 5246 //ucProfileId 5247 #define ATOM_ASIC_PROFILE_ID_EFUSE_VOLTAGE 1 5248 #define ATOM_ASIC_PROFILE_ID_EFUSE_PERFORMANCE_VOLTAGE 1 5249 #define ATOM_ASIC_PROFILE_ID_EFUSE_THERMAL_VOLTAGE 2 5250 5251 typedef struct _ATOM_ASIC_PROFILING_INFO 5252 { 5253 ATOM_COMMON_TABLE_HEADER asHeader; 5254 ATOM_ASIC_PROFILE_VOLTAGE asVoltage; 5255 }ATOM_ASIC_PROFILING_INFO; 5256 5257 typedef struct _ATOM_ASIC_PROFILING_INFO_V2_1 5258 { 5259 ATOM_COMMON_TABLE_HEADER asHeader; 5260 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table 5261 USHORT usLeakageBinArrayOffset; // offset of USHORT Leakage Bin list array ( from lower LeakageId to higher) 5262 5263 UCHAR ucElbVDDC_Num; 5264 USHORT usElbVDDC_IdArrayOffset; // offset of USHORT virtual VDDC voltage id ( 0xff01~0xff08 ) 5265 USHORT usElbVDDC_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5266 5267 UCHAR ucElbVDDCI_Num; 5268 USHORT usElbVDDCI_IdArrayOffset; // offset of USHORT virtual VDDCI voltage id ( 0xff01~0xff08 ) 5269 USHORT usElbVDDCI_LevelArrayOffset; // offset of 2 dimension voltage level USHORT array 5270 }ATOM_ASIC_PROFILING_INFO_V2_1; 5271 5272 5273 //Here is parameter to convert Efuse value to Measure value 5274 //Measured = LN((2^Bitsize-1)/EFUSE-1)*(Range)/(-alpha)+(Max+Min)/2 5275 typedef struct _EFUSE_LOGISTIC_FUNC_PARAM 5276 { 5277 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5278 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5279 UCHAR ucEfuseLength; // Efuse bits length, 5280 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5281 ULONG ulEfuseEncodeAverage; // Average = ( Max + Min )/2 5282 }EFUSE_LOGISTIC_FUNC_PARAM; 5283 5284 //Linear Function: Measured = Round ( Efuse * ( Max-Min )/(2^BitSize -1 ) + Min ) 5285 typedef struct _EFUSE_LINEAR_FUNC_PARAM 5286 { 5287 USHORT usEfuseIndex; // Efuse Index in DWORD address, for example Index 911, usEuseIndex=112 5288 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15 5289 UCHAR ucEfuseLength; // Efuse bits length, 5290 ULONG ulEfuseEncodeRange; // Range = Max - Min, bit31 indicate the efuse is negative number 5291 ULONG ulEfuseMin; // Min 5292 }EFUSE_LINEAR_FUNC_PARAM; 5293 5294 5295 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_1 5296 { 5297 ATOM_COMMON_TABLE_HEADER asHeader; 5298 ULONG ulEvvDerateTdp; 5299 ULONG ulEvvDerateTdc; 5300 ULONG ulBoardCoreTemp; 5301 ULONG ulMaxVddc; 5302 ULONG ulMinVddc; 5303 ULONG ulLoadLineSlop; 5304 ULONG ulLeakageTemp; 5305 ULONG ulLeakageVoltage; 5306 EFUSE_LINEAR_FUNC_PARAM sCACm; 5307 EFUSE_LINEAR_FUNC_PARAM sCACb; 5308 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5309 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5310 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5311 USHORT usLkgEuseIndex; 5312 UCHAR ucLkgEfuseBitLSB; 5313 UCHAR ucLkgEfuseLength; 5314 ULONG ulLkgEncodeLn_MaxDivMin; 5315 ULONG ulLkgEncodeMax; 5316 ULONG ulLkgEncodeMin; 5317 ULONG ulEfuseLogisticAlpha; 5318 USHORT usPowerDpm0; 5319 USHORT usCurrentDpm0; 5320 USHORT usPowerDpm1; 5321 USHORT usCurrentDpm1; 5322 USHORT usPowerDpm2; 5323 USHORT usCurrentDpm2; 5324 USHORT usPowerDpm3; 5325 USHORT usCurrentDpm3; 5326 USHORT usPowerDpm4; 5327 USHORT usCurrentDpm4; 5328 USHORT usPowerDpm5; 5329 USHORT usCurrentDpm5; 5330 USHORT usPowerDpm6; 5331 USHORT usCurrentDpm6; 5332 USHORT usPowerDpm7; 5333 USHORT usCurrentDpm7; 5334 }ATOM_ASIC_PROFILING_INFO_V3_1; 5335 5336 5337 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_2 5338 { 5339 ATOM_COMMON_TABLE_HEADER asHeader; 5340 ULONG ulEvvLkgFactor; 5341 ULONG ulBoardCoreTemp; 5342 ULONG ulMaxVddc; 5343 ULONG ulMinVddc; 5344 ULONG ulLoadLineSlop; 5345 ULONG ulLeakageTemp; 5346 ULONG ulLeakageVoltage; 5347 EFUSE_LINEAR_FUNC_PARAM sCACm; 5348 EFUSE_LINEAR_FUNC_PARAM sCACb; 5349 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5350 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5351 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5352 USHORT usLkgEuseIndex; 5353 UCHAR ucLkgEfuseBitLSB; 5354 UCHAR ucLkgEfuseLength; 5355 ULONG ulLkgEncodeLn_MaxDivMin; 5356 ULONG ulLkgEncodeMax; 5357 ULONG ulLkgEncodeMin; 5358 ULONG ulEfuseLogisticAlpha; 5359 USHORT usPowerDpm0; 5360 USHORT usPowerDpm1; 5361 USHORT usPowerDpm2; 5362 USHORT usPowerDpm3; 5363 USHORT usPowerDpm4; 5364 USHORT usPowerDpm5; 5365 USHORT usPowerDpm6; 5366 USHORT usPowerDpm7; 5367 ULONG ulTdpDerateDPM0; 5368 ULONG ulTdpDerateDPM1; 5369 ULONG ulTdpDerateDPM2; 5370 ULONG ulTdpDerateDPM3; 5371 ULONG ulTdpDerateDPM4; 5372 ULONG ulTdpDerateDPM5; 5373 ULONG ulTdpDerateDPM6; 5374 ULONG ulTdpDerateDPM7; 5375 }ATOM_ASIC_PROFILING_INFO_V3_2; 5376 5377 5378 // for Tonga/Fiji speed EVV algorithm 5379 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_3 5380 { 5381 ATOM_COMMON_TABLE_HEADER asHeader; 5382 ULONG ulEvvLkgFactor; 5383 ULONG ulBoardCoreTemp; 5384 ULONG ulMaxVddc; 5385 ULONG ulMinVddc; 5386 ULONG ulLoadLineSlop; 5387 ULONG ulLeakageTemp; 5388 ULONG ulLeakageVoltage; 5389 EFUSE_LINEAR_FUNC_PARAM sCACm; 5390 EFUSE_LINEAR_FUNC_PARAM sCACb; 5391 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5392 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5393 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5394 USHORT usLkgEuseIndex; 5395 UCHAR ucLkgEfuseBitLSB; 5396 UCHAR ucLkgEfuseLength; 5397 ULONG ulLkgEncodeLn_MaxDivMin; 5398 ULONG ulLkgEncodeMax; 5399 ULONG ulLkgEncodeMin; 5400 ULONG ulEfuseLogisticAlpha; 5401 5402 union{ 5403 USHORT usPowerDpm0; 5404 USHORT usParamNegFlag; //bit0 =1 :indicate ulRoBeta is Negative, bit1=1 indicate Kv_m max is postive 5405 }; 5406 USHORT usPowerDpm1; 5407 USHORT usPowerDpm2; 5408 USHORT usPowerDpm3; 5409 USHORT usPowerDpm4; 5410 USHORT usPowerDpm5; 5411 USHORT usPowerDpm6; 5412 USHORT usPowerDpm7; 5413 ULONG ulTdpDerateDPM0; 5414 ULONG ulTdpDerateDPM1; 5415 ULONG ulTdpDerateDPM2; 5416 ULONG ulTdpDerateDPM3; 5417 ULONG ulTdpDerateDPM4; 5418 ULONG ulTdpDerateDPM5; 5419 ULONG ulTdpDerateDPM6; 5420 ULONG ulTdpDerateDPM7; 5421 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5422 ULONG ulRoAlpha; 5423 ULONG ulRoBeta; 5424 ULONG ulRoGamma; 5425 ULONG ulRoEpsilon; 5426 ULONG ulATermRo; 5427 ULONG ulBTermRo; 5428 ULONG ulCTermRo; 5429 ULONG ulSclkMargin; 5430 ULONG ulFmaxPercent; 5431 ULONG ulCRPercent; 5432 ULONG ulSFmaxPercent; 5433 ULONG ulSCRPercent; 5434 ULONG ulSDCMargine; 5435 }ATOM_ASIC_PROFILING_INFO_V3_3; 5436 5437 // for Fiji speed EVV algorithm 5438 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 5439 { 5440 ATOM_COMMON_TABLE_HEADER asHeader; 5441 ULONG ulEvvLkgFactor; 5442 ULONG ulBoardCoreTemp; 5443 ULONG ulMaxVddc; 5444 ULONG ulMinVddc; 5445 ULONG ulLoadLineSlop; 5446 ULONG ulLeakageTemp; 5447 ULONG ulLeakageVoltage; 5448 EFUSE_LINEAR_FUNC_PARAM sCACm; 5449 EFUSE_LINEAR_FUNC_PARAM sCACb; 5450 EFUSE_LOGISTIC_FUNC_PARAM sKt_b; 5451 EFUSE_LOGISTIC_FUNC_PARAM sKv_m; 5452 EFUSE_LOGISTIC_FUNC_PARAM sKv_b; 5453 USHORT usLkgEuseIndex; 5454 UCHAR ucLkgEfuseBitLSB; 5455 UCHAR ucLkgEfuseLength; 5456 ULONG ulLkgEncodeLn_MaxDivMin; 5457 ULONG ulLkgEncodeMax; 5458 ULONG ulLkgEncodeMin; 5459 ULONG ulEfuseLogisticAlpha; 5460 USHORT usPowerDpm0; 5461 USHORT usPowerDpm1; 5462 USHORT usPowerDpm2; 5463 USHORT usPowerDpm3; 5464 USHORT usPowerDpm4; 5465 USHORT usPowerDpm5; 5466 USHORT usPowerDpm6; 5467 USHORT usPowerDpm7; 5468 ULONG ulTdpDerateDPM0; 5469 ULONG ulTdpDerateDPM1; 5470 ULONG ulTdpDerateDPM2; 5471 ULONG ulTdpDerateDPM3; 5472 ULONG ulTdpDerateDPM4; 5473 ULONG ulTdpDerateDPM5; 5474 ULONG ulTdpDerateDPM6; 5475 ULONG ulTdpDerateDPM7; 5476 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5477 ULONG ulEvvDefaultVddc; 5478 ULONG ulEvvNoCalcVddc; 5479 USHORT usParamNegFlag; 5480 USHORT usSpeed_Model; 5481 ULONG ulSM_A0; 5482 ULONG ulSM_A1; 5483 ULONG ulSM_A2; 5484 ULONG ulSM_A3; 5485 ULONG ulSM_A4; 5486 ULONG ulSM_A5; 5487 ULONG ulSM_A6; 5488 ULONG ulSM_A7; 5489 UCHAR ucSM_A0_sign; 5490 UCHAR ucSM_A1_sign; 5491 UCHAR ucSM_A2_sign; 5492 UCHAR ucSM_A3_sign; 5493 UCHAR ucSM_A4_sign; 5494 UCHAR ucSM_A5_sign; 5495 UCHAR ucSM_A6_sign; 5496 UCHAR ucSM_A7_sign; 5497 ULONG ulMargin_RO_a; 5498 ULONG ulMargin_RO_b; 5499 ULONG ulMargin_RO_c; 5500 ULONG ulMargin_fixed; 5501 ULONG ulMargin_Fmax_mean; 5502 ULONG ulMargin_plat_mean; 5503 ULONG ulMargin_Fmax_sigma; 5504 ULONG ulMargin_plat_sigma; 5505 ULONG ulMargin_DC_sigma; 5506 ULONG ulReserved[8]; // Reserved for future ASIC 5507 }ATOM_ASIC_PROFILING_INFO_V3_4; 5508 5509 // for Polaris10/Polaris11 speed EVV algorithm 5510 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 5511 { 5512 ATOM_COMMON_TABLE_HEADER asHeader; 5513 ULONG ulMaxVddc; //Maximum voltage for all parts, in unit of 0.01mv 5514 ULONG ulMinVddc; //Minimum voltage for all parts, in unit of 0.01mv 5515 USHORT usLkgEuseIndex; //Efuse Lkg_FT address ( BYTE address ) 5516 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD 5517 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length 5518 ULONG ulLkgEncodeLn_MaxDivMin; //value of ln(Max_Lkg_Ft/Min_Lkg_Ft ) in unit of 0.00001 ( unit=100000 ) 5519 ULONG ulLkgEncodeMax; //Maximum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5520 ULONG ulLkgEncodeMin; //Minimum Lkg_Ft measured value ( or efuse decode value ), in unit of 0.00001 ( unit=100000 ) 5521 EFUSE_LINEAR_FUNC_PARAM sRoFuse;//Efuse RO info: DWORD address, bit shift, length, max/min measure value. in unit of 1. 5522 ULONG ulEvvDefaultVddc; //def="EVV_DEFAULT_VDDC" descr="return default VDDC(v) when Efuse not cut" unit="100000"/> 5523 ULONG ulEvvNoCalcVddc; //def="EVV_NOCALC_VDDC" descr="return VDDC(v) when Calculation is bad" unit="100000"/> 5524 ULONG ulSpeed_Model; //def="EVV_SPEED_MODEL" descr="0 = Greek model, 1 = multivariate model" unit="1"/> 5525 ULONG ulSM_A0; //def="EVV_SM_A0" descr="Leakage coeff(Multivariant Mode)." unit="100000"/> 5526 ULONG ulSM_A1; //def="EVV_SM_A1" descr="Leakage/SCLK coeff(Multivariant Mode)." unit="1000000"/> 5527 ULONG ulSM_A2; //def="EVV_SM_A2" descr="Alpha( Greek Mode ) or VDDC/SCLK coeff(Multivariant Mode)." unit="100000"/> 5528 ULONG ulSM_A3; //def="EVV_SM_A3" descr="Beta( Greek Mode ) or SCLK coeff(Multivariant Mode)." unit="100000"/> 5529 ULONG ulSM_A4; //def="EVV_SM_A4" descr="VDDC^2/SCLK coeff(Multivariant Mode)." unit="100000"/> 5530 ULONG ulSM_A5; //def="EVV_SM_A5" descr="VDDC^2 coeff(Multivariant Mode)." unit="100000"/> 5531 ULONG ulSM_A6; //def="EVV_SM_A6" descr="Gamma( Greek Mode ) or VDDC coeff(Multivariant Mode)." unit="100000"/> 5532 ULONG ulSM_A7; //def="EVV_SM_A7" descr="Epsilon( Greek Mode ) or constant(Multivariant Mode)." unit="100000"/> 5533 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/> 5534 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/> 5535 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/> 5536 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/> 5537 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/> 5538 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/> 5539 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/> 5540 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/> 5541 ULONG ulMargin_RO_a; //def="EVV_MARGIN_RO_A" descr="A Term to represent RO equation in Ax2+Bx+C, unit=1" 5542 ULONG ulMargin_RO_b; //def="EVV_MARGIN_RO_B" descr="B Term to represent RO equation in Ax2+Bx+C, unit=1" 5543 ULONG ulMargin_RO_c; //def="EVV_MARGIN_RO_C" descr="C Term to represent RO equation in Ax2+Bx+C, unit=1" 5544 ULONG ulMargin_fixed; //def="EVV_MARGIN_FIXED" descr="Fixed MHz to add to SCLK margin, unit=1" unit="1"/> 5545 ULONG ulMargin_Fmax_mean; //def="EVV_MARGIN_FMAX_MEAN" descr="Percentage to add for Fmas mean margin unit=10000" unit="10000"/> 5546 ULONG ulMargin_plat_mean; //def="EVV_MARGIN_PLAT_MEAN" descr="Percentage to add for platform mean margin unit=10000" unit="10000"/> 5547 ULONG ulMargin_Fmax_sigma; //def="EVV_MARGIN_FMAX_SIGMA" descr="Percentage to add for Fmax sigma margin unit=10000" unit="10000"/> 5548 ULONG ulMargin_plat_sigma; //def="EVV_MARGIN_PLAT_SIGMA" descr="Percentage to add for platform sigma margin unit=10000" unit="10000"/> 5549 ULONG ulMargin_DC_sigma; //def="EVV_MARGIN_DC_SIGMA" descr="Regulator DC tolerance margin (mV) unit=100" unit="100"/> 5550 ULONG ulReserved[12]; 5551 }ATOM_ASIC_PROFILING_INFO_V3_5; 5552 5553 /* for Polars10/11 AVFS parameters */ 5554 typedef struct _ATOM_ASIC_PROFILING_INFO_V3_6 5555 { 5556 ATOM_COMMON_TABLE_HEADER asHeader; 5557 ULONG ulMaxVddc; 5558 ULONG ulMinVddc; 5559 USHORT usLkgEuseIndex; 5560 UCHAR ucLkgEfuseBitLSB; 5561 UCHAR ucLkgEfuseLength; 5562 ULONG ulLkgEncodeLn_MaxDivMin; 5563 ULONG ulLkgEncodeMax; 5564 ULONG ulLkgEncodeMin; 5565 EFUSE_LINEAR_FUNC_PARAM sRoFuse; 5566 ULONG ulEvvDefaultVddc; 5567 ULONG ulEvvNoCalcVddc; 5568 ULONG ulSpeed_Model; 5569 ULONG ulSM_A0; 5570 ULONG ulSM_A1; 5571 ULONG ulSM_A2; 5572 ULONG ulSM_A3; 5573 ULONG ulSM_A4; 5574 ULONG ulSM_A5; 5575 ULONG ulSM_A6; 5576 ULONG ulSM_A7; 5577 UCHAR ucSM_A0_sign; 5578 UCHAR ucSM_A1_sign; 5579 UCHAR ucSM_A2_sign; 5580 UCHAR ucSM_A3_sign; 5581 UCHAR ucSM_A4_sign; 5582 UCHAR ucSM_A5_sign; 5583 UCHAR ucSM_A6_sign; 5584 UCHAR ucSM_A7_sign; 5585 ULONG ulMargin_RO_a; 5586 ULONG ulMargin_RO_b; 5587 ULONG ulMargin_RO_c; 5588 ULONG ulMargin_fixed; 5589 ULONG ulMargin_Fmax_mean; 5590 ULONG ulMargin_plat_mean; 5591 ULONG ulMargin_Fmax_sigma; 5592 ULONG ulMargin_plat_sigma; 5593 ULONG ulMargin_DC_sigma; 5594 ULONG ulLoadLineSlop; 5595 ULONG ulaTDClimitPerDPM[8]; 5596 ULONG ulaNoCalcVddcPerDPM[8]; 5597 ULONG ulAVFS_meanNsigma_Acontant0; 5598 ULONG ulAVFS_meanNsigma_Acontant1; 5599 ULONG ulAVFS_meanNsigma_Acontant2; 5600 USHORT usAVFS_meanNsigma_DC_tol_sigma; 5601 USHORT usAVFS_meanNsigma_Platform_mean; 5602 USHORT usAVFS_meanNsigma_Platform_sigma; 5603 ULONG ulGB_VDROOP_TABLE_CKSOFF_a0; 5604 ULONG ulGB_VDROOP_TABLE_CKSOFF_a1; 5605 ULONG ulGB_VDROOP_TABLE_CKSOFF_a2; 5606 ULONG ulGB_VDROOP_TABLE_CKSON_a0; 5607 ULONG ulGB_VDROOP_TABLE_CKSON_a1; 5608 ULONG ulGB_VDROOP_TABLE_CKSON_a2; 5609 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_m1; 5610 USHORT usAVFSGB_FUSE_TABLE_CKSOFF_m2; 5611 ULONG ulAVFSGB_FUSE_TABLE_CKSOFF_b; 5612 ULONG ulAVFSGB_FUSE_TABLE_CKSON_m1; 5613 USHORT usAVFSGB_FUSE_TABLE_CKSON_m2; 5614 ULONG ulAVFSGB_FUSE_TABLE_CKSON_b; 5615 USHORT usMaxVoltage_0_25mv; 5616 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF; 5617 UCHAR ucEnableGB_VDROOP_TABLE_CKSON; 5618 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF; 5619 UCHAR ucEnableGB_FUSE_TABLE_CKSON; 5620 USHORT usPSM_Age_ComFactor; 5621 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage; 5622 UCHAR ucReserved; 5623 }ATOM_ASIC_PROFILING_INFO_V3_6; 5624 5625 5626 typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ 5627 ULONG ulMaxSclkFreq; 5628 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz 5629 UCHAR ucPostdiv; // divide by 2^n 5630 USHORT ucFcw_pcc; 5631 USHORT ucFcw_trans_upper; 5632 USHORT ucRcw_trans_lower; 5633 }ATOM_SCLK_FCW_RANGE_ENTRY_V1; 5634 5635 5636 // SMU_InfoTable for Polaris10/Polaris11 5637 typedef struct _ATOM_SMU_INFO_V2_1 5638 { 5639 ATOM_COMMON_TABLE_HEADER asHeader; 5640 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1 5641 UCHAR ucReserved[3]; 5642 ATOM_SCLK_FCW_RANGE_ENTRY_V1 asSclkFcwRangeEntry[8]; 5643 }ATOM_SMU_INFO_V2_1; 5644 5645 5646 // GFX_InfoTable for Polaris10/Polaris11 5647 typedef struct _ATOM_GFX_INFO_V2_1 5648 { 5649 ATOM_COMMON_TABLE_HEADER asHeader; 5650 UCHAR GfxIpMinVer; 5651 UCHAR GfxIpMajVer; 5652 UCHAR max_shader_engines; 5653 UCHAR max_tile_pipes; 5654 UCHAR max_cu_per_sh; 5655 UCHAR max_sh_per_se; 5656 UCHAR max_backends_per_se; 5657 UCHAR max_texture_channel_caches; 5658 }ATOM_GFX_INFO_V2_1; 5659 5660 5661 typedef struct _ATOM_POWER_SOURCE_OBJECT 5662 { 5663 UCHAR ucPwrSrcId; // Power source 5664 UCHAR ucPwrSensorType; // GPIO, I2C or none 5665 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id 5666 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect 5667 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect 5668 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect 5669 UCHAR ucPwrSensActiveState; // high active or low active 5670 UCHAR ucReserve[3]; // reserve 5671 USHORT usSensPwr; // in unit of watt 5672 }ATOM_POWER_SOURCE_OBJECT; 5673 5674 typedef struct _ATOM_POWER_SOURCE_INFO 5675 { 5676 ATOM_COMMON_TABLE_HEADER asHeader; 5677 UCHAR asPwrbehave[16]; 5678 ATOM_POWER_SOURCE_OBJECT asPwrObj[1]; 5679 }ATOM_POWER_SOURCE_INFO; 5680 5681 5682 //Define ucPwrSrcId 5683 #define POWERSOURCE_PCIE_ID1 0x00 5684 #define POWERSOURCE_6PIN_CONNECTOR_ID1 0x01 5685 #define POWERSOURCE_8PIN_CONNECTOR_ID1 0x02 5686 #define POWERSOURCE_6PIN_CONNECTOR_ID2 0x04 5687 #define POWERSOURCE_8PIN_CONNECTOR_ID2 0x08 5688 5689 //define ucPwrSensorId 5690 #define POWER_SENSOR_ALWAYS 0x00 5691 #define POWER_SENSOR_GPIO 0x01 5692 #define POWER_SENSOR_I2C 0x02 5693 5694 typedef struct _ATOM_CLK_VOLT_CAPABILITY 5695 { 5696 ULONG ulVoltageIndex; // The Voltage Index indicated by FUSE, same voltage index shared with SCLK DPM fuse table 5697 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5698 }ATOM_CLK_VOLT_CAPABILITY; 5699 5700 5701 typedef struct _ATOM_CLK_VOLT_CAPABILITY_V2 5702 { 5703 USHORT usVoltageLevel; // The real Voltage Level round up value in unit of mv, 5704 ULONG ulMaximumSupportedCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5705 }ATOM_CLK_VOLT_CAPABILITY_V2; 5706 5707 typedef struct _ATOM_AVAILABLE_SCLK_LIST 5708 { 5709 ULONG ulSupportedSCLK; // Maximum clock supported with specified voltage index, unit in 10kHz 5710 USHORT usVoltageIndex; // The Voltage Index indicated by FUSE for specified SCLK 5711 USHORT usVoltageID; // The Voltage ID indicated by FUSE for specified SCLK 5712 }ATOM_AVAILABLE_SCLK_LIST; 5713 5714 // ATOM_INTEGRATED_SYSTEM_INFO_V6 ulSystemConfig cap definition 5715 #define ATOM_IGP_INFO_V6_SYSTEM_CONFIG__PCIE_POWER_GATING_ENABLE 1 // refer to ulSystemConfig bit[0] 5716 5717 // this IntegrateSystemInfoTable is used for Liano/Ontario APU 5718 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 5719 { 5720 ATOM_COMMON_TABLE_HEADER sHeader; 5721 ULONG ulBootUpEngineClock; 5722 ULONG ulDentistVCOFreq; 5723 ULONG ulBootUpUMAClock; 5724 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5725 ULONG ulBootUpReqDisplayVector; 5726 ULONG ulOtherDisplayMisc; 5727 ULONG ulGPUCapInfo; 5728 ULONG ulSB_MMIO_Base_Addr; 5729 USHORT usRequestedPWMFreqInHz; 5730 UCHAR ucHtcTmpLmt; 5731 UCHAR ucHtcHystLmt; 5732 ULONG ulMinEngineClock; 5733 ULONG ulSystemConfig; 5734 ULONG ulCPUCapInfo; 5735 USHORT usNBP0Voltage; 5736 USHORT usNBP1Voltage; 5737 USHORT usBootUpNBVoltage; 5738 USHORT usExtDispConnInfoOffset; 5739 USHORT usPanelRefreshRateRange; 5740 UCHAR ucMemoryType; 5741 UCHAR ucUMAChannelNumber; 5742 ULONG ulCSR_M3_ARB_CNTL_DEFAULT[10]; 5743 ULONG ulCSR_M3_ARB_CNTL_UVD[10]; 5744 ULONG ulCSR_M3_ARB_CNTL_FS3D[10]; 5745 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5746 ULONG ulGMCRestoreResetTime; 5747 ULONG ulMinimumNClk; 5748 ULONG ulIdleNClk; 5749 ULONG ulDDR_DLL_PowerUpTime; 5750 ULONG ulDDR_PLL_PowerUpTime; 5751 USHORT usPCIEClkSSPercentage; 5752 USHORT usPCIEClkSSType; 5753 USHORT usLvdsSSPercentage; 5754 USHORT usLvdsSSpreadRateIn10Hz; 5755 USHORT usHDMISSPercentage; 5756 USHORT usHDMISSpreadRateIn10Hz; 5757 USHORT usDVISSPercentage; 5758 USHORT usDVISSpreadRateIn10Hz; 5759 ULONG SclkDpmBoostMargin; 5760 ULONG SclkDpmThrottleMargin; 5761 USHORT SclkDpmTdpLimitPG; 5762 USHORT SclkDpmTdpLimitBoost; 5763 ULONG ulBoostEngineCLock; 5764 UCHAR ulBoostVid_2bit; 5765 UCHAR EnableBoost; 5766 USHORT GnbTdpLimit; 5767 USHORT usMaxLVDSPclkFreqInSingleLink; 5768 UCHAR ucLvdsMisc; 5769 UCHAR ucLVDSReserved; 5770 ULONG ulReserved3[15]; 5771 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5772 }ATOM_INTEGRATED_SYSTEM_INFO_V6; 5773 5774 // ulGPUCapInfo 5775 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 5776 #define INTEGRATED_SYSTEM_INFO_V6_GPUCAPINFO__DISABLE_AUX_HW_MODE_DETECTION 0x08 5777 5778 //ucLVDSMisc: 5779 #define SYS_INFO_LVDSMISC__888_FPDI_MODE 0x01 5780 #define SYS_INFO_LVDSMISC__DL_CH_SWAP 0x02 5781 #define SYS_INFO_LVDSMISC__888_BPC 0x04 5782 #define SYS_INFO_LVDSMISC__OVERRIDE_EN 0x08 5783 #define SYS_INFO_LVDSMISC__BLON_ACTIVE_LOW 0x10 5784 // new since Trinity 5785 #define SYS_INFO_LVDSMISC__TRAVIS_LVDS_VOL_OVERRIDE_EN 0x20 5786 5787 // not used any more 5788 #define SYS_INFO_LVDSMISC__VSYNC_ACTIVE_LOW 0x04 5789 #define SYS_INFO_LVDSMISC__HSYNC_ACTIVE_LOW 0x08 5790 5791 /********************************************************************************************************************** 5792 ATOM_INTEGRATED_SYSTEM_INFO_V6 Description 5793 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 5794 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 5795 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 5796 sDISPCLK_Voltage: Report Display clock voltage requirement. 5797 5798 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Liano/Ontaio projects: 5799 ATOM_DEVICE_CRT1_SUPPORT 0x0001 5800 ATOM_DEVICE_CRT2_SUPPORT 0x0010 5801 ATOM_DEVICE_DFP1_SUPPORT 0x0008 5802 ATOM_DEVICE_DFP6_SUPPORT 0x0040 5803 ATOM_DEVICE_DFP2_SUPPORT 0x0080 5804 ATOM_DEVICE_DFP3_SUPPORT 0x0200 5805 ATOM_DEVICE_DFP4_SUPPORT 0x0400 5806 ATOM_DEVICE_DFP5_SUPPORT 0x0800 5807 ATOM_DEVICE_LCD1_SUPPORT 0x0002 5808 ulOtherDisplayMisc: Other display related flags, not defined yet. 5809 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 5810 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 5811 bit[3]=0: Enable HW AUX mode detection logic 5812 =1: Disable HW AUX mode dettion logic 5813 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 5814 5815 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 5816 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 5817 5818 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 5819 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 5820 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 5821 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 5822 and enabling VariBri under the driver environment from PP table is optional. 5823 5824 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 5825 that BL control from GPU is expected. 5826 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 5827 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 5828 it's per platform 5829 and enabling VariBri under the driver environment from PP table is optional. 5830 5831 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 5832 Threshold on value to enter HTC_active state. 5833 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 5834 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 5835 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 5836 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 5837 =1: PCIE Power Gating Enabled 5838 Bit[1]=0: DDR-DLL shut-down feature disabled. 5839 1: DDR-DLL shut-down feature enabled. 5840 Bit[2]=0: DDR-PLL Power down feature disabled. 5841 1: DDR-PLL Power down feature enabled. 5842 ulCPUCapInfo: TBD 5843 usNBP0Voltage: VID for voltage on NB P0 State 5844 usNBP1Voltage: VID for voltage on NB P1 State 5845 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 5846 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 5847 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 5848 to indicate a range. 5849 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 5850 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 5851 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 5852 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 5853 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 5854 ucUMAChannelNumber: System memory channel numbers. 5855 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 5856 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 5857 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 5858 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 5859 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 5860 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 5861 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 5862 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 5863 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 5864 usPCIEClkSSPercentage: PCIE Clock Spred Spectrum Percentage in unit 0.01%; 100 mean 1%. 5865 usPCIEClkSSType: PCIE Clock Spred Spectrum Type. 0 for Down spread(default); 1 for Center spread. 5866 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 5867 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5868 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5869 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5870 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 5871 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 5872 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 5873 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 5874 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 5875 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 5876 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 5877 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 5878 **********************************************************************************************************************/ 5879 5880 // this Table is used for Liano/Ontario APU 5881 typedef struct _ATOM_FUSION_SYSTEM_INFO_V1 5882 { 5883 ATOM_INTEGRATED_SYSTEM_INFO_V6 sIntegratedSysInfo; 5884 ULONG ulPowerplayTable[128]; 5885 }ATOM_FUSION_SYSTEM_INFO_V1; 5886 5887 5888 typedef struct _ATOM_TDP_CONFIG_BITS 5889 { 5890 #if ATOM_BIG_ENDIAN 5891 ULONG uReserved:2; 5892 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5893 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5894 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5895 #else 5896 ULONG uCTDP_Enable:2; // = (uCTDP_Value > uTDP_Value? 2: (uCTDP_Value < uTDP_Value)) 5897 ULONG uCTDP_Value:14; // Override value in tens of milli watts 5898 ULONG uTDP_Value:14; // Original TDP value in tens of milli watts 5899 ULONG uReserved:2; 5900 #endif 5901 }ATOM_TDP_CONFIG_BITS; 5902 5903 typedef union _ATOM_TDP_CONFIG 5904 { 5905 ATOM_TDP_CONFIG_BITS TDP_config; 5906 ULONG TDP_config_all; 5907 }ATOM_TDP_CONFIG; 5908 5909 /********************************************************************************************************************** 5910 ATOM_FUSION_SYSTEM_INFO_V1 Description 5911 sIntegratedSysInfo: refer to ATOM_INTEGRATED_SYSTEM_INFO_V6 definition. 5912 ulPowerplayTable[128]: This 512 bytes memory is used to save ATOM_PPLIB_POWERPLAYTABLE3, starting form ulPowerplayTable[0] 5913 **********************************************************************************************************************/ 5914 5915 // this IntegrateSystemInfoTable is used for Trinity APU 5916 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 5917 { 5918 ATOM_COMMON_TABLE_HEADER sHeader; 5919 ULONG ulBootUpEngineClock; 5920 ULONG ulDentistVCOFreq; 5921 ULONG ulBootUpUMAClock; 5922 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 5923 ULONG ulBootUpReqDisplayVector; 5924 ULONG ulOtherDisplayMisc; 5925 ULONG ulGPUCapInfo; 5926 ULONG ulSB_MMIO_Base_Addr; 5927 USHORT usRequestedPWMFreqInHz; 5928 UCHAR ucHtcTmpLmt; 5929 UCHAR ucHtcHystLmt; 5930 ULONG ulMinEngineClock; 5931 ULONG ulSystemConfig; 5932 ULONG ulCPUCapInfo; 5933 USHORT usNBP0Voltage; 5934 USHORT usNBP1Voltage; 5935 USHORT usBootUpNBVoltage; 5936 USHORT usExtDispConnInfoOffset; 5937 USHORT usPanelRefreshRateRange; 5938 UCHAR ucMemoryType; 5939 UCHAR ucUMAChannelNumber; 5940 UCHAR strVBIOSMsg[40]; 5941 ATOM_TDP_CONFIG asTdpConfig; 5942 ULONG ulReserved[19]; 5943 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 5944 ULONG ulGMCRestoreResetTime; 5945 ULONG ulMinimumNClk; 5946 ULONG ulIdleNClk; 5947 ULONG ulDDR_DLL_PowerUpTime; 5948 ULONG ulDDR_PLL_PowerUpTime; 5949 USHORT usPCIEClkSSPercentage; 5950 USHORT usPCIEClkSSType; 5951 USHORT usLvdsSSPercentage; 5952 USHORT usLvdsSSpreadRateIn10Hz; 5953 USHORT usHDMISSPercentage; 5954 USHORT usHDMISSpreadRateIn10Hz; 5955 USHORT usDVISSPercentage; 5956 USHORT usDVISSpreadRateIn10Hz; 5957 ULONG SclkDpmBoostMargin; 5958 ULONG SclkDpmThrottleMargin; 5959 USHORT SclkDpmTdpLimitPG; 5960 USHORT SclkDpmTdpLimitBoost; 5961 ULONG ulBoostEngineCLock; 5962 UCHAR ulBoostVid_2bit; 5963 UCHAR EnableBoost; 5964 USHORT GnbTdpLimit; 5965 USHORT usMaxLVDSPclkFreqInSingleLink; 5966 UCHAR ucLvdsMisc; 5967 UCHAR ucTravisLVDSVolAdjust; 5968 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 5969 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 5970 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 5971 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 5972 UCHAR ucLVDSOffToOnDelay_in4Ms; 5973 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 5974 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 5975 UCHAR ucMinAllowedBL_Level; 5976 ULONG ulLCDBitDepthControlVal; 5977 ULONG ulNbpStateMemclkFreq[4]; 5978 USHORT usNBP2Voltage; 5979 USHORT usNBP3Voltage; 5980 ULONG ulNbpStateNClkFreq[4]; 5981 UCHAR ucNBDPMEnable; 5982 UCHAR ucReserved[3]; 5983 UCHAR ucDPMState0VclkFid; 5984 UCHAR ucDPMState0DclkFid; 5985 UCHAR ucDPMState1VclkFid; 5986 UCHAR ucDPMState1DclkFid; 5987 UCHAR ucDPMState2VclkFid; 5988 UCHAR ucDPMState2DclkFid; 5989 UCHAR ucDPMState3VclkFid; 5990 UCHAR ucDPMState3DclkFid; 5991 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 5992 }ATOM_INTEGRATED_SYSTEM_INFO_V1_7; 5993 5994 // ulOtherDisplayMisc 5995 #define INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT 0x01 5996 #define INTEGRATED_SYSTEM_INFO__GET_BOOTUP_DISPLAY_CALLBACK_FUNC_SUPPORT 0x02 5997 #define INTEGRATED_SYSTEM_INFO__GET_EXPANSION_CALLBACK_FUNC_SUPPORT 0x04 5998 #define INTEGRATED_SYSTEM_INFO__FAST_BOOT_SUPPORT 0x08 5999 6000 // ulGPUCapInfo 6001 #define SYS_INFO_GPUCAPS__TMDSHDMI_COHERENT_SINGLEPLL_MODE 0x01 6002 #define SYS_INFO_GPUCAPS__DP_SINGLEPLL_MODE 0x02 6003 #define SYS_INFO_GPUCAPS__DISABLE_AUX_MODE_DETECT 0x08 6004 #define SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS 0x10 6005 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6006 #define SYS_INFO_GPUCAPS__GNB_FAST_RESUME_CAPABLE 0x00010000 6007 6008 //ulGPUCapInfo[17]=1 indicate battery boost feature is enable, from ML 6009 #define SYS_INFO_GPUCAPS__BATTERY_BOOST_ENABLE 0x00020000 6010 6011 /********************************************************************************************************************** 6012 ATOM_INTEGRATED_SYSTEM_INFO_V1_7 Description 6013 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6014 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6015 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6016 sDISPCLK_Voltage: Report Display clock voltage requirement. 6017 6018 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6019 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6020 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6021 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6022 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6023 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6024 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6025 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6026 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6027 ulOtherDisplayMisc: bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6028 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6029 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6030 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6031 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6032 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6033 bit[3]=0: VBIOS fast boot is disable 6034 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6035 ulGPUCapInfo: bit[0]=0: TMDS/HDMI Coherent Mode use cascade PLL mode. 6036 =1: TMDS/HDMI Coherent Mode use signel PLL mode. 6037 bit[1]=0: DP mode use cascade PLL mode ( New for Trinity ) 6038 =1: DP mode use single PLL mode 6039 bit[3]=0: Enable AUX HW mode detection logic 6040 =1: Disable AUX HW mode detection logic 6041 6042 ulSB_MMIO_Base_Addr: Physical Base address to SB MMIO space. Driver needs to initialize it for SMU usage. 6043 6044 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6045 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6046 6047 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6048 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6049 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6050 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6051 and enabling VariBri under the driver environment from PP table is optional. 6052 6053 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6054 that BL control from GPU is expected. 6055 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6056 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6057 it's per platform 6058 and enabling VariBri under the driver environment from PP table is optional. 6059 6060 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. 6061 Threshold on value to enter HTC_active state. 6062 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6063 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6064 ulMinEngineClock: Minimum SCLK allowed in 10kHz unit. This is calculated based on WRCK Fuse settings. 6065 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6066 =1: PCIE Power Gating Enabled 6067 Bit[1]=0: DDR-DLL shut-down feature disabled. 6068 1: DDR-DLL shut-down feature enabled. 6069 Bit[2]=0: DDR-PLL Power down feature disabled. 6070 1: DDR-PLL Power down feature enabled. 6071 ulCPUCapInfo: TBD 6072 usNBP0Voltage: VID for voltage on NB P0 State 6073 usNBP1Voltage: VID for voltage on NB P1 State 6074 usNBP2Voltage: VID for voltage on NB P2 State 6075 usNBP3Voltage: VID for voltage on NB P3 State 6076 usBootUpNBVoltage: Voltage Index of GNB voltage configured by SBIOS, which is suffcient to support VBIOS DISPCLK requirement. 6077 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6078 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6079 to indicate a range. 6080 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6081 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6082 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6083 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6084 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved. 6085 ucUMAChannelNumber: System memory channel numbers. 6086 ulCSR_M3_ARB_CNTL_DEFAULT[10]: Arrays with values for CSR M3 arbiter for default 6087 ulCSR_M3_ARB_CNTL_UVD[10]: Arrays with values for CSR M3 arbiter for UVD playback. 6088 ulCSR_M3_ARB_CNTL_FS3D[10]: Arrays with values for CSR M3 arbiter for Full Screen 3D applications. 6089 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6090 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6091 ulMinimumNClk: Minimum NCLK speed among all NB-Pstates to calcualte data reconnection latency. Unit in 10kHz. 6092 ulIdleNClk: NCLK speed while memory runs in self-refresh state. Unit in 10kHz. 6093 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6094 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6095 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6096 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6097 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6098 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6099 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6100 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6101 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6102 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6103 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6104 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6105 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6106 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6107 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6108 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6109 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6110 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6111 value to program Travis register LVDS_CTRL_4 6112 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6113 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6114 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6115 ucLVDSPwrOnDEtoVARY_BL_in4Ms: LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6116 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6117 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6118 6119 ucLVDSPwrOffVARY_BLtoDE_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6120 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6121 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6122 6123 ucLVDSPwrOffDEtoDIGON_in4Ms: LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6124 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6125 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6126 6127 ucLVDSOffToOnDelay_in4Ms: LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6128 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6129 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6130 6131 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6132 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6133 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6134 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6135 6136 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6137 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6138 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6139 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6140 6141 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6142 6143 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB pstate. 6144 6145 **********************************************************************************************************************/ 6146 6147 // this IntegrateSystemInfoTable is used for Kaveri & Kabini APU 6148 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 6149 { 6150 ATOM_COMMON_TABLE_HEADER sHeader; 6151 ULONG ulBootUpEngineClock; 6152 ULONG ulDentistVCOFreq; 6153 ULONG ulBootUpUMAClock; 6154 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; 6155 ULONG ulBootUpReqDisplayVector; 6156 ULONG ulVBIOSMisc; 6157 ULONG ulGPUCapInfo; 6158 ULONG ulDISP_CLK2Freq; 6159 USHORT usRequestedPWMFreqInHz; 6160 UCHAR ucHtcTmpLmt; 6161 UCHAR ucHtcHystLmt; 6162 ULONG ulReserved2; 6163 ULONG ulSystemConfig; 6164 ULONG ulCPUCapInfo; 6165 ULONG ulReserved3; 6166 USHORT usGPUReservedSysMemSize; 6167 USHORT usExtDispConnInfoOffset; 6168 USHORT usPanelRefreshRateRange; 6169 UCHAR ucMemoryType; 6170 UCHAR ucUMAChannelNumber; 6171 UCHAR strVBIOSMsg[40]; 6172 ATOM_TDP_CONFIG asTdpConfig; 6173 ULONG ulReserved[19]; 6174 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; 6175 ULONG ulGMCRestoreResetTime; 6176 ULONG ulReserved4; 6177 ULONG ulIdleNClk; 6178 ULONG ulDDR_DLL_PowerUpTime; 6179 ULONG ulDDR_PLL_PowerUpTime; 6180 USHORT usPCIEClkSSPercentage; 6181 USHORT usPCIEClkSSType; 6182 USHORT usLvdsSSPercentage; 6183 USHORT usLvdsSSpreadRateIn10Hz; 6184 USHORT usHDMISSPercentage; 6185 USHORT usHDMISSpreadRateIn10Hz; 6186 USHORT usDVISSPercentage; 6187 USHORT usDVISSpreadRateIn10Hz; 6188 ULONG ulGPUReservedSysMemBaseAddrLo; 6189 ULONG ulGPUReservedSysMemBaseAddrHi; 6190 ATOM_CLK_VOLT_CAPABILITY s5thDISPCLK_Voltage; 6191 ULONG ulReserved5; 6192 USHORT usMaxLVDSPclkFreqInSingleLink; 6193 UCHAR ucLvdsMisc; 6194 UCHAR ucTravisLVDSVolAdjust; 6195 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6196 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6197 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6198 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6199 UCHAR ucLVDSOffToOnDelay_in4Ms; 6200 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6201 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6202 UCHAR ucMinAllowedBL_Level; 6203 ULONG ulLCDBitDepthControlVal; 6204 ULONG ulNbpStateMemclkFreq[4]; 6205 ULONG ulPSPVersion; 6206 ULONG ulNbpStateNClkFreq[4]; 6207 USHORT usNBPStateVoltage[4]; 6208 USHORT usBootUpNBVoltage; 6209 USHORT usReserved2; 6210 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6211 }ATOM_INTEGRATED_SYSTEM_INFO_V1_8; 6212 6213 /********************************************************************************************************************** 6214 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 Description 6215 ulBootUpEngineClock: VBIOS bootup Engine clock frequency, in 10kHz unit. if it is equal 0, then VBIOS use pre-defined bootup engine clock 6216 ulDentistVCOFreq: Dentist VCO clock in 10kHz unit. 6217 ulBootUpUMAClock: System memory boot up clock frequency in 10Khz unit. 6218 sDISPCLK_Voltage: Report Display clock frequency requirement on GNB voltage(up to 4 voltage levels). 6219 6220 ulBootUpReqDisplayVector: VBIOS boot up display IDs, following are supported devices in Trinity projects: 6221 ATOM_DEVICE_CRT1_SUPPORT 0x0001 6222 ATOM_DEVICE_DFP1_SUPPORT 0x0008 6223 ATOM_DEVICE_DFP6_SUPPORT 0x0040 6224 ATOM_DEVICE_DFP2_SUPPORT 0x0080 6225 ATOM_DEVICE_DFP3_SUPPORT 0x0200 6226 ATOM_DEVICE_DFP4_SUPPORT 0x0400 6227 ATOM_DEVICE_DFP5_SUPPORT 0x0800 6228 ATOM_DEVICE_LCD1_SUPPORT 0x0002 6229 6230 ulVBIOSMisc: Miscellenous flags for VBIOS requirement and interface 6231 bit[0]=0: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is not supported by SBIOS. 6232 =1: INT15 callback function Get LCD EDID ( ax=4e08, bl=1b ) is supported by SBIOS. 6233 bit[1]=0: INT15 callback function Get boot display( ax=4e08, bl=01h) is not supported by SBIOS 6234 =1: INT15 callback function Get boot display( ax=4e08, bl=01h) is supported by SBIOS 6235 bit[2]=0: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is not supported by SBIOS 6236 =1: INT15 callback function Get panel Expansion ( ax=4e08, bl=02h) is supported by SBIOS 6237 bit[3]=0: VBIOS fast boot is disable 6238 =1: VBIOS fast boot is enable. ( VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open) 6239 6240 ulGPUCapInfo: bit[0~2]= Reserved 6241 bit[3]=0: Enable AUX HW mode detection logic 6242 =1: Disable AUX HW mode detection logic 6243 bit[4]=0: Disable DFS bypass feature 6244 =1: Enable DFS bypass feature 6245 6246 usRequestedPWMFreqInHz: When it's set to 0x0 by SBIOS: the LCD BackLight is not controlled by GPU(SW). 6247 Any attempt to change BL using VBIOS function or enable VariBri from PP table is not effective since ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==0; 6248 6249 When it's set to a non-zero frequency, the BackLight is controlled by GPU (SW) in one of two ways below: 6250 1. SW uses the GPU BL PWM output to control the BL, in chis case, this non-zero frequency determines what freq GPU should use; 6251 VBIOS will set up proper PWM frequency and ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1,as the result, 6252 Changing BL using VBIOS function is functional in both driver and non-driver present environment; 6253 and enabling VariBri under the driver environment from PP table is optional. 6254 6255 2. SW uses other means to control BL (like DPCD),this non-zero frequency serves as a flag only indicating 6256 that BL control from GPU is expected. 6257 VBIOS will NOT set up PWM frequency but make ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU==1 6258 Changing BL using VBIOS function could be functional in both driver and non-driver present environment,but 6259 it's per platform 6260 and enabling VariBri under the driver environment from PP table is optional. 6261 6262 ucHtcTmpLmt: Refer to D18F3x64 bit[22:16], HtcTmpLmt. Threshold on value to enter HTC_active state. 6263 ucHtcHystLmt: Refer to D18F3x64 bit[27:24], HtcHystLmt. 6264 To calculate threshold off value to exit HTC_active state, which is Threshold on vlaue minus ucHtcHystLmt. 6265 6266 ulSystemConfig: Bit[0]=0: PCIE Power Gating Disabled 6267 =1: PCIE Power Gating Enabled 6268 Bit[1]=0: DDR-DLL shut-down feature disabled. 6269 1: DDR-DLL shut-down feature enabled. 6270 Bit[2]=0: DDR-PLL Power down feature disabled. 6271 1: DDR-PLL Power down feature enabled. 6272 Bit[3]=0: GNB DPM is disabled 6273 =1: GNB DPM is enabled 6274 ulCPUCapInfo: TBD 6275 6276 usExtDispConnInfoOffset: Offset to sExtDispConnInfo inside the structure 6277 usPanelRefreshRateRange: Bit vector for LCD supported refresh rate range. If DRR is requestd by the platform, at least two bits need to be set 6278 to indicate a range. 6279 SUPPORTED_LCD_REFRESHRATE_30Hz 0x0004 6280 SUPPORTED_LCD_REFRESHRATE_40Hz 0x0008 6281 SUPPORTED_LCD_REFRESHRATE_50Hz 0x0010 6282 SUPPORTED_LCD_REFRESHRATE_60Hz 0x0020 6283 6284 ucMemoryType: [3:0]=1:DDR1;=2:DDR2;=3:DDR3;=5:GDDR5; [7:4] is reserved. 6285 ucUMAChannelNumber: System memory channel numbers. 6286 6287 strVBIOSMsg[40]: VBIOS boot up customized message string 6288 6289 sAvail_SCLK[5]: Arrays to provide availabe list of SLCK and corresponding voltage, order from low to high 6290 6291 ulGMCRestoreResetTime: GMC power restore and GMC reset time to calculate data reconnection latency. Unit in ns. 6292 ulIdleNClk: NCLK speed while memory runs in self-refresh state, used to calculate self-refresh latency. Unit in 10kHz. 6293 ulDDR_DLL_PowerUpTime: DDR PHY DLL power up time. Unit in ns. 6294 ulDDR_PLL_PowerUpTime: DDR PHY PLL power up time. Unit in ns. 6295 6296 usPCIEClkSSPercentage: PCIE Clock Spread Spectrum Percentage in unit 0.01%; 100 mean 1%. 6297 usPCIEClkSSType: PCIE Clock Spread Spectrum Type. 0 for Down spread(default); 1 for Center spread. 6298 usLvdsSSPercentage: LVDS panel ( not include eDP ) Spread Spectrum Percentage in unit of 0.01%, =0, use VBIOS default setting. 6299 usLvdsSSpreadRateIn10Hz: LVDS panel ( not include eDP ) Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6300 usHDMISSPercentage: HDMI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6301 usHDMISSpreadRateIn10Hz: HDMI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6302 usDVISSPercentage: DVI Spread Spectrum Percentage in unit 0.01%; 100 mean 1%, =0, use VBIOS default setting. 6303 usDVISSpreadRateIn10Hz: DVI Spread Spectrum frequency in unit of 10Hz, =0, use VBIOS default setting. 6304 6305 usGPUReservedSysMemSize: Reserved system memory size for ACP engine in APU GNB, units in MB. 0/2/4MB based on CMOS options, current default could be 0MB. KV only, not on KB. 6306 ulGPUReservedSysMemBaseAddrLo: Low 32 bits base address to the reserved system memory. 6307 ulGPUReservedSysMemBaseAddrHi: High 32 bits base address to the reserved system memory. 6308 6309 usMaxLVDSPclkFreqInSingleLink: Max pixel clock LVDS panel single link, if=0 means VBIOS use default threhold, right now it is 85Mhz 6310 ucLVDSMisc: [bit0] LVDS 888bit panel mode =0: LVDS 888 panel in LDI mode, =1: LVDS 888 panel in FPDI mode 6311 [bit1] LVDS panel lower and upper link mapping =0: lower link and upper link not swap, =1: lower link and upper link are swapped 6312 [bit2] LVDS 888bit per color mode =0: 666 bit per color =1:888 bit per color 6313 [bit3] LVDS parameter override enable =0: ucLvdsMisc parameter are not used =1: ucLvdsMisc parameter should be used 6314 [bit4] Polarity of signal sent to digital BLON output pin. =0: not inverted(active high) =1: inverted ( active low ) 6315 [bit5] Travid LVDS output voltage override enable, when =1, use ucTravisLVDSVolAdjust value to overwrite Traivs register LVDS_CTRL_4 6316 ucTravisLVDSVolAdjust When ucLVDSMisc[5]=1,it means platform SBIOS want to overwrite TravisLVDSVoltage. Then VBIOS will use ucTravisLVDSVolAdjust 6317 value to program Travis register LVDS_CTRL_4 6318 ucLVDSPwrOnSeqDIGONtoDE_in4Ms: 6319 LVDS power up sequence time in unit of 4ms, time delay from DIGON signal active to data enable signal active( DE ). 6320 =0 mean use VBIOS default which is 8 ( 32ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6321 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6322 ucLVDSPwrOnDEtoVARY_BL_in4Ms: 6323 LVDS power up sequence time in unit of 4ms., time delay from DE( data enable ) active to Vary Brightness enable signal active( VARY_BL ). 6324 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power up sequence is as following: DIGON->DE->VARY_BL->BLON. 6325 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6326 ucLVDSPwrOffVARY_BLtoDE_in4Ms: 6327 LVDS power down sequence time in unit of 4ms, time delay from data enable ( DE ) signal off to LCDVCC (DIGON) off. 6328 =0 mean use VBIOS default delay which is 8 ( 32ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6329 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6330 ucLVDSPwrOffDEtoDIGON_in4Ms: 6331 LVDS power down sequence time in unit of 4ms, time delay from vary brightness enable signal( VARY_BL) off to data enable ( DE ) signal off. 6332 =0 mean use VBIOS default which is 90 ( 360ms ). The LVDS power down sequence is as following: BLON->VARY_BL->DE->DIGON 6333 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6334 ucLVDSOffToOnDelay_in4Ms: 6335 LVDS power down sequence time in unit of 4ms. Time delay from DIGON signal off to DIGON signal active. 6336 =0 means to use VBIOS default delay which is 125 ( 500ms ). 6337 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6338 ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms: 6339 LVDS power up sequence time in unit of 4ms. Time delay from VARY_BL signal on to DLON signal active. 6340 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6341 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6342 6343 ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms: 6344 LVDS power down sequence time in unit of 4ms. Time delay from BLON signal off to VARY_BL signal off. 6345 =0 means to use VBIOS default delay which is 0 ( 0ms ). 6346 This parameter is used by VBIOS only. VBIOS will patch LVDS_InfoTable. 6347 ucMinAllowedBL_Level: Lowest LCD backlight PWM level. This is customer platform specific parameters. By default it is 0. 6348 6349 ulLCDBitDepthControlVal: GPU display control encoder bit dither control setting, used to program register mmFMT_BIT_DEPTH_CONTROL 6350 6351 ulNbpStateMemclkFreq[4]: system memory clock frequncey in unit of 10Khz in different NB P-State(P0, P1, P2 & P3). 6352 ulNbpStateNClkFreq[4]: NB P-State NClk frequency in different NB P-State 6353 usNBPStateVoltage[4]: NB P-State (P0/P1 & P2/P3) voltage; NBP3 refers to lowes voltage 6354 usBootUpNBVoltage: NB P-State voltage during boot up before driver loaded 6355 sExtDispConnInfo: Display connector information table provided to VBIOS 6356 6357 **********************************************************************************************************************/ 6358 6359 typedef struct _ATOM_I2C_REG_INFO 6360 { 6361 UCHAR ucI2cRegIndex; 6362 UCHAR ucI2cRegVal; 6363 }ATOM_I2C_REG_INFO; 6364 6365 // this IntegrateSystemInfoTable is used for Carrizo 6366 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_9 6367 { 6368 ATOM_COMMON_TABLE_HEADER sHeader; 6369 ULONG ulBootUpEngineClock; 6370 ULONG ulDentistVCOFreq; 6371 ULONG ulBootUpUMAClock; 6372 ATOM_CLK_VOLT_CAPABILITY sDISPCLK_Voltage[4]; // no longer used, keep it as is to avoid driver compiling error 6373 ULONG ulBootUpReqDisplayVector; 6374 ULONG ulVBIOSMisc; 6375 ULONG ulGPUCapInfo; 6376 ULONG ulDISP_CLK2Freq; 6377 USHORT usRequestedPWMFreqInHz; 6378 UCHAR ucHtcTmpLmt; 6379 UCHAR ucHtcHystLmt; 6380 ULONG ulReserved2; 6381 ULONG ulSystemConfig; 6382 ULONG ulCPUCapInfo; 6383 ULONG ulReserved3; 6384 USHORT usGPUReservedSysMemSize; 6385 USHORT usExtDispConnInfoOffset; 6386 USHORT usPanelRefreshRateRange; 6387 UCHAR ucMemoryType; 6388 UCHAR ucUMAChannelNumber; 6389 UCHAR strVBIOSMsg[40]; 6390 ATOM_TDP_CONFIG asTdpConfig; 6391 UCHAR ucExtHDMIReDrvSlvAddr; 6392 UCHAR ucExtHDMIReDrvRegNum; 6393 ATOM_I2C_REG_INFO asExtHDMIRegSetting[9]; 6394 ULONG ulReserved[2]; 6395 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6396 ATOM_AVAILABLE_SCLK_LIST sAvail_SCLK[5]; // no longer used, keep it as is to avoid driver compiling error 6397 ULONG ulGMCRestoreResetTime; 6398 ULONG ulReserved4; 6399 ULONG ulIdleNClk; 6400 ULONG ulDDR_DLL_PowerUpTime; 6401 ULONG ulDDR_PLL_PowerUpTime; 6402 USHORT usPCIEClkSSPercentage; 6403 USHORT usPCIEClkSSType; 6404 USHORT usLvdsSSPercentage; 6405 USHORT usLvdsSSpreadRateIn10Hz; 6406 USHORT usHDMISSPercentage; 6407 USHORT usHDMISSpreadRateIn10Hz; 6408 USHORT usDVISSPercentage; 6409 USHORT usDVISSpreadRateIn10Hz; 6410 ULONG ulGPUReservedSysMemBaseAddrLo; 6411 ULONG ulGPUReservedSysMemBaseAddrHi; 6412 ULONG ulReserved5[3]; 6413 USHORT usMaxLVDSPclkFreqInSingleLink; 6414 UCHAR ucLvdsMisc; 6415 UCHAR ucTravisLVDSVolAdjust; 6416 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6417 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6418 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6419 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6420 UCHAR ucLVDSOffToOnDelay_in4Ms; 6421 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6422 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6423 UCHAR ucMinAllowedBL_Level; 6424 ULONG ulLCDBitDepthControlVal; 6425 ULONG ulNbpStateMemclkFreq[4]; // only 2 level is changed. 6426 ULONG ulPSPVersion; 6427 ULONG ulNbpStateNClkFreq[4]; 6428 USHORT usNBPStateVoltage[4]; 6429 USHORT usBootUpNBVoltage; 6430 UCHAR ucEDPv1_4VSMode; 6431 UCHAR ucReserved2; 6432 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6433 }ATOM_INTEGRATED_SYSTEM_INFO_V1_9; 6434 6435 6436 // definition for ucEDPv1_4VSMode 6437 #define EDP_VS_LEGACY_MODE 0 6438 #define EDP_VS_LOW_VDIFF_MODE 1 6439 #define EDP_VS_HIGH_VDIFF_MODE 2 6440 #define EDP_VS_STRETCH_MODE 3 6441 #define EDP_VS_SINGLE_VDIFF_MODE 4 6442 #define EDP_VS_VARIABLE_PREM_MODE 5 6443 6444 6445 // ulGPUCapInfo 6446 #define SYS_INFO_V1_9_GPUCAPSINFO_DISABLE_AUX_MODE_DETECT 0x08 6447 #define SYS_INFO_V1_9_GPUCAPSINFO_ENABEL_DFS_BYPASS 0x10 6448 //ulGPUCapInfo[16]=1 indicate SMC firmware is able to support GNB fast resume function, so that driver can call SMC to program most of GNB register during resuming, from ML 6449 #define SYS_INFO_V1_9_GPUCAPSINFO_GNB_FAST_RESUME_CAPABLE 0x00010000 6450 //ulGPUCapInfo[18]=1 indicate the IOMMU is not available 6451 #define SYS_INFO_V1_9_GPUCAPINFO_IOMMU_DISABLE 0x00040000 6452 //ulGPUCapInfo[19]=1 indicate the MARC Aperture is opened. 6453 #define SYS_INFO_V1_9_GPUCAPINFO_MARC_APERTURE_ENABLE 0x00080000 6454 6455 6456 typedef struct _DPHY_TIMING_PARA 6457 { 6458 UCHAR ucProfileID; // SENSOR_PROFILES 6459 ULONG ucPara; 6460 } DPHY_TIMING_PARA; 6461 6462 typedef struct _DPHY_ELEC_PARA 6463 { 6464 USHORT usPara[3]; 6465 } DPHY_ELEC_PARA; 6466 6467 typedef struct _CAMERA_MODULE_INFO 6468 { 6469 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user 6470 UCHAR strModuleName[8]; 6471 DPHY_TIMING_PARA asTimingPara[6]; // Exact number is under estimation and confirmation from sensor vendor 6472 } CAMERA_MODULE_INFO; 6473 6474 typedef struct _FLASHLIGHT_INFO 6475 { 6476 UCHAR ucID; // 0: Rear, 1: Front 6477 UCHAR strName[8]; 6478 } FLASHLIGHT_INFO; 6479 6480 typedef struct _CAMERA_DATA 6481 { 6482 ULONG ulVersionCode; 6483 CAMERA_MODULE_INFO asCameraInfo[3]; // Assuming 3 camera sensors max 6484 FLASHLIGHT_INFO asFlashInfo; // Assuming 1 flashlight max 6485 DPHY_ELEC_PARA asDphyElecPara; 6486 ULONG ulCrcVal; // CRC 6487 }CAMERA_DATA; 6488 6489 typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_10 6490 { 6491 ATOM_COMMON_TABLE_HEADER sHeader; 6492 ULONG ulBootUpEngineClock; 6493 ULONG ulDentistVCOFreq; 6494 ULONG ulBootUpUMAClock; 6495 ULONG ulReserved0[8]; 6496 ULONG ulBootUpReqDisplayVector; 6497 ULONG ulVBIOSMisc; 6498 ULONG ulGPUCapInfo; 6499 ULONG ulReserved1; 6500 USHORT usRequestedPWMFreqInHz; 6501 UCHAR ucHtcTmpLmt; 6502 UCHAR ucHtcHystLmt; 6503 ULONG ulReserved2; 6504 ULONG ulSystemConfig; 6505 ULONG ulCPUCapInfo; 6506 ULONG ulReserved3; 6507 USHORT usGPUReservedSysMemSize; 6508 USHORT usExtDispConnInfoOffset; 6509 USHORT usPanelRefreshRateRange; 6510 UCHAR ucMemoryType; 6511 UCHAR ucUMAChannelNumber; 6512 ULONG ulMsgReserved[10]; 6513 ATOM_TDP_CONFIG asTdpConfig; 6514 ULONG ulReserved[7]; 6515 ATOM_CLK_VOLT_CAPABILITY_V2 sDispClkVoltageMapping[8]; 6516 ULONG ulReserved6[10]; 6517 ULONG ulGMCRestoreResetTime; 6518 ULONG ulReserved4; 6519 ULONG ulIdleNClk; 6520 ULONG ulDDR_DLL_PowerUpTime; 6521 ULONG ulDDR_PLL_PowerUpTime; 6522 USHORT usPCIEClkSSPercentage; 6523 USHORT usPCIEClkSSType; 6524 USHORT usLvdsSSPercentage; 6525 USHORT usLvdsSSpreadRateIn10Hz; 6526 USHORT usHDMISSPercentage; 6527 USHORT usHDMISSpreadRateIn10Hz; 6528 USHORT usDVISSPercentage; 6529 USHORT usDVISSpreadRateIn10Hz; 6530 ULONG ulGPUReservedSysMemBaseAddrLo; 6531 ULONG ulGPUReservedSysMemBaseAddrHi; 6532 ULONG ulReserved5[3]; 6533 USHORT usMaxLVDSPclkFreqInSingleLink; 6534 UCHAR ucLvdsMisc; 6535 UCHAR ucTravisLVDSVolAdjust; 6536 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms; 6537 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms; 6538 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms; 6539 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms; 6540 UCHAR ucLVDSOffToOnDelay_in4Ms; 6541 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms; 6542 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms; 6543 UCHAR ucMinAllowedBL_Level; 6544 ULONG ulLCDBitDepthControlVal; 6545 ULONG ulNbpStateMemclkFreq[2]; 6546 ULONG ulReserved7[2]; 6547 ULONG ulPSPVersion; 6548 ULONG ulNbpStateNClkFreq[4]; 6549 USHORT usNBPStateVoltage[4]; 6550 USHORT usBootUpNBVoltage; 6551 UCHAR ucEDPv1_4VSMode; 6552 UCHAR ucReserved2; 6553 ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO sExtDispConnInfo; 6554 CAMERA_DATA asCameraInfo; 6555 ULONG ulReserved8[29]; 6556 }ATOM_INTEGRATED_SYSTEM_INFO_V1_10; 6557 6558 6559 // this Table is used for Kaveri/Kabini APU 6560 typedef struct _ATOM_FUSION_SYSTEM_INFO_V2 6561 { 6562 ATOM_INTEGRATED_SYSTEM_INFO_V1_8 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6563 ULONG ulPowerplayTable[128]; // Update comments here to link new powerplay table definition structure 6564 }ATOM_FUSION_SYSTEM_INFO_V2; 6565 6566 6567 typedef struct _ATOM_FUSION_SYSTEM_INFO_V3 6568 { 6569 ATOM_INTEGRATED_SYSTEM_INFO_V1_10 sIntegratedSysInfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 6570 ULONG ulPowerplayTable[192]; // Reserve 768 bytes space for PowerPlayInfoTable 6571 }ATOM_FUSION_SYSTEM_INFO_V3; 6572 6573 #define FUSION_V3_OFFSET_FROM_TOP_OF_FB 0x800 6574 6575 /**************************************************************************/ 6576 // This portion is only used when ext thermal chip or engine/memory clock SS chip is populated on a design 6577 //Memory SS Info Table 6578 //Define Memory Clock SS chip ID 6579 #define ICS91719 1 6580 #define ICS91720 2 6581 6582 //Define one structure to inform SW a "block of data" writing to external SS chip via I2C protocol 6583 typedef struct _ATOM_I2C_DATA_RECORD 6584 { 6585 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop" 6586 UCHAR ucI2CData[1]; //I2C data in bytes, should be less than 16 bytes usually 6587 }ATOM_I2C_DATA_RECORD; 6588 6589 6590 //Define one structure to inform SW how many blocks of data writing to external SS chip via I2C protocol, in addition to other information 6591 typedef struct _ATOM_I2C_DEVICE_SETUP_INFO 6592 { 6593 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //I2C line and HW/SW assisted cap. 6594 UCHAR ucSSChipID; //SS chip being used 6595 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip 6596 UCHAR ucNumOfI2CDataRecords; //number of data block 6597 ATOM_I2C_DATA_RECORD asI2CData[1]; 6598 }ATOM_I2C_DEVICE_SETUP_INFO; 6599 6600 //========================================================================================== 6601 typedef struct _ATOM_ASIC_MVDD_INFO 6602 { 6603 ATOM_COMMON_TABLE_HEADER sHeader; 6604 ATOM_I2C_DEVICE_SETUP_INFO asI2CSetup[1]; 6605 }ATOM_ASIC_MVDD_INFO; 6606 6607 //========================================================================================== 6608 #define ATOM_MCLK_SS_INFO ATOM_ASIC_MVDD_INFO 6609 6610 //========================================================================================== 6611 /**************************************************************************/ 6612 6613 typedef struct _ATOM_ASIC_SS_ASSIGNMENT 6614 { 6615 ULONG ulTargetClockRange; //Clock Out frequence (VCO ), in unit of 10Khz 6616 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6617 USHORT usSpreadRateInKhz; //in unit of kHz, modulation freq 6618 UCHAR ucClockIndication; //Indicate which clock source needs SS 6619 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread. 6620 UCHAR ucReserved[2]; 6621 }ATOM_ASIC_SS_ASSIGNMENT; 6622 6623 //Define ucClockIndication, SW uses the IDs below to search if the SS is requried/enabled on a clock branch/signal type. 6624 //SS is not required or enabled if a match is not found. 6625 #define ASIC_INTERNAL_MEMORY_SS 1 6626 #define ASIC_INTERNAL_ENGINE_SS 2 6627 #define ASIC_INTERNAL_UVD_SS 3 6628 #define ASIC_INTERNAL_SS_ON_TMDS 4 6629 #define ASIC_INTERNAL_SS_ON_HDMI 5 6630 #define ASIC_INTERNAL_SS_ON_LVDS 6 6631 #define ASIC_INTERNAL_SS_ON_DP 7 6632 #define ASIC_INTERNAL_SS_ON_DCPLL 8 6633 #define ASIC_EXTERNAL_SS_ON_DP_CLOCK 9 6634 #define ASIC_INTERNAL_VCE_SS 10 6635 #define ASIC_INTERNAL_GPUPLL_SS 11 6636 6637 6638 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V2 6639 { 6640 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6641 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6642 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% 6643 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6644 UCHAR ucClockIndication; //Indicate which clock source needs SS 6645 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6646 UCHAR ucReserved[2]; 6647 }ATOM_ASIC_SS_ASSIGNMENT_V2; 6648 6649 //ucSpreadSpectrumMode 6650 //#define ATOM_SS_DOWN_SPREAD_MODE_MASK 0x00000000 6651 //#define ATOM_SS_DOWN_SPREAD_MODE 0x00000000 6652 //#define ATOM_SS_CENTRE_SPREAD_MODE_MASK 0x00000001 6653 //#define ATOM_SS_CENTRE_SPREAD_MODE 0x00000001 6654 //#define ATOM_INTERNAL_SS_MASK 0x00000000 6655 //#define ATOM_EXTERNAL_SS_MASK 0x00000002 6656 6657 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO 6658 { 6659 ATOM_COMMON_TABLE_HEADER sHeader; 6660 ATOM_ASIC_SS_ASSIGNMENT asSpreadSpectrum[4]; 6661 }ATOM_ASIC_INTERNAL_SS_INFO; 6662 6663 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 6664 { 6665 ATOM_COMMON_TABLE_HEADER sHeader; 6666 ATOM_ASIC_SS_ASSIGNMENT_V2 asSpreadSpectrum[1]; //this is point only. 6667 }ATOM_ASIC_INTERNAL_SS_INFO_V2; 6668 6669 typedef struct _ATOM_ASIC_SS_ASSIGNMENT_V3 6670 { 6671 ULONG ulTargetClockRange; //For mem/engine/uvd, Clock Out frequence (VCO ), in unit of 10Khz 6672 //For TMDS/HDMI/LVDS, it is pixel clock , for DP, it is link clock ( 27000 or 16200 ) 6673 USHORT usSpreadSpectrumPercentage; //in unit of 0.01% or 0.001%, decided by ucSpreadSpectrumMode bit4 6674 USHORT usSpreadRateIn10Hz; //in unit of 10Hz, modulation freq 6675 UCHAR ucClockIndication; //Indicate which clock source needs SS 6676 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS 6677 UCHAR ucReserved[2]; 6678 }ATOM_ASIC_SS_ASSIGNMENT_V3; 6679 6680 //ATOM_ASIC_SS_ASSIGNMENT_V3.ucSpreadSpectrumMode 6681 #define SS_MODE_V3_CENTRE_SPREAD_MASK 0x01 6682 #define SS_MODE_V3_EXTERNAL_SS_MASK 0x02 6683 #define SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK 0x10 6684 6685 typedef struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 6686 { 6687 ATOM_COMMON_TABLE_HEADER sHeader; 6688 ATOM_ASIC_SS_ASSIGNMENT_V3 asSpreadSpectrum[1]; //this is pointer only. 6689 }ATOM_ASIC_INTERNAL_SS_INFO_V3; 6690 6691 6692 //==============================Scratch Pad Definition Portion=============================== 6693 #define ATOM_DEVICE_CONNECT_INFO_DEF 0 6694 #define ATOM_ROM_LOCATION_DEF 1 6695 #define ATOM_TV_STANDARD_DEF 2 6696 #define ATOM_ACTIVE_INFO_DEF 3 6697 #define ATOM_LCD_INFO_DEF 4 6698 #define ATOM_DOS_REQ_INFO_DEF 5 6699 #define ATOM_ACC_CHANGE_INFO_DEF 6 6700 #define ATOM_DOS_MODE_INFO_DEF 7 6701 #define ATOM_I2C_CHANNEL_STATUS_DEF 8 6702 #define ATOM_I2C_CHANNEL_STATUS1_DEF 9 6703 #define ATOM_INTERNAL_TIMER_DEF 10 6704 6705 // BIOS_0_SCRATCH Definition 6706 #define ATOM_S0_CRT1_MONO 0x00000001L 6707 #define ATOM_S0_CRT1_COLOR 0x00000002L 6708 #define ATOM_S0_CRT1_MASK (ATOM_S0_CRT1_MONO+ATOM_S0_CRT1_COLOR) 6709 6710 #define ATOM_S0_TV1_COMPOSITE_A 0x00000004L 6711 #define ATOM_S0_TV1_SVIDEO_A 0x00000008L 6712 #define ATOM_S0_TV1_MASK_A (ATOM_S0_TV1_COMPOSITE_A+ATOM_S0_TV1_SVIDEO_A) 6713 6714 #define ATOM_S0_CV_A 0x00000010L 6715 #define ATOM_S0_CV_DIN_A 0x00000020L 6716 #define ATOM_S0_CV_MASK_A (ATOM_S0_CV_A+ATOM_S0_CV_DIN_A) 6717 6718 6719 #define ATOM_S0_CRT2_MONO 0x00000100L 6720 #define ATOM_S0_CRT2_COLOR 0x00000200L 6721 #define ATOM_S0_CRT2_MASK (ATOM_S0_CRT2_MONO+ATOM_S0_CRT2_COLOR) 6722 6723 #define ATOM_S0_TV1_COMPOSITE 0x00000400L 6724 #define ATOM_S0_TV1_SVIDEO 0x00000800L 6725 #define ATOM_S0_TV1_SCART 0x00004000L 6726 #define ATOM_S0_TV1_MASK (ATOM_S0_TV1_COMPOSITE+ATOM_S0_TV1_SVIDEO+ATOM_S0_TV1_SCART) 6727 6728 #define ATOM_S0_CV 0x00001000L 6729 #define ATOM_S0_CV_DIN 0x00002000L 6730 #define ATOM_S0_CV_MASK (ATOM_S0_CV+ATOM_S0_CV_DIN) 6731 6732 #define ATOM_S0_DFP1 0x00010000L 6733 #define ATOM_S0_DFP2 0x00020000L 6734 #define ATOM_S0_LCD1 0x00040000L 6735 #define ATOM_S0_LCD2 0x00080000L 6736 #define ATOM_S0_DFP6 0x00100000L 6737 #define ATOM_S0_DFP3 0x00200000L 6738 #define ATOM_S0_DFP4 0x00400000L 6739 #define ATOM_S0_DFP5 0x00800000L 6740 6741 6742 #define ATOM_S0_DFP_MASK ATOM_S0_DFP1 | ATOM_S0_DFP2 | ATOM_S0_DFP3 | ATOM_S0_DFP4 | ATOM_S0_DFP5 | ATOM_S0_DFP6 6743 6744 #define ATOM_S0_FAD_REGISTER_BUG 0x02000000L // If set, indicates we are running a PCIE asic with 6745 // the FAD/HDP reg access bug. Bit is read by DAL, this is obsolete from RV5xx 6746 6747 #define ATOM_S0_THERMAL_STATE_MASK 0x1C000000L 6748 #define ATOM_S0_THERMAL_STATE_SHIFT 26 6749 6750 #define ATOM_S0_SYSTEM_POWER_STATE_MASK 0xE0000000L 6751 #define ATOM_S0_SYSTEM_POWER_STATE_SHIFT 29 6752 6753 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_AC 1 6754 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_DC 2 6755 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LITEAC 3 6756 #define ATOM_S0_SYSTEM_POWER_STATE_VALUE_LIT2AC 4 6757 6758 //Byte aligned defintion for BIOS usage 6759 #define ATOM_S0_CRT1_MONOb0 0x01 6760 #define ATOM_S0_CRT1_COLORb0 0x02 6761 #define ATOM_S0_CRT1_MASKb0 (ATOM_S0_CRT1_MONOb0+ATOM_S0_CRT1_COLORb0) 6762 6763 #define ATOM_S0_TV1_COMPOSITEb0 0x04 6764 #define ATOM_S0_TV1_SVIDEOb0 0x08 6765 #define ATOM_S0_TV1_MASKb0 (ATOM_S0_TV1_COMPOSITEb0+ATOM_S0_TV1_SVIDEOb0) 6766 6767 #define ATOM_S0_CVb0 0x10 6768 #define ATOM_S0_CV_DINb0 0x20 6769 #define ATOM_S0_CV_MASKb0 (ATOM_S0_CVb0+ATOM_S0_CV_DINb0) 6770 6771 #define ATOM_S0_CRT2_MONOb1 0x01 6772 #define ATOM_S0_CRT2_COLORb1 0x02 6773 #define ATOM_S0_CRT2_MASKb1 (ATOM_S0_CRT2_MONOb1+ATOM_S0_CRT2_COLORb1) 6774 6775 #define ATOM_S0_TV1_COMPOSITEb1 0x04 6776 #define ATOM_S0_TV1_SVIDEOb1 0x08 6777 #define ATOM_S0_TV1_SCARTb1 0x40 6778 #define ATOM_S0_TV1_MASKb1 (ATOM_S0_TV1_COMPOSITEb1+ATOM_S0_TV1_SVIDEOb1+ATOM_S0_TV1_SCARTb1) 6779 6780 #define ATOM_S0_CVb1 0x10 6781 #define ATOM_S0_CV_DINb1 0x20 6782 #define ATOM_S0_CV_MASKb1 (ATOM_S0_CVb1+ATOM_S0_CV_DINb1) 6783 6784 #define ATOM_S0_DFP1b2 0x01 6785 #define ATOM_S0_DFP2b2 0x02 6786 #define ATOM_S0_LCD1b2 0x04 6787 #define ATOM_S0_LCD2b2 0x08 6788 #define ATOM_S0_DFP6b2 0x10 6789 #define ATOM_S0_DFP3b2 0x20 6790 #define ATOM_S0_DFP4b2 0x40 6791 #define ATOM_S0_DFP5b2 0x80 6792 6793 6794 #define ATOM_S0_THERMAL_STATE_MASKb3 0x1C 6795 #define ATOM_S0_THERMAL_STATE_SHIFTb3 2 6796 6797 #define ATOM_S0_SYSTEM_POWER_STATE_MASKb3 0xE0 6798 #define ATOM_S0_LCD1_SHIFT 18 6799 6800 // BIOS_1_SCRATCH Definition 6801 #define ATOM_S1_ROM_LOCATION_MASK 0x0000FFFFL 6802 #define ATOM_S1_PCI_BUS_DEV_MASK 0xFFFF0000L 6803 6804 // BIOS_2_SCRATCH Definition 6805 #define ATOM_S2_TV1_STANDARD_MASK 0x0000000FL 6806 #define ATOM_S2_CURRENT_BL_LEVEL_MASK 0x0000FF00L 6807 #define ATOM_S2_CURRENT_BL_LEVEL_SHIFT 8 6808 6809 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK 0x0C000000L 6810 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_MASK_SHIFT 26 6811 #define ATOM_S2_FORCEDLOWPWRMODE_STATE_CHANGE 0x10000000L 6812 6813 #define ATOM_S2_DEVICE_DPMS_STATE 0x00010000L 6814 #define ATOM_S2_VRI_BRIGHT_ENABLE 0x20000000L 6815 6816 #define ATOM_S2_DISPLAY_ROTATION_0_DEGREE 0x0 6817 #define ATOM_S2_DISPLAY_ROTATION_90_DEGREE 0x1 6818 #define ATOM_S2_DISPLAY_ROTATION_180_DEGREE 0x2 6819 #define ATOM_S2_DISPLAY_ROTATION_270_DEGREE 0x3 6820 #define ATOM_S2_DISPLAY_ROTATION_DEGREE_SHIFT 30 6821 #define ATOM_S2_DISPLAY_ROTATION_ANGLE_MASK 0xC0000000L 6822 6823 6824 //Byte aligned defintion for BIOS usage 6825 #define ATOM_S2_TV1_STANDARD_MASKb0 0x0F 6826 #define ATOM_S2_CURRENT_BL_LEVEL_MASKb1 0xFF 6827 #define ATOM_S2_DEVICE_DPMS_STATEb2 0x01 6828 6829 #define ATOM_S2_TMDS_COHERENT_MODEb3 0x10 // used by VBIOS code only, use coherent mode for TMDS/HDMI mode 6830 #define ATOM_S2_VRI_BRIGHT_ENABLEb3 0x20 6831 #define ATOM_S2_ROTATION_STATE_MASKb3 0xC0 6832 6833 6834 // BIOS_3_SCRATCH Definition 6835 #define ATOM_S3_CRT1_ACTIVE 0x00000001L 6836 #define ATOM_S3_LCD1_ACTIVE 0x00000002L 6837 #define ATOM_S3_TV1_ACTIVE 0x00000004L 6838 #define ATOM_S3_DFP1_ACTIVE 0x00000008L 6839 #define ATOM_S3_CRT2_ACTIVE 0x00000010L 6840 #define ATOM_S3_LCD2_ACTIVE 0x00000020L 6841 #define ATOM_S3_DFP6_ACTIVE 0x00000040L 6842 #define ATOM_S3_DFP2_ACTIVE 0x00000080L 6843 #define ATOM_S3_CV_ACTIVE 0x00000100L 6844 #define ATOM_S3_DFP3_ACTIVE 0x00000200L 6845 #define ATOM_S3_DFP4_ACTIVE 0x00000400L 6846 #define ATOM_S3_DFP5_ACTIVE 0x00000800L 6847 6848 6849 #define ATOM_S3_DEVICE_ACTIVE_MASK 0x00000FFFL 6850 6851 #define ATOM_S3_LCD_FULLEXPANSION_ACTIVE 0x00001000L 6852 #define ATOM_S3_LCD_EXPANSION_ASPEC_RATIO_ACTIVE 0x00002000L 6853 6854 #define ATOM_S3_CRT1_CRTC_ACTIVE 0x00010000L 6855 #define ATOM_S3_LCD1_CRTC_ACTIVE 0x00020000L 6856 #define ATOM_S3_TV1_CRTC_ACTIVE 0x00040000L 6857 #define ATOM_S3_DFP1_CRTC_ACTIVE 0x00080000L 6858 #define ATOM_S3_CRT2_CRTC_ACTIVE 0x00100000L 6859 #define ATOM_S3_LCD2_CRTC_ACTIVE 0x00200000L 6860 #define ATOM_S3_DFP6_CRTC_ACTIVE 0x00400000L 6861 #define ATOM_S3_DFP2_CRTC_ACTIVE 0x00800000L 6862 #define ATOM_S3_CV_CRTC_ACTIVE 0x01000000L 6863 #define ATOM_S3_DFP3_CRTC_ACTIVE 0x02000000L 6864 #define ATOM_S3_DFP4_CRTC_ACTIVE 0x04000000L 6865 #define ATOM_S3_DFP5_CRTC_ACTIVE 0x08000000L 6866 6867 6868 #define ATOM_S3_DEVICE_CRTC_ACTIVE_MASK 0x0FFF0000L 6869 #define ATOM_S3_ASIC_GUI_ENGINE_HUNG 0x20000000L 6870 //Below two definitions are not supported in pplib, but in the old powerplay in DAL 6871 #define ATOM_S3_ALLOW_FAST_PWR_SWITCH 0x40000000L 6872 #define ATOM_S3_RQST_GPU_USE_MIN_PWR 0x80000000L 6873 6874 6875 6876 //Byte aligned defintion for BIOS usage 6877 #define ATOM_S3_CRT1_ACTIVEb0 0x01 6878 #define ATOM_S3_LCD1_ACTIVEb0 0x02 6879 #define ATOM_S3_TV1_ACTIVEb0 0x04 6880 #define ATOM_S3_DFP1_ACTIVEb0 0x08 6881 #define ATOM_S3_CRT2_ACTIVEb0 0x10 6882 #define ATOM_S3_LCD2_ACTIVEb0 0x20 6883 #define ATOM_S3_DFP6_ACTIVEb0 0x40 6884 #define ATOM_S3_DFP2_ACTIVEb0 0x80 6885 #define ATOM_S3_CV_ACTIVEb1 0x01 6886 #define ATOM_S3_DFP3_ACTIVEb1 0x02 6887 #define ATOM_S3_DFP4_ACTIVEb1 0x04 6888 #define ATOM_S3_DFP5_ACTIVEb1 0x08 6889 6890 6891 #define ATOM_S3_ACTIVE_CRTC1w0 0xFFF 6892 6893 #define ATOM_S3_CRT1_CRTC_ACTIVEb2 0x01 6894 #define ATOM_S3_LCD1_CRTC_ACTIVEb2 0x02 6895 #define ATOM_S3_TV1_CRTC_ACTIVEb2 0x04 6896 #define ATOM_S3_DFP1_CRTC_ACTIVEb2 0x08 6897 #define ATOM_S3_CRT2_CRTC_ACTIVEb2 0x10 6898 #define ATOM_S3_LCD2_CRTC_ACTIVEb2 0x20 6899 #define ATOM_S3_DFP6_CRTC_ACTIVEb2 0x40 6900 #define ATOM_S3_DFP2_CRTC_ACTIVEb2 0x80 6901 #define ATOM_S3_CV_CRTC_ACTIVEb3 0x01 6902 #define ATOM_S3_DFP3_CRTC_ACTIVEb3 0x02 6903 #define ATOM_S3_DFP4_CRTC_ACTIVEb3 0x04 6904 #define ATOM_S3_DFP5_CRTC_ACTIVEb3 0x08 6905 6906 6907 #define ATOM_S3_ACTIVE_CRTC2w1 0xFFF 6908 6909 6910 // BIOS_4_SCRATCH Definition 6911 #define ATOM_S4_LCD1_PANEL_ID_MASK 0x000000FFL 6912 #define ATOM_S4_LCD1_REFRESH_MASK 0x0000FF00L 6913 #define ATOM_S4_LCD1_REFRESH_SHIFT 8 6914 6915 //Byte aligned defintion for BIOS usage 6916 #define ATOM_S4_LCD1_PANEL_ID_MASKb0 0x0FF 6917 #define ATOM_S4_LCD1_REFRESH_MASKb1 ATOM_S4_LCD1_PANEL_ID_MASKb0 6918 #define ATOM_S4_VRAM_INFO_MASKb2 ATOM_S4_LCD1_PANEL_ID_MASKb0 6919 6920 // BIOS_5_SCRATCH Definition, BIOS_5_SCRATCH is used by Firmware only !!!! 6921 #define ATOM_S5_DOS_REQ_CRT1b0 0x01 6922 #define ATOM_S5_DOS_REQ_LCD1b0 0x02 6923 #define ATOM_S5_DOS_REQ_TV1b0 0x04 6924 #define ATOM_S5_DOS_REQ_DFP1b0 0x08 6925 #define ATOM_S5_DOS_REQ_CRT2b0 0x10 6926 #define ATOM_S5_DOS_REQ_LCD2b0 0x20 6927 #define ATOM_S5_DOS_REQ_DFP6b0 0x40 6928 #define ATOM_S5_DOS_REQ_DFP2b0 0x80 6929 #define ATOM_S5_DOS_REQ_CVb1 0x01 6930 #define ATOM_S5_DOS_REQ_DFP3b1 0x02 6931 #define ATOM_S5_DOS_REQ_DFP4b1 0x04 6932 #define ATOM_S5_DOS_REQ_DFP5b1 0x08 6933 6934 6935 #define ATOM_S5_DOS_REQ_DEVICEw0 0x0FFF 6936 6937 #define ATOM_S5_DOS_REQ_CRT1 0x0001 6938 #define ATOM_S5_DOS_REQ_LCD1 0x0002 6939 #define ATOM_S5_DOS_REQ_TV1 0x0004 6940 #define ATOM_S5_DOS_REQ_DFP1 0x0008 6941 #define ATOM_S5_DOS_REQ_CRT2 0x0010 6942 #define ATOM_S5_DOS_REQ_LCD2 0x0020 6943 #define ATOM_S5_DOS_REQ_DFP6 0x0040 6944 #define ATOM_S5_DOS_REQ_DFP2 0x0080 6945 #define ATOM_S5_DOS_REQ_CV 0x0100 6946 #define ATOM_S5_DOS_REQ_DFP3 0x0200 6947 #define ATOM_S5_DOS_REQ_DFP4 0x0400 6948 #define ATOM_S5_DOS_REQ_DFP5 0x0800 6949 6950 #define ATOM_S5_DOS_FORCE_CRT1b2 ATOM_S5_DOS_REQ_CRT1b0 6951 #define ATOM_S5_DOS_FORCE_TV1b2 ATOM_S5_DOS_REQ_TV1b0 6952 #define ATOM_S5_DOS_FORCE_CRT2b2 ATOM_S5_DOS_REQ_CRT2b0 6953 #define ATOM_S5_DOS_FORCE_CVb3 ATOM_S5_DOS_REQ_CVb1 6954 #define ATOM_S5_DOS_FORCE_DEVICEw1 (ATOM_S5_DOS_FORCE_CRT1b2+ATOM_S5_DOS_FORCE_TV1b2+ATOM_S5_DOS_FORCE_CRT2b2+\ 6955 (ATOM_S5_DOS_FORCE_CVb3<<8)) 6956 // BIOS_6_SCRATCH Definition 6957 #define ATOM_S6_DEVICE_CHANGE 0x00000001L 6958 #define ATOM_S6_SCALER_CHANGE 0x00000002L 6959 #define ATOM_S6_LID_CHANGE 0x00000004L 6960 #define ATOM_S6_DOCKING_CHANGE 0x00000008L 6961 #define ATOM_S6_ACC_MODE 0x00000010L 6962 #define ATOM_S6_EXT_DESKTOP_MODE 0x00000020L 6963 #define ATOM_S6_LID_STATE 0x00000040L 6964 #define ATOM_S6_DOCK_STATE 0x00000080L 6965 #define ATOM_S6_CRITICAL_STATE 0x00000100L 6966 #define ATOM_S6_HW_I2C_BUSY_STATE 0x00000200L 6967 #define ATOM_S6_THERMAL_STATE_CHANGE 0x00000400L 6968 #define ATOM_S6_INTERRUPT_SET_BY_BIOS 0x00000800L 6969 #define ATOM_S6_REQ_LCD_EXPANSION_FULL 0x00001000L //Normal expansion Request bit for LCD 6970 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIO 0x00002000L //Aspect ratio expansion Request bit for LCD 6971 6972 #define ATOM_S6_DISPLAY_STATE_CHANGE 0x00004000L //This bit is recycled when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_H_expansion 6973 #define ATOM_S6_I2C_STATE_CHANGE 0x00008000L //This bit is recycled,when ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE is set,previously it's SCL2_V_expansion 6974 6975 #define ATOM_S6_ACC_REQ_CRT1 0x00010000L 6976 #define ATOM_S6_ACC_REQ_LCD1 0x00020000L 6977 #define ATOM_S6_ACC_REQ_TV1 0x00040000L 6978 #define ATOM_S6_ACC_REQ_DFP1 0x00080000L 6979 #define ATOM_S6_ACC_REQ_CRT2 0x00100000L 6980 #define ATOM_S6_ACC_REQ_LCD2 0x00200000L 6981 #define ATOM_S6_ACC_REQ_DFP6 0x00400000L 6982 #define ATOM_S6_ACC_REQ_DFP2 0x00800000L 6983 #define ATOM_S6_ACC_REQ_CV 0x01000000L 6984 #define ATOM_S6_ACC_REQ_DFP3 0x02000000L 6985 #define ATOM_S6_ACC_REQ_DFP4 0x04000000L 6986 #define ATOM_S6_ACC_REQ_DFP5 0x08000000L 6987 6988 #define ATOM_S6_ACC_REQ_MASK 0x0FFF0000L 6989 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE 0x10000000L 6990 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH 0x20000000L 6991 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE 0x40000000L 6992 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_MASK 0x80000000L 6993 6994 //Byte aligned defintion for BIOS usage 6995 #define ATOM_S6_DEVICE_CHANGEb0 0x01 6996 #define ATOM_S6_SCALER_CHANGEb0 0x02 6997 #define ATOM_S6_LID_CHANGEb0 0x04 6998 #define ATOM_S6_DOCKING_CHANGEb0 0x08 6999 #define ATOM_S6_ACC_MODEb0 0x10 7000 #define ATOM_S6_EXT_DESKTOP_MODEb0 0x20 7001 #define ATOM_S6_LID_STATEb0 0x40 7002 #define ATOM_S6_DOCK_STATEb0 0x80 7003 #define ATOM_S6_CRITICAL_STATEb1 0x01 7004 #define ATOM_S6_HW_I2C_BUSY_STATEb1 0x02 7005 #define ATOM_S6_THERMAL_STATE_CHANGEb1 0x04 7006 #define ATOM_S6_INTERRUPT_SET_BY_BIOSb1 0x08 7007 #define ATOM_S6_REQ_LCD_EXPANSION_FULLb1 0x10 7008 #define ATOM_S6_REQ_LCD_EXPANSION_ASPEC_RATIOb1 0x20 7009 7010 #define ATOM_S6_ACC_REQ_CRT1b2 0x01 7011 #define ATOM_S6_ACC_REQ_LCD1b2 0x02 7012 #define ATOM_S6_ACC_REQ_TV1b2 0x04 7013 #define ATOM_S6_ACC_REQ_DFP1b2 0x08 7014 #define ATOM_S6_ACC_REQ_CRT2b2 0x10 7015 #define ATOM_S6_ACC_REQ_LCD2b2 0x20 7016 #define ATOM_S6_ACC_REQ_DFP6b2 0x40 7017 #define ATOM_S6_ACC_REQ_DFP2b2 0x80 7018 #define ATOM_S6_ACC_REQ_CVb3 0x01 7019 #define ATOM_S6_ACC_REQ_DFP3b3 0x02 7020 #define ATOM_S6_ACC_REQ_DFP4b3 0x04 7021 #define ATOM_S6_ACC_REQ_DFP5b3 0x08 7022 7023 #define ATOM_S6_ACC_REQ_DEVICEw1 ATOM_S5_DOS_REQ_DEVICEw0 7024 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGEb3 0x10 7025 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCHb3 0x20 7026 #define ATOM_S6_VRI_BRIGHTNESS_CHANGEb3 0x40 7027 #define ATOM_S6_CONFIG_DISPLAY_CHANGEb3 0x80 7028 7029 #define ATOM_S6_DEVICE_CHANGE_SHIFT 0 7030 #define ATOM_S6_SCALER_CHANGE_SHIFT 1 7031 #define ATOM_S6_LID_CHANGE_SHIFT 2 7032 #define ATOM_S6_DOCKING_CHANGE_SHIFT 3 7033 #define ATOM_S6_ACC_MODE_SHIFT 4 7034 #define ATOM_S6_EXT_DESKTOP_MODE_SHIFT 5 7035 #define ATOM_S6_LID_STATE_SHIFT 6 7036 #define ATOM_S6_DOCK_STATE_SHIFT 7 7037 #define ATOM_S6_CRITICAL_STATE_SHIFT 8 7038 #define ATOM_S6_HW_I2C_BUSY_STATE_SHIFT 9 7039 #define ATOM_S6_THERMAL_STATE_CHANGE_SHIFT 10 7040 #define ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT 11 7041 #define ATOM_S6_REQ_SCALER_SHIFT 12 7042 #define ATOM_S6_REQ_SCALER_ARATIO_SHIFT 13 7043 #define ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT 14 7044 #define ATOM_S6_I2C_STATE_CHANGE_SHIFT 15 7045 #define ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT 28 7046 #define ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH_SHIFT 29 7047 #define ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT 30 7048 #define ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT 31 7049 7050 // BIOS_7_SCRATCH Definition, BIOS_7_SCRATCH is used by Firmware only !!!! 7051 #define ATOM_S7_DOS_MODE_TYPEb0 0x03 7052 #define ATOM_S7_DOS_MODE_VGAb0 0x00 7053 #define ATOM_S7_DOS_MODE_VESAb0 0x01 7054 #define ATOM_S7_DOS_MODE_EXTb0 0x02 7055 #define ATOM_S7_DOS_MODE_PIXEL_DEPTHb0 0x0C 7056 #define ATOM_S7_DOS_MODE_PIXEL_FORMATb0 0xF0 7057 #define ATOM_S7_DOS_8BIT_DAC_ENb1 0x01 7058 #define ATOM_S7_ASIC_INIT_COMPLETEb1 0x02 7059 #define ATOM_S7_ASIC_INIT_COMPLETE_MASK 0x00000200 7060 #define ATOM_S7_DOS_MODE_NUMBERw1 0x0FFFF 7061 7062 #define ATOM_S7_DOS_8BIT_DAC_EN_SHIFT 8 7063 7064 // BIOS_8_SCRATCH Definition 7065 #define ATOM_S8_I2C_CHANNEL_BUSY_MASK 0x00000FFFF 7066 #define ATOM_S8_I2C_HW_ENGINE_BUSY_MASK 0x0FFFF0000 7067 7068 #define ATOM_S8_I2C_CHANNEL_BUSY_SHIFT 0 7069 #define ATOM_S8_I2C_ENGINE_BUSY_SHIFT 16 7070 7071 // BIOS_9_SCRATCH Definition 7072 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 7073 #define ATOM_S9_I2C_CHANNEL_COMPLETED_MASK 0x0000FFFF 7074 #endif 7075 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_MASK 7076 #define ATOM_S9_I2C_CHANNEL_ABORTED_MASK 0xFFFF0000 7077 #endif 7078 #ifndef ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 7079 #define ATOM_S9_I2C_CHANNEL_COMPLETED_SHIFT 0 7080 #endif 7081 #ifndef ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 7082 #define ATOM_S9_I2C_CHANNEL_ABORTED_SHIFT 16 7083 #endif 7084 7085 7086 #define ATOM_FLAG_SET 0x20 7087 #define ATOM_FLAG_CLEAR 0 7088 #define CLEAR_ATOM_S6_ACC_MODE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_ACC_MODE_SHIFT | ATOM_FLAG_CLEAR) 7089 #define SET_ATOM_S6_DEVICE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DEVICE_CHANGE_SHIFT | ATOM_FLAG_SET) 7090 #define SET_ATOM_S6_VRI_BRIGHTNESS_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_VRI_BRIGHTNESS_CHANGE_SHIFT | ATOM_FLAG_SET) 7091 #define SET_ATOM_S6_SCALER_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SCALER_CHANGE_SHIFT | ATOM_FLAG_SET) 7092 #define SET_ATOM_S6_LID_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_CHANGE_SHIFT | ATOM_FLAG_SET) 7093 7094 #define SET_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_SET) 7095 #define CLEAR_ATOM_S6_LID_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_LID_STATE_SHIFT | ATOM_FLAG_CLEAR) 7096 7097 #define SET_ATOM_S6_DOCK_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCKING_CHANGE_SHIFT | ATOM_FLAG_SET) 7098 #define SET_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_SET) 7099 #define CLEAR_ATOM_S6_DOCK_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DOCK_STATE_SHIFT | ATOM_FLAG_CLEAR) 7100 7101 #define SET_ATOM_S6_THERMAL_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_THERMAL_STATE_CHANGE_SHIFT | ATOM_FLAG_SET) 7102 #define SET_ATOM_S6_SYSTEM_POWER_MODE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_SYSTEM_POWER_MODE_CHANGE_SHIFT | ATOM_FLAG_SET) 7103 #define SET_ATOM_S6_INTERRUPT_SET_BY_BIOS ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_INTERRUPT_SET_BY_BIOS_SHIFT | ATOM_FLAG_SET) 7104 7105 #define SET_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_SET) 7106 #define CLEAR_ATOM_S6_CRITICAL_STATE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CRITICAL_STATE_SHIFT | ATOM_FLAG_CLEAR) 7107 7108 #define SET_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_SET) 7109 #define CLEAR_ATOM_S6_REQ_SCALER ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_SHIFT | ATOM_FLAG_CLEAR ) 7110 7111 #define SET_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_SET ) 7112 #define CLEAR_ATOM_S6_REQ_SCALER_ARATIO ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_REQ_SCALER_ARATIO_SHIFT | ATOM_FLAG_CLEAR ) 7113 7114 #define SET_ATOM_S6_I2C_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_I2C_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7115 7116 #define SET_ATOM_S6_DISPLAY_STATE_CHANGE ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_DISPLAY_STATE_CHANGE_SHIFT | ATOM_FLAG_SET ) 7117 7118 #define SET_ATOM_S6_DEVICE_RECONFIG ((ATOM_ACC_CHANGE_INFO_DEF << 8 )|ATOM_S6_CONFIG_DISPLAY_CHANGE_SHIFT | ATOM_FLAG_SET) 7119 #define CLEAR_ATOM_S0_LCD1 ((ATOM_DEVICE_CONNECT_INFO_DEF << 8 )| ATOM_S0_LCD1_SHIFT | ATOM_FLAG_CLEAR ) 7120 #define SET_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_SET ) 7121 #define CLEAR_ATOM_S7_DOS_8BIT_DAC_EN ((ATOM_DOS_MODE_INFO_DEF << 8 )|ATOM_S7_DOS_8BIT_DAC_EN_SHIFT | ATOM_FLAG_CLEAR ) 7122 7123 /****************************************************************************/ 7124 //Portion II: Definitinos only used in Driver 7125 /****************************************************************************/ 7126 7127 // Macros used by driver 7128 7129 #ifdef __cplusplus 7130 #define GetIndexIntoMasterTable(MasterOrData, FieldName) ((reinterpret_cast<char*>(&(static_cast<ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*>(0))->FieldName)-static_cast<char*>(0))/sizeof(USHORT)) 7131 7132 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableFormatRevision )&0x3F) 7133 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) (((static_cast<ATOM_COMMON_TABLE_HEADER*>(TABLE_HEADER_OFFSET))->ucTableContentRevision)&0x3F) 7134 #else // not __cplusplus 7135 #define GetIndexIntoMasterTable(MasterOrData, FieldName) (((char*)(&((ATOM_MASTER_LIST_OF_##MasterOrData##_TABLES*)0)->FieldName)-(char*)0)/sizeof(USHORT)) 7136 7137 #define GET_COMMAND_TABLE_COMMANDSET_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableFormatRevision)&0x3F) 7138 #define GET_COMMAND_TABLE_PARAMETER_REVISION(TABLE_HEADER_OFFSET) ((((ATOM_COMMON_TABLE_HEADER*)TABLE_HEADER_OFFSET)->ucTableContentRevision)&0x3F) 7139 #endif // __cplusplus 7140 7141 #define GET_DATA_TABLE_MAJOR_REVISION GET_COMMAND_TABLE_COMMANDSET_REVISION 7142 #define GET_DATA_TABLE_MINOR_REVISION GET_COMMAND_TABLE_PARAMETER_REVISION 7143 7144 /****************************************************************************/ 7145 //Portion III: Definitinos only used in VBIOS 7146 /****************************************************************************/ 7147 #define ATOM_DAC_SRC 0x80 7148 #define ATOM_SRC_DAC1 0 7149 #define ATOM_SRC_DAC2 0x80 7150 7151 7152 7153 typedef struct _MEMORY_PLLINIT_PARAMETERS 7154 { 7155 ULONG ulTargetMemoryClock; //In 10Khz unit 7156 UCHAR ucAction; //not define yet 7157 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte 7158 UCHAR ucFbDiv; //FB value 7159 UCHAR ucPostDiv; //Post div 7160 }MEMORY_PLLINIT_PARAMETERS; 7161 7162 #define MEMORY_PLLINIT_PS_ALLOCATION MEMORY_PLLINIT_PARAMETERS 7163 7164 7165 #define GPIO_PIN_WRITE 0x01 7166 #define GPIO_PIN_READ 0x00 7167 7168 typedef struct _GPIO_PIN_CONTROL_PARAMETERS 7169 { 7170 UCHAR ucGPIO_ID; //return value, read from GPIO pins 7171 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update 7172 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask 7173 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write 7174 }GPIO_PIN_CONTROL_PARAMETERS; 7175 7176 typedef struct _ENABLE_SCALER_PARAMETERS 7177 { 7178 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2 7179 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION 7180 UCHAR ucTVStandard; // 7181 UCHAR ucPadding[1]; 7182 }ENABLE_SCALER_PARAMETERS; 7183 #define ENABLE_SCALER_PS_ALLOCATION ENABLE_SCALER_PARAMETERS 7184 7185 //ucEnable: 7186 #define SCALER_BYPASS_AUTO_CENTER_NO_REPLICATION 0 7187 #define SCALER_BYPASS_AUTO_CENTER_AUTO_REPLICATION 1 7188 #define SCALER_ENABLE_2TAP_ALPHA_MODE 2 7189 #define SCALER_ENABLE_MULTITAP_MODE 3 7190 7191 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS 7192 { 7193 ULONG usHWIconHorzVertPosn; // Hardware Icon Vertical position 7194 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset 7195 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset 7196 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2 7197 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7198 }ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS; 7199 7200 typedef struct _ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION 7201 { 7202 ENABLE_HARDWARE_ICON_CURSOR_PARAMETERS sEnableIcon; 7203 ENABLE_CRTC_PARAMETERS sReserved; 7204 }ENABLE_HARDWARE_ICON_CURSOR_PS_ALLOCATION; 7205 7206 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS 7207 { 7208 USHORT usHight; // Image Hight 7209 USHORT usWidth; // Image Width 7210 UCHAR ucSurface; // Surface 1 or 2 7211 UCHAR ucPadding[3]; 7212 }ENABLE_GRAPH_SURFACE_PARAMETERS; 7213 7214 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2 7215 { 7216 USHORT usHight; // Image Hight 7217 USHORT usWidth; // Image Width 7218 UCHAR ucSurface; // Surface 1 or 2 7219 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7220 UCHAR ucPadding[2]; 7221 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_2; 7222 7223 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3 7224 { 7225 USHORT usHight; // Image Hight 7226 USHORT usWidth; // Image Width 7227 UCHAR ucSurface; // Surface 1 or 2 7228 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7229 USHORT usDeviceId; // Active Device Id for this surface. If no device, set to 0. 7230 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_3; 7231 7232 typedef struct _ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4 7233 { 7234 USHORT usHight; // Image Hight 7235 USHORT usWidth; // Image Width 7236 USHORT usGraphPitch; 7237 UCHAR ucColorDepth; 7238 UCHAR ucPixelFormat; 7239 UCHAR ucSurface; // Surface 1 or 2 7240 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE 7241 UCHAR ucModeType; 7242 UCHAR ucReserved; 7243 }ENABLE_GRAPH_SURFACE_PARAMETERS_V1_4; 7244 7245 // ucEnable 7246 #define ATOM_GRAPH_CONTROL_SET_PITCH 0x0f 7247 #define ATOM_GRAPH_CONTROL_SET_DISP_START 0x10 7248 7249 typedef struct _ENABLE_GRAPH_SURFACE_PS_ALLOCATION 7250 { 7251 ENABLE_GRAPH_SURFACE_PARAMETERS sSetSurface; 7252 ENABLE_YUV_PS_ALLOCATION sReserved; // Don't set this one 7253 }ENABLE_GRAPH_SURFACE_PS_ALLOCATION; 7254 7255 typedef struct _MEMORY_CLEAN_UP_PARAMETERS 7256 { 7257 USHORT usMemoryStart; //in 8Kb boundry, offset from memory base address 7258 USHORT usMemorySize; //8Kb blocks aligned 7259 }MEMORY_CLEAN_UP_PARAMETERS; 7260 7261 #define MEMORY_CLEAN_UP_PS_ALLOCATION MEMORY_CLEAN_UP_PARAMETERS 7262 7263 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS 7264 { 7265 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7266 USHORT usY_Size; 7267 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS; 7268 7269 typedef struct _GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2 7270 { 7271 union{ 7272 USHORT usX_Size; //When use as input parameter, usX_Size indicates which CRTC 7273 USHORT usSurface; 7274 }; 7275 USHORT usY_Size; 7276 USHORT usDispXStart; 7277 USHORT usDispYStart; 7278 }GET_DISPLAY_SURFACE_SIZE_PARAMETERS_V2; 7279 7280 7281 typedef struct _PALETTE_DATA_CONTROL_PARAMETERS_V3 7282 { 7283 UCHAR ucLutId; 7284 UCHAR ucAction; 7285 USHORT usLutStartIndex; 7286 USHORT usLutLength; 7287 USHORT usLutOffsetInVram; 7288 }PALETTE_DATA_CONTROL_PARAMETERS_V3; 7289 7290 // ucAction: 7291 #define PALETTE_DATA_AUTO_FILL 1 7292 #define PALETTE_DATA_READ 2 7293 #define PALETTE_DATA_WRITE 3 7294 7295 7296 typedef struct _INTERRUPT_SERVICE_PARAMETERS_V2 7297 { 7298 UCHAR ucInterruptId; 7299 UCHAR ucServiceId; 7300 UCHAR ucStatus; 7301 UCHAR ucReserved; 7302 }INTERRUPT_SERVICE_PARAMETER_V2; 7303 7304 // ucInterruptId 7305 #define HDP1_INTERRUPT_ID 1 7306 #define HDP2_INTERRUPT_ID 2 7307 #define HDP3_INTERRUPT_ID 3 7308 #define HDP4_INTERRUPT_ID 4 7309 #define HDP5_INTERRUPT_ID 5 7310 #define HDP6_INTERRUPT_ID 6 7311 #define SW_INTERRUPT_ID 11 7312 7313 // ucAction 7314 #define INTERRUPT_SERVICE_GEN_SW_INT 1 7315 #define INTERRUPT_SERVICE_GET_STATUS 2 7316 7317 // ucStatus 7318 #define INTERRUPT_STATUS__INT_TRIGGER 1 7319 #define INTERRUPT_STATUS__HPD_HIGH 2 7320 7321 typedef struct _EFUSE_INPUT_PARAMETER 7322 { 7323 USHORT usEfuseIndex; 7324 UCHAR ucBitShift; 7325 UCHAR ucBitLength; 7326 }EFUSE_INPUT_PARAMETER; 7327 7328 // ReadEfuseValue command table input/output parameter 7329 typedef union _READ_EFUSE_VALUE_PARAMETER 7330 { 7331 EFUSE_INPUT_PARAMETER sEfuse; 7332 ULONG ulEfuseValue; 7333 }READ_EFUSE_VALUE_PARAMETER; 7334 7335 typedef struct _INDIRECT_IO_ACCESS 7336 { 7337 ATOM_COMMON_TABLE_HEADER sHeader; 7338 UCHAR IOAccessSequence[256]; 7339 } INDIRECT_IO_ACCESS; 7340 7341 #define INDIRECT_READ 0x00 7342 #define INDIRECT_WRITE 0x80 7343 7344 #define INDIRECT_IO_MM 0 7345 #define INDIRECT_IO_PLL 1 7346 #define INDIRECT_IO_MC 2 7347 #define INDIRECT_IO_PCIE 3 7348 #define INDIRECT_IO_PCIEP 4 7349 #define INDIRECT_IO_NBMISC 5 7350 #define INDIRECT_IO_SMU 5 7351 7352 #define INDIRECT_IO_PLL_READ INDIRECT_IO_PLL | INDIRECT_READ 7353 #define INDIRECT_IO_PLL_WRITE INDIRECT_IO_PLL | INDIRECT_WRITE 7354 #define INDIRECT_IO_MC_READ INDIRECT_IO_MC | INDIRECT_READ 7355 #define INDIRECT_IO_MC_WRITE INDIRECT_IO_MC | INDIRECT_WRITE 7356 #define INDIRECT_IO_PCIE_READ INDIRECT_IO_PCIE | INDIRECT_READ 7357 #define INDIRECT_IO_PCIE_WRITE INDIRECT_IO_PCIE | INDIRECT_WRITE 7358 #define INDIRECT_IO_PCIEP_READ INDIRECT_IO_PCIEP | INDIRECT_READ 7359 #define INDIRECT_IO_PCIEP_WRITE INDIRECT_IO_PCIEP | INDIRECT_WRITE 7360 #define INDIRECT_IO_NBMISC_READ INDIRECT_IO_NBMISC | INDIRECT_READ 7361 #define INDIRECT_IO_NBMISC_WRITE INDIRECT_IO_NBMISC | INDIRECT_WRITE 7362 #define INDIRECT_IO_SMU_READ INDIRECT_IO_SMU | INDIRECT_READ 7363 #define INDIRECT_IO_SMU_WRITE INDIRECT_IO_SMU | INDIRECT_WRITE 7364 7365 7366 typedef struct _ATOM_OEM_INFO 7367 { 7368 ATOM_COMMON_TABLE_HEADER sHeader; 7369 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 7370 }ATOM_OEM_INFO; 7371 7372 typedef struct _ATOM_TV_MODE 7373 { 7374 UCHAR ucVMode_Num; //Video mode number 7375 UCHAR ucTV_Mode_Num; //Internal TV mode number 7376 }ATOM_TV_MODE; 7377 7378 typedef struct _ATOM_BIOS_INT_TVSTD_MODE 7379 { 7380 ATOM_COMMON_TABLE_HEADER sHeader; 7381 USHORT usTV_Mode_LUT_Offset; // Pointer to standard to internal number conversion table 7382 USHORT usTV_FIFO_Offset; // Pointer to FIFO entry table 7383 USHORT usNTSC_Tbl_Offset; // Pointer to SDTV_Mode_NTSC table 7384 USHORT usPAL_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7385 USHORT usCV_Tbl_Offset; // Pointer to SDTV_Mode_PAL table 7386 }ATOM_BIOS_INT_TVSTD_MODE; 7387 7388 7389 typedef struct _ATOM_TV_MODE_SCALER_PTR 7390 { 7391 USHORT ucFilter0_Offset; //Pointer to filter format 0 coefficients 7392 USHORT usFilter1_Offset; //Pointer to filter format 0 coefficients 7393 UCHAR ucTV_Mode_Num; 7394 }ATOM_TV_MODE_SCALER_PTR; 7395 7396 typedef struct _ATOM_STANDARD_VESA_TIMING 7397 { 7398 ATOM_COMMON_TABLE_HEADER sHeader; 7399 ATOM_DTD_FORMAT aModeTimings[16]; // 16 is not the real array number, just for initial allocation 7400 }ATOM_STANDARD_VESA_TIMING; 7401 7402 7403 typedef struct _ATOM_STD_FORMAT 7404 { 7405 USHORT usSTD_HDisp; 7406 USHORT usSTD_VDisp; 7407 USHORT usSTD_RefreshRate; 7408 USHORT usReserved; 7409 }ATOM_STD_FORMAT; 7410 7411 typedef struct _ATOM_VESA_TO_EXTENDED_MODE 7412 { 7413 USHORT usVESA_ModeNumber; 7414 USHORT usExtendedModeNumber; 7415 }ATOM_VESA_TO_EXTENDED_MODE; 7416 7417 typedef struct _ATOM_VESA_TO_INTENAL_MODE_LUT 7418 { 7419 ATOM_COMMON_TABLE_HEADER sHeader; 7420 ATOM_VESA_TO_EXTENDED_MODE asVESA_ToExtendedModeInfo[76]; 7421 }ATOM_VESA_TO_INTENAL_MODE_LUT; 7422 7423 /*************** ATOM Memory Related Data Structure ***********************/ 7424 typedef struct _ATOM_MEMORY_VENDOR_BLOCK{ 7425 UCHAR ucMemoryType; 7426 UCHAR ucMemoryVendor; 7427 UCHAR ucAdjMCId; 7428 UCHAR ucDynClkId; 7429 ULONG ulDllResetClkRange; 7430 }ATOM_MEMORY_VENDOR_BLOCK; 7431 7432 7433 typedef struct _ATOM_MEMORY_SETTING_ID_CONFIG{ 7434 #if ATOM_BIG_ENDIAN 7435 ULONG ucMemBlkId:8; 7436 ULONG ulMemClockRange:24; 7437 #else 7438 ULONG ulMemClockRange:24; 7439 ULONG ucMemBlkId:8; 7440 #endif 7441 }ATOM_MEMORY_SETTING_ID_CONFIG; 7442 7443 typedef union _ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS 7444 { 7445 ATOM_MEMORY_SETTING_ID_CONFIG slAccess; 7446 ULONG ulAccess; 7447 }ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS; 7448 7449 7450 typedef struct _ATOM_MEMORY_SETTING_DATA_BLOCK{ 7451 ATOM_MEMORY_SETTING_ID_CONFIG_ACCESS ulMemoryID; 7452 ULONG aulMemData[1]; 7453 }ATOM_MEMORY_SETTING_DATA_BLOCK; 7454 7455 7456 typedef struct _ATOM_INIT_REG_INDEX_FORMAT{ 7457 USHORT usRegIndex; // MC register index 7458 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf 7459 }ATOM_INIT_REG_INDEX_FORMAT; 7460 7461 7462 typedef struct _ATOM_INIT_REG_BLOCK{ 7463 USHORT usRegIndexTblSize; //size of asRegIndexBuf 7464 USHORT usRegDataBlkSize; //size of ATOM_MEMORY_SETTING_DATA_BLOCK 7465 ATOM_INIT_REG_INDEX_FORMAT asRegIndexBuf[1]; 7466 ATOM_MEMORY_SETTING_DATA_BLOCK asRegDataBuf[1]; 7467 }ATOM_INIT_REG_BLOCK; 7468 7469 #define END_OF_REG_INDEX_BLOCK 0x0ffff 7470 #define END_OF_REG_DATA_BLOCK 0x00000000 7471 #define ATOM_INIT_REG_MASK_FLAG 0x80 //Not used in BIOS 7472 #define CLOCK_RANGE_HIGHEST 0x00ffffff 7473 7474 #define VALUE_DWORD SIZEOF ULONG 7475 #define VALUE_SAME_AS_ABOVE 0 7476 #define VALUE_MASK_DWORD 0x84 7477 7478 #define INDEX_ACCESS_RANGE_BEGIN (VALUE_DWORD + 1) 7479 #define INDEX_ACCESS_RANGE_END (INDEX_ACCESS_RANGE_BEGIN + 1) 7480 #define VALUE_INDEX_ACCESS_SINGLE (INDEX_ACCESS_RANGE_END + 1) 7481 //#define ACCESS_MCIODEBUGIND 0x40 //defined in BIOS code 7482 #define ACCESS_PLACEHOLDER 0x80 7483 7484 7485 typedef struct _ATOM_MC_INIT_PARAM_TABLE 7486 { 7487 ATOM_COMMON_TABLE_HEADER sHeader; 7488 USHORT usAdjustARB_SEQDataOffset; 7489 USHORT usMCInitMemTypeTblOffset; 7490 USHORT usMCInitCommonTblOffset; 7491 USHORT usMCInitPowerDownTblOffset; 7492 ULONG ulARB_SEQDataBuf[32]; 7493 ATOM_INIT_REG_BLOCK asMCInitMemType; 7494 ATOM_INIT_REG_BLOCK asMCInitCommon; 7495 }ATOM_MC_INIT_PARAM_TABLE; 7496 7497 7498 typedef struct _ATOM_REG_INIT_SETTING 7499 { 7500 USHORT usRegIndex; 7501 ULONG ulRegValue; 7502 }ATOM_REG_INIT_SETTING; 7503 7504 typedef struct _ATOM_MC_INIT_PARAM_TABLE_V2_1 7505 { 7506 ATOM_COMMON_TABLE_HEADER sHeader; 7507 ULONG ulMCUcodeVersion; 7508 ULONG ulMCUcodeRomStartAddr; 7509 ULONG ulMCUcodeLength; 7510 USHORT usMcRegInitTableOffset; // offset of ATOM_REG_INIT_SETTING array for MC core register settings. 7511 USHORT usReserved; // offset of ATOM_INIT_REG_BLOCK for MC SEQ/PHY register setting 7512 }ATOM_MC_INIT_PARAM_TABLE_V2_1; 7513 7514 7515 #define _4Mx16 0x2 7516 #define _4Mx32 0x3 7517 #define _8Mx16 0x12 7518 #define _8Mx32 0x13 7519 #define _8Mx128 0x15 7520 #define _16Mx16 0x22 7521 #define _16Mx32 0x23 7522 #define _16Mx128 0x25 7523 #define _32Mx16 0x32 7524 #define _32Mx32 0x33 7525 #define _32Mx128 0x35 7526 #define _64Mx8 0x41 7527 #define _64Mx16 0x42 7528 #define _64Mx32 0x43 7529 #define _64Mx128 0x45 7530 #define _128Mx8 0x51 7531 #define _128Mx16 0x52 7532 #define _128Mx32 0x53 7533 #define _256Mx8 0x61 7534 #define _256Mx16 0x62 7535 #define _256Mx32 0x63 7536 #define _512Mx8 0x71 7537 #define _512Mx16 0x72 7538 7539 7540 #define SAMSUNG 0x1 7541 #define INFINEON 0x2 7542 #define ELPIDA 0x3 7543 #define ETRON 0x4 7544 #define NANYA 0x5 7545 #define HYNIX 0x6 7546 #define MOSEL 0x7 7547 #define WINBOND 0x8 7548 #define ESMT 0x9 7549 #define MICRON 0xF 7550 7551 #define QIMONDA INFINEON 7552 #define PROMOS MOSEL 7553 #define KRETON INFINEON 7554 #define ELIXIR NANYA 7555 #define MEZZA ELPIDA 7556 7557 7558 /////////////Support for GDDR5 MC uCode to reside in upper 64K of ROM///////////// 7559 7560 #define UCODE_ROM_START_ADDRESS 0x1b800 7561 #define UCODE_SIGNATURE 0x4375434d // 'MCuC' - MC uCode 7562 7563 //uCode block header for reference 7564 7565 typedef struct _MCuCodeHeader 7566 { 7567 ULONG ulSignature; 7568 UCHAR ucRevision; 7569 UCHAR ucChecksum; 7570 UCHAR ucReserved1; 7571 UCHAR ucReserved2; 7572 USHORT usParametersLength; 7573 USHORT usUCodeLength; 7574 USHORT usReserved1; 7575 USHORT usReserved2; 7576 } MCuCodeHeader; 7577 7578 ////////////////////////////////////////////////////////////////////////////////// 7579 7580 #define ATOM_MAX_NUMBER_OF_VRAM_MODULE 16 7581 7582 #define ATOM_VRAM_MODULE_MEMORY_VENDOR_ID_MASK 0xF 7583 typedef struct _ATOM_VRAM_MODULE_V1 7584 { 7585 ULONG ulReserved; 7586 USHORT usEMRSValue; 7587 USHORT usMRSValue; 7588 USHORT usReserved; 7589 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7590 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved; 7591 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender 7592 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7593 UCHAR ucRow; // Number of Row,in power of 2; 7594 UCHAR ucColumn; // Number of Column,in power of 2; 7595 UCHAR ucBank; // Nunber of Bank; 7596 UCHAR ucRank; // Number of Rank, in power of 2 7597 UCHAR ucChannelNum; // Number of channel; 7598 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7599 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7600 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7601 UCHAR ucReserved[2]; 7602 }ATOM_VRAM_MODULE_V1; 7603 7604 7605 typedef struct _ATOM_VRAM_MODULE_V2 7606 { 7607 ULONG ulReserved; 7608 ULONG ulFlags; // To enable/disable functionalities based on memory type 7609 ULONG ulEngineClock; // Override of default engine clock for particular memory type 7610 ULONG ulMemoryClock; // Override of default memory clock for particular memory type 7611 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7612 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7613 USHORT usEMRSValue; 7614 USHORT usMRSValue; 7615 USHORT usReserved; 7616 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7617 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7618 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7619 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32... 7620 UCHAR ucRow; // Number of Row,in power of 2; 7621 UCHAR ucColumn; // Number of Column,in power of 2; 7622 UCHAR ucBank; // Nunber of Bank; 7623 UCHAR ucRank; // Number of Rank, in power of 2 7624 UCHAR ucChannelNum; // Number of channel; 7625 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2 7626 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data; 7627 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data; 7628 UCHAR ucRefreshRateFactor; 7629 UCHAR ucReserved[3]; 7630 }ATOM_VRAM_MODULE_V2; 7631 7632 7633 typedef struct _ATOM_MEMORY_TIMING_FORMAT 7634 { 7635 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7636 union{ 7637 USHORT usMRS; // mode register 7638 USHORT usDDR3_MR0; 7639 }; 7640 union{ 7641 USHORT usEMRS; // extended mode register 7642 USHORT usDDR3_MR1; 7643 }; 7644 UCHAR ucCL; // CAS latency 7645 UCHAR ucWL; // WRITE Latency 7646 UCHAR uctRAS; // tRAS 7647 UCHAR uctRC; // tRC 7648 UCHAR uctRFC; // tRFC 7649 UCHAR uctRCDR; // tRCDR 7650 UCHAR uctRCDW; // tRCDW 7651 UCHAR uctRP; // tRP 7652 UCHAR uctRRD; // tRRD 7653 UCHAR uctWR; // tWR 7654 UCHAR uctWTR; // tWTR 7655 UCHAR uctPDIX; // tPDIX 7656 UCHAR uctFAW; // tFAW 7657 UCHAR uctAOND; // tAOND 7658 union 7659 { 7660 struct { 7661 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7662 UCHAR ucReserved; 7663 }; 7664 USHORT usDDR3_MR2; 7665 }; 7666 }ATOM_MEMORY_TIMING_FORMAT; 7667 7668 7669 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V1 7670 { 7671 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7672 USHORT usMRS; // mode register 7673 USHORT usEMRS; // extended mode register 7674 UCHAR ucCL; // CAS latency 7675 UCHAR ucWL; // WRITE Latency 7676 UCHAR uctRAS; // tRAS 7677 UCHAR uctRC; // tRC 7678 UCHAR uctRFC; // tRFC 7679 UCHAR uctRCDR; // tRCDR 7680 UCHAR uctRCDW; // tRCDW 7681 UCHAR uctRP; // tRP 7682 UCHAR uctRRD; // tRRD 7683 UCHAR uctWR; // tWR 7684 UCHAR uctWTR; // tWTR 7685 UCHAR uctPDIX; // tPDIX 7686 UCHAR uctFAW; // tFAW 7687 UCHAR uctAOND; // tAOND 7688 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7689 ////////////////////////////////////GDDR parameters/////////////////////////////////// 7690 UCHAR uctCCDL; // 7691 UCHAR uctCRCRL; // 7692 UCHAR uctCRCWL; // 7693 UCHAR uctCKE; // 7694 UCHAR uctCKRSE; // 7695 UCHAR uctCKRSX; // 7696 UCHAR uctFAW32; // 7697 UCHAR ucMR5lo; // 7698 UCHAR ucMR5hi; // 7699 UCHAR ucTerminator; 7700 }ATOM_MEMORY_TIMING_FORMAT_V1; 7701 7702 7703 7704 7705 typedef struct _ATOM_MEMORY_TIMING_FORMAT_V2 7706 { 7707 ULONG ulClkRange; // memory clock in 10kHz unit, when target memory clock is below this clock, use this memory timing 7708 USHORT usMRS; // mode register 7709 USHORT usEMRS; // extended mode register 7710 UCHAR ucCL; // CAS latency 7711 UCHAR ucWL; // WRITE Latency 7712 UCHAR uctRAS; // tRAS 7713 UCHAR uctRC; // tRC 7714 UCHAR uctRFC; // tRFC 7715 UCHAR uctRCDR; // tRCDR 7716 UCHAR uctRCDW; // tRCDW 7717 UCHAR uctRP; // tRP 7718 UCHAR uctRRD; // tRRD 7719 UCHAR uctWR; // tWR 7720 UCHAR uctWTR; // tWTR 7721 UCHAR uctPDIX; // tPDIX 7722 UCHAR uctFAW; // tFAW 7723 UCHAR uctAOND; // tAOND 7724 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon 7725 ////////////////////////////////////GDDR parameters/////////////////////////////////// 7726 UCHAR uctCCDL; // 7727 UCHAR uctCRCRL; // 7728 UCHAR uctCRCWL; // 7729 UCHAR uctCKE; // 7730 UCHAR uctCKRSE; // 7731 UCHAR uctCKRSX; // 7732 UCHAR uctFAW32; // 7733 UCHAR ucMR4lo; // 7734 UCHAR ucMR4hi; // 7735 UCHAR ucMR5lo; // 7736 UCHAR ucMR5hi; // 7737 UCHAR ucTerminator; 7738 UCHAR ucReserved; 7739 }ATOM_MEMORY_TIMING_FORMAT_V2; 7740 7741 7742 typedef struct _ATOM_MEMORY_FORMAT 7743 { 7744 ULONG ulDllDisClock; // memory DLL will be disable when target memory clock is below this clock 7745 union{ 7746 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7747 USHORT usDDR3_Reserved; // Not used for DDR3 memory 7748 }; 7749 union{ 7750 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7751 USHORT usDDR3_MR3; // Used for DDR3 memory 7752 }; 7753 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now; 7754 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed 7755 UCHAR ucRow; // Number of Row,in power of 2; 7756 UCHAR ucColumn; // Number of Column,in power of 2; 7757 UCHAR ucBank; // Nunber of Bank; 7758 UCHAR ucRank; // Number of Rank, in power of 2 7759 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8 7760 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register ) 7761 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms 7762 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7763 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7764 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc 7765 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5]; // Memory Timing block sort from lower clock to higher clock 7766 }ATOM_MEMORY_FORMAT; 7767 7768 7769 typedef struct _ATOM_VRAM_MODULE_V3 7770 { 7771 ULONG ulChannelMapCfg; // board dependent paramenter:Channel combination 7772 USHORT usSize; // size of ATOM_VRAM_MODULE_V3 7773 USHORT usDefaultMVDDQ; // board dependent parameter:Default Memory Core Voltage 7774 USHORT usDefaultMVDDC; // board dependent parameter:Default Memory IO Voltage 7775 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7776 UCHAR ucChannelNum; // board dependent parameter:Number of channel; 7777 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit 7778 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv 7779 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7780 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7781 ATOM_MEMORY_FORMAT asMemory; // describ all of video memory parameters from memory spec 7782 }ATOM_VRAM_MODULE_V3; 7783 7784 7785 //ATOM_VRAM_MODULE_V3.ucNPL_RT 7786 #define NPL_RT_MASK 0x0f 7787 #define BATTERY_ODT_MASK 0xc0 7788 7789 #define ATOM_VRAM_MODULE ATOM_VRAM_MODULE_V3 7790 7791 typedef struct _ATOM_VRAM_MODULE_V4 7792 { 7793 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7794 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7795 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7796 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7797 USHORT usReserved; 7798 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7799 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7800 UCHAR ucChannelNum; // Number of channels present in this module config 7801 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7802 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7803 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7804 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7805 UCHAR ucVREFI; // board dependent parameter 7806 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7807 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7808 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7809 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7810 UCHAR ucReserved[3]; 7811 7812 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7813 union{ 7814 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7815 USHORT usDDR3_Reserved; 7816 }; 7817 union{ 7818 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7819 USHORT usDDR3_MR3; // Used for DDR3 memory 7820 }; 7821 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7822 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7823 UCHAR ucReserved2[2]; 7824 ATOM_MEMORY_TIMING_FORMAT asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7825 }ATOM_VRAM_MODULE_V4; 7826 7827 #define VRAM_MODULE_V4_MISC_RANK_MASK 0x3 7828 #define VRAM_MODULE_V4_MISC_DUAL_RANK 0x1 7829 #define VRAM_MODULE_V4_MISC_BL_MASK 0x4 7830 #define VRAM_MODULE_V4_MISC_BL8 0x4 7831 #define VRAM_MODULE_V4_MISC_DUAL_CS 0x10 7832 7833 typedef struct _ATOM_VRAM_MODULE_V5 7834 { 7835 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7836 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7837 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7838 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7839 USHORT usReserved; 7840 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7841 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7842 UCHAR ucChannelNum; // Number of channels present in this module config 7843 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7844 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7845 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7846 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7847 UCHAR ucVREFI; // board dependent parameter 7848 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7849 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7850 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7851 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7852 UCHAR ucReserved[3]; 7853 7854 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7855 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7856 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7857 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7858 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7859 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7860 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7861 ATOM_MEMORY_TIMING_FORMAT_V1 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7862 }ATOM_VRAM_MODULE_V5; 7863 7864 7865 typedef struct _ATOM_VRAM_MODULE_V6 7866 { 7867 ULONG ulChannelMapCfg; // board dependent parameter: Channel combination 7868 USHORT usModuleSize; // size of ATOM_VRAM_MODULE_V4, make it easy for VBIOS to look for next entry of VRAM_MODULE 7869 USHORT usPrivateReserved; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7870 // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7871 USHORT usReserved; 7872 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module 7873 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now; 7874 UCHAR ucChannelNum; // Number of channels present in this module config 7875 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits 7876 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7877 UCHAR ucFlag; // To enable/disable functionalities based on memory type 7878 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8 7879 UCHAR ucVREFI; // board dependent parameter 7880 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters 7881 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7882 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!! 7883 // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7884 UCHAR ucReserved[3]; 7885 7886 //compare with V3, we flat the struct by merging ATOM_MEMORY_FORMAT (as is) into V4 as the same level 7887 USHORT usEMRS2Value; // EMRS2 Value is used for GDDR2 and GDDR4 memory type 7888 USHORT usEMRS3Value; // EMRS3 Value is used for GDDR2 and GDDR4 memory type 7889 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed 7890 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7891 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth 7892 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7893 ATOM_MEMORY_TIMING_FORMAT_V2 asMemTiming[5];//Memory Timing block sort from lower clock to higher clock 7894 }ATOM_VRAM_MODULE_V6; 7895 7896 typedef struct _ATOM_VRAM_MODULE_V7 7897 { 7898 // Design Specific Values 7899 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7900 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7901 USHORT usPrivateReserved; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7902 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7903 UCHAR ucExtMemoryID; // Current memory module ID 7904 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7905 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7906 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7907 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7908 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used. 7909 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7910 UCHAR ucVREFI; // Not used. 7911 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2. 7912 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble 7913 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros 7914 USHORT usSEQSettingOffset; 7915 UCHAR ucReserved; 7916 // Memory Module specific values 7917 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7918 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7919 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7920 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7921 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7922 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7923 char strMemPNString[20]; // part number end with '0'. 7924 }ATOM_VRAM_MODULE_V7; 7925 7926 7927 typedef struct _ATOM_VRAM_MODULE_V8 7928 { 7929 // Design Specific Values 7930 ULONG ulChannelMapCfg; // mmMC_SHARED_CHREMAP 7931 USHORT usModuleSize; // Size of ATOM_VRAM_MODULE_V7 7932 USHORT usMcRamCfg; // MC_ARB_RAMCFG (includes NOOFBANK,NOOFRANKS,NOOFROWS,NOOFCOLS) 7933 USHORT usEnableChannels; // bit vector which indicate which channels are enabled 7934 UCHAR ucExtMemoryID; // Current memory module ID 7935 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5 7936 UCHAR ucChannelNum; // Number of mem. channels supported in this module 7937 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 7938 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 7939 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit ) 7940 UCHAR ucMisc; // RANK_OF_THISMEMORY etc. 7941 UCHAR ucVREFI; // Not used. 7942 USHORT usReserved; // Not used 7943 USHORT usMemorySize; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 7944 UCHAR ucMcTunningSetId; // MC phy registers set per. 7945 UCHAR ucRowNum; 7946 // Memory Module specific values 7947 USHORT usEMRS2Value; // EMRS2/MR2 Value. 7948 USHORT usEMRS3Value; // EMRS3/MR3 Value. 7949 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code 7950 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 7951 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory 7952 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth 7953 7954 ULONG ulChannelMapCfg1; // channel mapping for channel8~15 7955 ULONG ulBankMapCfg; 7956 ULONG ulReserved; 7957 char strMemPNString[20]; // part number end with '0'. 7958 }ATOM_VRAM_MODULE_V8; 7959 7960 7961 typedef struct _ATOM_VRAM_INFO_V2 7962 { 7963 ATOM_COMMON_TABLE_HEADER sHeader; 7964 UCHAR ucNumOfVRAMModule; 7965 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7966 }ATOM_VRAM_INFO_V2; 7967 7968 typedef struct _ATOM_VRAM_INFO_V3 7969 { 7970 ATOM_COMMON_TABLE_HEADER sHeader; 7971 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7972 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7973 USHORT usRerseved; 7974 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 7975 UCHAR ucNumOfVRAMModule; 7976 ATOM_VRAM_MODULE aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7977 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7978 7979 }ATOM_VRAM_INFO_V3; 7980 7981 #define ATOM_VRAM_INFO_LAST ATOM_VRAM_INFO_V3 7982 7983 typedef struct _ATOM_VRAM_INFO_V4 7984 { 7985 ATOM_COMMON_TABLE_HEADER sHeader; 7986 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 7987 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 7988 USHORT usRerseved; 7989 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3 7990 ULONG ulMemDQ7_0BitRemap; // each DQ line ( 7~0) use 3bits, like: DQ0=Bit[2:0], DQ1:[5:3], ... DQ7:[23:21] 7991 UCHAR ucReservde[4]; 7992 UCHAR ucNumOfVRAMModule; 7993 ATOM_VRAM_MODULE_V4 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 7994 ATOM_INIT_REG_BLOCK asMemPatch; // for allocation 7995 }ATOM_VRAM_INFO_V4; 7996 7997 typedef struct _ATOM_VRAM_INFO_HEADER_V2_1 7998 { 7999 ATOM_COMMON_TABLE_HEADER sHeader; 8000 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8001 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8002 USHORT usPerBytePresetOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8003 USHORT usReserved[3]; 8004 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8005 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8006 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8007 UCHAR ucReserved; 8008 ATOM_VRAM_MODULE_V7 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8009 }ATOM_VRAM_INFO_HEADER_V2_1; 8010 8011 typedef struct _ATOM_VRAM_INFO_HEADER_V2_2 8012 { 8013 ATOM_COMMON_TABLE_HEADER sHeader; 8014 USHORT usMemAdjustTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory vendor specific MC adjust setting 8015 USHORT usMemClkPatchTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for memory clock specific MC setting 8016 USHORT usMcAdjustPerTileTblOffset; // offset of ATOM_INIT_REG_BLOCK structure for Per Byte Offset Preset Settings 8017 USHORT usMcPhyInitTableOffset; // offset of ATOM_INIT_REG_BLOCK structure for MC phy init set 8018 USHORT usDramDataRemapTblOffset; // offset of ATOM_DRAM_DATA_REMAP array to indicate DRAM data lane to GPU mapping 8019 USHORT usReserved1; 8020 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module 8021 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list 8022 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version 8023 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 8024 ATOM_VRAM_MODULE_V8 aVramInfo[ATOM_MAX_NUMBER_OF_VRAM_MODULE]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 8025 }ATOM_VRAM_INFO_HEADER_V2_2; 8026 8027 8028 typedef struct _ATOM_DRAM_DATA_REMAP 8029 { 8030 UCHAR ucByteRemapCh0; 8031 UCHAR ucByteRemapCh1; 8032 ULONG ulByte0BitRemapCh0; 8033 ULONG ulByte1BitRemapCh0; 8034 ULONG ulByte2BitRemapCh0; 8035 ULONG ulByte3BitRemapCh0; 8036 ULONG ulByte0BitRemapCh1; 8037 ULONG ulByte1BitRemapCh1; 8038 ULONG ulByte2BitRemapCh1; 8039 ULONG ulByte3BitRemapCh1; 8040 }ATOM_DRAM_DATA_REMAP; 8041 8042 typedef struct _ATOM_VRAM_GPIO_DETECTION_INFO 8043 { 8044 ATOM_COMMON_TABLE_HEADER sHeader; 8045 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator 8046 }ATOM_VRAM_GPIO_DETECTION_INFO; 8047 8048 8049 typedef struct _ATOM_MEMORY_TRAINING_INFO 8050 { 8051 ATOM_COMMON_TABLE_HEADER sHeader; 8052 UCHAR ucTrainingLoop; 8053 UCHAR ucReserved[3]; 8054 ATOM_INIT_REG_BLOCK asMemTrainingSetting; 8055 }ATOM_MEMORY_TRAINING_INFO; 8056 8057 8058 typedef struct _ATOM_MEMORY_TRAINING_INFO_V3_1 8059 { 8060 ATOM_COMMON_TABLE_HEADER sHeader; 8061 ULONG ulMCUcodeVersion; 8062 USHORT usMCIOInitLen; //len of ATOM_REG_INIT_SETTING array 8063 USHORT usMCUcodeLen; //len of ATOM_MC_UCODE_DATA array 8064 USHORT usMCIORegInitOffset; //point of offset of ATOM_REG_INIT_SETTING array 8065 USHORT usMCUcodeOffset; //point of offset of MC uCode ULONG array. 8066 }ATOM_MEMORY_TRAINING_INFO_V3_1; 8067 8068 8069 typedef struct SW_I2C_CNTL_DATA_PARAMETERS 8070 { 8071 UCHAR ucControl; 8072 UCHAR ucData; 8073 UCHAR ucSatus; 8074 UCHAR ucTemp; 8075 } SW_I2C_CNTL_DATA_PARAMETERS; 8076 8077 #define SW_I2C_CNTL_DATA_PS_ALLOCATION SW_I2C_CNTL_DATA_PARAMETERS 8078 8079 typedef struct _SW_I2C_IO_DATA_PARAMETERS 8080 { 8081 USHORT GPIO_Info; 8082 UCHAR ucAct; 8083 UCHAR ucData; 8084 } SW_I2C_IO_DATA_PARAMETERS; 8085 8086 #define SW_I2C_IO_DATA_PS_ALLOCATION SW_I2C_IO_DATA_PARAMETERS 8087 8088 /****************************SW I2C CNTL DEFINITIONS**********************/ 8089 #define SW_I2C_IO_RESET 0 8090 #define SW_I2C_IO_GET 1 8091 #define SW_I2C_IO_DRIVE 2 8092 #define SW_I2C_IO_SET 3 8093 #define SW_I2C_IO_START 4 8094 8095 #define SW_I2C_IO_CLOCK 0 8096 #define SW_I2C_IO_DATA 0x80 8097 8098 #define SW_I2C_IO_ZERO 0 8099 #define SW_I2C_IO_ONE 0x100 8100 8101 #define SW_I2C_CNTL_READ 0 8102 #define SW_I2C_CNTL_WRITE 1 8103 #define SW_I2C_CNTL_START 2 8104 #define SW_I2C_CNTL_STOP 3 8105 #define SW_I2C_CNTL_OPEN 4 8106 #define SW_I2C_CNTL_CLOSE 5 8107 #define SW_I2C_CNTL_WRITE1BIT 6 8108 8109 //==============================VESA definition Portion=============================== 8110 #define VESA_OEM_PRODUCT_REV '01.00' 8111 #define VESA_MODE_ATTRIBUTE_MODE_SUPPORT 0xBB //refer to VBE spec p.32, no TTY support 8112 #define VESA_MODE_WIN_ATTRIBUTE 7 8113 #define VESA_WIN_SIZE 64 8114 8115 typedef struct _PTR_32_BIT_STRUCTURE 8116 { 8117 USHORT Offset16; 8118 USHORT Segment16; 8119 } PTR_32_BIT_STRUCTURE; 8120 8121 typedef union _PTR_32_BIT_UNION 8122 { 8123 PTR_32_BIT_STRUCTURE SegmentOffset; 8124 ULONG Ptr32_Bit; 8125 } PTR_32_BIT_UNION; 8126 8127 typedef struct _VBE_1_2_INFO_BLOCK_UPDATABLE 8128 { 8129 UCHAR VbeSignature[4]; 8130 USHORT VbeVersion; 8131 PTR_32_BIT_UNION OemStringPtr; 8132 UCHAR Capabilities[4]; 8133 PTR_32_BIT_UNION VideoModePtr; 8134 USHORT TotalMemory; 8135 } VBE_1_2_INFO_BLOCK_UPDATABLE; 8136 8137 8138 typedef struct _VBE_2_0_INFO_BLOCK_UPDATABLE 8139 { 8140 VBE_1_2_INFO_BLOCK_UPDATABLE CommonBlock; 8141 USHORT OemSoftRev; 8142 PTR_32_BIT_UNION OemVendorNamePtr; 8143 PTR_32_BIT_UNION OemProductNamePtr; 8144 PTR_32_BIT_UNION OemProductRevPtr; 8145 } VBE_2_0_INFO_BLOCK_UPDATABLE; 8146 8147 typedef union _VBE_VERSION_UNION 8148 { 8149 VBE_2_0_INFO_BLOCK_UPDATABLE VBE_2_0_InfoBlock; 8150 VBE_1_2_INFO_BLOCK_UPDATABLE VBE_1_2_InfoBlock; 8151 } VBE_VERSION_UNION; 8152 8153 typedef struct _VBE_INFO_BLOCK 8154 { 8155 VBE_VERSION_UNION UpdatableVBE_Info; 8156 UCHAR Reserved[222]; 8157 UCHAR OemData[256]; 8158 } VBE_INFO_BLOCK; 8159 8160 typedef struct _VBE_FP_INFO 8161 { 8162 USHORT HSize; 8163 USHORT VSize; 8164 USHORT FPType; 8165 UCHAR RedBPP; 8166 UCHAR GreenBPP; 8167 UCHAR BlueBPP; 8168 UCHAR ReservedBPP; 8169 ULONG RsvdOffScrnMemSize; 8170 ULONG RsvdOffScrnMEmPtr; 8171 UCHAR Reserved[14]; 8172 } VBE_FP_INFO; 8173 8174 typedef struct _VESA_MODE_INFO_BLOCK 8175 { 8176 // Mandatory information for all VBE revisions 8177 USHORT ModeAttributes; // dw ? ; mode attributes 8178 UCHAR WinAAttributes; // db ? ; window A attributes 8179 UCHAR WinBAttributes; // db ? ; window B attributes 8180 USHORT WinGranularity; // dw ? ; window granularity 8181 USHORT WinSize; // dw ? ; window size 8182 USHORT WinASegment; // dw ? ; window A start segment 8183 USHORT WinBSegment; // dw ? ; window B start segment 8184 ULONG WinFuncPtr; // dd ? ; real mode pointer to window function 8185 USHORT BytesPerScanLine;// dw ? ; bytes per scan line 8186 8187 //; Mandatory information for VBE 1.2 and above 8188 USHORT XResolution; // dw ? ; horizontal resolution in pixels or characters 8189 USHORT YResolution; // dw ? ; vertical resolution in pixels or characters 8190 UCHAR XCharSize; // db ? ; character cell width in pixels 8191 UCHAR YCharSize; // db ? ; character cell height in pixels 8192 UCHAR NumberOfPlanes; // db ? ; number of memory planes 8193 UCHAR BitsPerPixel; // db ? ; bits per pixel 8194 UCHAR NumberOfBanks; // db ? ; number of banks 8195 UCHAR MemoryModel; // db ? ; memory model type 8196 UCHAR BankSize; // db ? ; bank size in KB 8197 UCHAR NumberOfImagePages;// db ? ; number of images 8198 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function 8199 8200 //; Direct Color fields(required for direct/6 and YUV/7 memory models) 8201 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits 8202 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask 8203 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits 8204 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask 8205 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits 8206 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask 8207 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits 8208 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask 8209 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes 8210 8211 //; Mandatory information for VBE 2.0 and above 8212 ULONG PhysBasePtr; // dd ? ; physical address for flat memory frame buffer 8213 ULONG Reserved_1; // dd 0 ; reserved - always set to 0 8214 USHORT Reserved_2; // dw 0 ; reserved - always set to 0 8215 8216 //; Mandatory information for VBE 3.0 and above 8217 USHORT LinBytesPerScanLine; // dw ? ; bytes per scan line for linear modes 8218 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes 8219 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes 8220 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes) 8221 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes) 8222 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes) 8223 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes) 8224 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes) 8225 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes) 8226 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes) 8227 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes) 8228 ULONG MaxPixelClock; // dd ? ; maximum pixel clock(in Hz) for graphics mode 8229 UCHAR Reserved; // db 190 dup (0) 8230 } VESA_MODE_INFO_BLOCK; 8231 8232 // BIOS function CALLS 8233 #define ATOM_BIOS_EXTENDED_FUNCTION_CODE 0xA0 // ATI Extended Function code 8234 #define ATOM_BIOS_FUNCTION_COP_MODE 0x00 8235 #define ATOM_BIOS_FUNCTION_SHORT_QUERY1 0x04 8236 #define ATOM_BIOS_FUNCTION_SHORT_QUERY2 0x05 8237 #define ATOM_BIOS_FUNCTION_SHORT_QUERY3 0x06 8238 #define ATOM_BIOS_FUNCTION_GET_DDC 0x0B 8239 #define ATOM_BIOS_FUNCTION_ASIC_DSTATE 0x0E 8240 #define ATOM_BIOS_FUNCTION_DEBUG_PLAY 0x0F 8241 #define ATOM_BIOS_FUNCTION_STV_STD 0x16 8242 #define ATOM_BIOS_FUNCTION_DEVICE_DET 0x17 8243 #define ATOM_BIOS_FUNCTION_DEVICE_SWITCH 0x18 8244 8245 #define ATOM_BIOS_FUNCTION_PANEL_CONTROL 0x82 8246 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_DET 0x83 8247 #define ATOM_BIOS_FUNCTION_OLD_DEVICE_SWITCH 0x84 8248 #define ATOM_BIOS_FUNCTION_HW_ICON 0x8A 8249 #define ATOM_BIOS_FUNCTION_SET_CMOS 0x8B 8250 #define SUB_FUNCTION_UPDATE_DISPLAY_INFO 0x8000 // Sub function 80 8251 #define SUB_FUNCTION_UPDATE_EXPANSION_INFO 0x8100 // Sub function 80 8252 8253 #define ATOM_BIOS_FUNCTION_DISPLAY_INFO 0x8D 8254 #define ATOM_BIOS_FUNCTION_DEVICE_ON_OFF 0x8E 8255 #define ATOM_BIOS_FUNCTION_VIDEO_STATE 0x8F 8256 #define ATOM_SUB_FUNCTION_GET_CRITICAL_STATE 0x0300 // Sub function 03 8257 #define ATOM_SUB_FUNCTION_GET_LIDSTATE 0x0700 // Sub function 7 8258 #define ATOM_SUB_FUNCTION_THERMAL_STATE_NOTICE 0x1400 // Notify caller the current thermal state 8259 #define ATOM_SUB_FUNCTION_CRITICAL_STATE_NOTICE 0x8300 // Notify caller the current critical state 8260 #define ATOM_SUB_FUNCTION_SET_LIDSTATE 0x8500 // Sub function 85 8261 #define ATOM_SUB_FUNCTION_GET_REQ_DISPLAY_FROM_SBIOS_MODE 0x8900// Sub function 89 8262 #define ATOM_SUB_FUNCTION_INFORM_ADC_SUPPORT 0x9400 // Notify caller that ADC is supported 8263 8264 8265 #define ATOM_BIOS_FUNCTION_VESA_DPMS 0x4F10 // Set DPMS 8266 #define ATOM_SUB_FUNCTION_SET_DPMS 0x0001 // BL: Sub function 01 8267 #define ATOM_SUB_FUNCTION_GET_DPMS 0x0002 // BL: Sub function 02 8268 #define ATOM_PARAMETER_VESA_DPMS_ON 0x0000 // BH Parameter for DPMS ON. 8269 #define ATOM_PARAMETER_VESA_DPMS_STANDBY 0x0100 // BH Parameter for DPMS STANDBY 8270 #define ATOM_PARAMETER_VESA_DPMS_SUSPEND 0x0200 // BH Parameter for DPMS SUSPEND 8271 #define ATOM_PARAMETER_VESA_DPMS_OFF 0x0400 // BH Parameter for DPMS OFF 8272 #define ATOM_PARAMETER_VESA_DPMS_REDUCE_ON 0x0800 // BH Parameter for DPMS REDUCE ON (NOT SUPPORTED) 8273 8274 #define ATOM_BIOS_RETURN_CODE_MASK 0x0000FF00L 8275 #define ATOM_BIOS_REG_HIGH_MASK 0x0000FF00L 8276 #define ATOM_BIOS_REG_LOW_MASK 0x000000FFL 8277 8278 // structure used for VBIOS only 8279 8280 //DispOutInfoTable 8281 typedef struct _ASIC_TRANSMITTER_INFO 8282 { 8283 USHORT usTransmitterObjId; 8284 USHORT usSupportDevice; 8285 UCHAR ucTransmitterCmdTblId; 8286 UCHAR ucConfig; 8287 UCHAR ucEncoderID; //available 1st encoder ( default ) 8288 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional ) 8289 UCHAR uc2ndEncoderID; 8290 UCHAR ucReserved; 8291 }ASIC_TRANSMITTER_INFO; 8292 8293 #define ASIC_TRANSMITTER_INFO_CONFIG__DVO_SDR_MODE 0x01 8294 #define ASIC_TRANSMITTER_INFO_CONFIG__COHERENT_MODE 0x02 8295 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODEROBJ_ID_MASK 0xc4 8296 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_A 0x00 8297 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_B 0x04 8298 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_C 0x40 8299 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_D 0x44 8300 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_E 0x80 8301 #define ASIC_TRANSMITTER_INFO_CONFIG__ENCODER_F 0x84 8302 8303 typedef struct _ASIC_ENCODER_INFO 8304 { 8305 UCHAR ucEncoderID; 8306 UCHAR ucEncoderConfig; 8307 USHORT usEncoderCmdTblId; 8308 }ASIC_ENCODER_INFO; 8309 8310 typedef struct _ATOM_DISP_OUT_INFO 8311 { 8312 ATOM_COMMON_TABLE_HEADER sHeader; 8313 USHORT ptrTransmitterInfo; 8314 USHORT ptrEncoderInfo; 8315 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8316 ASIC_ENCODER_INFO asEncoderInfo[1]; 8317 }ATOM_DISP_OUT_INFO; 8318 8319 8320 typedef struct _ATOM_DISP_OUT_INFO_V2 8321 { 8322 ATOM_COMMON_TABLE_HEADER sHeader; 8323 USHORT ptrTransmitterInfo; 8324 USHORT ptrEncoderInfo; 8325 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8326 ASIC_TRANSMITTER_INFO asTransmitterInfo[1]; 8327 ASIC_ENCODER_INFO asEncoderInfo[1]; 8328 }ATOM_DISP_OUT_INFO_V2; 8329 8330 8331 typedef struct _ATOM_DISP_CLOCK_ID { 8332 UCHAR ucPpllId; 8333 UCHAR ucPpllAttribute; 8334 }ATOM_DISP_CLOCK_ID; 8335 8336 // ucPpllAttribute 8337 #define CLOCK_SOURCE_SHAREABLE 0x01 8338 #define CLOCK_SOURCE_DP_MODE 0x02 8339 #define CLOCK_SOURCE_NONE_DP_MODE 0x04 8340 8341 //DispOutInfoTable 8342 typedef struct _ASIC_TRANSMITTER_INFO_V2 8343 { 8344 USHORT usTransmitterObjId; 8345 USHORT usDispClkIdOffset; // point to clock source id list supported by Encoder Object 8346 UCHAR ucTransmitterCmdTblId; 8347 UCHAR ucConfig; 8348 UCHAR ucEncoderID; // available 1st encoder ( default ) 8349 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional ) 8350 UCHAR uc2ndEncoderID; 8351 UCHAR ucReserved; 8352 }ASIC_TRANSMITTER_INFO_V2; 8353 8354 typedef struct _ATOM_DISP_OUT_INFO_V3 8355 { 8356 ATOM_COMMON_TABLE_HEADER sHeader; 8357 USHORT ptrTransmitterInfo; 8358 USHORT ptrEncoderInfo; 8359 USHORT ptrMainCallParserFar; // direct address of main parser call in VBIOS binary. 8360 USHORT usReserved; 8361 UCHAR ucDCERevision; 8362 UCHAR ucMaxDispEngineNum; 8363 UCHAR ucMaxActiveDispEngineNum; 8364 UCHAR ucMaxPPLLNum; 8365 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE 8366 UCHAR ucDispCaps; 8367 UCHAR ucReserved[2]; 8368 ASIC_TRANSMITTER_INFO_V2 asTransmitterInfo[1]; // for alligment only 8369 }ATOM_DISP_OUT_INFO_V3; 8370 8371 //ucDispCaps 8372 #define DISPLAY_CAPS__DP_PCLK_FROM_PPLL 0x01 8373 #define DISPLAY_CAPS__FORCE_DISPDEV_CONNECTED 0x02 8374 8375 typedef enum CORE_REF_CLK_SOURCE{ 8376 CLOCK_SRC_XTALIN=0, 8377 CLOCK_SRC_XO_IN=1, 8378 CLOCK_SRC_XO_IN2=2, 8379 }CORE_REF_CLK_SOURCE; 8380 8381 // DispDevicePriorityInfo 8382 typedef struct _ATOM_DISPLAY_DEVICE_PRIORITY_INFO 8383 { 8384 ATOM_COMMON_TABLE_HEADER sHeader; 8385 USHORT asDevicePriority[16]; 8386 }ATOM_DISPLAY_DEVICE_PRIORITY_INFO; 8387 8388 //ProcessAuxChannelTransactionTable 8389 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8390 { 8391 USHORT lpAuxRequest; 8392 USHORT lpDataOut; 8393 UCHAR ucChannelID; 8394 union 8395 { 8396 UCHAR ucReplyStatus; 8397 UCHAR ucDelay; 8398 }; 8399 UCHAR ucDataOutLen; 8400 UCHAR ucReserved; 8401 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS; 8402 8403 //ProcessAuxChannelTransactionTable 8404 typedef struct _PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 8405 { 8406 USHORT lpAuxRequest; 8407 USHORT lpDataOut; 8408 UCHAR ucChannelID; 8409 union 8410 { 8411 UCHAR ucReplyStatus; 8412 UCHAR ucDelay; 8413 }; 8414 UCHAR ucDataOutLen; 8415 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 8416 }PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2; 8417 8418 #define PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS 8419 8420 //GetSinkType 8421 8422 typedef struct _DP_ENCODER_SERVICE_PARAMETERS 8423 { 8424 USHORT ucLinkClock; 8425 union 8426 { 8427 UCHAR ucConfig; // for DP training command 8428 UCHAR ucI2cId; // use for GET_SINK_TYPE command 8429 }; 8430 UCHAR ucAction; 8431 UCHAR ucStatus; 8432 UCHAR ucLaneNum; 8433 UCHAR ucReserved[2]; 8434 }DP_ENCODER_SERVICE_PARAMETERS; 8435 8436 // ucAction 8437 #define ATOM_DP_ACTION_GET_SINK_TYPE 0x01 8438 8439 #define DP_ENCODER_SERVICE_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS 8440 8441 8442 typedef struct _DP_ENCODER_SERVICE_PARAMETERS_V2 8443 { 8444 USHORT usExtEncoderObjId; // External Encoder Object Id, output parameter only, use when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8445 UCHAR ucAuxId; 8446 UCHAR ucAction; 8447 UCHAR ucSinkType; // Iput and Output parameters. 8448 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION 8449 UCHAR ucReserved[2]; 8450 }DP_ENCODER_SERVICE_PARAMETERS_V2; 8451 8452 typedef struct _DP_ENCODER_SERVICE_PS_ALLOCATION_V2 8453 { 8454 DP_ENCODER_SERVICE_PARAMETERS_V2 asDPServiceParam; 8455 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 asAuxParam; 8456 }DP_ENCODER_SERVICE_PS_ALLOCATION_V2; 8457 8458 // ucAction 8459 #define DP_SERVICE_V2_ACTION_GET_SINK_TYPE 0x01 8460 #define DP_SERVICE_V2_ACTION_DET_LCD_CONNECTION 0x02 8461 8462 8463 // DP_TRAINING_TABLE 8464 #define DPCD_SET_LINKRATE_LANENUM_PATTERN1_TBL_ADDR ATOM_DP_TRAINING_TBL_ADDR 8465 #define DPCD_SET_SS_CNTL_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 8 ) 8466 #define DPCD_SET_LANE_VSWING_PREEMP_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 16 ) 8467 #define DPCD_SET_TRAINING_PATTERN0_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 24 ) 8468 #define DPCD_SET_TRAINING_PATTERN2_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 32) 8469 #define DPCD_GET_LINKRATE_LANENUM_SS_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 40) 8470 #define DPCD_GET_LANE_STATUS_ADJUST_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 48) 8471 #define DP_I2C_AUX_DDC_WRITE_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 60) 8472 #define DP_I2C_AUX_DDC_WRITE_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 64) 8473 #define DP_I2C_AUX_DDC_READ_START_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 72) 8474 #define DP_I2C_AUX_DDC_READ_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 76) 8475 #define DP_I2C_AUX_DDC_WRITE_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 80) 8476 #define DP_I2C_AUX_DDC_READ_END_TBL_ADDR (ATOM_DP_TRAINING_TBL_ADDR + 84) 8477 8478 8479 typedef struct _PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8480 { 8481 UCHAR ucI2CSpeed; 8482 union 8483 { 8484 UCHAR ucRegIndex; 8485 UCHAR ucStatus; 8486 }; 8487 USHORT lpI2CDataOut; 8488 UCHAR ucFlag; 8489 UCHAR ucTransBytes; 8490 UCHAR ucSlaveAddr; 8491 UCHAR ucLineNumber; 8492 }PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS; 8493 8494 #define PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS 8495 8496 //ucFlag 8497 #define HW_I2C_WRITE 1 8498 #define HW_I2C_READ 0 8499 #define I2C_2BYTE_ADDR 0x02 8500 8501 /****************************************************************************/ 8502 // Structures used by HW_Misc_OperationTable 8503 /****************************************************************************/ 8504 typedef struct _ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 8505 { 8506 UCHAR ucCmd; // Input: To tell which action to take 8507 UCHAR ucReserved[3]; 8508 ULONG ulReserved; 8509 }ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1; 8510 8511 typedef struct _ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1 8512 { 8513 UCHAR ucReturnCode; // Output: Return value base on action was taken 8514 UCHAR ucReserved[3]; 8515 ULONG ulReserved; 8516 }ATOM_HW_MISC_OPERATION_OUTPUT_PARAMETER_V1_1; 8517 8518 // Actions code 8519 #define ATOM_GET_SDI_SUPPORT 0xF0 8520 8521 // Return code 8522 #define ATOM_UNKNOWN_CMD 0 8523 #define ATOM_FEATURE_NOT_SUPPORTED 1 8524 #define ATOM_FEATURE_SUPPORTED 2 8525 8526 typedef struct _ATOM_HW_MISC_OPERATION_PS_ALLOCATION 8527 { 8528 ATOM_HW_MISC_OPERATION_INPUT_PARAMETER_V1_1 sInput_Output; 8529 PROCESS_I2C_CHANNEL_TRANSACTION_PARAMETERS sReserved; 8530 }ATOM_HW_MISC_OPERATION_PS_ALLOCATION; 8531 8532 /****************************************************************************/ 8533 8534 typedef struct _SET_HWBLOCK_INSTANCE_PARAMETER_V2 8535 { 8536 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ... 8537 UCHAR ucReserved[3]; 8538 }SET_HWBLOCK_INSTANCE_PARAMETER_V2; 8539 8540 #define HWBLKINST_INSTANCE_MASK 0x07 8541 #define HWBLKINST_HWBLK_MASK 0xF0 8542 #define HWBLKINST_HWBLK_SHIFT 0x04 8543 8544 //ucHWBlock 8545 #define SELECT_DISP_ENGINE 0 8546 #define SELECT_DISP_PLL 1 8547 #define SELECT_DCIO_UNIPHY_LINK0 2 8548 #define SELECT_DCIO_UNIPHY_LINK1 3 8549 #define SELECT_DCIO_IMPCAL 4 8550 #define SELECT_DCIO_DIG 6 8551 #define SELECT_CRTC_PIXEL_RATE 7 8552 #define SELECT_VGA_BLK 8 8553 8554 // DIGTransmitterInfoTable structure used to program UNIPHY settings 8555 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_1{ 8556 ATOM_COMMON_TABLE_HEADER sHeader; 8557 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8558 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8559 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8560 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8561 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8562 }DIG_TRANSMITTER_INFO_HEADER_V3_1; 8563 8564 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_2{ 8565 ATOM_COMMON_TABLE_HEADER sHeader; 8566 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8567 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8568 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8569 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8570 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8571 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8572 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8573 }DIG_TRANSMITTER_INFO_HEADER_V3_2; 8574 8575 8576 typedef struct _DIG_TRANSMITTER_INFO_HEADER_V3_3{ 8577 ATOM_COMMON_TABLE_HEADER sHeader; 8578 USHORT usDPVsPreEmphSettingOffset; // offset of PHY_ANALOG_SETTING_INFO * with DP Voltage Swing and Pre-Emphasis for each Link clock 8579 USHORT usPhyAnalogRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with None-DP mode Analog Setting's register Info 8580 USHORT usPhyAnalogSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with None-DP mode Analog Setting for each link clock range 8581 USHORT usPhyPllRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy Pll register Info 8582 USHORT usPhyPllSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy Pll Settings 8583 USHORT usDPSSRegListOffset; // offset of CLOCK_CONDITION_REGESTER_INFO* with Phy SS Pll register Info 8584 USHORT usDPSSSettingOffset; // offset of CLOCK_CONDITION_SETTING_ENTRY* with Phy SS Pll Settings 8585 USHORT usEDPVsLegacyModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Legacy Mode Voltage Swing and Pre-Emphasis for each Link clock 8586 USHORT useDPVsLowVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Low VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8587 USHORT useDPVsHighVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP High VDiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8588 USHORT useDPVsStretchModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Stretch Mode Voltage Swing and Pre-Emphasis for each Link clock 8589 USHORT useDPVsSingleVdiffModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vdiff Mode Voltage Swing and Pre-Emphasis for each Link clock 8590 USHORT useDPVsVariablePremModeOffset; // offset of PHY_ANALOG_SETTING_INFO * with eDP Single Vidff+Variable PreEmphasis Voltage Swing and Pre-Emphasis for each Link clock 8591 }DIG_TRANSMITTER_INFO_HEADER_V3_3; 8592 8593 8594 typedef struct _CLOCK_CONDITION_REGESTER_INFO{ 8595 USHORT usRegisterIndex; 8596 UCHAR ucStartBit; 8597 UCHAR ucEndBit; 8598 }CLOCK_CONDITION_REGESTER_INFO; 8599 8600 typedef struct _CLOCK_CONDITION_SETTING_ENTRY{ 8601 USHORT usMaxClockFreq; 8602 UCHAR ucEncodeMode; 8603 UCHAR ucPhySel; 8604 ULONG ulAnalogSetting[1]; 8605 }CLOCK_CONDITION_SETTING_ENTRY; 8606 8607 typedef struct _CLOCK_CONDITION_SETTING_INFO{ 8608 USHORT usEntrySize; 8609 CLOCK_CONDITION_SETTING_ENTRY asClkCondSettingEntry[1]; 8610 }CLOCK_CONDITION_SETTING_INFO; 8611 8612 typedef struct _PHY_CONDITION_REG_VAL{ 8613 ULONG ulCondition; 8614 ULONG ulRegVal; 8615 }PHY_CONDITION_REG_VAL; 8616 8617 typedef struct _PHY_CONDITION_REG_VAL_V2{ 8618 ULONG ulCondition; 8619 UCHAR ucCondition2; 8620 ULONG ulRegVal; 8621 }PHY_CONDITION_REG_VAL_V2; 8622 8623 typedef struct _PHY_CONDITION_REG_INFO{ 8624 USHORT usRegIndex; 8625 USHORT usSize; 8626 PHY_CONDITION_REG_VAL asRegVal[1]; 8627 }PHY_CONDITION_REG_INFO; 8628 8629 typedef struct _PHY_CONDITION_REG_INFO_V2{ 8630 USHORT usRegIndex; 8631 USHORT usSize; 8632 PHY_CONDITION_REG_VAL_V2 asRegVal[1]; 8633 }PHY_CONDITION_REG_INFO_V2; 8634 8635 typedef struct _PHY_ANALOG_SETTING_INFO{ 8636 UCHAR ucEncodeMode; 8637 UCHAR ucPhySel; 8638 USHORT usSize; 8639 PHY_CONDITION_REG_INFO asAnalogSetting[1]; 8640 }PHY_ANALOG_SETTING_INFO; 8641 8642 typedef struct _PHY_ANALOG_SETTING_INFO_V2{ 8643 UCHAR ucEncodeMode; 8644 UCHAR ucPhySel; 8645 USHORT usSize; 8646 PHY_CONDITION_REG_INFO_V2 asAnalogSetting[1]; 8647 }PHY_ANALOG_SETTING_INFO_V2; 8648 8649 8650 typedef struct _GFX_HAVESTING_PARAMETERS { 8651 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM 8652 UCHAR ucReserved; //reserved 8653 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array 8654 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array 8655 } GFX_HAVESTING_PARAMETERS; 8656 8657 //ucGfxBlkId 8658 #define GFX_HARVESTING_CU_ID 0 8659 #define GFX_HARVESTING_RB_ID 1 8660 #define GFX_HARVESTING_PRIM_ID 2 8661 8662 8663 typedef struct _VBIOS_ROM_HEADER{ 8664 UCHAR PciRomSignature[2]; 8665 UCHAR ucPciRomSizeIn512bytes; 8666 UCHAR ucJumpCoreMainInitBIOS; 8667 USHORT usLabelCoreMainInitBIOS; 8668 UCHAR PciReservedSpace[18]; 8669 USHORT usPciDataStructureOffset; 8670 UCHAR Rsvd1d_1a[4]; 8671 char strIbm[3]; 8672 UCHAR CheckSum[14]; 8673 UCHAR ucBiosMsgNumber; 8674 char str761295520[16]; 8675 USHORT usLabelCoreVPOSTNoMode; 8676 USHORT usSpecialPostOffset; 8677 UCHAR ucSpeicalPostImageSizeIn512Bytes; 8678 UCHAR Rsved47_45[3]; 8679 USHORT usROM_HeaderInformationTableOffset; 8680 UCHAR Rsved4f_4a[6]; 8681 char strBuildTimeStamp[20]; 8682 UCHAR ucJumpCoreXFuncFarHandler; 8683 USHORT usCoreXFuncFarHandlerOffset; 8684 UCHAR ucRsved67; 8685 UCHAR ucJumpCoreVFuncFarHandler; 8686 USHORT usCoreVFuncFarHandlerOffset; 8687 UCHAR Rsved6d_6b[3]; 8688 USHORT usATOM_BIOS_MESSAGE_Offset; 8689 }VBIOS_ROM_HEADER; 8690 8691 /****************************************************************************/ 8692 //Portion VI: Definitinos for vbios MC scratch registers that driver used 8693 /****************************************************************************/ 8694 8695 #define MC_MISC0__MEMORY_TYPE_MASK 0xF0000000 8696 #define MC_MISC0__MEMORY_TYPE__GDDR1 0x10000000 8697 #define MC_MISC0__MEMORY_TYPE__DDR2 0x20000000 8698 #define MC_MISC0__MEMORY_TYPE__GDDR3 0x30000000 8699 #define MC_MISC0__MEMORY_TYPE__GDDR4 0x40000000 8700 #define MC_MISC0__MEMORY_TYPE__GDDR5 0x50000000 8701 #define MC_MISC0__MEMORY_TYPE__HBM 0x60000000 8702 #define MC_MISC0__MEMORY_TYPE__DDR3 0xB0000000 8703 8704 #define ATOM_MEM_TYPE_DDR_STRING "DDR" 8705 #define ATOM_MEM_TYPE_DDR2_STRING "DDR2" 8706 #define ATOM_MEM_TYPE_GDDR3_STRING "GDDR3" 8707 #define ATOM_MEM_TYPE_GDDR4_STRING "GDDR4" 8708 #define ATOM_MEM_TYPE_GDDR5_STRING "GDDR5" 8709 #define ATOM_MEM_TYPE_HBM_STRING "HBM" 8710 #define ATOM_MEM_TYPE_DDR3_STRING "DDR3" 8711 8712 /****************************************************************************/ 8713 //Portion VII: Definitinos being oboselete 8714 /****************************************************************************/ 8715 8716 //========================================================================================== 8717 //Remove the definitions below when driver is ready! 8718 typedef struct _ATOM_DAC_INFO 8719 { 8720 ATOM_COMMON_TABLE_HEADER sHeader; 8721 USHORT usMaxFrequency; // in 10kHz unit 8722 USHORT usReserved; 8723 }ATOM_DAC_INFO; 8724 8725 8726 typedef struct _COMPASSIONATE_DATA 8727 { 8728 ATOM_COMMON_TABLE_HEADER sHeader; 8729 8730 //============================== DAC1 portion 8731 UCHAR ucDAC1_BG_Adjustment; 8732 UCHAR ucDAC1_DAC_Adjustment; 8733 USHORT usDAC1_FORCE_Data; 8734 //============================== DAC2 portion 8735 UCHAR ucDAC2_CRT2_BG_Adjustment; 8736 UCHAR ucDAC2_CRT2_DAC_Adjustment; 8737 USHORT usDAC2_CRT2_FORCE_Data; 8738 USHORT usDAC2_CRT2_MUX_RegisterIndex; 8739 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8740 UCHAR ucDAC2_NTSC_BG_Adjustment; 8741 UCHAR ucDAC2_NTSC_DAC_Adjustment; 8742 USHORT usDAC2_TV1_FORCE_Data; 8743 USHORT usDAC2_TV1_MUX_RegisterIndex; 8744 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8745 UCHAR ucDAC2_CV_BG_Adjustment; 8746 UCHAR ucDAC2_CV_DAC_Adjustment; 8747 USHORT usDAC2_CV_FORCE_Data; 8748 USHORT usDAC2_CV_MUX_RegisterIndex; 8749 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low 8750 UCHAR ucDAC2_PAL_BG_Adjustment; 8751 UCHAR ucDAC2_PAL_DAC_Adjustment; 8752 USHORT usDAC2_TV2_FORCE_Data; 8753 }COMPASSIONATE_DATA; 8754 8755 /****************************Supported Device Info Table Definitions**********************/ 8756 // ucConnectInfo: 8757 // [7:4] - connector type 8758 // = 1 - VGA connector 8759 // = 2 - DVI-I 8760 // = 3 - DVI-D 8761 // = 4 - DVI-A 8762 // = 5 - SVIDEO 8763 // = 6 - COMPOSITE 8764 // = 7 - LVDS 8765 // = 8 - DIGITAL LINK 8766 // = 9 - SCART 8767 // = 0xA - HDMI_type A 8768 // = 0xB - HDMI_type B 8769 // = 0xE - Special case1 (DVI+DIN) 8770 // Others=TBD 8771 // [3:0] - DAC Associated 8772 // = 0 - no DAC 8773 // = 1 - DACA 8774 // = 2 - DACB 8775 // = 3 - External DAC 8776 // Others=TBD 8777 // 8778 8779 typedef struct _ATOM_CONNECTOR_INFO 8780 { 8781 #if ATOM_BIG_ENDIAN 8782 UCHAR bfConnectorType:4; 8783 UCHAR bfAssociatedDAC:4; 8784 #else 8785 UCHAR bfAssociatedDAC:4; 8786 UCHAR bfConnectorType:4; 8787 #endif 8788 }ATOM_CONNECTOR_INFO; 8789 8790 typedef union _ATOM_CONNECTOR_INFO_ACCESS 8791 { 8792 ATOM_CONNECTOR_INFO sbfAccess; 8793 UCHAR ucAccess; 8794 }ATOM_CONNECTOR_INFO_ACCESS; 8795 8796 typedef struct _ATOM_CONNECTOR_INFO_I2C 8797 { 8798 ATOM_CONNECTOR_INFO_ACCESS sucConnectorInfo; 8799 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; 8800 }ATOM_CONNECTOR_INFO_I2C; 8801 8802 8803 typedef struct _ATOM_SUPPORTED_DEVICES_INFO 8804 { 8805 ATOM_COMMON_TABLE_HEADER sHeader; 8806 USHORT usDeviceSupport; 8807 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO]; 8808 }ATOM_SUPPORTED_DEVICES_INFO; 8809 8810 #define NO_INT_SRC_MAPPED 0xFF 8811 8812 typedef struct _ATOM_CONNECTOR_INC_SRC_BITMAP 8813 { 8814 UCHAR ucIntSrcBitmap; 8815 }ATOM_CONNECTOR_INC_SRC_BITMAP; 8816 8817 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2 8818 { 8819 ATOM_COMMON_TABLE_HEADER sHeader; 8820 USHORT usDeviceSupport; 8821 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8822 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE_INFO_2]; 8823 }ATOM_SUPPORTED_DEVICES_INFO_2; 8824 8825 typedef struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 8826 { 8827 ATOM_COMMON_TABLE_HEADER sHeader; 8828 USHORT usDeviceSupport; 8829 ATOM_CONNECTOR_INFO_I2C asConnInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8830 ATOM_CONNECTOR_INC_SRC_BITMAP asIntSrcInfo[ATOM_MAX_SUPPORTED_DEVICE]; 8831 }ATOM_SUPPORTED_DEVICES_INFO_2d1; 8832 8833 #define ATOM_SUPPORTED_DEVICES_INFO_LAST ATOM_SUPPORTED_DEVICES_INFO_2d1 8834 8835 8836 8837 typedef struct _ATOM_MISC_CONTROL_INFO 8838 { 8839 USHORT usFrequency; 8840 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control 8841 UCHAR ucPLL_DutyCycle; // PLL duty cycle control 8842 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control 8843 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control 8844 }ATOM_MISC_CONTROL_INFO; 8845 8846 8847 #define ATOM_MAX_MISC_INFO 4 8848 8849 typedef struct _ATOM_TMDS_INFO 8850 { 8851 ATOM_COMMON_TABLE_HEADER sHeader; 8852 USHORT usMaxFrequency; // in 10Khz 8853 ATOM_MISC_CONTROL_INFO asMiscInfo[ATOM_MAX_MISC_INFO]; 8854 }ATOM_TMDS_INFO; 8855 8856 8857 typedef struct _ATOM_ENCODER_ANALOG_ATTRIBUTE 8858 { 8859 UCHAR ucTVStandard; //Same as TV standards defined above, 8860 UCHAR ucPadding[1]; 8861 }ATOM_ENCODER_ANALOG_ATTRIBUTE; 8862 8863 typedef struct _ATOM_ENCODER_DIGITAL_ATTRIBUTE 8864 { 8865 UCHAR ucAttribute; //Same as other digital encoder attributes defined above 8866 UCHAR ucPadding[1]; 8867 }ATOM_ENCODER_DIGITAL_ATTRIBUTE; 8868 8869 typedef union _ATOM_ENCODER_ATTRIBUTE 8870 { 8871 ATOM_ENCODER_ANALOG_ATTRIBUTE sAlgAttrib; 8872 ATOM_ENCODER_DIGITAL_ATTRIBUTE sDigAttrib; 8873 }ATOM_ENCODER_ATTRIBUTE; 8874 8875 8876 typedef struct _DVO_ENCODER_CONTROL_PARAMETERS 8877 { 8878 USHORT usPixelClock; 8879 USHORT usEncoderID; 8880 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only. 8881 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT 8882 ATOM_ENCODER_ATTRIBUTE usDevAttr; 8883 }DVO_ENCODER_CONTROL_PARAMETERS; 8884 8885 typedef struct _DVO_ENCODER_CONTROL_PS_ALLOCATION 8886 { 8887 DVO_ENCODER_CONTROL_PARAMETERS sDVOEncoder; 8888 WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion 8889 }DVO_ENCODER_CONTROL_PS_ALLOCATION; 8890 8891 8892 #define ATOM_XTMDS_ASIC_SI164_ID 1 8893 #define ATOM_XTMDS_ASIC_SI178_ID 2 8894 #define ATOM_XTMDS_ASIC_TFP513_ID 3 8895 #define ATOM_XTMDS_SUPPORTED_SINGLELINK 0x00000001 8896 #define ATOM_XTMDS_SUPPORTED_DUALLINK 0x00000002 8897 #define ATOM_XTMDS_MVPU_FPGA 0x00000004 8898 8899 8900 typedef struct _ATOM_XTMDS_INFO 8901 { 8902 ATOM_COMMON_TABLE_HEADER sHeader; 8903 USHORT usSingleLinkMaxFrequency; 8904 ATOM_I2C_ID_CONFIG_ACCESS sucI2cId; //Point the ID on which I2C is used to control external chip 8905 UCHAR ucXtransimitterID; 8906 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported 8907 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters 8908 // due to design. This ID is used to alert driver that the sequence is not "standard"! 8909 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip 8910 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip 8911 }ATOM_XTMDS_INFO; 8912 8913 typedef struct _DFP_DPMS_STATUS_CHANGE_PARAMETERS 8914 { 8915 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off 8916 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX.... 8917 UCHAR ucPadding[2]; 8918 }DFP_DPMS_STATUS_CHANGE_PARAMETERS; 8919 8920 /****************************Legacy Power Play Table Definitions **********************/ 8921 8922 //Definitions for ulPowerPlayMiscInfo 8923 #define ATOM_PM_MISCINFO_SPLIT_CLOCK 0x00000000L 8924 #define ATOM_PM_MISCINFO_USING_MCLK_SRC 0x00000001L 8925 #define ATOM_PM_MISCINFO_USING_SCLK_SRC 0x00000002L 8926 8927 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT 0x00000004L 8928 #define ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH 0x00000008L 8929 8930 #define ATOM_PM_MISCINFO_LOAD_PERFORMANCE_EN 0x00000010L 8931 8932 #define ATOM_PM_MISCINFO_ENGINE_CLOCK_CONTRL_EN 0x00000020L 8933 #define ATOM_PM_MISCINFO_MEMORY_CLOCK_CONTRL_EN 0x00000040L 8934 #define ATOM_PM_MISCINFO_PROGRAM_VOLTAGE 0x00000080L //When this bit set, ucVoltageDropIndex is not an index for GPIO pin, but a voltage ID that SW needs program 8935 8936 #define ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN 0x00000100L 8937 #define ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN 0x00000200L 8938 #define ATOM_PM_MISCINFO_ASIC_SLEEP_MODE_EN 0x00000400L 8939 #define ATOM_PM_MISCINFO_LOAD_BALANCE_EN 0x00000800L 8940 #define ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE 0x00001000L 8941 #define ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE 0x00002000L 8942 #define ATOM_PM_MISCINFO_LOW_LCD_REFRESH_RATE 0x00004000L 8943 8944 #define ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE 0x00008000L 8945 #define ATOM_PM_MISCINFO_OVER_CLOCK_MODE 0x00010000L 8946 #define ATOM_PM_MISCINFO_OVER_DRIVE_MODE 0x00020000L 8947 #define ATOM_PM_MISCINFO_POWER_SAVING_MODE 0x00040000L 8948 #define ATOM_PM_MISCINFO_THERMAL_DIODE_MODE 0x00080000L 8949 8950 #define ATOM_PM_MISCINFO_FRAME_MODULATION_MASK 0x00300000L //0-FM Disable, 1-2 level FM, 2-4 level FM, 3-Reserved 8951 #define ATOM_PM_MISCINFO_FRAME_MODULATION_SHIFT 20 8952 8953 #define ATOM_PM_MISCINFO_DYN_CLK_3D_IDLE 0x00400000L 8954 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2 0x00800000L 8955 #define ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4 0x01000000L 8956 #define ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN 0x02000000L //When set, Dynamic 8957 #define ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN 0x04000000L //When set, Dynamic 8958 #define ATOM_PM_MISCINFO_3D_ACCELERATION_EN 0x08000000L //When set, This mode is for acceleated 3D mode 8959 8960 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_MASK 0x70000000L //1-Optimal Battery Life Group, 2-High Battery, 3-Balanced, 4-High Performance, 5- Optimal Performance (Default state with Default clocks) 8961 #define ATOM_PM_MISCINFO_POWERPLAY_SETTINGS_GROUP_SHIFT 28 8962 #define ATOM_PM_MISCINFO_ENABLE_BACK_BIAS 0x80000000L 8963 8964 #define ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE 0x00000001L 8965 #define ATOM_PM_MISCINFO2_MULTI_DISPLAY_SUPPORT 0x00000002L 8966 #define ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN 0x00000004L 8967 #define ATOM_PM_MISCINFO2_FS3D_OVERDRIVE_INFO 0x00000008L 8968 #define ATOM_PM_MISCINFO2_FORCEDLOWPWR_MODE 0x00000010L 8969 #define ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN 0x00000020L 8970 #define ATOM_PM_MISCINFO2_VIDEO_PLAYBACK_CAPABLE 0x00000040L //If this bit is set in multi-pp mode, then driver will pack up one with the minior power consumption. 8971 //If it's not set in any pp mode, driver will use its default logic to pick a pp mode in video playback 8972 #define ATOM_PM_MISCINFO2_NOT_VALID_ON_DC 0x00000080L 8973 #define ATOM_PM_MISCINFO2_STUTTER_MODE_EN 0x00000100L 8974 #define ATOM_PM_MISCINFO2_UVD_SUPPORT_MODE 0x00000200L 8975 8976 //ucTableFormatRevision=1 8977 //ucTableContentRevision=1 8978 typedef struct _ATOM_POWERMODE_INFO 8979 { 8980 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8981 ULONG ulReserved1; // must set to 0 8982 ULONG ulReserved2; // must set to 0 8983 USHORT usEngineClock; 8984 USHORT usMemoryClock; 8985 UCHAR ucVoltageDropIndex; // index to GPIO table 8986 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 8987 UCHAR ucMinTemperature; 8988 UCHAR ucMaxTemperature; 8989 UCHAR ucNumPciELanes; // number of PCIE lanes 8990 }ATOM_POWERMODE_INFO; 8991 8992 //ucTableFormatRevision=2 8993 //ucTableContentRevision=1 8994 typedef struct _ATOM_POWERMODE_INFO_V2 8995 { 8996 ULONG ulMiscInfo; //The power level should be arranged in ascending order 8997 ULONG ulMiscInfo2; 8998 ULONG ulEngineClock; 8999 ULONG ulMemoryClock; 9000 UCHAR ucVoltageDropIndex; // index to GPIO table 9001 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9002 UCHAR ucMinTemperature; 9003 UCHAR ucMaxTemperature; 9004 UCHAR ucNumPciELanes; // number of PCIE lanes 9005 }ATOM_POWERMODE_INFO_V2; 9006 9007 //ucTableFormatRevision=2 9008 //ucTableContentRevision=2 9009 typedef struct _ATOM_POWERMODE_INFO_V3 9010 { 9011 ULONG ulMiscInfo; //The power level should be arranged in ascending order 9012 ULONG ulMiscInfo2; 9013 ULONG ulEngineClock; 9014 ULONG ulMemoryClock; 9015 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table 9016 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate 9017 UCHAR ucMinTemperature; 9018 UCHAR ucMaxTemperature; 9019 UCHAR ucNumPciELanes; // number of PCIE lanes 9020 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table 9021 }ATOM_POWERMODE_INFO_V3; 9022 9023 9024 #define ATOM_MAX_NUMBEROF_POWER_BLOCK 8 9025 9026 #define ATOM_PP_OVERDRIVE_INTBITMAP_AUXWIN 0x01 9027 #define ATOM_PP_OVERDRIVE_INTBITMAP_OVERDRIVE 0x02 9028 9029 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM63 0x01 9030 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1032 0x02 9031 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ADM1030 0x03 9032 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_MUA6649 0x04 9033 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_LM64 0x05 9034 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_F75375 0x06 9035 #define ATOM_PP_OVERDRIVE_THERMALCONTROLLER_ASC7512 0x07 // Andigilog 9036 9037 9038 typedef struct _ATOM_POWERPLAY_INFO 9039 { 9040 ATOM_COMMON_TABLE_HEADER sHeader; 9041 UCHAR ucOverdriveThermalController; 9042 UCHAR ucOverdriveI2cLine; 9043 UCHAR ucOverdriveIntBitmap; 9044 UCHAR ucOverdriveControllerAddress; 9045 UCHAR ucSizeOfPowerModeEntry; 9046 UCHAR ucNumOfPowerModeEntries; 9047 ATOM_POWERMODE_INFO asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9048 }ATOM_POWERPLAY_INFO; 9049 9050 typedef struct _ATOM_POWERPLAY_INFO_V2 9051 { 9052 ATOM_COMMON_TABLE_HEADER sHeader; 9053 UCHAR ucOverdriveThermalController; 9054 UCHAR ucOverdriveI2cLine; 9055 UCHAR ucOverdriveIntBitmap; 9056 UCHAR ucOverdriveControllerAddress; 9057 UCHAR ucSizeOfPowerModeEntry; 9058 UCHAR ucNumOfPowerModeEntries; 9059 ATOM_POWERMODE_INFO_V2 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9060 }ATOM_POWERPLAY_INFO_V2; 9061 9062 typedef struct _ATOM_POWERPLAY_INFO_V3 9063 { 9064 ATOM_COMMON_TABLE_HEADER sHeader; 9065 UCHAR ucOverdriveThermalController; 9066 UCHAR ucOverdriveI2cLine; 9067 UCHAR ucOverdriveIntBitmap; 9068 UCHAR ucOverdriveControllerAddress; 9069 UCHAR ucSizeOfPowerModeEntry; 9070 UCHAR ucNumOfPowerModeEntries; 9071 ATOM_POWERMODE_INFO_V3 asPowerPlayInfo[ATOM_MAX_NUMBEROF_POWER_BLOCK]; 9072 }ATOM_POWERPLAY_INFO_V3; 9073 9074 9075 9076 /**************************************************************************/ 9077 9078 9079 // Following definitions are for compatiblity issue in different SW components. 9080 #define ATOM_MASTER_DATA_TABLE_REVISION 0x01 9081 #define Object_Info Object_Header 9082 #define AdjustARB_SEQ MC_InitParameter 9083 #define VRAM_GPIO_DetectionInfo VoltageObjectInfo 9084 #define ASIC_VDDCI_Info ASIC_ProfilingInfo 9085 #define ASIC_MVDDQ_Info MemoryTrainingInfo 9086 #define SS_Info PPLL_SS_Info 9087 #define ASIC_MVDDC_Info ASIC_InternalSS_Info 9088 #define DispDevicePriorityInfo SaveRestoreInfo 9089 #define DispOutInfo TV_VideoMode 9090 9091 9092 #define ATOM_ENCODER_OBJECT_TABLE ATOM_OBJECT_TABLE 9093 #define ATOM_CONNECTOR_OBJECT_TABLE ATOM_OBJECT_TABLE 9094 9095 //New device naming, remove them when both DAL/VBIOS is ready 9096 #define DFP2I_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9097 #define DFP2I_OUTPUT_CONTROL_PS_ALLOCATION DFP2I_OUTPUT_CONTROL_PARAMETERS 9098 9099 #define DFP1X_OUTPUT_CONTROL_PARAMETERS CRT1_OUTPUT_CONTROL_PARAMETERS 9100 #define DFP1X_OUTPUT_CONTROL_PS_ALLOCATION DFP1X_OUTPUT_CONTROL_PARAMETERS 9101 9102 #define DFP1I_OUTPUT_CONTROL_PARAMETERS DFP1_OUTPUT_CONTROL_PARAMETERS 9103 #define DFP1I_OUTPUT_CONTROL_PS_ALLOCATION DFP1_OUTPUT_CONTROL_PS_ALLOCATION 9104 9105 #define ATOM_DEVICE_DFP1I_SUPPORT ATOM_DEVICE_DFP1_SUPPORT 9106 #define ATOM_DEVICE_DFP1X_SUPPORT ATOM_DEVICE_DFP2_SUPPORT 9107 9108 #define ATOM_DEVICE_DFP1I_INDEX ATOM_DEVICE_DFP1_INDEX 9109 #define ATOM_DEVICE_DFP1X_INDEX ATOM_DEVICE_DFP2_INDEX 9110 9111 #define ATOM_DEVICE_DFP2I_INDEX 0x00000009 9112 #define ATOM_DEVICE_DFP2I_SUPPORT (0x1L << ATOM_DEVICE_DFP2I_INDEX) 9113 9114 #define ATOM_S0_DFP1I ATOM_S0_DFP1 9115 #define ATOM_S0_DFP1X ATOM_S0_DFP2 9116 9117 #define ATOM_S0_DFP2I 0x00200000L 9118 #define ATOM_S0_DFP2Ib2 0x20 9119 9120 #define ATOM_S2_DFP1I_DPMS_STATE ATOM_S2_DFP1_DPMS_STATE 9121 #define ATOM_S2_DFP1X_DPMS_STATE ATOM_S2_DFP2_DPMS_STATE 9122 9123 #define ATOM_S2_DFP2I_DPMS_STATE 0x02000000L 9124 #define ATOM_S2_DFP2I_DPMS_STATEb3 0x02 9125 9126 #define ATOM_S3_DFP2I_ACTIVEb1 0x02 9127 9128 #define ATOM_S3_DFP1I_ACTIVE ATOM_S3_DFP1_ACTIVE 9129 #define ATOM_S3_DFP1X_ACTIVE ATOM_S3_DFP2_ACTIVE 9130 9131 #define ATOM_S3_DFP2I_ACTIVE 0x00000200L 9132 9133 #define ATOM_S3_DFP1I_CRTC_ACTIVE ATOM_S3_DFP1_CRTC_ACTIVE 9134 #define ATOM_S3_DFP1X_CRTC_ACTIVE ATOM_S3_DFP2_CRTC_ACTIVE 9135 #define ATOM_S3_DFP2I_CRTC_ACTIVE 0x02000000L 9136 9137 9138 #define ATOM_S3_DFP2I_CRTC_ACTIVEb3 0x02 9139 #define ATOM_S5_DOS_REQ_DFP2Ib1 0x02 9140 9141 #define ATOM_S5_DOS_REQ_DFP2I 0x0200 9142 #define ATOM_S6_ACC_REQ_DFP1I ATOM_S6_ACC_REQ_DFP1 9143 #define ATOM_S6_ACC_REQ_DFP1X ATOM_S6_ACC_REQ_DFP2 9144 9145 #define ATOM_S6_ACC_REQ_DFP2Ib3 0x02 9146 #define ATOM_S6_ACC_REQ_DFP2I 0x02000000L 9147 9148 #define TMDS1XEncoderControl DVOEncoderControl 9149 #define DFP1XOutputControl DVOOutputControl 9150 9151 #define ExternalDFPOutputControl DFP1XOutputControl 9152 #define EnableExternalTMDS_Encoder TMDS1XEncoderControl 9153 9154 #define DFP1IOutputControl TMDSAOutputControl 9155 #define DFP2IOutputControl LVTMAOutputControl 9156 9157 #define DAC1_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9158 #define DAC1_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9159 9160 #define DAC2_ENCODER_CONTROL_PARAMETERS DAC_ENCODER_CONTROL_PARAMETERS 9161 #define DAC2_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PS_ALLOCATION 9162 9163 #define ucDac1Standard ucDacStandard 9164 #define ucDac2Standard ucDacStandard 9165 9166 #define TMDS1EncoderControl TMDSAEncoderControl 9167 #define TMDS2EncoderControl LVTMAEncoderControl 9168 9169 #define DFP1OutputControl TMDSAOutputControl 9170 #define DFP2OutputControl LVTMAOutputControl 9171 #define CRT1OutputControl DAC1OutputControl 9172 #define CRT2OutputControl DAC2OutputControl 9173 9174 //These two lines will be removed for sure in a few days, will follow up with Michael V. 9175 #define EnableLVDS_SS EnableSpreadSpectrumOnPPLL 9176 #define ENABLE_LVDS_SS_PARAMETERS_V3 ENABLE_SPREAD_SPECTRUM_ON_PPLL 9177 9178 #define ATOM_S2_CRT1_DPMS_STATE 0x00010000L 9179 #define ATOM_S2_LCD1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9180 #define ATOM_S2_TV1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9181 #define ATOM_S2_DFP1_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9182 #define ATOM_S2_CRT2_DPMS_STATE ATOM_S2_CRT1_DPMS_STATE 9183 9184 #define ATOM_S6_ACC_REQ_TV2 0x00400000L 9185 #define ATOM_DEVICE_TV2_INDEX 0x00000006 9186 #define ATOM_DEVICE_TV2_SUPPORT (0x1L << ATOM_DEVICE_TV2_INDEX) 9187 #define ATOM_S0_TV2 0x00100000L 9188 #define ATOM_S3_TV2_ACTIVE ATOM_S3_DFP6_ACTIVE 9189 #define ATOM_S3_TV2_CRTC_ACTIVE ATOM_S3_DFP6_CRTC_ACTIVE 9190 9191 /*********************************************************************************/ 9192 9193 #pragma pack() // BIOS data must use byte alignment 9194 9195 #pragma pack(1) 9196 9197 typedef struct _ATOM_HOLE_INFO 9198 { 9199 USHORT usOffset; // offset of the hole ( from the start of the binary ) 9200 USHORT usLength; // length of the hole ( in bytes ) 9201 }ATOM_HOLE_INFO; 9202 9203 typedef struct _ATOM_SERVICE_DESCRIPTION 9204 { 9205 UCHAR ucRevision; // Holes set revision 9206 UCHAR ucAlgorithm; // Hash algorithm 9207 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production ) 9208 UCHAR ucReserved; 9209 USHORT usSigOffset; // Signature offset ( from the start of the binary ) 9210 USHORT usSigLength; // Signature length 9211 }ATOM_SERVICE_DESCRIPTION; 9212 9213 9214 typedef struct _ATOM_SERVICE_INFO 9215 { 9216 ATOM_COMMON_TABLE_HEADER asHeader; 9217 ATOM_SERVICE_DESCRIPTION asDescr; 9218 UCHAR ucholesNo; // number of holes that follow 9219 ATOM_HOLE_INFO holes[1]; // array of hole descriptions 9220 }ATOM_SERVICE_INFO; 9221 9222 9223 9224 #pragma pack() // BIOS data must use byte alignment 9225 9226 // 9227 // AMD ACPI Table 9228 // 9229 #pragma pack(1) 9230 9231 typedef struct { 9232 ULONG Signature; 9233 ULONG TableLength; //Length 9234 UCHAR Revision; 9235 UCHAR Checksum; 9236 UCHAR OemId[6]; 9237 UCHAR OemTableId[8]; //UINT64 OemTableId; 9238 ULONG OemRevision; 9239 ULONG CreatorId; 9240 ULONG CreatorRevision; 9241 } AMD_ACPI_DESCRIPTION_HEADER; 9242 /* 9243 //EFI_ACPI_DESCRIPTION_HEADER from AcpiCommon.h 9244 typedef struct { 9245 UINT32 Signature; //0x0 9246 UINT32 Length; //0x4 9247 UINT8 Revision; //0x8 9248 UINT8 Checksum; //0x9 9249 UINT8 OemId[6]; //0xA 9250 UINT64 OemTableId; //0x10 9251 UINT32 OemRevision; //0x18 9252 UINT32 CreatorId; //0x1C 9253 UINT32 CreatorRevision; //0x20 9254 }EFI_ACPI_DESCRIPTION_HEADER; 9255 */ 9256 typedef struct { 9257 AMD_ACPI_DESCRIPTION_HEADER SHeader; 9258 UCHAR TableUUID[16]; //0x24 9259 ULONG VBIOSImageOffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 9260 ULONG Lib1ImageOffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 9261 ULONG Reserved[4]; //0x3C 9262 }UEFI_ACPI_VFCT; 9263 9264 typedef struct { 9265 ULONG PCIBus; //0x4C 9266 ULONG PCIDevice; //0x50 9267 ULONG PCIFunction; //0x54 9268 USHORT VendorID; //0x58 9269 USHORT DeviceID; //0x5A 9270 USHORT SSVID; //0x5C 9271 USHORT SSID; //0x5E 9272 ULONG Revision; //0x60 9273 ULONG ImageLength; //0x64 9274 }VFCT_IMAGE_HEADER; 9275 9276 9277 typedef struct { 9278 VFCT_IMAGE_HEADER VbiosHeader; 9279 UCHAR VbiosContent[1]; 9280 }GOP_VBIOS_CONTENT; 9281 9282 typedef struct { 9283 VFCT_IMAGE_HEADER Lib1Header; 9284 UCHAR Lib1Content[1]; 9285 }GOP_LIB1_CONTENT; 9286 9287 #pragma pack() 9288 9289 9290 #endif /* _ATOMBIOS_H */ 9291 9292 #include "pptable.h" 9293 9294
Indexes created Tue Oct 14 21:09:58 GMT 2025