cgs_common.h revision 1.1
1 /* $NetBSD: cgs_common.h,v 1.1 2018/08/27 01:34:47 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * 25 */ 26 #ifndef _CGS_COMMON_H 27 #define _CGS_COMMON_H 28 29 #include "amd_shared.h" 30 31 /** 32 * enum cgs_gpu_mem_type - GPU memory types 33 */ 34 enum cgs_gpu_mem_type { 35 CGS_GPU_MEM_TYPE__VISIBLE_FB, 36 CGS_GPU_MEM_TYPE__INVISIBLE_FB, 37 CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB, 38 CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB, 39 CGS_GPU_MEM_TYPE__GART_CACHEABLE, 40 CGS_GPU_MEM_TYPE__GART_WRITECOMBINE 41 }; 42 43 /** 44 * enum cgs_ind_reg - Indirect register spaces 45 */ 46 enum cgs_ind_reg { 47 CGS_IND_REG__MMIO, 48 CGS_IND_REG__PCIE, 49 CGS_IND_REG__SMC, 50 CGS_IND_REG__UVD_CTX, 51 CGS_IND_REG__DIDT, 52 CGS_IND_REG__AUDIO_ENDPT 53 }; 54 55 /** 56 * enum cgs_clock - Clocks controlled by the SMU 57 */ 58 enum cgs_clock { 59 CGS_CLOCK__SCLK, 60 CGS_CLOCK__MCLK, 61 CGS_CLOCK__VCLK, 62 CGS_CLOCK__DCLK, 63 CGS_CLOCK__ECLK, 64 CGS_CLOCK__ACLK, 65 CGS_CLOCK__ICLK, 66 /* ... */ 67 }; 68 69 /** 70 * enum cgs_engine - Engines that can be statically power-gated 71 */ 72 enum cgs_engine { 73 CGS_ENGINE__UVD, 74 CGS_ENGINE__VCE, 75 CGS_ENGINE__VP8, 76 CGS_ENGINE__ACP_DMA, 77 CGS_ENGINE__ACP_DSP0, 78 CGS_ENGINE__ACP_DSP1, 79 CGS_ENGINE__ISP, 80 /* ... */ 81 }; 82 83 /** 84 * enum cgs_voltage_planes - Voltage planes for external camera HW 85 */ 86 enum cgs_voltage_planes { 87 CGS_VOLTAGE_PLANE__SENSOR0, 88 CGS_VOLTAGE_PLANE__SENSOR1, 89 /* ... */ 90 }; 91 92 /* 93 * enum cgs_ucode_id - Firmware types for different IPs 94 */ 95 enum cgs_ucode_id { 96 CGS_UCODE_ID_SMU = 0, 97 CGS_UCODE_ID_SDMA0, 98 CGS_UCODE_ID_SDMA1, 99 CGS_UCODE_ID_CP_CE, 100 CGS_UCODE_ID_CP_PFP, 101 CGS_UCODE_ID_CP_ME, 102 CGS_UCODE_ID_CP_MEC, 103 CGS_UCODE_ID_CP_MEC_JT1, 104 CGS_UCODE_ID_CP_MEC_JT2, 105 CGS_UCODE_ID_GMCON_RENG, 106 CGS_UCODE_ID_RLC_G, 107 CGS_UCODE_ID_MAXIMUM, 108 }; 109 110 /** 111 * struct cgs_clock_limits - Clock limits 112 * 113 * Clocks are specified in 10KHz units. 114 */ 115 struct cgs_clock_limits { 116 unsigned min; /**< Minimum supported frequency */ 117 unsigned max; /**< Maxumim supported frequency */ 118 unsigned sustainable; /**< Thermally sustainable frequency */ 119 }; 120 121 /** 122 * struct cgs_firmware_info - Firmware information 123 */ 124 struct cgs_firmware_info { 125 uint16_t version; 126 uint16_t feature_version; 127 uint32_t image_size; 128 uint64_t mc_addr; 129 void *kptr; 130 }; 131 132 typedef unsigned long cgs_handle_t; 133 134 /** 135 * cgs_gpu_mem_info() - Return information about memory heaps 136 * @cgs_device: opaque device handle 137 * @type: memory type 138 * @mc_start: Start MC address of the heap (output) 139 * @mc_size: MC address space size (output) 140 * @mem_size: maximum amount of memory available for allocation (output) 141 * 142 * This function returns information about memory heaps. The type 143 * parameter is used to select the memory heap. The mc_start and 144 * mc_size for GART heaps may be bigger than the memory available for 145 * allocation. 146 * 147 * mc_start and mc_size are undefined for non-contiguous FB memory 148 * types, since buffers allocated with these types may or may not be 149 * GART mapped. 150 * 151 * Return: 0 on success, -errno otherwise 152 */ 153 typedef int (*cgs_gpu_mem_info_t)(void *cgs_device, enum cgs_gpu_mem_type type, 154 uint64_t *mc_start, uint64_t *mc_size, 155 uint64_t *mem_size); 156 157 /** 158 * cgs_gmap_kmem() - map kernel memory to GART aperture 159 * @cgs_device: opaque device handle 160 * @kmem: pointer to kernel memory 161 * @size: size to map 162 * @min_offset: minimum offset from start of GART aperture 163 * @max_offset: maximum offset from start of GART aperture 164 * @kmem_handle: kernel memory handle (output) 165 * @mcaddr: MC address (output) 166 * 167 * Return: 0 on success, -errno otherwise 168 */ 169 typedef int (*cgs_gmap_kmem_t)(void *cgs_device, void *kmem, uint64_t size, 170 uint64_t min_offset, uint64_t max_offset, 171 cgs_handle_t *kmem_handle, uint64_t *mcaddr); 172 173 /** 174 * cgs_gunmap_kmem() - unmap kernel memory 175 * @cgs_device: opaque device handle 176 * @kmem_handle: kernel memory handle returned by gmap_kmem 177 * 178 * Return: 0 on success, -errno otherwise 179 */ 180 typedef int (*cgs_gunmap_kmem_t)(void *cgs_device, cgs_handle_t kmem_handle); 181 182 /** 183 * cgs_alloc_gpu_mem() - Allocate GPU memory 184 * @cgs_device: opaque device handle 185 * @type: memory type 186 * @size: size in bytes 187 * @align: alignment in bytes 188 * @min_offset: minimum offset from start of heap 189 * @max_offset: maximum offset from start of heap 190 * @handle: memory handle (output) 191 * 192 * The memory types CGS_GPU_MEM_TYPE_*_CONTIG_FB force contiguous 193 * memory allocation. This guarantees that the MC address returned by 194 * cgs_gmap_gpu_mem is not mapped through the GART. The non-contiguous 195 * FB memory types may be GART mapped depending on memory 196 * fragmentation and memory allocator policies. 197 * 198 * If min/max_offset are non-0, the allocation will be forced to 199 * reside between these offsets in its respective memory heap. The 200 * base address that the offset relates to, depends on the memory 201 * type. 202 * 203 * - CGS_GPU_MEM_TYPE__*_CONTIG_FB: FB MC base address 204 * - CGS_GPU_MEM_TYPE__GART_*: GART aperture base address 205 * - others: undefined, don't use with max_offset 206 * 207 * Return: 0 on success, -errno otherwise 208 */ 209 typedef int (*cgs_alloc_gpu_mem_t)(void *cgs_device, enum cgs_gpu_mem_type type, 210 uint64_t size, uint64_t align, 211 uint64_t min_offset, uint64_t max_offset, 212 cgs_handle_t *handle); 213 214 /** 215 * cgs_free_gpu_mem() - Free GPU memory 216 * @cgs_device: opaque device handle 217 * @handle: memory handle returned by alloc or import 218 * 219 * Return: 0 on success, -errno otherwise 220 */ 221 typedef int (*cgs_free_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 222 223 /** 224 * cgs_gmap_gpu_mem() - GPU-map GPU memory 225 * @cgs_device: opaque device handle 226 * @handle: memory handle returned by alloc or import 227 * @mcaddr: MC address (output) 228 * 229 * Ensures that a buffer is GPU accessible and returns its MC address. 230 * 231 * Return: 0 on success, -errno otherwise 232 */ 233 typedef int (*cgs_gmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 234 uint64_t *mcaddr); 235 236 /** 237 * cgs_gunmap_gpu_mem() - GPU-unmap GPU memory 238 * @cgs_device: opaque device handle 239 * @handle: memory handle returned by alloc or import 240 * 241 * Allows the buffer to be migrated while it's not used by the GPU. 242 * 243 * Return: 0 on success, -errno otherwise 244 */ 245 typedef int (*cgs_gunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 246 247 /** 248 * cgs_kmap_gpu_mem() - Kernel-map GPU memory 249 * 250 * @cgs_device: opaque device handle 251 * @handle: memory handle returned by alloc or import 252 * @map: Kernel virtual address the memory was mapped to (output) 253 * 254 * Return: 0 on success, -errno otherwise 255 */ 256 typedef int (*cgs_kmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle, 257 void **map); 258 259 /** 260 * cgs_kunmap_gpu_mem() - Kernel-unmap GPU memory 261 * @cgs_device: opaque device handle 262 * @handle: memory handle returned by alloc or import 263 * 264 * Return: 0 on success, -errno otherwise 265 */ 266 typedef int (*cgs_kunmap_gpu_mem_t)(void *cgs_device, cgs_handle_t handle); 267 268 /** 269 * cgs_read_register() - Read an MMIO register 270 * @cgs_device: opaque device handle 271 * @offset: register offset 272 * 273 * Return: register value 274 */ 275 typedef uint32_t (*cgs_read_register_t)(void *cgs_device, unsigned offset); 276 277 /** 278 * cgs_write_register() - Write an MMIO register 279 * @cgs_device: opaque device handle 280 * @offset: register offset 281 * @value: register value 282 */ 283 typedef void (*cgs_write_register_t)(void *cgs_device, unsigned offset, 284 uint32_t value); 285 286 /** 287 * cgs_read_ind_register() - Read an indirect register 288 * @cgs_device: opaque device handle 289 * @offset: register offset 290 * 291 * Return: register value 292 */ 293 typedef uint32_t (*cgs_read_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 294 unsigned index); 295 296 /** 297 * cgs_write_ind_register() - Write an indirect register 298 * @cgs_device: opaque device handle 299 * @offset: register offset 300 * @value: register value 301 */ 302 typedef void (*cgs_write_ind_register_t)(void *cgs_device, enum cgs_ind_reg space, 303 unsigned index, uint32_t value); 304 305 /** 306 * cgs_read_pci_config_byte() - Read byte from PCI configuration space 307 * @cgs_device: opaque device handle 308 * @addr: address 309 * 310 * Return: Value read 311 */ 312 typedef uint8_t (*cgs_read_pci_config_byte_t)(void *cgs_device, unsigned addr); 313 314 /** 315 * cgs_read_pci_config_word() - Read word from PCI configuration space 316 * @cgs_device: opaque device handle 317 * @addr: address, must be word-aligned 318 * 319 * Return: Value read 320 */ 321 typedef uint16_t (*cgs_read_pci_config_word_t)(void *cgs_device, unsigned addr); 322 323 /** 324 * cgs_read_pci_config_dword() - Read dword from PCI configuration space 325 * @cgs_device: opaque device handle 326 * @addr: address, must be dword-aligned 327 * 328 * Return: Value read 329 */ 330 typedef uint32_t (*cgs_read_pci_config_dword_t)(void *cgs_device, 331 unsigned addr); 332 333 /** 334 * cgs_write_pci_config_byte() - Write byte to PCI configuration space 335 * @cgs_device: opaque device handle 336 * @addr: address 337 * @value: value to write 338 */ 339 typedef void (*cgs_write_pci_config_byte_t)(void *cgs_device, unsigned addr, 340 uint8_t value); 341 342 /** 343 * cgs_write_pci_config_word() - Write byte to PCI configuration space 344 * @cgs_device: opaque device handle 345 * @addr: address, must be word-aligned 346 * @value: value to write 347 */ 348 typedef void (*cgs_write_pci_config_word_t)(void *cgs_device, unsigned addr, 349 uint16_t value); 350 351 /** 352 * cgs_write_pci_config_dword() - Write byte to PCI configuration space 353 * @cgs_device: opaque device handle 354 * @addr: address, must be dword-aligned 355 * @value: value to write 356 */ 357 typedef void (*cgs_write_pci_config_dword_t)(void *cgs_device, unsigned addr, 358 uint32_t value); 359 360 /** 361 * cgs_atom_get_data_table() - Get a pointer to an ATOM BIOS data table 362 * @cgs_device: opaque device handle 363 * @table: data table index 364 * @size: size of the table (output, may be NULL) 365 * @frev: table format revision (output, may be NULL) 366 * @crev: table content revision (output, may be NULL) 367 * 368 * Return: Pointer to start of the table, or NULL on failure 369 */ 370 typedef const void *(*cgs_atom_get_data_table_t)( 371 void *cgs_device, unsigned table, 372 uint16_t *size, uint8_t *frev, uint8_t *crev); 373 374 /** 375 * cgs_atom_get_cmd_table_revs() - Get ATOM BIOS command table revisions 376 * @cgs_device: opaque device handle 377 * @table: data table index 378 * @frev: table format revision (output, may be NULL) 379 * @crev: table content revision (output, may be NULL) 380 * 381 * Return: 0 on success, -errno otherwise 382 */ 383 typedef int (*cgs_atom_get_cmd_table_revs_t)(void *cgs_device, unsigned table, 384 uint8_t *frev, uint8_t *crev); 385 386 /** 387 * cgs_atom_exec_cmd_table() - Execute an ATOM BIOS command table 388 * @cgs_device: opaque device handle 389 * @table: command table index 390 * @args: arguments 391 * 392 * Return: 0 on success, -errno otherwise 393 */ 394 typedef int (*cgs_atom_exec_cmd_table_t)(void *cgs_device, 395 unsigned table, void *args); 396 397 /** 398 * cgs_create_pm_request() - Create a power management request 399 * @cgs_device: opaque device handle 400 * @request: handle of created PM request (output) 401 * 402 * Return: 0 on success, -errno otherwise 403 */ 404 typedef int (*cgs_create_pm_request_t)(void *cgs_device, cgs_handle_t *request); 405 406 /** 407 * cgs_destroy_pm_request() - Destroy a power management request 408 * @cgs_device: opaque device handle 409 * @request: handle of created PM request 410 * 411 * Return: 0 on success, -errno otherwise 412 */ 413 typedef int (*cgs_destroy_pm_request_t)(void *cgs_device, cgs_handle_t request); 414 415 /** 416 * cgs_set_pm_request() - Activate or deactiveate a PM request 417 * @cgs_device: opaque device handle 418 * @request: PM request handle 419 * @active: 0 = deactivate, non-0 = activate 420 * 421 * While a PM request is active, its minimum clock requests are taken 422 * into account as the requested engines are powered up. When the 423 * request is inactive, the engines may be powered down and clocks may 424 * be lower, depending on other PM requests by other driver 425 * components. 426 * 427 * Return: 0 on success, -errno otherwise 428 */ 429 typedef int (*cgs_set_pm_request_t)(void *cgs_device, cgs_handle_t request, 430 int active); 431 432 /** 433 * cgs_pm_request_clock() - Request a minimum frequency for a specific clock 434 * @cgs_device: opaque device handle 435 * @request: PM request handle 436 * @clock: which clock? 437 * @freq: requested min. frequency in 10KHz units (0 to clear request) 438 * 439 * Return: 0 on success, -errno otherwise 440 */ 441 typedef int (*cgs_pm_request_clock_t)(void *cgs_device, cgs_handle_t request, 442 enum cgs_clock clock, unsigned freq); 443 444 /** 445 * cgs_pm_request_engine() - Request an engine to be powered up 446 * @cgs_device: opaque device handle 447 * @request: PM request handle 448 * @engine: which engine? 449 * @powered: 0 = powered down, non-0 = powered up 450 * 451 * Return: 0 on success, -errno otherwise 452 */ 453 typedef int (*cgs_pm_request_engine_t)(void *cgs_device, cgs_handle_t request, 454 enum cgs_engine engine, int powered); 455 456 /** 457 * cgs_pm_query_clock_limits() - Query clock frequency limits 458 * @cgs_device: opaque device handle 459 * @clock: which clock? 460 * @limits: clock limits 461 * 462 * Return: 0 on success, -errno otherwise 463 */ 464 typedef int (*cgs_pm_query_clock_limits_t)(void *cgs_device, 465 enum cgs_clock clock, 466 struct cgs_clock_limits *limits); 467 468 /** 469 * cgs_set_camera_voltages() - Apply specific voltages to PMIC voltage planes 470 * @cgs_device: opaque device handle 471 * @mask: bitmask of voltages to change (1<<CGS_VOLTAGE_PLANE__xyz|...) 472 * @voltages: pointer to array of voltage values in 1mV units 473 * 474 * Return: 0 on success, -errno otherwise 475 */ 476 typedef int (*cgs_set_camera_voltages_t)(void *cgs_device, uint32_t mask, 477 const uint32_t *voltages); 478 /** 479 * cgs_get_firmware_info - Get the firmware information from core driver 480 * @cgs_device: opaque device handle 481 * @type: the firmware type 482 * @info: returend firmware information 483 * 484 * Return: 0 on success, -errno otherwise 485 */ 486 typedef int (*cgs_get_firmware_info)(void *cgs_device, 487 enum cgs_ucode_id type, 488 struct cgs_firmware_info *info); 489 490 typedef int(*cgs_set_powergating_state)(void *cgs_device, 491 enum amd_ip_block_type block_type, 492 enum amd_powergating_state state); 493 494 typedef int(*cgs_set_clockgating_state)(void *cgs_device, 495 enum amd_ip_block_type block_type, 496 enum amd_clockgating_state state); 497 498 struct cgs_ops { 499 /* memory management calls (similar to KFD interface) */ 500 cgs_gpu_mem_info_t gpu_mem_info; 501 cgs_gmap_kmem_t gmap_kmem; 502 cgs_gunmap_kmem_t gunmap_kmem; 503 cgs_alloc_gpu_mem_t alloc_gpu_mem; 504 cgs_free_gpu_mem_t free_gpu_mem; 505 cgs_gmap_gpu_mem_t gmap_gpu_mem; 506 cgs_gunmap_gpu_mem_t gunmap_gpu_mem; 507 cgs_kmap_gpu_mem_t kmap_gpu_mem; 508 cgs_kunmap_gpu_mem_t kunmap_gpu_mem; 509 /* MMIO access */ 510 cgs_read_register_t read_register; 511 cgs_write_register_t write_register; 512 cgs_read_ind_register_t read_ind_register; 513 cgs_write_ind_register_t write_ind_register; 514 /* PCI configuration space access */ 515 cgs_read_pci_config_byte_t read_pci_config_byte; 516 cgs_read_pci_config_word_t read_pci_config_word; 517 cgs_read_pci_config_dword_t read_pci_config_dword; 518 cgs_write_pci_config_byte_t write_pci_config_byte; 519 cgs_write_pci_config_word_t write_pci_config_word; 520 cgs_write_pci_config_dword_t write_pci_config_dword; 521 /* ATOM BIOS */ 522 cgs_atom_get_data_table_t atom_get_data_table; 523 cgs_atom_get_cmd_table_revs_t atom_get_cmd_table_revs; 524 cgs_atom_exec_cmd_table_t atom_exec_cmd_table; 525 /* Power management */ 526 cgs_create_pm_request_t create_pm_request; 527 cgs_destroy_pm_request_t destroy_pm_request; 528 cgs_set_pm_request_t set_pm_request; 529 cgs_pm_request_clock_t pm_request_clock; 530 cgs_pm_request_engine_t pm_request_engine; 531 cgs_pm_query_clock_limits_t pm_query_clock_limits; 532 cgs_set_camera_voltages_t set_camera_voltages; 533 /* Firmware Info */ 534 cgs_get_firmware_info get_firmware_info; 535 /* cg pg interface*/ 536 cgs_set_powergating_state set_powergating_state; 537 cgs_set_clockgating_state set_clockgating_state; 538 /* ACPI (TODO) */ 539 }; 540 541 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 542 543 struct cgs_device 544 { 545 const struct cgs_ops *ops; 546 const struct cgs_os_ops *os_ops; 547 /* to be embedded at the start of driver private structure */ 548 }; 549 550 /* Convenience macros that make CGS indirect function calls look like 551 * normal function calls */ 552 #define CGS_CALL(func,dev,...) \ 553 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 554 #define CGS_OS_CALL(func,dev,...) \ 555 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 556 557 #define cgs_gpu_mem_info(dev,type,mc_start,mc_size,mem_size) \ 558 CGS_CALL(gpu_mem_info,dev,type,mc_start,mc_size,mem_size) 559 #define cgs_gmap_kmem(dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) \ 560 CGS_CALL(gmap_kmem,dev,kmem,size,min_off,max_off,kmem_handle,mcaddr) 561 #define cgs_gunmap_kmem(dev,kmem_handle) \ 562 CGS_CALL(gunmap_kmem,dev,keme_handle) 563 #define cgs_alloc_gpu_mem(dev,type,size,align,min_off,max_off,handle) \ 564 CGS_CALL(alloc_gpu_mem,dev,type,size,align,min_off,max_off,handle) 565 #define cgs_free_gpu_mem(dev,handle) \ 566 CGS_CALL(free_gpu_mem,dev,handle) 567 #define cgs_gmap_gpu_mem(dev,handle,mcaddr) \ 568 CGS_CALL(gmap_gpu_mem,dev,handle,mcaddr) 569 #define cgs_gunmap_gpu_mem(dev,handle) \ 570 CGS_CALL(gunmap_gpu_mem,dev,handle) 571 #define cgs_kmap_gpu_mem(dev,handle,map) \ 572 CGS_CALL(kmap_gpu_mem,dev,handle,map) 573 #define cgs_kunmap_gpu_mem(dev,handle) \ 574 CGS_CALL(kunmap_gpu_mem,dev,handle) 575 576 #define cgs_read_register(dev,offset) \ 577 CGS_CALL(read_register,dev,offset) 578 #define cgs_write_register(dev,offset,value) \ 579 CGS_CALL(write_register,dev,offset,value) 580 #define cgs_read_ind_register(dev,space,index) \ 581 CGS_CALL(read_ind_register,dev,space,index) 582 #define cgs_write_ind_register(dev,space,index,value) \ 583 CGS_CALL(write_ind_register,dev,space,index,value) 584 585 #define cgs_read_pci_config_byte(dev,addr) \ 586 CGS_CALL(read_pci_config_byte,dev,addr) 587 #define cgs_read_pci_config_word(dev,addr) \ 588 CGS_CALL(read_pci_config_word,dev,addr) 589 #define cgs_read_pci_config_dword(dev,addr) \ 590 CGS_CALL(read_pci_config_dword,dev,addr) 591 #define cgs_write_pci_config_byte(dev,addr,value) \ 592 CGS_CALL(write_pci_config_byte,dev,addr,value) 593 #define cgs_write_pci_config_word(dev,addr,value) \ 594 CGS_CALL(write_pci_config_word,dev,addr,value) 595 #define cgs_write_pci_config_dword(dev,addr,value) \ 596 CGS_CALL(write_pci_config_dword,dev,addr,value) 597 598 #define cgs_atom_get_data_table(dev,table,size,frev,crev) \ 599 CGS_CALL(atom_get_data_table,dev,table,size,frev,crev) 600 #define cgs_atom_get_cmd_table_revs(dev,table,frev,crev) \ 601 CGS_CALL(atom_get_cmd_table_revs,dev,table,frev,crev) 602 #define cgs_atom_exec_cmd_table(dev,table,args) \ 603 CGS_CALL(atom_exec_cmd_table,dev,table,args) 604 605 #define cgs_create_pm_request(dev,request) \ 606 CGS_CALL(create_pm_request,dev,request) 607 #define cgs_destroy_pm_request(dev,request) \ 608 CGS_CALL(destroy_pm_request,dev,request) 609 #define cgs_set_pm_request(dev,request,active) \ 610 CGS_CALL(set_pm_request,dev,request,active) 611 #define cgs_pm_request_clock(dev,request,clock,freq) \ 612 CGS_CALL(pm_request_clock,dev,request,clock,freq) 613 #define cgs_pm_request_engine(dev,request,engine,powered) \ 614 CGS_CALL(pm_request_engine,dev,request,engine,powered) 615 #define cgs_pm_query_clock_limits(dev,clock,limits) \ 616 CGS_CALL(pm_query_clock_limits,dev,clock,limits) 617 #define cgs_set_camera_voltages(dev,mask,voltages) \ 618 CGS_CALL(set_camera_voltages,dev,mask,voltages) 619 #define cgs_get_firmware_info(dev, type, info) \ 620 CGS_CALL(get_firmware_info, dev, type, info) 621 #define cgs_set_powergating_state(dev, block_type, state) \ 622 CGS_CALL(set_powergating_state, dev, block_type, state) 623 #define cgs_set_clockgating_state(dev, block_type, state) \ 624 CGS_CALL(set_clockgating_state, dev, block_type, state) 625 626 #endif /* _CGS_COMMON_H */ 627
Indexes created Thu Oct 02 14:10:14 GMT 2025