cgs_common.h revision 1.3
1 /* $NetBSD: cgs_common.h,v 1.3 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * 25 */ 26 #ifndef _CGS_COMMON_H 27 #define _CGS_COMMON_H 28 29 #include "amd_shared.h" 30 31 struct cgs_device; 32 33 /** 34 * enum cgs_ind_reg - Indirect register spaces 35 */ 36 enum cgs_ind_reg { 37 CGS_IND_REG__MMIO, 38 CGS_IND_REG__PCIE, 39 CGS_IND_REG__SMC, 40 CGS_IND_REG__UVD_CTX, 41 CGS_IND_REG__DIDT, 42 CGS_IND_REG_GC_CAC, 43 CGS_IND_REG_SE_CAC, 44 CGS_IND_REG__AUDIO_ENDPT 45 }; 46 47 /* 48 * enum cgs_ucode_id - Firmware types for different IPs 49 */ 50 enum cgs_ucode_id { 51 CGS_UCODE_ID_SMU = 0, 52 CGS_UCODE_ID_SMU_SK, 53 CGS_UCODE_ID_SDMA0, 54 CGS_UCODE_ID_SDMA1, 55 CGS_UCODE_ID_CP_CE, 56 CGS_UCODE_ID_CP_PFP, 57 CGS_UCODE_ID_CP_ME, 58 CGS_UCODE_ID_CP_MEC, 59 CGS_UCODE_ID_CP_MEC_JT1, 60 CGS_UCODE_ID_CP_MEC_JT2, 61 CGS_UCODE_ID_GMCON_RENG, 62 CGS_UCODE_ID_RLC_G, 63 CGS_UCODE_ID_STORAGE, 64 CGS_UCODE_ID_MAXIMUM, 65 }; 66 67 /** 68 * struct cgs_firmware_info - Firmware information 69 */ 70 struct cgs_firmware_info { 71 uint16_t version; 72 uint16_t fw_version; 73 uint16_t feature_version; 74 uint32_t image_size; 75 uint64_t mc_addr; 76 77 /* only for smc firmware */ 78 uint32_t ucode_start_address; 79 80 void *kptr; 81 bool is_kicker; 82 }; 83 84 typedef unsigned long cgs_handle_t; 85 86 /** 87 * cgs_read_register() - Read an MMIO register 88 * @cgs_device: opaque device handle 89 * @offset: register offset 90 * 91 * Return: register value 92 */ 93 typedef uint32_t (*cgs_read_register_t)(struct cgs_device *cgs_device, unsigned offset); 94 95 /** 96 * cgs_write_register() - Write an MMIO register 97 * @cgs_device: opaque device handle 98 * @offset: register offset 99 * @value: register value 100 */ 101 typedef void (*cgs_write_register_t)(struct cgs_device *cgs_device, unsigned offset, 102 uint32_t value); 103 104 /** 105 * cgs_read_ind_register() - Read an indirect register 106 * @cgs_device: opaque device handle 107 * @offset: register offset 108 * 109 * Return: register value 110 */ 111 typedef uint32_t (*cgs_read_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 112 unsigned index); 113 114 /** 115 * cgs_write_ind_register() - Write an indirect register 116 * @cgs_device: opaque device handle 117 * @offset: register offset 118 * @value: register value 119 */ 120 typedef void (*cgs_write_ind_register_t)(struct cgs_device *cgs_device, enum cgs_ind_reg space, 121 unsigned index, uint32_t value); 122 123 #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 124 #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK 125 126 #define CGS_REG_SET_FIELD(orig_val, reg, field, field_val) \ 127 (((orig_val) & ~CGS_REG_FIELD_MASK(reg, field)) | \ 128 (CGS_REG_FIELD_MASK(reg, field) & ((field_val) << CGS_REG_FIELD_SHIFT(reg, field)))) 129 130 #define CGS_REG_GET_FIELD(value, reg, field) \ 131 (((value) & CGS_REG_FIELD_MASK(reg, field)) >> CGS_REG_FIELD_SHIFT(reg, field)) 132 133 #define CGS_WREG32_FIELD(device, reg, field, val) \ 134 cgs_write_register(device, mm##reg, (cgs_read_register(device, mm##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) 135 136 #define CGS_WREG32_FIELD_IND(device, space, reg, field, val) \ 137 cgs_write_ind_register(device, space, ix##reg, (cgs_read_ind_register(device, space, ix##reg) & ~CGS_REG_FIELD_MASK(reg, field)) | (val) << CGS_REG_FIELD_SHIFT(reg, field)) 138 139 typedef int (*cgs_get_firmware_info)(struct cgs_device *cgs_device, 140 enum cgs_ucode_id type, 141 struct cgs_firmware_info *info); 142 143 struct cgs_ops { 144 /* MMIO access */ 145 cgs_read_register_t read_register; 146 cgs_write_register_t write_register; 147 cgs_read_ind_register_t read_ind_register; 148 cgs_write_ind_register_t write_ind_register; 149 /* Firmware Info */ 150 cgs_get_firmware_info get_firmware_info; 151 }; 152 153 struct cgs_os_ops; /* To be define in OS-specific CGS header */ 154 155 struct cgs_device 156 { 157 const struct cgs_ops *ops; 158 /* to be embedded at the start of driver private structure */ 159 }; 160 161 /* Convenience macros that make CGS indirect function calls look like 162 * normal function calls */ 163 #define CGS_CALL(func,dev,...) \ 164 (((struct cgs_device *)dev)->ops->func(dev, ##__VA_ARGS__)) 165 #define CGS_OS_CALL(func,dev,...) \ 166 (((struct cgs_device *)dev)->os_ops->func(dev, ##__VA_ARGS__)) 167 168 #define cgs_read_register(dev,offset) \ 169 CGS_CALL(read_register,dev,offset) 170 #define cgs_write_register(dev,offset,value) \ 171 CGS_CALL(write_register,dev,offset,value) 172 #define cgs_read_ind_register(dev,space,index) \ 173 CGS_CALL(read_ind_register,dev,space,index) 174 #define cgs_write_ind_register(dev,space,index,value) \ 175 CGS_CALL(write_ind_register,dev,space,index,value) 176 177 #define cgs_get_firmware_info(dev, type, info) \ 178 CGS_CALL(get_firmware_info, dev, type, info) 179 180 #endif /* _CGS_COMMON_H */ 181
Indexes created Thu Oct 02 14:10:14 GMT 2025