ppatomfwctrl.h revision 1.1
1 /* $NetBSD: ppatomfwctrl.h,v 1.1 2021/12/18 20:15:21 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef PP_ATOMFWCTRL_H 27 #define PP_ATOMFWCTRL_H 28 29 #include "hwmgr.h" 30 31 typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID; 32 33 #define GetIndexIntoMasterCmdTable(FieldName) \ 34 (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) 35 #define GetIndexIntoMasterDataTable(FieldName) \ 36 (((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t)) 37 38 #define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32 39 40 struct pp_atomfwctrl_voltage_table_entry { 41 uint16_t value; 42 uint32_t smio_low; 43 }; 44 45 struct pp_atomfwctrl_voltage_table { 46 uint32_t count; 47 uint32_t mask_low; 48 uint32_t phase_delay; 49 uint8_t psi0_enable; 50 uint8_t psi1_enable; 51 uint8_t max_vid_step; 52 uint8_t telemetry_offset; 53 uint8_t telemetry_slope; 54 struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES]; 55 }; 56 57 struct pp_atomfwctrl_gpio_pin_assignment { 58 uint16_t us_gpio_pin_aindex; 59 uint8_t uc_gpio_pin_bit_shift; 60 }; 61 62 struct pp_atomfwctrl_clock_dividers_soc15 { 63 uint32_t ulClock; /* the actual clock */ 64 uint32_t ulDid; /* DFS divider */ 65 uint32_t ulPll_fb_mult; /* Feedback Multiplier: bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */ 66 uint32_t ulPll_ss_fbsmult; /* Spread FB Multiplier: bit 8:0 int, bit 31:16 frac */ 67 uint16_t usPll_ss_slew_frac; 68 uint8_t ucPll_ss_enable; 69 uint8_t ucReserve; 70 uint32_t ulReserve[2]; 71 }; 72 73 struct pp_atomfwctrl_avfs_parameters { 74 uint32_t ulMaxVddc; 75 uint32_t ulMinVddc; 76 77 uint32_t ulMeanNsigmaAcontant0; 78 uint32_t ulMeanNsigmaAcontant1; 79 uint32_t ulMeanNsigmaAcontant2; 80 uint16_t usMeanNsigmaDcTolSigma; 81 uint16_t usMeanNsigmaPlatformMean; 82 uint16_t usMeanNsigmaPlatformSigma; 83 uint32_t ulGbVdroopTableCksoffA0; 84 uint32_t ulGbVdroopTableCksoffA1; 85 uint32_t ulGbVdroopTableCksoffA2; 86 uint32_t ulGbVdroopTableCksonA0; 87 uint32_t ulGbVdroopTableCksonA1; 88 uint32_t ulGbVdroopTableCksonA2; 89 90 uint32_t ulGbFuseTableCksoffM1; 91 uint32_t ulGbFuseTableCksoffM2; 92 uint32_t ulGbFuseTableCksoffB; 93 94 uint32_t ulGbFuseTableCksonM1; 95 uint32_t ulGbFuseTableCksonM2; 96 uint32_t ulGbFuseTableCksonB; 97 98 uint8_t ucEnableGbVdroopTableCkson; 99 uint8_t ucEnableGbFuseTableCkson; 100 uint16_t usPsmAgeComfactor; 101 102 uint32_t ulDispclk2GfxclkM1; 103 uint32_t ulDispclk2GfxclkM2; 104 uint32_t ulDispclk2GfxclkB; 105 uint32_t ulDcefclk2GfxclkM1; 106 uint32_t ulDcefclk2GfxclkM2; 107 uint32_t ulDcefclk2GfxclkB; 108 uint32_t ulPixelclk2GfxclkM1; 109 uint32_t ulPixelclk2GfxclkM2; 110 uint32_t ulPixelclk2GfxclkB; 111 uint32_t ulPhyclk2GfxclkM1; 112 uint32_t ulPhyclk2GfxclkM2; 113 uint32_t ulPhyclk2GfxclkB; 114 uint32_t ulAcgGbVdroopTableA0; 115 uint32_t ulAcgGbVdroopTableA1; 116 uint32_t ulAcgGbVdroopTableA2; 117 uint32_t ulAcgGbFuseTableM1; 118 uint32_t ulAcgGbFuseTableM2; 119 uint32_t ulAcgGbFuseTableB; 120 uint32_t ucAcgEnableGbVdroopTable; 121 uint32_t ucAcgEnableGbFuseTable; 122 }; 123 124 struct pp_atomfwctrl_gpio_parameters { 125 uint8_t ucAcDcGpio; 126 uint8_t ucAcDcPolarity; 127 uint8_t ucVR0HotGpio; 128 uint8_t ucVR0HotPolarity; 129 uint8_t ucVR1HotGpio; 130 uint8_t ucVR1HotPolarity; 131 uint8_t ucFwCtfGpio; 132 uint8_t ucFwCtfPolarity; 133 }; 134 135 struct pp_atomfwctrl_bios_boot_up_values { 136 uint32_t ulRevision; 137 uint32_t ulGfxClk; 138 uint32_t ulUClk; 139 uint32_t ulSocClk; 140 uint32_t ulDCEFClk; 141 uint32_t ulEClk; 142 uint32_t ulVClk; 143 uint32_t ulDClk; 144 uint32_t ulFClk; 145 uint16_t usVddc; 146 uint16_t usVddci; 147 uint16_t usMvddc; 148 uint16_t usVddGfx; 149 uint8_t ucCoolingID; 150 }; 151 152 struct pp_atomfwctrl_smc_dpm_parameters 153 { 154 uint8_t liquid1_i2c_address; 155 uint8_t liquid2_i2c_address; 156 uint8_t vr_i2c_address; 157 uint8_t plx_i2c_address; 158 uint8_t liquid_i2c_linescl; 159 uint8_t liquid_i2c_linesda; 160 uint8_t vr_i2c_linescl; 161 uint8_t vr_i2c_linesda; 162 uint8_t plx_i2c_linescl; 163 uint8_t plx_i2c_linesda; 164 uint8_t vrsensorpresent; 165 uint8_t liquidsensorpresent; 166 uint16_t maxvoltagestepgfx; 167 uint16_t maxvoltagestepsoc; 168 uint8_t vddgfxvrmapping; 169 uint8_t vddsocvrmapping; 170 uint8_t vddmem0vrmapping; 171 uint8_t vddmem1vrmapping; 172 uint8_t gfxulvphasesheddingmask; 173 uint8_t soculvphasesheddingmask; 174 175 uint16_t gfxmaxcurrent; 176 uint8_t gfxoffset; 177 uint8_t padding_telemetrygfx; 178 uint16_t socmaxcurrent; 179 uint8_t socoffset; 180 uint8_t padding_telemetrysoc; 181 uint16_t mem0maxcurrent; 182 uint8_t mem0offset; 183 uint8_t padding_telemetrymem0; 184 uint16_t mem1maxcurrent; 185 uint8_t mem1offset; 186 uint8_t padding_telemetrymem1; 187 188 uint8_t acdcgpio; 189 uint8_t acdcpolarity; 190 uint8_t vr0hotgpio; 191 uint8_t vr0hotpolarity; 192 uint8_t vr1hotgpio; 193 uint8_t vr1hotpolarity; 194 uint8_t padding1; 195 uint8_t padding2; 196 197 uint8_t ledpin0; 198 uint8_t ledpin1; 199 uint8_t ledpin2; 200 201 uint8_t pllgfxclkspreadenabled; 202 uint8_t pllgfxclkspreadpercent; 203 uint16_t pllgfxclkspreadfreq; 204 205 uint8_t uclkspreadenabled; 206 uint8_t uclkspreadpercent; 207 uint16_t uclkspreadfreq; 208 209 uint8_t socclkspreadenabled; 210 uint8_t socclkspreadpercent; 211 uint16_t socclkspreadfreq; 212 213 uint8_t acggfxclkspreadenabled; 214 uint8_t acggfxclkspreadpercent; 215 uint16_t acggfxclkspreadfreq; 216 217 uint8_t Vr2_I2C_address; 218 }; 219 220 int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr, 221 uint32_t clock_type, uint32_t clock_value, 222 struct pp_atomfwctrl_clock_dividers_soc15 *dividers); 223 int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr); 224 bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id, 225 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment); 226 227 int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 228 uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table); 229 bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr, 230 uint8_t voltage_type, uint8_t voltage_mode); 231 232 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, 233 struct pp_atomfwctrl_avfs_parameters *param); 234 int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr, 235 struct pp_atomfwctrl_gpio_parameters *param); 236 237 int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr, 238 struct pp_atomfwctrl_bios_boot_up_values *boot_values); 239 int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr, 240 struct pp_atomfwctrl_smc_dpm_parameters *param); 241 int pp_atomfwctrl_get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, 242 uint8_t clk_id, uint8_t syspll_id, 243 uint32_t *frequency); 244 245 #endif 246 247
Indexes created Sat Oct 25 16:10:12 GMT 2025