smu9.h revision 1.1.1.1
1 /* $NetBSD: smu9.h,v 1.1.1.1 2021/12/18 20:15:22 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef SMU9_H 27 #define SMU9_H 28 29 #pragma pack(push, 1) 30 31 #define ENABLE_DEBUG_FEATURES 32 33 /* Feature Control Defines */ 34 #define FEATURE_DPM_PREFETCHER_BIT 0 35 #define FEATURE_DPM_GFXCLK_BIT 1 36 #define FEATURE_DPM_UCLK_BIT 2 37 #define FEATURE_DPM_SOCCLK_BIT 3 38 #define FEATURE_DPM_UVD_BIT 4 39 #define FEATURE_DPM_VCE_BIT 5 40 #define FEATURE_ULV_BIT 6 41 #define FEATURE_DPM_MP0CLK_BIT 7 42 #define FEATURE_DPM_LINK_BIT 8 43 #define FEATURE_DPM_DCEFCLK_BIT 9 44 #define FEATURE_AVFS_BIT 10 45 #define FEATURE_DS_GFXCLK_BIT 11 46 #define FEATURE_DS_SOCCLK_BIT 12 47 #define FEATURE_DS_LCLK_BIT 13 48 #define FEATURE_PPT_BIT 14 49 #define FEATURE_TDC_BIT 15 50 #define FEATURE_THERMAL_BIT 16 51 #define FEATURE_GFX_PER_CU_CG_BIT 17 52 #define FEATURE_RM_BIT 18 53 #define FEATURE_DS_DCEFCLK_BIT 19 54 #define FEATURE_ACDC_BIT 20 55 #define FEATURE_VR0HOT_BIT 21 56 #define FEATURE_VR1HOT_BIT 22 57 #define FEATURE_FW_CTF_BIT 23 58 #define FEATURE_LED_DISPLAY_BIT 24 59 #define FEATURE_FAN_CONTROL_BIT 25 60 #define FEATURE_FAST_PPT_BIT 26 61 #define FEATURE_GFX_EDC_BIT 27 62 #define FEATURE_ACG_BIT 28 63 #define FEATURE_PCC_LIMIT_CONTROL_BIT 29 64 #define FEATURE_SPARE_30_BIT 30 65 #define FEATURE_SPARE_31_BIT 31 66 67 #define NUM_FEATURES 32 68 69 #define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT ) 70 #define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT ) 71 #define FFEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT ) 72 #define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT ) 73 #define FFEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT ) 74 #define FFEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT ) 75 #define FFEATURE_ULV_MASK (1 << FEATURE_ULV_BIT ) 76 #define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT ) 77 #define FFEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT ) 78 #define FFEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT ) 79 #define FFEATURE_AVFS_MASK (1 << FEATURE_AVFS_BIT ) 80 #define FFEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT ) 81 #define FFEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT ) 82 #define FFEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT ) 83 #define FFEATURE_PPT_MASK (1 << FEATURE_PPT_BIT ) 84 #define FFEATURE_TDC_MASK (1 << FEATURE_TDC_BIT ) 85 #define FFEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT ) 86 #define FFEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT ) 87 #define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT ) 88 #define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT ) 89 #define FFEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT ) 90 #define FFEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT ) 91 #define FFEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT ) 92 #define FFEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT ) 93 #define FFEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT ) 94 #define FFEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT ) 95 96 #define FEATURE_FAST_PPT_MASK (1 << FAST_PPT_BIT ) 97 #define FEATURE_GFX_EDC_MASK (1 << FEATURE_GFX_EDC_BIT ) 98 #define FEATURE_ACG_MASK (1 << FEATURE_ACG_BIT ) 99 #define FEATURE_PCC_LIMIT_CONTROL_MASK (1 << FEATURE_PCC_LIMIT_CONTROL_BIT ) 100 #define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT ) 101 #define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT ) 102 /* Workload types */ 103 #define WORKLOAD_VR_BIT 0 104 #define WORKLOAD_FRTC_BIT 1 105 #define WORKLOAD_VIDEO_BIT 2 106 #define WORKLOAD_COMPUTE_BIT 3 107 #define NUM_WORKLOADS 4 108 109 /* ULV Client Masks */ 110 #define ULV_CLIENT_RLC_MASK 0x00000001 111 #define ULV_CLIENT_UVD_MASK 0x00000002 112 #define ULV_CLIENT_VCE_MASK 0x00000004 113 #define ULV_CLIENT_SDMA0_MASK 0x00000008 114 #define ULV_CLIENT_SDMA1_MASK 0x00000010 115 #define ULV_CLIENT_JPEG_MASK 0x00000020 116 #define ULV_CLIENT_GFXCLK_DPM_MASK 0x00000040 117 #define ULV_CLIENT_UVD_DPM_MASK 0x00000080 118 #define ULV_CLIENT_VCE_DPM_MASK 0x00000100 119 #define ULV_CLIENT_MP0CLK_DPM_MASK 0x00000200 120 #define ULV_CLIENT_UCLK_DPM_MASK 0x00000400 121 #define ULV_CLIENT_SOCCLK_DPM_MASK 0x00000800 122 #define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000 123 124 typedef struct { 125 /* MP1_EXT_SCRATCH0 */ 126 uint32_t CurrLevel_GFXCLK : 4; 127 uint32_t CurrLevel_UVD : 4; 128 uint32_t CurrLevel_VCE : 4; 129 uint32_t CurrLevel_LCLK : 4; 130 uint32_t CurrLevel_MP0CLK : 4; 131 uint32_t CurrLevel_UCLK : 4; 132 uint32_t CurrLevel_SOCCLK : 4; 133 uint32_t CurrLevel_DCEFCLK : 4; 134 /* MP1_EXT_SCRATCH1 */ 135 uint32_t TargLevel_GFXCLK : 4; 136 uint32_t TargLevel_UVD : 4; 137 uint32_t TargLevel_VCE : 4; 138 uint32_t TargLevel_LCLK : 4; 139 uint32_t TargLevel_MP0CLK : 4; 140 uint32_t TargLevel_UCLK : 4; 141 uint32_t TargLevel_SOCCLK : 4; 142 uint32_t TargLevel_DCEFCLK : 4; 143 /* MP1_EXT_SCRATCH2-7 */ 144 uint32_t Reserved[6]; 145 } FwStatus_t; 146 147 #pragma pack(pop) 148 149 #endif 150 151
Indexes created Mon Oct 27 04:09:48 GMT 2025