drm_dsc.c revision 1.1
1 /* $NetBSD: drm_dsc.c,v 1.1 2021/12/18 20:11:01 riastradh Exp $ */ 2 3 // SPDX-License-Identifier: MIT 4 /* 5 * Copyright 2018 Intel Corp 6 * 7 * Author: 8 * Manasi Navare <manasi.d.navare (at) intel.com> 9 */ 10 11 #include <sys/cdefs.h> 12 __KERNEL_RCSID(0, "$NetBSD: drm_dsc.c,v 1.1 2021/12/18 20:11:01 riastradh Exp $"); 13 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/init.h> 17 #include <linux/errno.h> 18 #include <linux/byteorder/generic.h> 19 #include <drm/drm_print.h> 20 #include <drm/drm_dp_helper.h> 21 #include <drm/drm_dsc.h> 22 23 /** 24 * DOC: dsc helpers 25 * 26 * VESA specification for DP 1.4 adds a new feature called Display Stream 27 * Compression (DSC) used to compress the pixel bits before sending it on 28 * DP/eDP/MIPI DSI interface. DSC is required to be enabled so that the existing 29 * display interfaces can support high resolutions at higher frames rates uisng 30 * the maximum available link capacity of these interfaces. 31 * 32 * These functions contain some common logic and helpers to deal with VESA 33 * Display Stream Compression standard required for DSC on Display Port/eDP or 34 * MIPI display interfaces. 35 */ 36 37 /** 38 * drm_dsc_dp_pps_header_init() - Initializes the PPS Header 39 * for DisplayPort as per the DP 1.4 spec. 40 * @pps_header: Secondary data packet header for DSC Picture 41 * Parameter Set as defined in &struct dp_sdp_header 42 * 43 * DP 1.4 spec defines the secondary data packet for sending the 44 * picture parameter infoframes from the source to the sink. 45 * This function populates the SDP header defined in 46 * &struct dp_sdp_header. 47 */ 48 void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header) 49 { 50 memset(pps_header, 0, sizeof(*pps_header)); 51 52 pps_header->HB1 = DP_SDP_PPS; 53 pps_header->HB2 = DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1; 54 } 55 EXPORT_SYMBOL(drm_dsc_dp_pps_header_init); 56 57 /** 58 * drm_dsc_pps_payload_pack() - Populates the DSC PPS 59 * 60 * @pps_payload: 61 * Bitwise struct for DSC Picture Parameter Set. This is defined 62 * by &struct drm_dsc_picture_parameter_set 63 * @dsc_cfg: 64 * DSC Configuration data filled by driver as defined by 65 * &struct drm_dsc_config 66 * 67 * DSC source device sends a picture parameter set (PPS) containing the 68 * information required by the sink to decode the compressed frame. Driver 69 * populates the DSC PPS struct using the DSC configuration parameters in 70 * the order expected by the DSC Display Sink device. For the DSC, the sink 71 * device expects the PPS payload in big endian format for fields 72 * that span more than 1 byte. 73 */ 74 void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, 75 const struct drm_dsc_config *dsc_cfg) 76 { 77 int i; 78 79 /* Protect against someone accidently changing struct size */ 80 BUILD_BUG_ON(sizeof(*pps_payload) != 81 DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); 82 83 memset(pps_payload, 0, sizeof(*pps_payload)); 84 85 /* PPS 0 */ 86 pps_payload->dsc_version = 87 dsc_cfg->dsc_version_minor | 88 dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; 89 90 /* PPS 1, 2 is 0 */ 91 92 /* PPS 3 */ 93 pps_payload->pps_3 = 94 dsc_cfg->line_buf_depth | 95 dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; 96 97 /* PPS 4 */ 98 pps_payload->pps_4 = 99 ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> 100 DSC_PPS_MSB_SHIFT) | 101 dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | 102 dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | 103 dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | 104 dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; 105 106 /* PPS 5 */ 107 pps_payload->bits_per_pixel_low = 108 (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); 109 110 /* 111 * The DSC panel expects the PPS packet to have big endian format 112 * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert 113 * to big endian format. If format is little endian, it will swap 114 * bytes to convert to Big endian else keep it unchanged. 115 */ 116 117 /* PPS 6, 7 */ 118 pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); 119 120 /* PPS 8, 9 */ 121 pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); 122 123 /* PPS 10, 11 */ 124 pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); 125 126 /* PPS 12, 13 */ 127 pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); 128 129 /* PPS 14, 15 */ 130 pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); 131 132 /* PPS 16 */ 133 pps_payload->initial_xmit_delay_high = 134 ((dsc_cfg->initial_xmit_delay & 135 DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> 136 DSC_PPS_MSB_SHIFT); 137 138 /* PPS 17 */ 139 pps_payload->initial_xmit_delay_low = 140 (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); 141 142 /* PPS 18, 19 */ 143 pps_payload->initial_dec_delay = 144 cpu_to_be16(dsc_cfg->initial_dec_delay); 145 146 /* PPS 20 is 0 */ 147 148 /* PPS 21 */ 149 pps_payload->initial_scale_value = 150 dsc_cfg->initial_scale_value; 151 152 /* PPS 22, 23 */ 153 pps_payload->scale_increment_interval = 154 cpu_to_be16(dsc_cfg->scale_increment_interval); 155 156 /* PPS 24 */ 157 pps_payload->scale_decrement_interval_high = 158 ((dsc_cfg->scale_decrement_interval & 159 DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> 160 DSC_PPS_MSB_SHIFT); 161 162 /* PPS 25 */ 163 pps_payload->scale_decrement_interval_low = 164 (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); 165 166 /* PPS 26[7:0], PPS 27[7:5] RESERVED */ 167 168 /* PPS 27 */ 169 pps_payload->first_line_bpg_offset = 170 dsc_cfg->first_line_bpg_offset; 171 172 /* PPS 28, 29 */ 173 pps_payload->nfl_bpg_offset = 174 cpu_to_be16(dsc_cfg->nfl_bpg_offset); 175 176 /* PPS 30, 31 */ 177 pps_payload->slice_bpg_offset = 178 cpu_to_be16(dsc_cfg->slice_bpg_offset); 179 180 /* PPS 32, 33 */ 181 pps_payload->initial_offset = 182 cpu_to_be16(dsc_cfg->initial_offset); 183 184 /* PPS 34, 35 */ 185 pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); 186 187 /* PPS 36 */ 188 pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; 189 190 /* PPS 37 */ 191 pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; 192 193 /* PPS 38, 39 */ 194 pps_payload->rc_model_size = 195 cpu_to_be16(DSC_RC_MODEL_SIZE_CONST); 196 197 /* PPS 40 */ 198 pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; 199 200 /* PPS 41 */ 201 pps_payload->rc_quant_incr_limit0 = 202 dsc_cfg->rc_quant_incr_limit0; 203 204 /* PPS 42 */ 205 pps_payload->rc_quant_incr_limit1 = 206 dsc_cfg->rc_quant_incr_limit1; 207 208 /* PPS 43 */ 209 pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | 210 DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; 211 212 /* PPS 44 - 57 */ 213 for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) 214 pps_payload->rc_buf_thresh[i] = 215 dsc_cfg->rc_buf_thresh[i]; 216 217 /* PPS 58 - 87 */ 218 /* 219 * For DSC sink programming the RC Range parameter fields 220 * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] 221 */ 222 for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { 223 pps_payload->rc_range_parameters[i] = 224 cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << 225 DSC_PPS_RC_RANGE_MINQP_SHIFT) | 226 (dsc_cfg->rc_range_params[i].range_max_qp << 227 DSC_PPS_RC_RANGE_MAXQP_SHIFT) | 228 (dsc_cfg->rc_range_params[i].range_bpg_offset)); 229 } 230 231 /* PPS 88 */ 232 pps_payload->native_422_420 = dsc_cfg->native_422 | 233 dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; 234 235 /* PPS 89 */ 236 pps_payload->second_line_bpg_offset = 237 dsc_cfg->second_line_bpg_offset; 238 239 /* PPS 90, 91 */ 240 pps_payload->nsl_bpg_offset = 241 cpu_to_be16(dsc_cfg->nsl_bpg_offset); 242 243 /* PPS 92, 93 */ 244 pps_payload->second_line_offset_adj = 245 cpu_to_be16(dsc_cfg->second_line_offset_adj); 246 247 /* PPS 94 - 127 are O */ 248 } 249 EXPORT_SYMBOL(drm_dsc_pps_payload_pack); 250 251 /** 252 * drm_dsc_compute_rc_parameters() - Write rate control 253 * parameters to the dsc configuration defined in 254 * &struct drm_dsc_config in accordance with the DSC 1.2 255 * specification. Some configuration fields must be present 256 * beforehand. 257 * 258 * @vdsc_cfg: 259 * DSC Configuration data partially filled by driver 260 */ 261 int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) 262 { 263 unsigned long groups_per_line = 0; 264 unsigned long groups_total = 0; 265 unsigned long num_extra_mux_bits = 0; 266 unsigned long slice_bits = 0; 267 unsigned long hrd_delay = 0; 268 unsigned long final_scale = 0; 269 unsigned long rbs_min = 0; 270 271 if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { 272 /* Number of groups used to code each line of a slice */ 273 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, 274 DSC_RC_PIXELS_PER_GROUP); 275 276 /* chunksize in Bytes */ 277 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * 278 vdsc_cfg->bits_per_pixel, 279 (8 * 16)); 280 } else { 281 /* Number of groups used to code each line of a slice */ 282 groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, 283 DSC_RC_PIXELS_PER_GROUP); 284 285 /* chunksize in Bytes */ 286 vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * 287 vdsc_cfg->bits_per_pixel, 288 (8 * 16)); 289 } 290 291 if (vdsc_cfg->convert_rgb) 292 num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + 293 (4 * vdsc_cfg->bits_per_component + 4) 294 - 2); 295 else if (vdsc_cfg->native_422) 296 num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + 297 (4 * vdsc_cfg->bits_per_component + 4) + 298 3 * (4 * vdsc_cfg->bits_per_component) - 2; 299 else 300 num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + 301 (4 * vdsc_cfg->bits_per_component + 4) + 302 2 * (4 * vdsc_cfg->bits_per_component) - 2; 303 /* Number of bits in one Slice */ 304 slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; 305 306 while ((num_extra_mux_bits > 0) && 307 ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) 308 num_extra_mux_bits--; 309 310 if (groups_per_line < vdsc_cfg->initial_scale_value - 8) 311 vdsc_cfg->initial_scale_value = groups_per_line + 8; 312 313 /* scale_decrement_interval calculation according to DSC spec 1.11 */ 314 if (vdsc_cfg->initial_scale_value > 8) 315 vdsc_cfg->scale_decrement_interval = groups_per_line / 316 (vdsc_cfg->initial_scale_value - 8); 317 else 318 vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; 319 320 vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - 321 (vdsc_cfg->initial_xmit_delay * 322 vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; 323 324 if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { 325 DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); 326 return -ERANGE; 327 } 328 329 final_scale = (vdsc_cfg->rc_model_size * 8) / 330 (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); 331 if (vdsc_cfg->slice_height > 1) 332 /* 333 * NflBpgOffset is 16 bit value with 11 fractional bits 334 * hence we multiply by 2^11 for preserving the 335 * fractional part 336 */ 337 vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), 338 (vdsc_cfg->slice_height - 1)); 339 else 340 vdsc_cfg->nfl_bpg_offset = 0; 341 342 /* Number of groups used to code the entire slice */ 343 groups_total = groups_per_line * vdsc_cfg->slice_height; 344 345 /* slice_bpg_offset is 16 bit value with 11 fractional bits */ 346 vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - 347 vdsc_cfg->initial_offset + 348 num_extra_mux_bits) << 11), 349 groups_total); 350 351 if (final_scale > 9) { 352 /* 353 * ScaleIncrementInterval = 354 * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) 355 * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, 356 * we need divide by 2^11 from pstDscCfg values 357 */ 358 vdsc_cfg->scale_increment_interval = 359 (vdsc_cfg->final_offset * (1 << 11)) / 360 ((vdsc_cfg->nfl_bpg_offset + 361 vdsc_cfg->slice_bpg_offset) * 362 (final_scale - 9)); 363 } else { 364 /* 365 * If finalScaleValue is less than or equal to 9, a value of 0 should 366 * be used to disable the scale increment at the end of the slice 367 */ 368 vdsc_cfg->scale_increment_interval = 0; 369 } 370 371 /* 372 * DSC spec mentions that bits_per_pixel specifies the target 373 * bits/pixel (bpp) rate that is used by the encoder, 374 * in steps of 1/16 of a bit per pixel 375 */ 376 rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + 377 DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * 378 vdsc_cfg->bits_per_pixel, 16) + 379 groups_per_line * vdsc_cfg->first_line_bpg_offset; 380 381 hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); 382 vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; 383 vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; 384 385 return 0; 386 } 387 EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); 388
Indexes created Sat Sep 27 22:09:54 GMT 2025