drm_edid.c revision 1.4.4.3
1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes (at) intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie (at) cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 #include <linux/kernel.h> 31 #include <linux/slab.h> 32 #include <linux/hdmi.h> 33 #include <linux/i2c.h> 34 #include <linux/module.h> 35 #include <linux/moduleparam.h> 36 #include <linux/export.h> 37 #include <linux/printk.h> 38 #include <linux/device.h> 39 #include <linux/string.h> 40 #include <linux/errno.h> 41 #include <asm/byteorder.h> 42 #include <drm/drmP.h> 43 #include <drm/drm_edid.h> 44 45 #define version_greater(edid, maj, min) \ 46 (((edid)->version > (maj)) || \ 47 ((edid)->version == (maj) && (edid)->revision > (min))) 48 49 #define EDID_EST_TIMINGS 16 50 #define EDID_STD_TIMINGS 8 51 #define EDID_DETAILED_TIMINGS 4 52 53 /* 54 * EDID blocks out in the wild have a variety of bugs, try to collect 55 * them here (note that userspace may work around broken monitors first, 56 * but fixes should make their way here so that the kernel "just works" 57 * on as many displays as possible). 58 */ 59 60 /* First detailed mode wrong, use largest 60Hz mode */ 61 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 62 /* Reported 135MHz pixel clock is too high, needs adjustment */ 63 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 64 /* Prefer the largest mode at 75 Hz */ 65 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 66 /* Detail timing is in cm not mm */ 67 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 68 /* Detailed timing descriptors have bogus size values, so just take the 69 * maximum size and use that. 70 */ 71 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 72 /* Monitor forgot to set the first detailed is preferred bit. */ 73 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 74 /* use +hsync +vsync for detailed mode */ 75 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 76 /* Force reduced-blanking timings for detailed modes */ 77 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 78 /* Force 8bpc */ 79 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 80 81 struct detailed_mode_closure { 82 struct drm_connector *connector; 83 struct edid *edid; 84 bool preferred; 85 u32 quirks; 86 int modes; 87 }; 88 89 #define LEVEL_DMT 0 90 #define LEVEL_GTF 1 91 #define LEVEL_GTF2 2 92 #define LEVEL_CVT 3 93 94 static struct edid_quirk { 95 char vendor[4]; 96 int product_id; 97 u32 quirks; 98 } edid_quirk_list[] = { 99 /* Acer AL1706 */ 100 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 101 /* Acer F51 */ 102 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 103 /* Unknown Acer */ 104 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 105 106 /* Belinea 10 15 55 */ 107 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 108 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 109 110 /* Envision Peripherals, Inc. EN-7100e */ 111 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 112 /* Envision EN2028 */ 113 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 114 115 /* Funai Electronics PM36B */ 116 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 117 EDID_QUIRK_DETAILED_IN_CM }, 118 119 /* LG Philips LCD LP154W01-A5 */ 120 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 121 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 122 123 /* Philips 107p5 CRT */ 124 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 125 126 /* Proview AY765C */ 127 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 128 129 /* Samsung SyncMaster 205BW. Note: irony */ 130 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 131 /* Samsung SyncMaster 22[5-6]BW */ 132 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 133 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 134 135 /* ViewSonic VA2026w */ 136 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 137 138 /* Medion MD 30217 PG */ 139 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 140 141 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 142 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 143 }; 144 145 /* 146 * Autogenerated from the DMT spec. 147 * This table is copied from xfree86/modes/xf86EdidModes.c. 148 */ 149 static const struct drm_display_mode drm_dmt_modes[] = { 150 /* 640x350@85Hz */ 151 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 152 736, 832, 0, 350, 382, 385, 445, 0, 153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 154 /* 640x400@85Hz */ 155 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 156 736, 832, 0, 400, 401, 404, 445, 0, 157 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 158 /* 720x400@85Hz */ 159 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 160 828, 936, 0, 400, 401, 404, 446, 0, 161 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 162 /* 640x480@60Hz */ 163 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 164 752, 800, 0, 480, 489, 492, 525, 0, 165 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 166 /* 640x480@72Hz */ 167 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 168 704, 832, 0, 480, 489, 492, 520, 0, 169 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 170 /* 640x480@75Hz */ 171 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 172 720, 840, 0, 480, 481, 484, 500, 0, 173 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 174 /* 640x480@85Hz */ 175 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 176 752, 832, 0, 480, 481, 484, 509, 0, 177 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 178 /* 800x600@56Hz */ 179 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 180 896, 1024, 0, 600, 601, 603, 625, 0, 181 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 182 /* 800x600@60Hz */ 183 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 184 968, 1056, 0, 600, 601, 605, 628, 0, 185 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 186 /* 800x600@72Hz */ 187 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 188 976, 1040, 0, 600, 637, 643, 666, 0, 189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 190 /* 800x600@75Hz */ 191 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 192 896, 1056, 0, 600, 601, 604, 625, 0, 193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 194 /* 800x600@85Hz */ 195 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 196 896, 1048, 0, 600, 601, 604, 631, 0, 197 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 198 /* 800x600@120Hz RB */ 199 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 200 880, 960, 0, 600, 603, 607, 636, 0, 201 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 202 /* 848x480@60Hz */ 203 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 204 976, 1088, 0, 480, 486, 494, 517, 0, 205 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 206 /* 1024x768@43Hz, interlace */ 207 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 208 1208, 1264, 0, 768, 768, 772, 817, 0, 209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 210 DRM_MODE_FLAG_INTERLACE) }, 211 /* 1024x768@60Hz */ 212 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 213 1184, 1344, 0, 768, 771, 777, 806, 0, 214 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 215 /* 1024x768@70Hz */ 216 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 217 1184, 1328, 0, 768, 771, 777, 806, 0, 218 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 219 /* 1024x768@75Hz */ 220 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 221 1136, 1312, 0, 768, 769, 772, 800, 0, 222 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 223 /* 1024x768@85Hz */ 224 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 225 1168, 1376, 0, 768, 769, 772, 808, 0, 226 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 227 /* 1024x768@120Hz RB */ 228 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 229 1104, 1184, 0, 768, 771, 775, 813, 0, 230 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 231 /* 1152x864@75Hz */ 232 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 233 1344, 1600, 0, 864, 865, 868, 900, 0, 234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 235 /* 1280x768@60Hz RB */ 236 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 237 1360, 1440, 0, 768, 771, 778, 790, 0, 238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 239 /* 1280x768@60Hz */ 240 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 241 1472, 1664, 0, 768, 771, 778, 798, 0, 242 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 243 /* 1280x768@75Hz */ 244 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 245 1488, 1696, 0, 768, 771, 778, 805, 0, 246 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 247 /* 1280x768@85Hz */ 248 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 249 1496, 1712, 0, 768, 771, 778, 809, 0, 250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 251 /* 1280x768@120Hz RB */ 252 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 253 1360, 1440, 0, 768, 771, 778, 813, 0, 254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 255 /* 1280x800@60Hz RB */ 256 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 257 1360, 1440, 0, 800, 803, 809, 823, 0, 258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 259 /* 1280x800@60Hz */ 260 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 261 1480, 1680, 0, 800, 803, 809, 831, 0, 262 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 263 /* 1280x800@75Hz */ 264 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 265 1488, 1696, 0, 800, 803, 809, 838, 0, 266 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 267 /* 1280x800@85Hz */ 268 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 269 1496, 1712, 0, 800, 803, 809, 843, 0, 270 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 271 /* 1280x800@120Hz RB */ 272 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 273 1360, 1440, 0, 800, 803, 809, 847, 0, 274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 275 /* 1280x960@60Hz */ 276 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 277 1488, 1800, 0, 960, 961, 964, 1000, 0, 278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 279 /* 1280x960@85Hz */ 280 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 281 1504, 1728, 0, 960, 961, 964, 1011, 0, 282 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 283 /* 1280x960@120Hz RB */ 284 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 285 1360, 1440, 0, 960, 963, 967, 1017, 0, 286 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 287 /* 1280x1024@60Hz */ 288 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 289 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 290 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 291 /* 1280x1024@75Hz */ 292 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 293 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 295 /* 1280x1024@85Hz */ 296 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 297 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 299 /* 1280x1024@120Hz RB */ 300 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 301 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 302 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 303 /* 1360x768@60Hz */ 304 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 305 1536, 1792, 0, 768, 771, 777, 795, 0, 306 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 307 /* 1360x768@120Hz RB */ 308 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 309 1440, 1520, 0, 768, 771, 776, 813, 0, 310 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 311 /* 1400x1050@60Hz RB */ 312 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 313 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 315 /* 1400x1050@60Hz */ 316 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 317 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 318 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 319 /* 1400x1050@75Hz */ 320 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 321 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 322 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 323 /* 1400x1050@85Hz */ 324 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 325 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 326 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 327 /* 1400x1050@120Hz RB */ 328 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 329 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 330 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 331 /* 1440x900@60Hz RB */ 332 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 333 1520, 1600, 0, 900, 903, 909, 926, 0, 334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 335 /* 1440x900@60Hz */ 336 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 337 1672, 1904, 0, 900, 903, 909, 934, 0, 338 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 339 /* 1440x900@75Hz */ 340 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 341 1688, 1936, 0, 900, 903, 909, 942, 0, 342 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 343 /* 1440x900@85Hz */ 344 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 345 1696, 1952, 0, 900, 903, 909, 948, 0, 346 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 347 /* 1440x900@120Hz RB */ 348 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 349 1520, 1600, 0, 900, 903, 909, 953, 0, 350 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 351 /* 1600x1200@60Hz */ 352 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 353 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 355 /* 1600x1200@65Hz */ 356 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 357 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 359 /* 1600x1200@70Hz */ 360 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 361 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 362 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 363 /* 1600x1200@75Hz */ 364 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 365 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 366 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 367 /* 1600x1200@85Hz */ 368 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 369 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 370 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 371 /* 1600x1200@120Hz RB */ 372 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 373 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 375 /* 1680x1050@60Hz RB */ 376 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 377 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 379 /* 1680x1050@60Hz */ 380 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 381 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 382 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 383 /* 1680x1050@75Hz */ 384 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 385 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 386 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 387 /* 1680x1050@85Hz */ 388 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 389 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 390 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 391 /* 1680x1050@120Hz RB */ 392 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 393 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 394 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 395 /* 1792x1344@60Hz */ 396 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 397 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 398 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 399 /* 1792x1344@75Hz */ 400 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 401 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 402 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 403 /* 1792x1344@120Hz RB */ 404 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 405 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 406 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 407 /* 1856x1392@60Hz */ 408 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 409 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 410 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 411 /* 1856x1392@75Hz */ 412 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 413 2208, 2560, 0, 1392, 1395, 1399, 1500, 0, 414 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 415 /* 1856x1392@120Hz RB */ 416 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 417 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 418 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 419 /* 1920x1200@60Hz RB */ 420 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 421 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 423 /* 1920x1200@60Hz */ 424 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 425 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 426 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 427 /* 1920x1200@75Hz */ 428 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 429 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 430 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 431 /* 1920x1200@85Hz */ 432 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 433 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 434 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 435 /* 1920x1200@120Hz RB */ 436 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 437 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 439 /* 1920x1440@60Hz */ 440 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 441 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 442 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 443 /* 1920x1440@75Hz */ 444 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 445 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 446 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 447 /* 1920x1440@120Hz RB */ 448 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 449 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 451 /* 2560x1600@60Hz RB */ 452 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 453 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 455 /* 2560x1600@60Hz */ 456 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 457 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 458 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 459 /* 2560x1600@75HZ */ 460 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 461 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 462 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 463 /* 2560x1600@85HZ */ 464 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 465 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 466 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 467 /* 2560x1600@120Hz RB */ 468 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 469 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 471 }; 472 473 /* 474 * These more or less come from the DMT spec. The 720x400 modes are 475 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 476 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 477 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 478 * mode. 479 * 480 * The DMT modes have been fact-checked; the rest are mild guesses. 481 */ 482 static const struct drm_display_mode edid_est_modes[] = { 483 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 484 968, 1056, 0, 600, 601, 605, 628, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 486 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 487 896, 1024, 0, 600, 601, 603, 625, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 489 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 490 720, 840, 0, 480, 481, 484, 500, 0, 491 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 492 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 493 704, 832, 0, 480, 489, 491, 520, 0, 494 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 495 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 496 768, 864, 0, 480, 483, 486, 525, 0, 497 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 498 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 499 752, 800, 0, 480, 490, 492, 525, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 501 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 502 846, 900, 0, 400, 421, 423, 449, 0, 503 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 504 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 505 846, 900, 0, 400, 412, 414, 449, 0, 506 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 507 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 508 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 509 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 510 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 511 1136, 1312, 0, 768, 769, 772, 800, 0, 512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 513 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 514 1184, 1328, 0, 768, 771, 777, 806, 0, 515 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 516 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 517 1184, 1344, 0, 768, 771, 777, 806, 0, 518 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 519 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 520 1208, 1264, 0, 768, 768, 776, 817, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 522 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 523 928, 1152, 0, 624, 625, 628, 667, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 525 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 526 896, 1056, 0, 600, 601, 604, 625, 0, 527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 528 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 529 976, 1040, 0, 600, 637, 643, 666, 0, 530 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 531 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 532 1344, 1600, 0, 864, 865, 868, 900, 0, 533 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 534 }; 535 536 struct minimode { 537 short w; 538 short h; 539 short r; 540 short rb; 541 }; 542 543 static const struct minimode est3_modes[] = { 544 /* byte 6 */ 545 { 640, 350, 85, 0 }, 546 { 640, 400, 85, 0 }, 547 { 720, 400, 85, 0 }, 548 { 640, 480, 85, 0 }, 549 { 848, 480, 60, 0 }, 550 { 800, 600, 85, 0 }, 551 { 1024, 768, 85, 0 }, 552 { 1152, 864, 75, 0 }, 553 /* byte 7 */ 554 { 1280, 768, 60, 1 }, 555 { 1280, 768, 60, 0 }, 556 { 1280, 768, 75, 0 }, 557 { 1280, 768, 85, 0 }, 558 { 1280, 960, 60, 0 }, 559 { 1280, 960, 85, 0 }, 560 { 1280, 1024, 60, 0 }, 561 { 1280, 1024, 85, 0 }, 562 /* byte 8 */ 563 { 1360, 768, 60, 0 }, 564 { 1440, 900, 60, 1 }, 565 { 1440, 900, 60, 0 }, 566 { 1440, 900, 75, 0 }, 567 { 1440, 900, 85, 0 }, 568 { 1400, 1050, 60, 1 }, 569 { 1400, 1050, 60, 0 }, 570 { 1400, 1050, 75, 0 }, 571 /* byte 9 */ 572 { 1400, 1050, 85, 0 }, 573 { 1680, 1050, 60, 1 }, 574 { 1680, 1050, 60, 0 }, 575 { 1680, 1050, 75, 0 }, 576 { 1680, 1050, 85, 0 }, 577 { 1600, 1200, 60, 0 }, 578 { 1600, 1200, 65, 0 }, 579 { 1600, 1200, 70, 0 }, 580 /* byte 10 */ 581 { 1600, 1200, 75, 0 }, 582 { 1600, 1200, 85, 0 }, 583 { 1792, 1344, 60, 0 }, 584 { 1792, 1344, 75, 0 }, 585 { 1856, 1392, 60, 0 }, 586 { 1856, 1392, 75, 0 }, 587 { 1920, 1200, 60, 1 }, 588 { 1920, 1200, 60, 0 }, 589 /* byte 11 */ 590 { 1920, 1200, 75, 0 }, 591 { 1920, 1200, 85, 0 }, 592 { 1920, 1440, 60, 0 }, 593 { 1920, 1440, 75, 0 }, 594 }; 595 596 static const struct minimode extra_modes[] = { 597 { 1024, 576, 60, 0 }, 598 { 1366, 768, 60, 0 }, 599 { 1600, 900, 60, 0 }, 600 { 1680, 945, 60, 0 }, 601 { 1920, 1080, 60, 0 }, 602 { 2048, 1152, 60, 0 }, 603 { 2048, 1536, 60, 0 }, 604 }; 605 606 /* 607 * Probably taken from CEA-861 spec. 608 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 609 */ 610 static const struct drm_display_mode edid_cea_modes[] = { 611 /* 1 - 640x480@60Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 613 752, 800, 0, 480, 490, 492, 525, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 615 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 616 /* 2 - 720x480@60Hz */ 617 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 618 798, 858, 0, 480, 489, 495, 525, 0, 619 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 620 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 621 /* 3 - 720x480@60Hz */ 622 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 623 798, 858, 0, 480, 489, 495, 525, 0, 624 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 625 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 626 /* 4 - 1280x720@60Hz */ 627 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 628 1430, 1650, 0, 720, 725, 730, 750, 0, 629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 630 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 631 /* 5 - 1920x1080i@60Hz */ 632 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 633 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 634 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 635 DRM_MODE_FLAG_INTERLACE), 636 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 637 /* 6 - 1440x480i@60Hz */ 638 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 639 1602, 1716, 0, 480, 488, 494, 525, 0, 640 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 641 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 642 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 643 /* 7 - 1440x480i@60Hz */ 644 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 645 1602, 1716, 0, 480, 488, 494, 525, 0, 646 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 647 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 648 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 649 /* 8 - 1440x240@60Hz */ 650 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 651 1602, 1716, 0, 240, 244, 247, 262, 0, 652 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 653 DRM_MODE_FLAG_DBLCLK), 654 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 655 /* 9 - 1440x240@60Hz */ 656 { DRM_MODE("1440x240", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1478, 657 1602, 1716, 0, 240, 244, 247, 262, 0, 658 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 659 DRM_MODE_FLAG_DBLCLK), 660 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 661 /* 10 - 2880x480i@60Hz */ 662 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 663 3204, 3432, 0, 480, 488, 494, 525, 0, 664 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 665 DRM_MODE_FLAG_INTERLACE), 666 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 667 /* 11 - 2880x480i@60Hz */ 668 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 669 3204, 3432, 0, 480, 488, 494, 525, 0, 670 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 671 DRM_MODE_FLAG_INTERLACE), 672 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 673 /* 12 - 2880x240@60Hz */ 674 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 675 3204, 3432, 0, 240, 244, 247, 262, 0, 676 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 677 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 678 /* 13 - 2880x240@60Hz */ 679 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 680 3204, 3432, 0, 240, 244, 247, 262, 0, 681 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 682 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 683 /* 14 - 1440x480@60Hz */ 684 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 685 1596, 1716, 0, 480, 489, 495, 525, 0, 686 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 687 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 688 /* 15 - 1440x480@60Hz */ 689 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 690 1596, 1716, 0, 480, 489, 495, 525, 0, 691 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 692 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 693 /* 16 - 1920x1080@60Hz */ 694 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 695 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 696 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 697 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 698 /* 17 - 720x576@50Hz */ 699 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 700 796, 864, 0, 576, 581, 586, 625, 0, 701 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 702 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 703 /* 18 - 720x576@50Hz */ 704 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 705 796, 864, 0, 576, 581, 586, 625, 0, 706 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 707 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 708 /* 19 - 1280x720@50Hz */ 709 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 710 1760, 1980, 0, 720, 725, 730, 750, 0, 711 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 712 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 713 /* 20 - 1920x1080i@50Hz */ 714 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 715 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 716 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 717 DRM_MODE_FLAG_INTERLACE), 718 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 719 /* 21 - 1440x576i@50Hz */ 720 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 721 1590, 1728, 0, 576, 580, 586, 625, 0, 722 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 723 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 724 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 725 /* 22 - 1440x576i@50Hz */ 726 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 727 1590, 1728, 0, 576, 580, 586, 625, 0, 728 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 729 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 730 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 731 /* 23 - 1440x288@50Hz */ 732 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 733 1590, 1728, 0, 288, 290, 293, 312, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 735 DRM_MODE_FLAG_DBLCLK), 736 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 24 - 1440x288@50Hz */ 738 { DRM_MODE("1440x288", DRM_MODE_TYPE_DRIVER, 27000, 1440, 1464, 739 1590, 1728, 0, 288, 290, 293, 312, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 741 DRM_MODE_FLAG_DBLCLK), 742 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 743 /* 25 - 2880x576i@50Hz */ 744 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 745 3180, 3456, 0, 576, 580, 586, 625, 0, 746 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 747 DRM_MODE_FLAG_INTERLACE), 748 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 749 /* 26 - 2880x576i@50Hz */ 750 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 751 3180, 3456, 0, 576, 580, 586, 625, 0, 752 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 753 DRM_MODE_FLAG_INTERLACE), 754 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 755 /* 27 - 2880x288@50Hz */ 756 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 757 3180, 3456, 0, 288, 290, 293, 312, 0, 758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 759 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 760 /* 28 - 2880x288@50Hz */ 761 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 762 3180, 3456, 0, 288, 290, 293, 312, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 764 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 29 - 1440x576@50Hz */ 766 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 767 1592, 1728, 0, 576, 581, 586, 625, 0, 768 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 769 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 770 /* 30 - 1440x576@50Hz */ 771 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 772 1592, 1728, 0, 576, 581, 586, 625, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 774 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 775 /* 31 - 1920x1080@50Hz */ 776 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 777 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 778 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 779 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 780 /* 32 - 1920x1080@24Hz */ 781 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 782 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 783 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 784 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 785 /* 33 - 1920x1080@25Hz */ 786 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 787 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 788 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 789 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 34 - 1920x1080@30Hz */ 791 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 792 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 794 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 795 /* 35 - 2880x480@60Hz */ 796 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 797 3192, 3432, 0, 480, 489, 495, 525, 0, 798 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 799 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 800 /* 36 - 2880x480@60Hz */ 801 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 802 3192, 3432, 0, 480, 489, 495, 525, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 804 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 805 /* 37 - 2880x576@50Hz */ 806 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 807 3184, 3456, 0, 576, 581, 586, 625, 0, 808 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 809 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 810 /* 38 - 2880x576@50Hz */ 811 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 812 3184, 3456, 0, 576, 581, 586, 625, 0, 813 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 814 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 815 /* 39 - 1920x1080i@50Hz */ 816 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 817 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 818 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 819 DRM_MODE_FLAG_INTERLACE), 820 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 821 /* 40 - 1920x1080i@100Hz */ 822 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 823 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 824 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 825 DRM_MODE_FLAG_INTERLACE), 826 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 827 /* 41 - 1280x720@100Hz */ 828 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 829 1760, 1980, 0, 720, 725, 730, 750, 0, 830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 831 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 42 - 720x576@100Hz */ 833 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 834 796, 864, 0, 576, 581, 586, 625, 0, 835 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 836 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 837 /* 43 - 720x576@100Hz */ 838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 839 796, 864, 0, 576, 581, 586, 625, 0, 840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 841 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 842 /* 44 - 1440x576i@100Hz */ 843 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 844 1590, 1728, 0, 576, 580, 586, 625, 0, 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 846 DRM_MODE_FLAG_DBLCLK), 847 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 848 /* 45 - 1440x576i@100Hz */ 849 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 850 1590, 1728, 0, 576, 580, 586, 625, 0, 851 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 852 DRM_MODE_FLAG_DBLCLK), 853 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 46 - 1920x1080i@120Hz */ 855 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 856 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 858 DRM_MODE_FLAG_INTERLACE), 859 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 860 /* 47 - 1280x720@120Hz */ 861 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 862 1430, 1650, 0, 720, 725, 730, 750, 0, 863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 864 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 865 /* 48 - 720x480@120Hz */ 866 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 867 798, 858, 0, 480, 489, 495, 525, 0, 868 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 869 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 870 /* 49 - 720x480@120Hz */ 871 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 872 798, 858, 0, 480, 489, 495, 525, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 874 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 875 /* 50 - 1440x480i@120Hz */ 876 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 877 1602, 1716, 0, 480, 488, 494, 525, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 879 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 880 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 881 /* 51 - 1440x480i@120Hz */ 882 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1478, 883 1602, 1716, 0, 480, 488, 494, 525, 0, 884 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 885 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 886 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 887 /* 52 - 720x576@200Hz */ 888 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 889 796, 864, 0, 576, 581, 586, 625, 0, 890 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 891 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 892 /* 53 - 720x576@200Hz */ 893 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 894 796, 864, 0, 576, 581, 586, 625, 0, 895 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 896 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 897 /* 54 - 1440x576i@200Hz */ 898 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 899 1590, 1728, 0, 576, 580, 586, 625, 0, 900 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 901 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 902 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 903 /* 55 - 1440x576i@200Hz */ 904 { DRM_MODE("1440x576i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1464, 905 1590, 1728, 0, 576, 580, 586, 625, 0, 906 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 907 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 908 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 909 /* 56 - 720x480@240Hz */ 910 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 911 798, 858, 0, 480, 489, 495, 525, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 914 /* 57 - 720x480@240Hz */ 915 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 916 798, 858, 0, 480, 489, 495, 525, 0, 917 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 918 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 58 - 1440x480i@240 */ 920 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 921 1602, 1716, 0, 480, 488, 494, 525, 0, 922 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 923 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 924 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 925 /* 59 - 1440x480i@240 */ 926 { DRM_MODE("1440x480i", DRM_MODE_TYPE_DRIVER, 108000, 1440, 1478, 927 1602, 1716, 0, 480, 488, 494, 525, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 929 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 930 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 931 /* 60 - 1280x720@24Hz */ 932 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 933 3080, 3300, 0, 720, 725, 730, 750, 0, 934 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 935 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 61 - 1280x720@25Hz */ 937 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 938 3740, 3960, 0, 720, 725, 730, 750, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 940 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 941 /* 62 - 1280x720@30Hz */ 942 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 943 3080, 3300, 0, 720, 725, 730, 750, 0, 944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 945 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 946 /* 63 - 1920x1080@120Hz */ 947 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 948 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 949 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 950 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 951 /* 64 - 1920x1080@100Hz */ 952 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 953 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 954 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 955 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 }; 957 958 /* 959 * HDMI 1.4 4k modes. 960 */ 961 static const struct drm_display_mode edid_4k_modes[] = { 962 /* 1 - 3840x2160@30Hz */ 963 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 964 3840, 4016, 4104, 4400, 0, 965 2160, 2168, 2178, 2250, 0, 966 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 967 .vrefresh = 30, }, 968 /* 2 - 3840x2160@25Hz */ 969 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 970 3840, 4896, 4984, 5280, 0, 971 2160, 2168, 2178, 2250, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 973 .vrefresh = 25, }, 974 /* 3 - 3840x2160@24Hz */ 975 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 976 3840, 5116, 5204, 5500, 0, 977 2160, 2168, 2178, 2250, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 979 .vrefresh = 24, }, 980 /* 4 - 4096x2160@24Hz (SMPTE) */ 981 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 982 4096, 5116, 5204, 5500, 0, 983 2160, 2168, 2178, 2250, 0, 984 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 985 .vrefresh = 24, }, 986 }; 987 988 /*** DDC fetch and block validation ***/ 989 990 static const u8 edid_header[] = { 991 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 992 }; 993 994 /* 995 * Sanity check the header of the base EDID block. Return 8 if the header 996 * is perfect, down to 0 if it's totally wrong. 997 */ 998 int drm_edid_header_is_valid(const u8 *raw_edid) 999 { 1000 int i, score = 0; 1001 1002 for (i = 0; i < sizeof(edid_header); i++) 1003 if (raw_edid[i] == edid_header[i]) 1004 score++; 1005 1006 return score; 1007 } 1008 EXPORT_SYMBOL(drm_edid_header_is_valid); 1009 1010 static int edid_fixup __read_mostly = 6; 1011 module_param_named(edid_fixup, edid_fixup, int, 0400); 1012 MODULE_PARM_DESC(edid_fixup, 1013 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1014 1015 /* 1016 * Sanity check the EDID block (base or extension). Return 0 if the block 1017 * doesn't check out, or 1 if it's valid. 1018 */ 1019 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid) 1020 { 1021 int i; 1022 u8 csum = 0; 1023 struct edid *edid = (struct edid *)raw_edid; 1024 1025 if (WARN_ON(!raw_edid)) 1026 return false; 1027 1028 if (edid_fixup > 8 || edid_fixup < 0) 1029 edid_fixup = 6; 1030 1031 if (block == 0) { 1032 int score = drm_edid_header_is_valid(raw_edid); 1033 if (score == 8) ; 1034 else if (score >= edid_fixup) { 1035 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1036 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1037 } else { 1038 goto bad; 1039 } 1040 } 1041 1042 for (i = 0; i < EDID_LENGTH; i++) 1043 csum += raw_edid[i]; 1044 if (csum) { 1045 if (print_bad_edid) { 1046 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1047 } 1048 1049 /* allow CEA to slide through, switches mangle this */ 1050 if (raw_edid[0] != 0x02) 1051 goto bad; 1052 } 1053 1054 /* per-block-type checks */ 1055 switch (raw_edid[0]) { 1056 case 0: /* base */ 1057 if (edid->version != 1) { 1058 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1059 goto bad; 1060 } 1061 1062 if (edid->revision > 4) 1063 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1064 break; 1065 1066 default: 1067 break; 1068 } 1069 1070 return true; 1071 1072 bad: 1073 if (print_bad_edid) { 1074 printk(KERN_ERR "Raw EDID:\n"); 1075 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1076 raw_edid, EDID_LENGTH, false); 1077 } 1078 return false; 1079 } 1080 EXPORT_SYMBOL(drm_edid_block_valid); 1081 1082 /** 1083 * drm_edid_is_valid - sanity check EDID data 1084 * @edid: EDID data 1085 * 1086 * Sanity-check an entire EDID record (including extensions) 1087 */ 1088 bool drm_edid_is_valid(struct edid *edid) 1089 { 1090 int i; 1091 u8 *raw = (u8 *)edid; 1092 1093 if (!edid) 1094 return false; 1095 1096 for (i = 0; i <= edid->extensions; i++) 1097 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true)) 1098 return false; 1099 1100 return true; 1101 } 1102 EXPORT_SYMBOL(drm_edid_is_valid); 1103 1104 #define DDC_SEGMENT_ADDR 0x30 1105 /** 1106 * Get EDID information via I2C. 1107 * 1108 * @adapter : i2c device adaptor 1109 * @buf: EDID data buffer to be filled 1110 * @block: 128 byte EDID block to start fetching from 1111 * @len: EDID data buffer length to fetch 1112 * 1113 * Returns: 1114 * 1115 * 0 on success or -1 on failure. 1116 * 1117 * Try to fetch EDID information by calling i2c driver function. 1118 */ 1119 static int 1120 drm_do_probe_ddc_edid(struct i2c_adapter *adapter, unsigned char *buf, 1121 int block, int len) 1122 { 1123 unsigned char start = block * EDID_LENGTH; 1124 unsigned char segment = block >> 1; 1125 unsigned char xfers = segment ? 3 : 2; 1126 int ret, retries = 5; 1127 1128 /* The core i2c driver will automatically retry the transfer if the 1129 * adapter reports EAGAIN. However, we find that bit-banging transfers 1130 * are susceptible to errors under a heavily loaded machine and 1131 * generate spurious NAKs and timeouts. Retrying the transfer 1132 * of the individual block a few times seems to overcome this. 1133 */ 1134 do { 1135 struct i2c_msg msgs[] = { 1136 { 1137 .addr = DDC_SEGMENT_ADDR, 1138 .flags = 0, 1139 .len = 1, 1140 .buf = &segment, 1141 }, { 1142 .addr = DDC_ADDR, 1143 .flags = 0, 1144 .len = 1, 1145 .buf = &start, 1146 }, { 1147 .addr = DDC_ADDR, 1148 .flags = I2C_M_RD, 1149 .len = len, 1150 .buf = buf, 1151 } 1152 }; 1153 1154 /* 1155 * Avoid sending the segment addr to not upset non-compliant ddc 1156 * monitors. 1157 */ 1158 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1159 1160 if (ret == -ENXIO) { 1161 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1162 adapter->name); 1163 break; 1164 } 1165 } while (ret != xfers && --retries); 1166 1167 return ret == xfers ? 0 : -1; 1168 } 1169 1170 static bool drm_edid_is_zero(u8 *in_edid, int length) 1171 { 1172 if (memchr_inv(in_edid, 0, length)) 1173 return false; 1174 1175 return true; 1176 } 1177 1178 static u8 * 1179 drm_do_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) 1180 { 1181 int i, j = 0, valid_extensions = 0; 1182 u8 *block, *new; 1183 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1184 1185 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1186 return NULL; 1187 1188 /* base block fetch */ 1189 for (i = 0; i < 4; i++) { 1190 if (drm_do_probe_ddc_edid(adapter, block, 0, EDID_LENGTH)) 1191 goto out; 1192 if (drm_edid_block_valid(block, 0, print_bad_edid)) 1193 break; 1194 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1195 connector->null_edid_counter++; 1196 goto carp; 1197 } 1198 } 1199 if (i == 4) 1200 goto carp; 1201 1202 /* if there's no extensions, we're done */ 1203 if (block[0x7e] == 0) 1204 return block; 1205 1206 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1207 if (!new) 1208 goto out; 1209 block = new; 1210 1211 for (j = 1; j <= block[0x7e]; j++) { 1212 for (i = 0; i < 4; i++) { 1213 if (drm_do_probe_ddc_edid(adapter, 1214 block + (valid_extensions + 1) * EDID_LENGTH, 1215 j, EDID_LENGTH)) 1216 goto out; 1217 if (drm_edid_block_valid(block + (valid_extensions + 1) * EDID_LENGTH, j, print_bad_edid)) { 1218 valid_extensions++; 1219 break; 1220 } 1221 } 1222 1223 if (i == 4 && print_bad_edid) { 1224 dev_warn(connector->dev->dev, 1225 "%s: Ignoring invalid EDID block %d.\n", 1226 drm_get_connector_name(connector), j); 1227 1228 connector->bad_edid_counter++; 1229 } 1230 } 1231 1232 if (valid_extensions != block[0x7e]) { 1233 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1234 block[0x7e] = valid_extensions; 1235 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1236 if (!new) 1237 goto out; 1238 block = new; 1239 } 1240 1241 return block; 1242 1243 carp: 1244 if (print_bad_edid) { 1245 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1246 drm_get_connector_name(connector), j); 1247 } 1248 connector->bad_edid_counter++; 1249 1250 out: 1251 kfree(block); 1252 return NULL; 1253 } 1254 1255 /** 1256 * Probe DDC presence. 1257 * @adapter: i2c adapter to probe 1258 * 1259 * Returns: 1260 * 1261 * 1 on success 1262 */ 1263 bool 1264 drm_probe_ddc(struct i2c_adapter *adapter) 1265 { 1266 unsigned char out; 1267 1268 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1269 } 1270 EXPORT_SYMBOL(drm_probe_ddc); 1271 1272 /** 1273 * drm_get_edid - get EDID data, if available 1274 * @connector: connector we're probing 1275 * @adapter: i2c adapter to use for DDC 1276 * 1277 * Poke the given i2c channel to grab EDID data if possible. If found, 1278 * attach it to the connector. 1279 * 1280 * Return edid data or NULL if we couldn't find any. 1281 */ 1282 struct edid *drm_get_edid(struct drm_connector *connector, 1283 struct i2c_adapter *adapter) 1284 { 1285 struct edid *edid = NULL; 1286 1287 if (drm_probe_ddc(adapter)) 1288 edid = (struct edid *)drm_do_get_edid(connector, adapter); 1289 1290 return edid; 1291 } 1292 EXPORT_SYMBOL(drm_get_edid); 1293 1294 /** 1295 * drm_edid_duplicate - duplicate an EDID and the extensions 1296 * @edid: EDID to duplicate 1297 * 1298 * Return duplicate edid or NULL on allocation failure. 1299 */ 1300 struct edid *drm_edid_duplicate(const struct edid *edid) 1301 { 1302 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1303 } 1304 EXPORT_SYMBOL(drm_edid_duplicate); 1305 1306 /*** EDID parsing ***/ 1307 1308 /** 1309 * edid_vendor - match a string against EDID's obfuscated vendor field 1310 * @edid: EDID to match 1311 * @vendor: vendor string 1312 * 1313 * Returns true if @vendor is in @edid, false otherwise 1314 */ 1315 static bool edid_vendor(struct edid *edid, char *vendor) 1316 { 1317 char edid_vendor[3]; 1318 1319 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1320 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1321 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1322 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1323 1324 return !strncmp(edid_vendor, vendor, 3); 1325 } 1326 1327 /** 1328 * edid_get_quirks - return quirk flags for a given EDID 1329 * @edid: EDID to process 1330 * 1331 * This tells subsequent routines what fixes they need to apply. 1332 */ 1333 static u32 edid_get_quirks(struct edid *edid) 1334 { 1335 struct edid_quirk *quirk; 1336 int i; 1337 1338 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1339 quirk = &edid_quirk_list[i]; 1340 1341 if (edid_vendor(edid, quirk->vendor) && 1342 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1343 return quirk->quirks; 1344 } 1345 1346 return 0; 1347 } 1348 1349 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1350 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1351 1352 /** 1353 * edid_fixup_preferred - set preferred modes based on quirk list 1354 * @connector: has mode list to fix up 1355 * @quirks: quirks list 1356 * 1357 * Walk the mode list for @connector, clearing the preferred status 1358 * on existing modes and setting it anew for the right mode ala @quirks. 1359 */ 1360 static void edid_fixup_preferred(struct drm_connector *connector, 1361 u32 quirks) 1362 { 1363 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1364 int target_refresh = 0; 1365 int cur_vrefresh, preferred_vrefresh; 1366 1367 if (list_empty(&connector->probed_modes)) 1368 return; 1369 1370 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1371 target_refresh = 60; 1372 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1373 target_refresh = 75; 1374 1375 preferred_mode = list_first_entry(&connector->probed_modes, 1376 struct drm_display_mode, head); 1377 1378 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1379 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1380 1381 if (cur_mode == preferred_mode) 1382 continue; 1383 1384 /* Largest mode is preferred */ 1385 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1386 preferred_mode = cur_mode; 1387 1388 cur_vrefresh = cur_mode->vrefresh ? 1389 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1390 preferred_vrefresh = preferred_mode->vrefresh ? 1391 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1392 /* At a given size, try to get closest to target refresh */ 1393 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1394 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1395 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1396 preferred_mode = cur_mode; 1397 } 1398 } 1399 1400 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1401 } 1402 1403 static bool 1404 mode_is_rb(const struct drm_display_mode *mode) 1405 { 1406 return (mode->htotal - mode->hdisplay == 160) && 1407 (mode->hsync_end - mode->hdisplay == 80) && 1408 (mode->hsync_end - mode->hsync_start == 32) && 1409 (mode->vsync_start - mode->vdisplay == 3); 1410 } 1411 1412 /* 1413 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1414 * @dev: Device to duplicate against 1415 * @hsize: Mode width 1416 * @vsize: Mode height 1417 * @fresh: Mode refresh rate 1418 * @rb: Mode reduced-blanking-ness 1419 * 1420 * Walk the DMT mode list looking for a match for the given parameters. 1421 * Return a newly allocated copy of the mode, or NULL if not found. 1422 */ 1423 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1424 int hsize, int vsize, int fresh, 1425 bool rb) 1426 { 1427 int i; 1428 1429 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1430 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1431 if (hsize != ptr->hdisplay) 1432 continue; 1433 if (vsize != ptr->vdisplay) 1434 continue; 1435 if (fresh != drm_mode_vrefresh(ptr)) 1436 continue; 1437 if (rb != mode_is_rb(ptr)) 1438 continue; 1439 1440 return drm_mode_duplicate(dev, ptr); 1441 } 1442 1443 return NULL; 1444 } 1445 EXPORT_SYMBOL(drm_mode_find_dmt); 1446 1447 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1448 1449 static void 1450 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1451 { 1452 int i, n = 0; 1453 u8 d = ext[0x02]; 1454 u8 *det_base = ext + d; 1455 1456 n = (127 - d) / 18; 1457 for (i = 0; i < n; i++) 1458 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1459 } 1460 1461 static void 1462 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1463 { 1464 unsigned int i, n = min((int)ext[0x02], 6); 1465 u8 *det_base = ext + 5; 1466 1467 if (ext[0x01] != 1) 1468 return; /* unknown version */ 1469 1470 for (i = 0; i < n; i++) 1471 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1472 } 1473 1474 static void 1475 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1476 { 1477 int i; 1478 struct edid *edid = (struct edid *)raw_edid; 1479 1480 if (edid == NULL) 1481 return; 1482 1483 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1484 cb(&(edid->detailed_timings[i]), closure); 1485 1486 for (i = 1; i <= raw_edid[0x7e]; i++) { 1487 u8 *ext = raw_edid + (i * EDID_LENGTH); 1488 switch (*ext) { 1489 case CEA_EXT: 1490 cea_for_each_detailed_block(ext, cb, closure); 1491 break; 1492 case VTB_EXT: 1493 vtb_for_each_detailed_block(ext, cb, closure); 1494 break; 1495 default: 1496 break; 1497 } 1498 } 1499 } 1500 1501 static void 1502 is_rb(struct detailed_timing *t, void *data) 1503 { 1504 u8 *r = (u8 *)t; 1505 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1506 if (r[15] & 0x10) 1507 *(bool *)data = true; 1508 } 1509 1510 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1511 static bool 1512 drm_monitor_supports_rb(struct edid *edid) 1513 { 1514 if (edid->revision >= 4) { 1515 bool ret = false; 1516 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1517 return ret; 1518 } 1519 1520 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1521 } 1522 1523 static void 1524 find_gtf2(struct detailed_timing *t, void *data) 1525 { 1526 u8 *r = (u8 *)t; 1527 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1528 *(u8 **)data = r; 1529 } 1530 1531 /* Secondary GTF curve kicks in above some break frequency */ 1532 static int 1533 drm_gtf2_hbreak(struct edid *edid) 1534 { 1535 u8 *r = NULL; 1536 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1537 return r ? (r[12] * 2) : 0; 1538 } 1539 1540 static int 1541 drm_gtf2_2c(struct edid *edid) 1542 { 1543 u8 *r = NULL; 1544 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1545 return r ? r[13] : 0; 1546 } 1547 1548 static int 1549 drm_gtf2_m(struct edid *edid) 1550 { 1551 u8 *r = NULL; 1552 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1553 return r ? (r[15] << 8) + r[14] : 0; 1554 } 1555 1556 static int 1557 drm_gtf2_k(struct edid *edid) 1558 { 1559 u8 *r = NULL; 1560 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1561 return r ? r[16] : 0; 1562 } 1563 1564 static int 1565 drm_gtf2_2j(struct edid *edid) 1566 { 1567 u8 *r = NULL; 1568 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1569 return r ? r[17] : 0; 1570 } 1571 1572 /** 1573 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1574 * @edid: EDID block to scan 1575 */ 1576 static int standard_timing_level(struct edid *edid) 1577 { 1578 if (edid->revision >= 2) { 1579 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1580 return LEVEL_CVT; 1581 if (drm_gtf2_hbreak(edid)) 1582 return LEVEL_GTF2; 1583 return LEVEL_GTF; 1584 } 1585 return LEVEL_DMT; 1586 } 1587 1588 /* 1589 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1590 * monitors fill with ascii space (0x20) instead. 1591 */ 1592 static int 1593 bad_std_timing(u8 a, u8 b) 1594 { 1595 return (a == 0x00 && b == 0x00) || 1596 (a == 0x01 && b == 0x01) || 1597 (a == 0x20 && b == 0x20); 1598 } 1599 1600 /** 1601 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1602 * @connector: connector of for the EDID block 1603 * @edid: EDID block to scan 1604 * @t: standard timing params 1605 * @revision: standard timing level 1606 * 1607 * Take the standard timing params (in this case width, aspect, and refresh) 1608 * and convert them into a real mode using CVT/GTF/DMT. 1609 */ 1610 static struct drm_display_mode * 1611 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1612 struct std_timing *t, int revision) 1613 { 1614 struct drm_device *dev = connector->dev; 1615 struct drm_display_mode *m, *mode = NULL; 1616 int hsize, vsize; 1617 int vrefresh_rate; 1618 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1619 >> EDID_TIMING_ASPECT_SHIFT; 1620 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1621 >> EDID_TIMING_VFREQ_SHIFT; 1622 int timing_level = standard_timing_level(edid); 1623 1624 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1625 return NULL; 1626 1627 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1628 hsize = t->hsize * 8 + 248; 1629 /* vrefresh_rate = vfreq + 60 */ 1630 vrefresh_rate = vfreq + 60; 1631 /* the vdisplay is calculated based on the aspect ratio */ 1632 if (aspect_ratio == 0) { 1633 if (revision < 3) 1634 vsize = hsize; 1635 else 1636 vsize = (hsize * 10) / 16; 1637 } else if (aspect_ratio == 1) 1638 vsize = (hsize * 3) / 4; 1639 else if (aspect_ratio == 2) 1640 vsize = (hsize * 4) / 5; 1641 else 1642 vsize = (hsize * 9) / 16; 1643 1644 /* HDTV hack, part 1 */ 1645 if (vrefresh_rate == 60 && 1646 ((hsize == 1360 && vsize == 765) || 1647 (hsize == 1368 && vsize == 769))) { 1648 hsize = 1366; 1649 vsize = 768; 1650 } 1651 1652 /* 1653 * If this connector already has a mode for this size and refresh 1654 * rate (because it came from detailed or CVT info), use that 1655 * instead. This way we don't have to guess at interlace or 1656 * reduced blanking. 1657 */ 1658 list_for_each_entry(m, &connector->probed_modes, head) 1659 if (m->hdisplay == hsize && m->vdisplay == vsize && 1660 drm_mode_vrefresh(m) == vrefresh_rate) 1661 return NULL; 1662 1663 /* HDTV hack, part 2 */ 1664 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1665 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1666 false); 1667 mode->hdisplay = 1366; 1668 mode->hsync_start = mode->hsync_start - 1; 1669 mode->hsync_end = mode->hsync_end - 1; 1670 return mode; 1671 } 1672 1673 /* check whether it can be found in default mode table */ 1674 if (drm_monitor_supports_rb(edid)) { 1675 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1676 true); 1677 if (mode) 1678 return mode; 1679 } 1680 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1681 if (mode) 1682 return mode; 1683 1684 /* okay, generate it */ 1685 switch (timing_level) { 1686 case LEVEL_DMT: 1687 break; 1688 case LEVEL_GTF: 1689 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1690 break; 1691 case LEVEL_GTF2: 1692 /* 1693 * This is potentially wrong if there's ever a monitor with 1694 * more than one ranges section, each claiming a different 1695 * secondary GTF curve. Please don't do that. 1696 */ 1697 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1698 if (!mode) 1699 return NULL; 1700 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1701 drm_mode_destroy(dev, mode); 1702 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1703 vrefresh_rate, 0, 0, 1704 drm_gtf2_m(edid), 1705 drm_gtf2_2c(edid), 1706 drm_gtf2_k(edid), 1707 drm_gtf2_2j(edid)); 1708 } 1709 break; 1710 case LEVEL_CVT: 1711 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1712 false); 1713 break; 1714 } 1715 return mode; 1716 } 1717 1718 /* 1719 * EDID is delightfully ambiguous about how interlaced modes are to be 1720 * encoded. Our internal representation is of frame height, but some 1721 * HDTV detailed timings are encoded as field height. 1722 * 1723 * The format list here is from CEA, in frame size. Technically we 1724 * should be checking refresh rate too. Whatever. 1725 */ 1726 static void 1727 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1728 struct detailed_pixel_timing *pt) 1729 { 1730 int i; 1731 static const struct { 1732 int w, h; 1733 } cea_interlaced[] = { 1734 { 1920, 1080 }, 1735 { 720, 480 }, 1736 { 1440, 480 }, 1737 { 2880, 480 }, 1738 { 720, 576 }, 1739 { 1440, 576 }, 1740 { 2880, 576 }, 1741 }; 1742 1743 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1744 return; 1745 1746 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1747 if ((mode->hdisplay == cea_interlaced[i].w) && 1748 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1749 mode->vdisplay *= 2; 1750 mode->vsync_start *= 2; 1751 mode->vsync_end *= 2; 1752 mode->vtotal *= 2; 1753 mode->vtotal |= 1; 1754 } 1755 } 1756 1757 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1758 } 1759 1760 /** 1761 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1762 * @dev: DRM device (needed to create new mode) 1763 * @edid: EDID block 1764 * @timing: EDID detailed timing info 1765 * @quirks: quirks to apply 1766 * 1767 * An EDID detailed timing block contains enough info for us to create and 1768 * return a new struct drm_display_mode. 1769 */ 1770 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1771 struct edid *edid, 1772 struct detailed_timing *timing, 1773 u32 quirks) 1774 { 1775 struct drm_display_mode *mode; 1776 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1777 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1778 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1779 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1780 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1781 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1782 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1783 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1784 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1785 1786 /* ignore tiny modes */ 1787 if (hactive < 64 || vactive < 64) 1788 return NULL; 1789 1790 if (pt->misc & DRM_EDID_PT_STEREO) { 1791 DRM_DEBUG_KMS("stereo mode not supported\n"); 1792 return NULL; 1793 } 1794 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1795 DRM_DEBUG_KMS("composite sync not supported\n"); 1796 } 1797 1798 /* it is incorrect if hsync/vsync width is zero */ 1799 if (!hsync_pulse_width || !vsync_pulse_width) { 1800 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1801 "Wrong Hsync/Vsync pulse width\n"); 1802 return NULL; 1803 } 1804 1805 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1806 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1807 if (!mode) 1808 return NULL; 1809 1810 goto set_size; 1811 } 1812 1813 mode = drm_mode_create(dev); 1814 if (!mode) 1815 return NULL; 1816 1817 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1818 timing->pixel_clock = cpu_to_le16(1088); 1819 1820 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1821 1822 mode->hdisplay = hactive; 1823 mode->hsync_start = mode->hdisplay + hsync_offset; 1824 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1825 mode->htotal = mode->hdisplay + hblank; 1826 1827 mode->vdisplay = vactive; 1828 mode->vsync_start = mode->vdisplay + vsync_offset; 1829 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1830 mode->vtotal = mode->vdisplay + vblank; 1831 1832 /* Some EDIDs have bogus h/vtotal values */ 1833 if (mode->hsync_end > mode->htotal) 1834 mode->htotal = mode->hsync_end + 1; 1835 if (mode->vsync_end > mode->vtotal) 1836 mode->vtotal = mode->vsync_end + 1; 1837 1838 drm_mode_do_interlace_quirk(mode, pt); 1839 1840 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1841 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1842 } 1843 1844 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1845 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1846 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1847 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1848 1849 set_size: 1850 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1851 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1852 1853 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1854 mode->width_mm *= 10; 1855 mode->height_mm *= 10; 1856 } 1857 1858 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1859 mode->width_mm = edid->width_cm * 10; 1860 mode->height_mm = edid->height_cm * 10; 1861 } 1862 1863 mode->type = DRM_MODE_TYPE_DRIVER; 1864 mode->vrefresh = drm_mode_vrefresh(mode); 1865 drm_mode_set_name(mode); 1866 1867 return mode; 1868 } 1869 1870 static bool 1871 mode_in_hsync_range(const struct drm_display_mode *mode, 1872 struct edid *edid, u8 *t) 1873 { 1874 int hsync, hmin, hmax; 1875 1876 hmin = t[7]; 1877 if (edid->revision >= 4) 1878 hmin += ((t[4] & 0x04) ? 255 : 0); 1879 hmax = t[8]; 1880 if (edid->revision >= 4) 1881 hmax += ((t[4] & 0x08) ? 255 : 0); 1882 hsync = drm_mode_hsync(mode); 1883 1884 return (hsync <= hmax && hsync >= hmin); 1885 } 1886 1887 static bool 1888 mode_in_vsync_range(const struct drm_display_mode *mode, 1889 struct edid *edid, u8 *t) 1890 { 1891 int vsync, vmin, vmax; 1892 1893 vmin = t[5]; 1894 if (edid->revision >= 4) 1895 vmin += ((t[4] & 0x01) ? 255 : 0); 1896 vmax = t[6]; 1897 if (edid->revision >= 4) 1898 vmax += ((t[4] & 0x02) ? 255 : 0); 1899 vsync = drm_mode_vrefresh(mode); 1900 1901 return (vsync <= vmax && vsync >= vmin); 1902 } 1903 1904 static u32 1905 range_pixel_clock(struct edid *edid, u8 *t) 1906 { 1907 /* unspecified */ 1908 if (t[9] == 0 || t[9] == 255) 1909 return 0; 1910 1911 /* 1.4 with CVT support gives us real precision, yay */ 1912 if (edid->revision >= 4 && t[10] == 0x04) 1913 return (t[9] * 10000) - ((t[12] >> 2) * 250); 1914 1915 /* 1.3 is pathetic, so fuzz up a bit */ 1916 return t[9] * 10000 + 5001; 1917 } 1918 1919 static bool 1920 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 1921 struct detailed_timing *timing) 1922 { 1923 u32 max_clock; 1924 u8 *t = (u8 *)timing; 1925 1926 if (!mode_in_hsync_range(mode, edid, t)) 1927 return false; 1928 1929 if (!mode_in_vsync_range(mode, edid, t)) 1930 return false; 1931 1932 if ((max_clock = range_pixel_clock(edid, t))) 1933 if (mode->clock > max_clock) 1934 return false; 1935 1936 /* 1.4 max horizontal check */ 1937 if (edid->revision >= 4 && t[10] == 0x04) 1938 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 1939 return false; 1940 1941 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 1942 return false; 1943 1944 return true; 1945 } 1946 1947 static bool valid_inferred_mode(const struct drm_connector *connector, 1948 const struct drm_display_mode *mode) 1949 { 1950 struct drm_display_mode *m; 1951 bool ok = false; 1952 1953 list_for_each_entry(m, &connector->probed_modes, head) { 1954 if (mode->hdisplay == m->hdisplay && 1955 mode->vdisplay == m->vdisplay && 1956 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 1957 return false; /* duplicated */ 1958 if (mode->hdisplay <= m->hdisplay && 1959 mode->vdisplay <= m->vdisplay) 1960 ok = true; 1961 } 1962 return ok; 1963 } 1964 1965 static int 1966 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 1967 struct detailed_timing *timing) 1968 { 1969 int i, modes = 0; 1970 struct drm_display_mode *newmode; 1971 struct drm_device *dev = connector->dev; 1972 1973 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1974 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 1975 valid_inferred_mode(connector, drm_dmt_modes + i)) { 1976 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 1977 if (newmode) { 1978 drm_mode_probed_add(connector, newmode); 1979 modes++; 1980 } 1981 } 1982 } 1983 1984 return modes; 1985 } 1986 1987 /* fix up 1366x768 mode from 1368x768; 1988 * GFT/CVT can't express 1366 width which isn't dividable by 8 1989 */ 1990 static void fixup_mode_1366x768(struct drm_display_mode *mode) 1991 { 1992 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 1993 mode->hdisplay = 1366; 1994 mode->hsync_start--; 1995 mode->hsync_end--; 1996 drm_mode_set_name(mode); 1997 } 1998 } 1999 2000 static int 2001 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2002 struct detailed_timing *timing) 2003 { 2004 int i, modes = 0; 2005 struct drm_display_mode *newmode; 2006 struct drm_device *dev = connector->dev; 2007 2008 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2009 const struct minimode *m = &extra_modes[i]; 2010 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2011 if (!newmode) 2012 return modes; 2013 2014 fixup_mode_1366x768(newmode); 2015 if (!mode_in_range(newmode, edid, timing) || 2016 !valid_inferred_mode(connector, newmode)) { 2017 drm_mode_destroy(dev, newmode); 2018 continue; 2019 } 2020 2021 drm_mode_probed_add(connector, newmode); 2022 modes++; 2023 } 2024 2025 return modes; 2026 } 2027 2028 static int 2029 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2030 struct detailed_timing *timing) 2031 { 2032 int i, modes = 0; 2033 struct drm_display_mode *newmode; 2034 struct drm_device *dev = connector->dev; 2035 bool rb = drm_monitor_supports_rb(edid); 2036 2037 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2038 const struct minimode *m = &extra_modes[i]; 2039 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2040 if (!newmode) 2041 return modes; 2042 2043 fixup_mode_1366x768(newmode); 2044 if (!mode_in_range(newmode, edid, timing) || 2045 !valid_inferred_mode(connector, newmode)) { 2046 drm_mode_destroy(dev, newmode); 2047 continue; 2048 } 2049 2050 drm_mode_probed_add(connector, newmode); 2051 modes++; 2052 } 2053 2054 return modes; 2055 } 2056 2057 static void 2058 do_inferred_modes(struct detailed_timing *timing, void *c) 2059 { 2060 struct detailed_mode_closure *closure = c; 2061 struct detailed_non_pixel *data = &timing->data.other_data; 2062 struct detailed_data_monitor_range *range = &data->data.range; 2063 2064 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2065 return; 2066 2067 closure->modes += drm_dmt_modes_for_range(closure->connector, 2068 closure->edid, 2069 timing); 2070 2071 if (!version_greater(closure->edid, 1, 1)) 2072 return; /* GTF not defined yet */ 2073 2074 switch (range->flags) { 2075 case 0x02: /* secondary gtf, XXX could do more */ 2076 case 0x00: /* default gtf */ 2077 closure->modes += drm_gtf_modes_for_range(closure->connector, 2078 closure->edid, 2079 timing); 2080 break; 2081 case 0x04: /* cvt, only in 1.4+ */ 2082 if (!version_greater(closure->edid, 1, 3)) 2083 break; 2084 2085 closure->modes += drm_cvt_modes_for_range(closure->connector, 2086 closure->edid, 2087 timing); 2088 break; 2089 case 0x01: /* just the ranges, no formula */ 2090 default: 2091 break; 2092 } 2093 } 2094 2095 static int 2096 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2097 { 2098 struct detailed_mode_closure closure = { 2099 connector, edid, 0, 0, 0 2100 }; 2101 2102 if (version_greater(edid, 1, 0)) 2103 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2104 &closure); 2105 2106 return closure.modes; 2107 } 2108 2109 static int 2110 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2111 { 2112 int i, j, m, modes = 0; 2113 struct drm_display_mode *mode; 2114 u8 *est = ((u8 *)timing) + 5; 2115 2116 for (i = 0; i < 6; i++) { 2117 for (j = 7; j >= 0; j--) { 2118 m = (i * 8) + (7 - j); 2119 if (m >= ARRAY_SIZE(est3_modes)) 2120 break; 2121 if (est[i] & (1 << j)) { 2122 mode = drm_mode_find_dmt(connector->dev, 2123 est3_modes[m].w, 2124 est3_modes[m].h, 2125 est3_modes[m].r, 2126 est3_modes[m].rb); 2127 if (mode) { 2128 drm_mode_probed_add(connector, mode); 2129 modes++; 2130 } 2131 } 2132 } 2133 } 2134 2135 return modes; 2136 } 2137 2138 static void 2139 do_established_modes(struct detailed_timing *timing, void *c) 2140 { 2141 struct detailed_mode_closure *closure = c; 2142 struct detailed_non_pixel *data = &timing->data.other_data; 2143 2144 if (data->type == EDID_DETAIL_EST_TIMINGS) 2145 closure->modes += drm_est3_modes(closure->connector, timing); 2146 } 2147 2148 /** 2149 * add_established_modes - get est. modes from EDID and add them 2150 * @connector: connector of for the EDID block 2151 * @edid: EDID block to scan 2152 * 2153 * Each EDID block contains a bitmap of the supported "established modes" list 2154 * (defined above). Tease them out and add them to the global modes list. 2155 */ 2156 static int 2157 add_established_modes(struct drm_connector *connector, struct edid *edid) 2158 { 2159 struct drm_device *dev = connector->dev; 2160 unsigned long est_bits = edid->established_timings.t1 | 2161 (edid->established_timings.t2 << 8) | 2162 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2163 int i, modes = 0; 2164 struct detailed_mode_closure closure = { 2165 connector, edid, 0, 0, 0 2166 }; 2167 2168 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2169 if (est_bits & (1<<i)) { 2170 struct drm_display_mode *newmode; 2171 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2172 if (newmode) { 2173 drm_mode_probed_add(connector, newmode); 2174 modes++; 2175 } 2176 } 2177 } 2178 2179 if (version_greater(edid, 1, 0)) 2180 drm_for_each_detailed_block((u8 *)edid, 2181 do_established_modes, &closure); 2182 2183 return modes + closure.modes; 2184 } 2185 2186 static void 2187 do_standard_modes(struct detailed_timing *timing, void *c) 2188 { 2189 struct detailed_mode_closure *closure = c; 2190 struct detailed_non_pixel *data = &timing->data.other_data; 2191 struct drm_connector *connector = closure->connector; 2192 struct edid *edid = closure->edid; 2193 2194 if (data->type == EDID_DETAIL_STD_MODES) { 2195 int i; 2196 for (i = 0; i < 6; i++) { 2197 struct std_timing *std; 2198 struct drm_display_mode *newmode; 2199 2200 std = &data->data.timings[i]; 2201 newmode = drm_mode_std(connector, edid, std, 2202 edid->revision); 2203 if (newmode) { 2204 drm_mode_probed_add(connector, newmode); 2205 closure->modes++; 2206 } 2207 } 2208 } 2209 } 2210 2211 /** 2212 * add_standard_modes - get std. modes from EDID and add them 2213 * @connector: connector of for the EDID block 2214 * @edid: EDID block to scan 2215 * 2216 * Standard modes can be calculated using the appropriate standard (DMT, 2217 * GTF or CVT. Grab them from @edid and add them to the list. 2218 */ 2219 static int 2220 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2221 { 2222 int i, modes = 0; 2223 struct detailed_mode_closure closure = { 2224 connector, edid, 0, 0, 0 2225 }; 2226 2227 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2228 struct drm_display_mode *newmode; 2229 2230 newmode = drm_mode_std(connector, edid, 2231 &edid->standard_timings[i], 2232 edid->revision); 2233 if (newmode) { 2234 drm_mode_probed_add(connector, newmode); 2235 modes++; 2236 } 2237 } 2238 2239 if (version_greater(edid, 1, 0)) 2240 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2241 &closure); 2242 2243 /* XXX should also look for standard codes in VTB blocks */ 2244 2245 return modes + closure.modes; 2246 } 2247 2248 static int drm_cvt_modes(struct drm_connector *connector, 2249 struct detailed_timing *timing) 2250 { 2251 int i, j, modes = 0; 2252 struct drm_display_mode *newmode; 2253 struct drm_device *dev = connector->dev; 2254 struct cvt_timing *cvt; 2255 const int rates[] = { 60, 85, 75, 60, 50 }; 2256 const u8 empty[3] = { 0, 0, 0 }; 2257 2258 for (i = 0; i < 4; i++) { 2259 int uninitialized_var(width), height; 2260 cvt = &(timing->data.other_data.data.cvt[i]); 2261 2262 if (!memcmp(cvt->code, empty, 3)) 2263 continue; 2264 2265 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2266 switch (cvt->code[1] & 0x0c) { 2267 case 0x00: 2268 width = height * 4 / 3; 2269 break; 2270 case 0x04: 2271 width = height * 16 / 9; 2272 break; 2273 case 0x08: 2274 width = height * 16 / 10; 2275 break; 2276 case 0x0c: 2277 width = height * 15 / 9; 2278 break; 2279 } 2280 2281 for (j = 1; j < 5; j++) { 2282 if (cvt->code[2] & (1 << j)) { 2283 newmode = drm_cvt_mode(dev, width, height, 2284 rates[j], j == 0, 2285 false, false); 2286 if (newmode) { 2287 drm_mode_probed_add(connector, newmode); 2288 modes++; 2289 } 2290 } 2291 } 2292 } 2293 2294 return modes; 2295 } 2296 2297 static void 2298 do_cvt_mode(struct detailed_timing *timing, void *c) 2299 { 2300 struct detailed_mode_closure *closure = c; 2301 struct detailed_non_pixel *data = &timing->data.other_data; 2302 2303 if (data->type == EDID_DETAIL_CVT_3BYTE) 2304 closure->modes += drm_cvt_modes(closure->connector, timing); 2305 } 2306 2307 static int 2308 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2309 { 2310 struct detailed_mode_closure closure = { 2311 connector, edid, 0, 0, 0 2312 }; 2313 2314 if (version_greater(edid, 1, 2)) 2315 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2316 2317 /* XXX should also look for CVT codes in VTB blocks */ 2318 2319 return closure.modes; 2320 } 2321 2322 static void 2323 do_detailed_mode(struct detailed_timing *timing, void *c) 2324 { 2325 struct detailed_mode_closure *closure = c; 2326 struct drm_display_mode *newmode; 2327 2328 if (timing->pixel_clock) { 2329 newmode = drm_mode_detailed(closure->connector->dev, 2330 closure->edid, timing, 2331 closure->quirks); 2332 if (!newmode) 2333 return; 2334 2335 if (closure->preferred) 2336 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2337 2338 drm_mode_probed_add(closure->connector, newmode); 2339 closure->modes++; 2340 closure->preferred = 0; 2341 } 2342 } 2343 2344 /* 2345 * add_detailed_modes - Add modes from detailed timings 2346 * @connector: attached connector 2347 * @edid: EDID block to scan 2348 * @quirks: quirks to apply 2349 */ 2350 static int 2351 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2352 u32 quirks) 2353 { 2354 struct detailed_mode_closure closure = { 2355 connector, 2356 edid, 2357 1, 2358 quirks, 2359 0 2360 }; 2361 2362 if (closure.preferred && !version_greater(edid, 1, 3)) 2363 closure.preferred = 2364 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2365 2366 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2367 2368 return closure.modes; 2369 } 2370 2371 #define AUDIO_BLOCK 0x01 2372 #define VIDEO_BLOCK 0x02 2373 #define VENDOR_BLOCK 0x03 2374 #define SPEAKER_BLOCK 0x04 2375 #define VIDEO_CAPABILITY_BLOCK 0x07 2376 #define EDID_BASIC_AUDIO (1 << 6) 2377 #define EDID_CEA_YCRCB444 (1 << 5) 2378 #define EDID_CEA_YCRCB422 (1 << 4) 2379 #define EDID_CEA_VCDB_QS (1 << 6) 2380 2381 /* 2382 * Search EDID for CEA extension block. 2383 */ 2384 static u8 *drm_find_cea_extension(struct edid *edid) 2385 { 2386 u8 *edid_ext = NULL; 2387 int i; 2388 2389 /* No EDID or EDID extensions */ 2390 if (edid == NULL || edid->extensions == 0) 2391 return NULL; 2392 2393 /* Find CEA extension */ 2394 for (i = 0; i < edid->extensions; i++) { 2395 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2396 if (edid_ext[0] == CEA_EXT) 2397 break; 2398 } 2399 2400 if (i == edid->extensions) 2401 return NULL; 2402 2403 return edid_ext; 2404 } 2405 2406 /* 2407 * Calculate the alternate clock for the CEA mode 2408 * (60Hz vs. 59.94Hz etc.) 2409 */ 2410 static unsigned int 2411 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2412 { 2413 unsigned int clock = cea_mode->clock; 2414 2415 if (cea_mode->vrefresh % 6 != 0) 2416 return clock; 2417 2418 /* 2419 * edid_cea_modes contains the 59.94Hz 2420 * variant for 240 and 480 line modes, 2421 * and the 60Hz variant otherwise. 2422 */ 2423 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2424 clock = clock * 1001 / 1000; 2425 else 2426 clock = DIV_ROUND_UP(clock * 1000, 1001); 2427 2428 return clock; 2429 } 2430 2431 /** 2432 * drm_match_cea_mode - look for a CEA mode matching given mode 2433 * @to_match: display mode 2434 * 2435 * Returns the CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2436 * mode. 2437 */ 2438 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2439 { 2440 u8 mode; 2441 2442 if (!to_match->clock) 2443 return 0; 2444 2445 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2446 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2447 unsigned int clock1, clock2; 2448 2449 /* Check both 60Hz and 59.94Hz */ 2450 clock1 = cea_mode->clock; 2451 clock2 = cea_mode_alternate_clock(cea_mode); 2452 2453 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2454 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2455 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2456 return mode + 1; 2457 } 2458 return 0; 2459 } 2460 EXPORT_SYMBOL(drm_match_cea_mode); 2461 2462 /* 2463 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2464 * specific block). 2465 * 2466 * It's almost like cea_mode_alternate_clock(), we just need to add an 2467 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2468 * one. 2469 */ 2470 static unsigned int 2471 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2472 { 2473 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2474 return hdmi_mode->clock; 2475 2476 return cea_mode_alternate_clock(hdmi_mode); 2477 } 2478 2479 /* 2480 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2481 * @to_match: display mode 2482 * 2483 * An HDMI mode is one defined in the HDMI vendor specific block. 2484 * 2485 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2486 */ 2487 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2488 { 2489 u8 mode; 2490 2491 if (!to_match->clock) 2492 return 0; 2493 2494 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2495 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2496 unsigned int clock1, clock2; 2497 2498 /* Make sure to also match alternate clocks */ 2499 clock1 = hdmi_mode->clock; 2500 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2501 2502 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2503 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2504 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2505 return mode + 1; 2506 } 2507 return 0; 2508 } 2509 2510 static int 2511 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2512 { 2513 struct drm_device *dev = connector->dev; 2514 struct drm_display_mode *mode, *tmp; 2515 struct list_head list = LIST_HEAD_INIT(list); 2516 int modes = 0; 2517 2518 /* Don't add CEA modes if the CEA extension block is missing */ 2519 if (!drm_find_cea_extension(edid)) 2520 return 0; 2521 2522 /* 2523 * Go through all probed modes and create a new mode 2524 * with the alternate clock for certain CEA modes. 2525 */ 2526 list_for_each_entry(mode, &connector->probed_modes, head) { 2527 const struct drm_display_mode *cea_mode = NULL; 2528 struct drm_display_mode *newmode; 2529 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2530 unsigned int clock1, clock2; 2531 2532 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2533 cea_mode = &edid_cea_modes[mode_idx]; 2534 clock2 = cea_mode_alternate_clock(cea_mode); 2535 } else { 2536 mode_idx = drm_match_hdmi_mode(mode) - 1; 2537 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2538 cea_mode = &edid_4k_modes[mode_idx]; 2539 clock2 = hdmi_mode_alternate_clock(cea_mode); 2540 } 2541 } 2542 2543 if (!cea_mode) 2544 continue; 2545 2546 clock1 = cea_mode->clock; 2547 2548 if (clock1 == clock2) 2549 continue; 2550 2551 if (mode->clock != clock1 && mode->clock != clock2) 2552 continue; 2553 2554 newmode = drm_mode_duplicate(dev, cea_mode); 2555 if (!newmode) 2556 continue; 2557 2558 /* Carry over the stereo flags */ 2559 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2560 2561 /* 2562 * The current mode could be either variant. Make 2563 * sure to pick the "other" clock for the new mode. 2564 */ 2565 if (mode->clock != clock1) 2566 newmode->clock = clock1; 2567 else 2568 newmode->clock = clock2; 2569 2570 list_add_tail(&newmode->head, &list); 2571 } 2572 2573 list_for_each_entry_safe(mode, tmp, &list, head) { 2574 list_del(&mode->head); 2575 drm_mode_probed_add(connector, mode); 2576 modes++; 2577 } 2578 2579 return modes; 2580 } 2581 2582 static struct drm_display_mode * 2583 drm_display_mode_from_vic_index(struct drm_connector *connector, 2584 const u8 *video_db, u8 video_len, 2585 u8 video_index) 2586 { 2587 struct drm_device *dev = connector->dev; 2588 struct drm_display_mode *newmode; 2589 u8 cea_mode; 2590 2591 if (video_db == NULL || video_index >= video_len) 2592 return NULL; 2593 2594 /* CEA modes are numbered 1..127 */ 2595 cea_mode = (video_db[video_index] & 127) - 1; 2596 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2597 return NULL; 2598 2599 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2600 if (!newmode) 2601 return NULL; 2602 2603 newmode->vrefresh = 0; 2604 2605 return newmode; 2606 } 2607 2608 static int 2609 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2610 { 2611 int i, modes = 0; 2612 2613 for (i = 0; i < len; i++) { 2614 struct drm_display_mode *mode; 2615 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2616 if (mode) { 2617 drm_mode_probed_add(connector, mode); 2618 modes++; 2619 } 2620 } 2621 2622 return modes; 2623 } 2624 2625 struct stereo_mandatory_mode { 2626 int width, height, vrefresh; 2627 unsigned int flags; 2628 }; 2629 2630 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2631 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2632 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2633 { 1920, 1080, 50, 2634 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2635 { 1920, 1080, 60, 2636 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2637 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2638 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2639 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2640 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2641 }; 2642 2643 static bool 2644 stereo_match_mandatory(const struct drm_display_mode *mode, 2645 const struct stereo_mandatory_mode *stereo_mode) 2646 { 2647 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2648 2649 return mode->hdisplay == stereo_mode->width && 2650 mode->vdisplay == stereo_mode->height && 2651 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2652 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2653 } 2654 2655 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2656 { 2657 struct drm_device *dev = connector->dev; 2658 const struct drm_display_mode *mode; 2659 struct list_head stereo_modes; 2660 int modes = 0, i; 2661 2662 INIT_LIST_HEAD(&stereo_modes); 2663 2664 list_for_each_entry(mode, &connector->probed_modes, head) { 2665 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2666 const struct stereo_mandatory_mode *mandatory; 2667 struct drm_display_mode *new_mode; 2668 2669 if (!stereo_match_mandatory(mode, 2670 &stereo_mandatory_modes[i])) 2671 continue; 2672 2673 mandatory = &stereo_mandatory_modes[i]; 2674 new_mode = drm_mode_duplicate(dev, mode); 2675 if (!new_mode) 2676 continue; 2677 2678 new_mode->flags |= mandatory->flags; 2679 list_add_tail(&new_mode->head, &stereo_modes); 2680 modes++; 2681 } 2682 } 2683 2684 list_splice_tail(&stereo_modes, &connector->probed_modes); 2685 2686 return modes; 2687 } 2688 2689 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2690 { 2691 struct drm_device *dev = connector->dev; 2692 struct drm_display_mode *newmode; 2693 2694 vic--; /* VICs start at 1 */ 2695 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2696 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2697 return 0; 2698 } 2699 2700 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2701 if (!newmode) 2702 return 0; 2703 2704 drm_mode_probed_add(connector, newmode); 2705 2706 return 1; 2707 } 2708 2709 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2710 const u8 *video_db, u8 video_len, u8 video_index) 2711 { 2712 struct drm_display_mode *newmode; 2713 int modes = 0; 2714 2715 if (structure & (1 << 0)) { 2716 newmode = drm_display_mode_from_vic_index(connector, video_db, 2717 video_len, 2718 video_index); 2719 if (newmode) { 2720 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2721 drm_mode_probed_add(connector, newmode); 2722 modes++; 2723 } 2724 } 2725 if (structure & (1 << 6)) { 2726 newmode = drm_display_mode_from_vic_index(connector, video_db, 2727 video_len, 2728 video_index); 2729 if (newmode) { 2730 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2731 drm_mode_probed_add(connector, newmode); 2732 modes++; 2733 } 2734 } 2735 if (structure & (1 << 8)) { 2736 newmode = drm_display_mode_from_vic_index(connector, video_db, 2737 video_len, 2738 video_index); 2739 if (newmode) { 2740 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2741 drm_mode_probed_add(connector, newmode); 2742 modes++; 2743 } 2744 } 2745 2746 return modes; 2747 } 2748 2749 /* 2750 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2751 * @connector: connector corresponding to the HDMI sink 2752 * @db: start of the CEA vendor specific block 2753 * @len: length of the CEA block payload, ie. one can access up to db[len] 2754 * 2755 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2756 * also adds the stereo 3d modes when applicable. 2757 */ 2758 static int 2759 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2760 const u8 *video_db, u8 video_len) 2761 { 2762 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2763 u8 vic_len, hdmi_3d_len = 0; 2764 u16 mask; 2765 u16 structure_all; 2766 2767 if (len < 8) 2768 goto out; 2769 2770 /* no HDMI_Video_Present */ 2771 if (!(db[8] & (1 << 5))) 2772 goto out; 2773 2774 /* Latency_Fields_Present */ 2775 if (db[8] & (1 << 7)) 2776 offset += 2; 2777 2778 /* I_Latency_Fields_Present */ 2779 if (db[8] & (1 << 6)) 2780 offset += 2; 2781 2782 /* the declared length is not long enough for the 2 first bytes 2783 * of additional video format capabilities */ 2784 if (len < (8 + offset + 2)) 2785 goto out; 2786 2787 /* 3D_Present */ 2788 offset++; 2789 if (db[8 + offset] & (1 << 7)) { 2790 modes += add_hdmi_mandatory_stereo_modes(connector); 2791 2792 /* 3D_Multi_present */ 2793 multi_present = (db[8 + offset] & 0x60) >> 5; 2794 } 2795 2796 offset++; 2797 vic_len = db[8 + offset] >> 5; 2798 hdmi_3d_len = db[8 + offset] & 0x1f; 2799 2800 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2801 u8 vic; 2802 2803 vic = db[9 + offset + i]; 2804 modes += add_hdmi_mode(connector, vic); 2805 } 2806 offset += 1 + vic_len; 2807 2808 if (multi_present == 1) 2809 multi_len = 2; 2810 else if (multi_present == 2) 2811 multi_len = 4; 2812 else 2813 multi_len = 0; 2814 2815 if (len < (8 + offset + hdmi_3d_len - 1)) 2816 goto out; 2817 2818 if (hdmi_3d_len < multi_len) 2819 goto out; 2820 2821 if (multi_present == 1 || multi_present == 2) { 2822 /* 3D_Structure_ALL */ 2823 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2824 2825 /* check if 3D_MASK is present */ 2826 if (multi_present == 2) 2827 mask = (db[10 + offset] << 8) | db[11 + offset]; 2828 else 2829 mask = 0xffff; 2830 2831 for (i = 0; i < 16; i++) { 2832 if (mask & (1 << i)) 2833 modes += add_3d_struct_modes(connector, 2834 structure_all, 2835 video_db, 2836 video_len, i); 2837 } 2838 } 2839 2840 offset += multi_len; 2841 2842 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 2843 int vic_index; 2844 struct drm_display_mode *newmode = NULL; 2845 unsigned int newflag = 0; 2846 bool detail_present; 2847 2848 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 2849 2850 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 2851 break; 2852 2853 /* 2D_VIC_order_X */ 2854 vic_index = db[8 + offset + i] >> 4; 2855 2856 /* 3D_Structure_X */ 2857 switch (db[8 + offset + i] & 0x0f) { 2858 case 0: 2859 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 2860 break; 2861 case 6: 2862 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2863 break; 2864 case 8: 2865 /* 3D_Detail_X */ 2866 if ((db[9 + offset + i] >> 4) == 1) 2867 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2868 break; 2869 } 2870 2871 if (newflag != 0) { 2872 newmode = drm_display_mode_from_vic_index(connector, 2873 video_db, 2874 video_len, 2875 vic_index); 2876 2877 if (newmode) { 2878 newmode->flags |= newflag; 2879 drm_mode_probed_add(connector, newmode); 2880 modes++; 2881 } 2882 } 2883 2884 if (detail_present) 2885 i++; 2886 } 2887 2888 out: 2889 return modes; 2890 } 2891 2892 static int 2893 cea_db_payload_len(const u8 *db) 2894 { 2895 return db[0] & 0x1f; 2896 } 2897 2898 static int 2899 cea_db_tag(const u8 *db) 2900 { 2901 return db[0] >> 5; 2902 } 2903 2904 static int 2905 cea_revision(const u8 *cea) 2906 { 2907 return cea[1]; 2908 } 2909 2910 static int 2911 cea_db_offsets(const u8 *cea, int *start, int *end) 2912 { 2913 /* Data block offset in CEA extension block */ 2914 *start = 4; 2915 *end = cea[2]; 2916 if (*end == 0) 2917 *end = 127; 2918 if (*end < 4 || *end > 127) 2919 return -ERANGE; 2920 return 0; 2921 } 2922 2923 static bool cea_db_is_hdmi_vsdb(const u8 *db) 2924 { 2925 int hdmi_id; 2926 2927 if (cea_db_tag(db) != VENDOR_BLOCK) 2928 return false; 2929 2930 if (cea_db_payload_len(db) < 5) 2931 return false; 2932 2933 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 2934 2935 return hdmi_id == HDMI_IEEE_OUI; 2936 } 2937 2938 #define for_each_cea_db(cea, i, start, end) \ 2939 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 2940 2941 static int 2942 add_cea_modes(struct drm_connector *connector, struct edid *edid) 2943 { 2944 const u8 *cea = drm_find_cea_extension(edid); 2945 const u8 *db, *hdmi = NULL, *video = NULL; 2946 u8 dbl, hdmi_len, video_len = 0; 2947 int modes = 0; 2948 2949 if (cea && cea_revision(cea) >= 3) { 2950 int i, start, end; 2951 2952 if (cea_db_offsets(cea, &start, &end)) 2953 return 0; 2954 2955 for_each_cea_db(cea, i, start, end) { 2956 db = &cea[i]; 2957 dbl = cea_db_payload_len(db); 2958 2959 if (cea_db_tag(db) == VIDEO_BLOCK) { 2960 video = db + 1; 2961 video_len = dbl; 2962 modes += do_cea_modes(connector, video, dbl); 2963 } 2964 else if (cea_db_is_hdmi_vsdb(db)) { 2965 hdmi = db; 2966 hdmi_len = dbl; 2967 } 2968 } 2969 } 2970 2971 /* 2972 * We parse the HDMI VSDB after having added the cea modes as we will 2973 * be patching their flags when the sink supports stereo 3D. 2974 */ 2975 if (hdmi) 2976 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 2977 video_len); 2978 2979 return modes; 2980 } 2981 2982 static void 2983 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 2984 { 2985 u8 len = cea_db_payload_len(db); 2986 2987 if (len >= 5) { 2988 connector->physical_address = (db[4] << 8) | db[5]; 2989 } 2990 if (len >= 6) { 2991 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 2992 connector->dvi_dual = db[6] & 1; 2993 } 2994 if (len >= 7) 2995 connector->max_tmds_clock = db[7] * 5; 2996 if (len >= 8) { 2997 connector->latency_present[0] = db[8] >> 7; 2998 connector->latency_present[1] = (db[8] >> 6) & 1; 2999 } 3000 if (len >= 9) 3001 connector->video_latency[0] = db[9]; 3002 if (len >= 10) 3003 connector->audio_latency[0] = db[10]; 3004 if (len >= 11) 3005 connector->video_latency[1] = db[11]; 3006 if (len >= 12) 3007 connector->audio_latency[1] = db[12]; 3008 3009 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3010 "max TMDS clock %d, " 3011 "latency present %d %d, " 3012 "video latency %d %d, " 3013 "audio latency %d %d\n", 3014 connector->dvi_dual, 3015 connector->max_tmds_clock, 3016 (int) connector->latency_present[0], 3017 (int) connector->latency_present[1], 3018 connector->video_latency[0], 3019 connector->video_latency[1], 3020 connector->audio_latency[0], 3021 connector->audio_latency[1]); 3022 } 3023 3024 static void 3025 monitor_name(struct detailed_timing *t, void *data) 3026 { 3027 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3028 *(u8 **)data = t->data.other_data.data.str.str; 3029 } 3030 3031 /** 3032 * drm_edid_to_eld - build ELD from EDID 3033 * @connector: connector corresponding to the HDMI/DP sink 3034 * @edid: EDID to parse 3035 * 3036 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. 3037 * Some ELD fields are left to the graphics driver caller: 3038 * - Conn_Type 3039 * - HDCP 3040 * - Port_ID 3041 */ 3042 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3043 { 3044 uint8_t *eld = connector->eld; 3045 u8 *cea; 3046 u8 *name; 3047 u8 *db; 3048 int sad_count = 0; 3049 int mnl; 3050 int dbl; 3051 3052 memset(eld, 0, sizeof(connector->eld)); 3053 3054 cea = drm_find_cea_extension(edid); 3055 if (!cea) { 3056 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3057 return; 3058 } 3059 3060 name = NULL; 3061 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3062 for (mnl = 0; name && mnl < 13; mnl++) { 3063 if (name[mnl] == 0x0a) 3064 break; 3065 eld[20 + mnl] = name[mnl]; 3066 } 3067 eld[4] = (cea[1] << 5) | mnl; 3068 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3069 3070 eld[0] = 2 << 3; /* ELD version: 2 */ 3071 3072 eld[16] = edid->mfg_id[0]; 3073 eld[17] = edid->mfg_id[1]; 3074 eld[18] = edid->prod_code[0]; 3075 eld[19] = edid->prod_code[1]; 3076 3077 if (cea_revision(cea) >= 3) { 3078 int i, start, end; 3079 3080 if (cea_db_offsets(cea, &start, &end)) { 3081 start = 0; 3082 end = 0; 3083 } 3084 3085 for_each_cea_db(cea, i, start, end) { 3086 db = &cea[i]; 3087 dbl = cea_db_payload_len(db); 3088 3089 switch (cea_db_tag(db)) { 3090 case AUDIO_BLOCK: 3091 /* Audio Data Block, contains SADs */ 3092 sad_count = dbl / 3; 3093 if (dbl >= 1) 3094 memcpy(eld + 20 + mnl, &db[1], dbl); 3095 break; 3096 case SPEAKER_BLOCK: 3097 /* Speaker Allocation Data Block */ 3098 if (dbl >= 1) 3099 eld[7] = db[1]; 3100 break; 3101 case VENDOR_BLOCK: 3102 /* HDMI Vendor-Specific Data Block */ 3103 if (cea_db_is_hdmi_vsdb(db)) 3104 parse_hdmi_vsdb(connector, db); 3105 break; 3106 default: 3107 break; 3108 } 3109 } 3110 } 3111 eld[5] |= sad_count << 4; 3112 eld[2] = (20 + mnl + sad_count * 3 + 3) / 4; 3113 3114 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); 3115 } 3116 EXPORT_SYMBOL(drm_edid_to_eld); 3117 3118 /** 3119 * drm_edid_to_sad - extracts SADs from EDID 3120 * @edid: EDID to parse 3121 * @sads: pointer that will be set to the extracted SADs 3122 * 3123 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3124 * Note: returned pointer needs to be kfreed 3125 * 3126 * Return number of found SADs or negative number on error. 3127 */ 3128 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3129 { 3130 int count = 0; 3131 int i, start, end, dbl; 3132 u8 *cea; 3133 3134 cea = drm_find_cea_extension(edid); 3135 if (!cea) { 3136 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3137 return -ENOENT; 3138 } 3139 3140 if (cea_revision(cea) < 3) { 3141 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3142 return -ENOTSUPP; 3143 } 3144 3145 if (cea_db_offsets(cea, &start, &end)) { 3146 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3147 return -EPROTO; 3148 } 3149 3150 for_each_cea_db(cea, i, start, end) { 3151 u8 *db = &cea[i]; 3152 3153 if (cea_db_tag(db) == AUDIO_BLOCK) { 3154 int j; 3155 dbl = cea_db_payload_len(db); 3156 3157 count = dbl / 3; /* SAD is 3B */ 3158 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3159 if (!*sads) 3160 return -ENOMEM; 3161 for (j = 0; j < count; j++) { 3162 u8 *sad = &db[1 + j * 3]; 3163 3164 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3165 (*sads)[j].channels = sad[0] & 0x7; 3166 (*sads)[j].freq = sad[1] & 0x7F; 3167 (*sads)[j].byte2 = sad[2]; 3168 } 3169 break; 3170 } 3171 } 3172 3173 return count; 3174 } 3175 EXPORT_SYMBOL(drm_edid_to_sad); 3176 3177 /** 3178 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3179 * @edid: EDID to parse 3180 * @sadb: pointer to the speaker block 3181 * 3182 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3183 * Note: returned pointer needs to be kfreed 3184 * 3185 * Return number of found Speaker Allocation Blocks or negative number on error. 3186 */ 3187 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3188 { 3189 int count = 0; 3190 int i, start, end, dbl; 3191 const u8 *cea; 3192 3193 cea = drm_find_cea_extension(edid); 3194 if (!cea) { 3195 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3196 return -ENOENT; 3197 } 3198 3199 if (cea_revision(cea) < 3) { 3200 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3201 return -ENOTSUPP; 3202 } 3203 3204 if (cea_db_offsets(cea, &start, &end)) { 3205 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3206 return -EPROTO; 3207 } 3208 3209 for_each_cea_db(cea, i, start, end) { 3210 const u8 *db = &cea[i]; 3211 3212 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3213 dbl = cea_db_payload_len(db); 3214 3215 /* Speaker Allocation Data Block */ 3216 if (dbl == 3) { 3217 *sadb = kmalloc(dbl, GFP_KERNEL); 3218 if (!*sadb) 3219 return -ENOMEM; 3220 memcpy(*sadb, &db[1], dbl); 3221 count = dbl; 3222 break; 3223 } 3224 } 3225 } 3226 3227 return count; 3228 } 3229 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3230 3231 /** 3232 * drm_av_sync_delay - HDMI/DP sink audio-video sync delay in millisecond 3233 * @connector: connector associated with the HDMI/DP sink 3234 * @mode: the display mode 3235 */ 3236 int drm_av_sync_delay(struct drm_connector *connector, 3237 struct drm_display_mode *mode) 3238 { 3239 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3240 int a, v; 3241 3242 if (!connector->latency_present[0]) 3243 return 0; 3244 if (!connector->latency_present[1]) 3245 i = 0; 3246 3247 a = connector->audio_latency[i]; 3248 v = connector->video_latency[i]; 3249 3250 /* 3251 * HDMI/DP sink doesn't support audio or video? 3252 */ 3253 if (a == 255 || v == 255) 3254 return 0; 3255 3256 /* 3257 * Convert raw EDID values to millisecond. 3258 * Treat unknown latency as 0ms. 3259 */ 3260 if (a) 3261 a = min(2 * (a - 1), 500); 3262 if (v) 3263 v = min(2 * (v - 1), 500); 3264 3265 return max(v - a, 0); 3266 } 3267 EXPORT_SYMBOL(drm_av_sync_delay); 3268 3269 /** 3270 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3271 * @encoder: the encoder just changed display mode 3272 * @mode: the adjusted display mode 3273 * 3274 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3275 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3276 */ 3277 struct drm_connector *drm_select_eld(struct drm_encoder *encoder, 3278 struct drm_display_mode *mode) 3279 { 3280 struct drm_connector *connector; 3281 struct drm_device *dev = encoder->dev; 3282 3283 list_for_each_entry(connector, &dev->mode_config.connector_list, head) 3284 if (connector->encoder == encoder && connector->eld[0]) 3285 return connector; 3286 3287 return NULL; 3288 } 3289 EXPORT_SYMBOL(drm_select_eld); 3290 3291 /** 3292 * drm_detect_hdmi_monitor - detect whether monitor is hdmi. 3293 * @edid: monitor EDID information 3294 * 3295 * Parse the CEA extension according to CEA-861-B. 3296 * Return true if HDMI, false if not or unknown. 3297 */ 3298 bool drm_detect_hdmi_monitor(struct edid *edid) 3299 { 3300 u8 *edid_ext; 3301 int i; 3302 int start_offset, end_offset; 3303 3304 edid_ext = drm_find_cea_extension(edid); 3305 if (!edid_ext) 3306 return false; 3307 3308 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3309 return false; 3310 3311 /* 3312 * Because HDMI identifier is in Vendor Specific Block, 3313 * search it from all data blocks of CEA extension. 3314 */ 3315 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3316 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3317 return true; 3318 } 3319 3320 return false; 3321 } 3322 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3323 3324 /** 3325 * drm_detect_monitor_audio - check monitor audio capability 3326 * @edid: EDID block to scan 3327 * 3328 * Monitor should have CEA extension block. 3329 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3330 * audio' only. If there is any audio extension block and supported 3331 * audio format, assume at least 'basic audio' support, even if 'basic 3332 * audio' is not defined in EDID. 3333 * 3334 */ 3335 bool drm_detect_monitor_audio(struct edid *edid) 3336 { 3337 u8 *edid_ext; 3338 int i, j; 3339 bool has_audio = false; 3340 int start_offset, end_offset; 3341 3342 edid_ext = drm_find_cea_extension(edid); 3343 if (!edid_ext) 3344 goto end; 3345 3346 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3347 3348 if (has_audio) { 3349 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3350 goto end; 3351 } 3352 3353 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3354 goto end; 3355 3356 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3357 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3358 has_audio = true; 3359 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3360 DRM_DEBUG_KMS("CEA audio format %d\n", 3361 (edid_ext[i + j] >> 3) & 0xf); 3362 goto end; 3363 } 3364 } 3365 end: 3366 return has_audio; 3367 } 3368 EXPORT_SYMBOL(drm_detect_monitor_audio); 3369 3370 /** 3371 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3372 * @edid: EDID block to scan 3373 * 3374 * Check whether the monitor reports the RGB quantization range selection 3375 * as supported. The AVI infoframe can then be used to inform the monitor 3376 * which quantization range (full or limited) is used. 3377 */ 3378 bool drm_rgb_quant_range_selectable(struct edid *edid) 3379 { 3380 u8 *edid_ext; 3381 int i, start, end; 3382 3383 edid_ext = drm_find_cea_extension(edid); 3384 if (!edid_ext) 3385 return false; 3386 3387 if (cea_db_offsets(edid_ext, &start, &end)) 3388 return false; 3389 3390 for_each_cea_db(edid_ext, i, start, end) { 3391 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3392 cea_db_payload_len(&edid_ext[i]) == 2) { 3393 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3394 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3395 } 3396 } 3397 3398 return false; 3399 } 3400 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3401 3402 /** 3403 * drm_add_display_info - pull display info out if present 3404 * @edid: EDID data 3405 * @info: display info (attached to connector) 3406 * 3407 * Grab any available display info and stuff it into the drm_display_info 3408 * structure that's part of the connector. Useful for tracking bpp and 3409 * color spaces. 3410 */ 3411 static void drm_add_display_info(struct edid *edid, 3412 struct drm_display_info *info) 3413 { 3414 u8 *edid_ext; 3415 3416 info->width_mm = edid->width_cm * 10; 3417 info->height_mm = edid->height_cm * 10; 3418 3419 /* driver figures it out in this case */ 3420 info->bpc = 0; 3421 info->color_formats = 0; 3422 3423 if (edid->revision < 3) 3424 return; 3425 3426 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3427 return; 3428 3429 /* Get data from CEA blocks if present */ 3430 edid_ext = drm_find_cea_extension(edid); 3431 if (edid_ext) { 3432 info->cea_rev = edid_ext[1]; 3433 3434 /* The existence of a CEA block should imply RGB support */ 3435 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3436 if (edid_ext[3] & EDID_CEA_YCRCB444) 3437 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3438 if (edid_ext[3] & EDID_CEA_YCRCB422) 3439 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3440 } 3441 3442 /* Only defined for 1.4 with digital displays */ 3443 if (edid->revision < 4) 3444 return; 3445 3446 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3447 case DRM_EDID_DIGITAL_DEPTH_6: 3448 info->bpc = 6; 3449 break; 3450 case DRM_EDID_DIGITAL_DEPTH_8: 3451 info->bpc = 8; 3452 break; 3453 case DRM_EDID_DIGITAL_DEPTH_10: 3454 info->bpc = 10; 3455 break; 3456 case DRM_EDID_DIGITAL_DEPTH_12: 3457 info->bpc = 12; 3458 break; 3459 case DRM_EDID_DIGITAL_DEPTH_14: 3460 info->bpc = 14; 3461 break; 3462 case DRM_EDID_DIGITAL_DEPTH_16: 3463 info->bpc = 16; 3464 break; 3465 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3466 default: 3467 info->bpc = 0; 3468 break; 3469 } 3470 3471 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3472 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3473 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3474 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3475 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3476 } 3477 3478 /** 3479 * drm_add_edid_modes - add modes from EDID data, if available 3480 * @connector: connector we're probing 3481 * @edid: edid data 3482 * 3483 * Add the specified modes to the connector's mode list. 3484 * 3485 * Return number of modes added or 0 if we couldn't find any. 3486 */ 3487 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3488 { 3489 int num_modes = 0; 3490 u32 quirks; 3491 3492 if (edid == NULL) { 3493 return 0; 3494 } 3495 if (!drm_edid_is_valid(edid)) { 3496 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3497 drm_get_connector_name(connector)); 3498 return 0; 3499 } 3500 3501 quirks = edid_get_quirks(edid); 3502 3503 /* 3504 * EDID spec says modes should be preferred in this order: 3505 * - preferred detailed mode 3506 * - other detailed modes from base block 3507 * - detailed modes from extension blocks 3508 * - CVT 3-byte code modes 3509 * - standard timing codes 3510 * - established timing codes 3511 * - modes inferred from GTF or CVT range information 3512 * 3513 * We get this pretty much right. 3514 * 3515 * XXX order for additional mode types in extension blocks? 3516 */ 3517 num_modes += add_detailed_modes(connector, edid, quirks); 3518 num_modes += add_cvt_modes(connector, edid); 3519 num_modes += add_standard_modes(connector, edid); 3520 num_modes += add_established_modes(connector, edid); 3521 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3522 num_modes += add_inferred_modes(connector, edid); 3523 num_modes += add_cea_modes(connector, edid); 3524 num_modes += add_alternate_cea_modes(connector, edid); 3525 3526 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3527 edid_fixup_preferred(connector, quirks); 3528 3529 drm_add_display_info(edid, &connector->display_info); 3530 3531 if (quirks & EDID_QUIRK_FORCE_8BPC) 3532 connector->display_info.bpc = 8; 3533 3534 return num_modes; 3535 } 3536 EXPORT_SYMBOL(drm_add_edid_modes); 3537 3538 /** 3539 * drm_add_modes_noedid - add modes for the connectors without EDID 3540 * @connector: connector we're probing 3541 * @hdisplay: the horizontal display limit 3542 * @vdisplay: the vertical display limit 3543 * 3544 * Add the specified modes to the connector's mode list. Only when the 3545 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3546 * 3547 * Return number of modes added or 0 if we couldn't find any. 3548 */ 3549 int drm_add_modes_noedid(struct drm_connector *connector, 3550 int hdisplay, int vdisplay) 3551 { 3552 int i, count, num_modes = 0; 3553 struct drm_display_mode *mode; 3554 struct drm_device *dev = connector->dev; 3555 3556 count = sizeof(drm_dmt_modes) / sizeof(struct drm_display_mode); 3557 if (hdisplay < 0) 3558 hdisplay = 0; 3559 if (vdisplay < 0) 3560 vdisplay = 0; 3561 3562 for (i = 0; i < count; i++) { 3563 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3564 if (hdisplay && vdisplay) { 3565 /* 3566 * Only when two are valid, they will be used to check 3567 * whether the mode should be added to the mode list of 3568 * the connector. 3569 */ 3570 if (ptr->hdisplay > hdisplay || 3571 ptr->vdisplay > vdisplay) 3572 continue; 3573 } 3574 if (drm_mode_vrefresh(ptr) > 61) 3575 continue; 3576 mode = drm_mode_duplicate(dev, ptr); 3577 if (mode) { 3578 drm_mode_probed_add(connector, mode); 3579 num_modes++; 3580 } 3581 } 3582 return num_modes; 3583 } 3584 EXPORT_SYMBOL(drm_add_modes_noedid); 3585 3586 void drm_set_preferred_mode(struct drm_connector *connector, 3587 int hpref, int vpref) 3588 { 3589 struct drm_display_mode *mode; 3590 3591 list_for_each_entry(mode, &connector->probed_modes, head) { 3592 if (mode->hdisplay == hpref && 3593 mode->vdisplay == vpref) 3594 mode->type |= DRM_MODE_TYPE_PREFERRED; 3595 } 3596 } 3597 EXPORT_SYMBOL(drm_set_preferred_mode); 3598 3599 /** 3600 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3601 * data from a DRM display mode 3602 * @frame: HDMI AVI infoframe 3603 * @mode: DRM display mode 3604 * 3605 * Returns 0 on success or a negative error code on failure. 3606 */ 3607 int 3608 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3609 const struct drm_display_mode *mode) 3610 { 3611 int err; 3612 3613 if (!frame || !mode) 3614 return -EINVAL; 3615 3616 err = hdmi_avi_infoframe_init(frame); 3617 if (err < 0) 3618 return err; 3619 3620 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3621 frame->pixel_repeat = 1; 3622 3623 frame->video_code = drm_match_cea_mode(mode); 3624 3625 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3626 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3627 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3628 3629 return 0; 3630 } 3631 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3632 3633 static enum hdmi_3d_structure 3634 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3635 { 3636 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3637 3638 switch (layout) { 3639 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3640 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3641 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 3642 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 3643 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 3644 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 3645 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 3646 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 3647 case DRM_MODE_FLAG_3D_L_DEPTH: 3648 return HDMI_3D_STRUCTURE_L_DEPTH; 3649 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 3650 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 3651 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 3652 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 3653 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 3654 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 3655 default: 3656 return HDMI_3D_STRUCTURE_INVALID; 3657 } 3658 } 3659 3660 /** 3661 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 3662 * data from a DRM display mode 3663 * @frame: HDMI vendor infoframe 3664 * @mode: DRM display mode 3665 * 3666 * Note that there's is a need to send HDMI vendor infoframes only when using a 3667 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 3668 * function will return -EINVAL, error that can be safely ignored. 3669 * 3670 * Returns 0 on success or a negative error code on failure. 3671 */ 3672 int 3673 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 3674 const struct drm_display_mode *mode) 3675 { 3676 int err; 3677 u32 s3d_flags; 3678 u8 vic; 3679 3680 if (!frame || !mode) 3681 return -EINVAL; 3682 3683 vic = drm_match_hdmi_mode(mode); 3684 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 3685 3686 if (!vic && !s3d_flags) 3687 return -EINVAL; 3688 3689 if (vic && s3d_flags) 3690 return -EINVAL; 3691 3692 err = hdmi_vendor_infoframe_init(frame); 3693 if (err < 0) 3694 return err; 3695 3696 if (vic) 3697 frame->vic = vic; 3698 else 3699 frame->s3d_struct = s3d_structure_from_display_mode(mode); 3700 3701 return 0; 3702 } 3703 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 3704
Indexes created Fri Oct 17 03:10:13 GMT 2025