drm_edid.c revision 1.6
1 /* $NetBSD: drm_edid.c,v 1.6 2018/08/27 04:58:19 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Luc Verhaegen (quirks list) 5 * Copyright (c) 2007-2008 Intel Corporation 6 * Jesse Barnes <jesse.barnes (at) intel.com> 7 * Copyright 2010 Red Hat, Inc. 8 * 9 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 10 * FB layer. 11 * Copyright (C) 2006 Dennis Munsie <dmunsie (at) cecropia.com> 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sub license, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 29 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30 * DEALINGS IN THE SOFTWARE. 31 */ 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: drm_edid.c,v 1.6 2018/08/27 04:58:19 riastradh Exp $"); 34 35 #include <linux/kernel.h> 36 #include <linux/slab.h> 37 #include <linux/hdmi.h> 38 #include <linux/i2c.h> 39 #include <linux/module.h> 40 #include <linux/moduleparam.h> 41 #include <linux/export.h> 42 #include <linux/printk.h> 43 #include <linux/device.h> 44 #include <linux/string.h> 45 #include <linux/errno.h> 46 #include <asm/byteorder.h> 47 #include <drm/drmP.h> 48 #include <drm/drm_edid.h> 49 #include <drm/drm_displayid.h> 50 51 #define version_greater(edid, maj, min) \ 52 (((edid)->version > (maj)) || \ 53 ((edid)->version == (maj) && (edid)->revision > (min))) 54 55 #define EDID_EST_TIMINGS 16 56 #define EDID_STD_TIMINGS 8 57 #define EDID_DETAILED_TIMINGS 4 58 59 /* 60 * EDID blocks out in the wild have a variety of bugs, try to collect 61 * them here (note that userspace may work around broken monitors first, 62 * but fixes should make their way here so that the kernel "just works" 63 * on as many displays as possible). 64 */ 65 66 /* First detailed mode wrong, use largest 60Hz mode */ 67 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 68 /* Reported 135MHz pixel clock is too high, needs adjustment */ 69 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 70 /* Prefer the largest mode at 75 Hz */ 71 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 72 /* Detail timing is in cm not mm */ 73 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 74 /* Detailed timing descriptors have bogus size values, so just take the 75 * maximum size and use that. 76 */ 77 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 78 /* Monitor forgot to set the first detailed is preferred bit. */ 79 #define EDID_QUIRK_FIRST_DETAILED_PREFERRED (1 << 5) 80 /* use +hsync +vsync for detailed mode */ 81 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 82 /* Force reduced-blanking timings for detailed modes */ 83 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 84 /* Force 8bpc */ 85 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 86 /* Force 12bpc */ 87 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 88 /* Force 6bpc */ 89 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 90 /* Force 10bpc */ 91 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 92 93 struct detailed_mode_closure { 94 struct drm_connector *connector; 95 struct edid *edid; 96 bool preferred; 97 u32 quirks; 98 int modes; 99 }; 100 101 #define LEVEL_DMT 0 102 #define LEVEL_GTF 1 103 #define LEVEL_GTF2 2 104 #define LEVEL_CVT 3 105 106 static struct edid_quirk { 107 char vendor[4]; 108 int product_id; 109 u32 quirks; 110 } edid_quirk_list[] = { 111 /* Acer AL1706 */ 112 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 113 /* Acer F51 */ 114 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 115 /* Unknown Acer */ 116 { "ACR", 2423, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 117 118 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 119 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 120 121 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 122 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 123 124 /* Belinea 10 15 55 */ 125 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 126 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 127 128 /* Envision Peripherals, Inc. EN-7100e */ 129 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 130 /* Envision EN2028 */ 131 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 132 133 /* Funai Electronics PM36B */ 134 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 135 EDID_QUIRK_DETAILED_IN_CM }, 136 137 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 138 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 139 140 /* LG Philips LCD LP154W01-A5 */ 141 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 142 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 143 144 /* Philips 107p5 CRT */ 145 { "PHL", 57364, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 146 147 /* Proview AY765C */ 148 { "PTS", 765, EDID_QUIRK_FIRST_DETAILED_PREFERRED }, 149 150 /* Samsung SyncMaster 205BW. Note: irony */ 151 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 152 /* Samsung SyncMaster 22[5-6]BW */ 153 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 154 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 155 156 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 157 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 158 159 /* ViewSonic VA2026w */ 160 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 161 162 /* Medion MD 30217 PG */ 163 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 164 165 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 166 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 167 168 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 169 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 170 }; 171 172 /* 173 * Autogenerated from the DMT spec. 174 * This table is copied from xfree86/modes/xf86EdidModes.c. 175 */ 176 static const struct drm_display_mode drm_dmt_modes[] = { 177 /* 0x01 - 640x350@85Hz */ 178 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 179 736, 832, 0, 350, 382, 385, 445, 0, 180 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 181 /* 0x02 - 640x400@85Hz */ 182 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 183 736, 832, 0, 400, 401, 404, 445, 0, 184 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 185 /* 0x03 - 720x400@85Hz */ 186 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 187 828, 936, 0, 400, 401, 404, 446, 0, 188 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 189 /* 0x04 - 640x480@60Hz */ 190 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 191 752, 800, 0, 480, 490, 492, 525, 0, 192 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 193 /* 0x05 - 640x480@72Hz */ 194 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 195 704, 832, 0, 480, 489, 492, 520, 0, 196 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 197 /* 0x06 - 640x480@75Hz */ 198 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 199 720, 840, 0, 480, 481, 484, 500, 0, 200 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 201 /* 0x07 - 640x480@85Hz */ 202 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 203 752, 832, 0, 480, 481, 484, 509, 0, 204 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 205 /* 0x08 - 800x600@56Hz */ 206 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 207 896, 1024, 0, 600, 601, 603, 625, 0, 208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 209 /* 0x09 - 800x600@60Hz */ 210 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 211 968, 1056, 0, 600, 601, 605, 628, 0, 212 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 213 /* 0x0a - 800x600@72Hz */ 214 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 215 976, 1040, 0, 600, 637, 643, 666, 0, 216 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 217 /* 0x0b - 800x600@75Hz */ 218 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 219 896, 1056, 0, 600, 601, 604, 625, 0, 220 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 221 /* 0x0c - 800x600@85Hz */ 222 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 223 896, 1048, 0, 600, 601, 604, 631, 0, 224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 225 /* 0x0d - 800x600@120Hz RB */ 226 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 227 880, 960, 0, 600, 603, 607, 636, 0, 228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 229 /* 0x0e - 848x480@60Hz */ 230 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 231 976, 1088, 0, 480, 486, 494, 517, 0, 232 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 233 /* 0x0f - 1024x768@43Hz, interlace */ 234 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 235 1208, 1264, 0, 768, 768, 772, 817, 0, 236 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 237 DRM_MODE_FLAG_INTERLACE) }, 238 /* 0x10 - 1024x768@60Hz */ 239 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 240 1184, 1344, 0, 768, 771, 777, 806, 0, 241 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 242 /* 0x11 - 1024x768@70Hz */ 243 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 244 1184, 1328, 0, 768, 771, 777, 806, 0, 245 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 246 /* 0x12 - 1024x768@75Hz */ 247 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 248 1136, 1312, 0, 768, 769, 772, 800, 0, 249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 250 /* 0x13 - 1024x768@85Hz */ 251 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 252 1168, 1376, 0, 768, 769, 772, 808, 0, 253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 254 /* 0x14 - 1024x768@120Hz RB */ 255 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 256 1104, 1184, 0, 768, 771, 775, 813, 0, 257 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 258 /* 0x15 - 1152x864@75Hz */ 259 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 260 1344, 1600, 0, 864, 865, 868, 900, 0, 261 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 262 /* 0x55 - 1280x720@60Hz */ 263 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 264 1430, 1650, 0, 720, 725, 730, 750, 0, 265 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 266 /* 0x16 - 1280x768@60Hz RB */ 267 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 268 1360, 1440, 0, 768, 771, 778, 790, 0, 269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 270 /* 0x17 - 1280x768@60Hz */ 271 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 272 1472, 1664, 0, 768, 771, 778, 798, 0, 273 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 274 /* 0x18 - 1280x768@75Hz */ 275 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 276 1488, 1696, 0, 768, 771, 778, 805, 0, 277 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 278 /* 0x19 - 1280x768@85Hz */ 279 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 280 1496, 1712, 0, 768, 771, 778, 809, 0, 281 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 282 /* 0x1a - 1280x768@120Hz RB */ 283 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 284 1360, 1440, 0, 768, 771, 778, 813, 0, 285 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 286 /* 0x1b - 1280x800@60Hz RB */ 287 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 288 1360, 1440, 0, 800, 803, 809, 823, 0, 289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 290 /* 0x1c - 1280x800@60Hz */ 291 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 292 1480, 1680, 0, 800, 803, 809, 831, 0, 293 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 294 /* 0x1d - 1280x800@75Hz */ 295 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 296 1488, 1696, 0, 800, 803, 809, 838, 0, 297 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 298 /* 0x1e - 1280x800@85Hz */ 299 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 300 1496, 1712, 0, 800, 803, 809, 843, 0, 301 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 302 /* 0x1f - 1280x800@120Hz RB */ 303 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 304 1360, 1440, 0, 800, 803, 809, 847, 0, 305 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 306 /* 0x20 - 1280x960@60Hz */ 307 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 308 1488, 1800, 0, 960, 961, 964, 1000, 0, 309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 310 /* 0x21 - 1280x960@85Hz */ 311 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 312 1504, 1728, 0, 960, 961, 964, 1011, 0, 313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 314 /* 0x22 - 1280x960@120Hz RB */ 315 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 316 1360, 1440, 0, 960, 963, 967, 1017, 0, 317 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 318 /* 0x23 - 1280x1024@60Hz */ 319 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 320 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 321 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 322 /* 0x24 - 1280x1024@75Hz */ 323 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 324 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 325 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 326 /* 0x25 - 1280x1024@85Hz */ 327 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 328 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 330 /* 0x26 - 1280x1024@120Hz RB */ 331 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 332 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 334 /* 0x27 - 1360x768@60Hz */ 335 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 336 1536, 1792, 0, 768, 771, 777, 795, 0, 337 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 338 /* 0x28 - 1360x768@120Hz RB */ 339 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 340 1440, 1520, 0, 768, 771, 776, 813, 0, 341 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 342 /* 0x51 - 1366x768@60Hz */ 343 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 344 1579, 1792, 0, 768, 771, 774, 798, 0, 345 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 346 /* 0x56 - 1366x768@60Hz */ 347 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 348 1436, 1500, 0, 768, 769, 772, 800, 0, 349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 350 /* 0x29 - 1400x1050@60Hz RB */ 351 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 352 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 354 /* 0x2a - 1400x1050@60Hz */ 355 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 356 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 357 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 358 /* 0x2b - 1400x1050@75Hz */ 359 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 360 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 361 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 362 /* 0x2c - 1400x1050@85Hz */ 363 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 364 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 365 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 366 /* 0x2d - 1400x1050@120Hz RB */ 367 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 368 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 370 /* 0x2e - 1440x900@60Hz RB */ 371 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 372 1520, 1600, 0, 900, 903, 909, 926, 0, 373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 374 /* 0x2f - 1440x900@60Hz */ 375 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 376 1672, 1904, 0, 900, 903, 909, 934, 0, 377 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 378 /* 0x30 - 1440x900@75Hz */ 379 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 380 1688, 1936, 0, 900, 903, 909, 942, 0, 381 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 382 /* 0x31 - 1440x900@85Hz */ 383 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 384 1696, 1952, 0, 900, 903, 909, 948, 0, 385 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 386 /* 0x32 - 1440x900@120Hz RB */ 387 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 388 1520, 1600, 0, 900, 903, 909, 953, 0, 389 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 390 /* 0x53 - 1600x900@60Hz */ 391 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 392 1704, 1800, 0, 900, 901, 904, 1000, 0, 393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 394 /* 0x33 - 1600x1200@60Hz */ 395 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 396 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 398 /* 0x34 - 1600x1200@65Hz */ 399 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 400 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 401 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 402 /* 0x35 - 1600x1200@70Hz */ 403 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 404 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 405 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 406 /* 0x36 - 1600x1200@75Hz */ 407 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 408 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 409 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 410 /* 0x37 - 1600x1200@85Hz */ 411 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 412 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 413 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 414 /* 0x38 - 1600x1200@120Hz RB */ 415 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 416 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 418 /* 0x39 - 1680x1050@60Hz RB */ 419 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 420 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 422 /* 0x3a - 1680x1050@60Hz */ 423 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 424 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 425 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 426 /* 0x3b - 1680x1050@75Hz */ 427 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 428 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 429 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 430 /* 0x3c - 1680x1050@85Hz */ 431 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 432 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 433 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 434 /* 0x3d - 1680x1050@120Hz RB */ 435 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 436 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 438 /* 0x3e - 1792x1344@60Hz */ 439 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 440 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 441 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 442 /* 0x3f - 1792x1344@75Hz */ 443 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 444 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 445 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 446 /* 0x40 - 1792x1344@120Hz RB */ 447 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 448 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 450 /* 0x41 - 1856x1392@60Hz */ 451 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 452 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 453 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 454 /* 0x42 - 1856x1392@75Hz */ 455 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 456 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 457 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 458 /* 0x43 - 1856x1392@120Hz RB */ 459 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 460 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 462 /* 0x52 - 1920x1080@60Hz */ 463 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 464 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 465 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 466 /* 0x44 - 1920x1200@60Hz RB */ 467 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 468 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 470 /* 0x45 - 1920x1200@60Hz */ 471 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 472 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 473 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 474 /* 0x46 - 1920x1200@75Hz */ 475 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 476 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 477 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 478 /* 0x47 - 1920x1200@85Hz */ 479 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 480 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 481 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 482 /* 0x48 - 1920x1200@120Hz RB */ 483 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 484 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 486 /* 0x49 - 1920x1440@60Hz */ 487 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 488 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 489 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 490 /* 0x4a - 1920x1440@75Hz */ 491 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 492 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 493 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 494 /* 0x4b - 1920x1440@120Hz RB */ 495 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 496 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 498 /* 0x54 - 2048x1152@60Hz */ 499 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 500 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 502 /* 0x4c - 2560x1600@60Hz RB */ 503 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 504 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 506 /* 0x4d - 2560x1600@60Hz */ 507 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 508 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 509 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 510 /* 0x4e - 2560x1600@75Hz */ 511 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 512 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 513 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 514 /* 0x4f - 2560x1600@85Hz */ 515 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 516 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 517 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 518 /* 0x50 - 2560x1600@120Hz RB */ 519 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 520 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 522 /* 0x57 - 4096x2160@60Hz RB */ 523 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 524 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 526 /* 0x58 - 4096x2160 (at) 59.94Hz RB */ 527 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 528 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 529 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 530 }; 531 532 /* 533 * These more or less come from the DMT spec. The 720x400 modes are 534 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 535 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 536 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 537 * mode. 538 * 539 * The DMT modes have been fact-checked; the rest are mild guesses. 540 */ 541 static const struct drm_display_mode edid_est_modes[] = { 542 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 543 968, 1056, 0, 600, 601, 605, 628, 0, 544 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 545 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 546 896, 1024, 0, 600, 601, 603, 625, 0, 547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 548 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 549 720, 840, 0, 480, 481, 484, 500, 0, 550 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 551 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 552 704, 832, 0, 480, 489, 491, 520, 0, 553 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 554 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 555 768, 864, 0, 480, 483, 486, 525, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 557 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25200, 640, 656, 558 752, 800, 0, 480, 490, 492, 525, 0, 559 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 560 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 561 846, 900, 0, 400, 421, 423, 449, 0, 562 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 563 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 564 846, 900, 0, 400, 412, 414, 449, 0, 565 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 566 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 567 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 568 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 569 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78800, 1024, 1040, 570 1136, 1312, 0, 768, 769, 772, 800, 0, 571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 572 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 573 1184, 1328, 0, 768, 771, 777, 806, 0, 574 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 575 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 576 1184, 1344, 0, 768, 771, 777, 806, 0, 577 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 578 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 579 1208, 1264, 0, 768, 768, 776, 817, 0, 580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 581 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 582 928, 1152, 0, 624, 625, 628, 667, 0, 583 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 584 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 585 896, 1056, 0, 600, 601, 604, 625, 0, 586 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 587 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 588 976, 1040, 0, 600, 637, 643, 666, 0, 589 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 590 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 591 1344, 1600, 0, 864, 865, 868, 900, 0, 592 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 593 }; 594 595 struct minimode { 596 short w; 597 short h; 598 short r; 599 short rb; 600 }; 601 602 static const struct minimode est3_modes[] = { 603 /* byte 6 */ 604 { 640, 350, 85, 0 }, 605 { 640, 400, 85, 0 }, 606 { 720, 400, 85, 0 }, 607 { 640, 480, 85, 0 }, 608 { 848, 480, 60, 0 }, 609 { 800, 600, 85, 0 }, 610 { 1024, 768, 85, 0 }, 611 { 1152, 864, 75, 0 }, 612 /* byte 7 */ 613 { 1280, 768, 60, 1 }, 614 { 1280, 768, 60, 0 }, 615 { 1280, 768, 75, 0 }, 616 { 1280, 768, 85, 0 }, 617 { 1280, 960, 60, 0 }, 618 { 1280, 960, 85, 0 }, 619 { 1280, 1024, 60, 0 }, 620 { 1280, 1024, 85, 0 }, 621 /* byte 8 */ 622 { 1360, 768, 60, 0 }, 623 { 1440, 900, 60, 1 }, 624 { 1440, 900, 60, 0 }, 625 { 1440, 900, 75, 0 }, 626 { 1440, 900, 85, 0 }, 627 { 1400, 1050, 60, 1 }, 628 { 1400, 1050, 60, 0 }, 629 { 1400, 1050, 75, 0 }, 630 /* byte 9 */ 631 { 1400, 1050, 85, 0 }, 632 { 1680, 1050, 60, 1 }, 633 { 1680, 1050, 60, 0 }, 634 { 1680, 1050, 75, 0 }, 635 { 1680, 1050, 85, 0 }, 636 { 1600, 1200, 60, 0 }, 637 { 1600, 1200, 65, 0 }, 638 { 1600, 1200, 70, 0 }, 639 /* byte 10 */ 640 { 1600, 1200, 75, 0 }, 641 { 1600, 1200, 85, 0 }, 642 { 1792, 1344, 60, 0 }, 643 { 1792, 1344, 75, 0 }, 644 { 1856, 1392, 60, 0 }, 645 { 1856, 1392, 75, 0 }, 646 { 1920, 1200, 60, 1 }, 647 { 1920, 1200, 60, 0 }, 648 /* byte 11 */ 649 { 1920, 1200, 75, 0 }, 650 { 1920, 1200, 85, 0 }, 651 { 1920, 1440, 60, 0 }, 652 { 1920, 1440, 75, 0 }, 653 }; 654 655 static const struct minimode extra_modes[] = { 656 { 1024, 576, 60, 0 }, 657 { 1366, 768, 60, 0 }, 658 { 1600, 900, 60, 0 }, 659 { 1680, 945, 60, 0 }, 660 { 1920, 1080, 60, 0 }, 661 { 2048, 1152, 60, 0 }, 662 { 2048, 1536, 60, 0 }, 663 }; 664 665 /* 666 * Probably taken from CEA-861 spec. 667 * This table is converted from xorg's hw/xfree86/modes/xf86EdidModes.c. 668 */ 669 static const struct drm_display_mode edid_cea_modes[] = { 670 /* 1 - 640x480@60Hz */ 671 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 672 752, 800, 0, 480, 490, 492, 525, 0, 673 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 674 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 675 /* 2 - 720x480@60Hz */ 676 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 677 798, 858, 0, 480, 489, 495, 525, 0, 678 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 679 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 680 /* 3 - 720x480@60Hz */ 681 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 682 798, 858, 0, 480, 489, 495, 525, 0, 683 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 684 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 685 /* 4 - 1280x720@60Hz */ 686 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 687 1430, 1650, 0, 720, 725, 730, 750, 0, 688 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 689 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 690 /* 5 - 1920x1080i@60Hz */ 691 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 692 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 693 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 694 DRM_MODE_FLAG_INTERLACE), 695 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 696 /* 6 - 720(1440)x480i@60Hz */ 697 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 698 801, 858, 0, 480, 488, 494, 525, 0, 699 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 700 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 701 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 702 /* 7 - 720(1440)x480i@60Hz */ 703 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 704 801, 858, 0, 480, 488, 494, 525, 0, 705 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 706 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 707 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 708 /* 8 - 720(1440)x240@60Hz */ 709 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 710 801, 858, 0, 240, 244, 247, 262, 0, 711 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 712 DRM_MODE_FLAG_DBLCLK), 713 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 714 /* 9 - 720(1440)x240@60Hz */ 715 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 716 801, 858, 0, 240, 244, 247, 262, 0, 717 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 718 DRM_MODE_FLAG_DBLCLK), 719 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 720 /* 10 - 2880x480i@60Hz */ 721 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 722 3204, 3432, 0, 480, 488, 494, 525, 0, 723 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 724 DRM_MODE_FLAG_INTERLACE), 725 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 726 /* 11 - 2880x480i@60Hz */ 727 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 728 3204, 3432, 0, 480, 488, 494, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 730 DRM_MODE_FLAG_INTERLACE), 731 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 732 /* 12 - 2880x240@60Hz */ 733 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 734 3204, 3432, 0, 240, 244, 247, 262, 0, 735 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 736 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 737 /* 13 - 2880x240@60Hz */ 738 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 739 3204, 3432, 0, 240, 244, 247, 262, 0, 740 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 741 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 742 /* 14 - 1440x480@60Hz */ 743 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 744 1596, 1716, 0, 480, 489, 495, 525, 0, 745 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 746 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 747 /* 15 - 1440x480@60Hz */ 748 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 749 1596, 1716, 0, 480, 489, 495, 525, 0, 750 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 752 /* 16 - 1920x1080@60Hz */ 753 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 754 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 755 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 756 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 757 /* 17 - 720x576@50Hz */ 758 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 759 796, 864, 0, 576, 581, 586, 625, 0, 760 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 761 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 762 /* 18 - 720x576@50Hz */ 763 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 764 796, 864, 0, 576, 581, 586, 625, 0, 765 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 766 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 767 /* 19 - 1280x720@50Hz */ 768 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 769 1760, 1980, 0, 720, 725, 730, 750, 0, 770 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 771 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 772 /* 20 - 1920x1080i@50Hz */ 773 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 774 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 776 DRM_MODE_FLAG_INTERLACE), 777 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 778 /* 21 - 720(1440)x576i@50Hz */ 779 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 780 795, 864, 0, 576, 580, 586, 625, 0, 781 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 782 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 783 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 784 /* 22 - 720(1440)x576i@50Hz */ 785 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 786 795, 864, 0, 576, 580, 586, 625, 0, 787 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 788 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 789 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 790 /* 23 - 720(1440)x288@50Hz */ 791 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 792 795, 864, 0, 288, 290, 293, 312, 0, 793 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 794 DRM_MODE_FLAG_DBLCLK), 795 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 796 /* 24 - 720(1440)x288@50Hz */ 797 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 798 795, 864, 0, 288, 290, 293, 312, 0, 799 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 800 DRM_MODE_FLAG_DBLCLK), 801 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 802 /* 25 - 2880x576i@50Hz */ 803 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 804 3180, 3456, 0, 576, 580, 586, 625, 0, 805 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 806 DRM_MODE_FLAG_INTERLACE), 807 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 808 /* 26 - 2880x576i@50Hz */ 809 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 810 3180, 3456, 0, 576, 580, 586, 625, 0, 811 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 812 DRM_MODE_FLAG_INTERLACE), 813 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 814 /* 27 - 2880x288@50Hz */ 815 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 816 3180, 3456, 0, 288, 290, 293, 312, 0, 817 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 818 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 819 /* 28 - 2880x288@50Hz */ 820 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 821 3180, 3456, 0, 288, 290, 293, 312, 0, 822 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 823 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 824 /* 29 - 1440x576@50Hz */ 825 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 826 1592, 1728, 0, 576, 581, 586, 625, 0, 827 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 828 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 829 /* 30 - 1440x576@50Hz */ 830 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 831 1592, 1728, 0, 576, 581, 586, 625, 0, 832 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 31 - 1920x1080@50Hz */ 835 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 836 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 838 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 839 /* 32 - 1920x1080@24Hz */ 840 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 841 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 843 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 844 /* 33 - 1920x1080@25Hz */ 845 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 846 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 848 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 849 /* 34 - 1920x1080@30Hz */ 850 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 851 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 853 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 854 /* 35 - 2880x480@60Hz */ 855 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 856 3192, 3432, 0, 480, 489, 495, 525, 0, 857 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 858 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 859 /* 36 - 2880x480@60Hz */ 860 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 861 3192, 3432, 0, 480, 489, 495, 525, 0, 862 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 863 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 864 /* 37 - 2880x576@50Hz */ 865 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 866 3184, 3456, 0, 576, 581, 586, 625, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 868 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 869 /* 38 - 2880x576@50Hz */ 870 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 871 3184, 3456, 0, 576, 581, 586, 625, 0, 872 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 873 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 874 /* 39 - 1920x1080i@50Hz */ 875 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 876 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 877 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 878 DRM_MODE_FLAG_INTERLACE), 879 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 40 - 1920x1080i@100Hz */ 881 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 882 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 883 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 884 DRM_MODE_FLAG_INTERLACE), 885 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 886 /* 41 - 1280x720@100Hz */ 887 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 888 1760, 1980, 0, 720, 725, 730, 750, 0, 889 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 890 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 891 /* 42 - 720x576@100Hz */ 892 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 893 796, 864, 0, 576, 581, 586, 625, 0, 894 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 895 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 896 /* 43 - 720x576@100Hz */ 897 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 898 796, 864, 0, 576, 581, 586, 625, 0, 899 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 900 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 901 /* 44 - 720(1440)x576i@100Hz */ 902 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 903 795, 864, 0, 576, 580, 586, 625, 0, 904 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 905 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 906 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 907 /* 45 - 720(1440)x576i@100Hz */ 908 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 909 795, 864, 0, 576, 580, 586, 625, 0, 910 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 911 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 912 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 913 /* 46 - 1920x1080i@120Hz */ 914 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 915 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 916 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 917 DRM_MODE_FLAG_INTERLACE), 918 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 47 - 1280x720@120Hz */ 920 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 921 1430, 1650, 0, 720, 725, 730, 750, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 924 /* 48 - 720x480@120Hz */ 925 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 926 798, 858, 0, 480, 489, 495, 525, 0, 927 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 928 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 929 /* 49 - 720x480@120Hz */ 930 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 931 798, 858, 0, 480, 489, 495, 525, 0, 932 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 933 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 50 - 720(1440)x480i@120Hz */ 935 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 936 801, 858, 0, 480, 488, 494, 525, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 938 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 939 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 940 /* 51 - 720(1440)x480i@120Hz */ 941 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 942 801, 858, 0, 480, 488, 494, 525, 0, 943 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 944 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 945 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 946 /* 52 - 720x576@200Hz */ 947 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 948 796, 864, 0, 576, 581, 586, 625, 0, 949 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 950 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 951 /* 53 - 720x576@200Hz */ 952 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 953 796, 864, 0, 576, 581, 586, 625, 0, 954 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 955 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 956 /* 54 - 720(1440)x576i@200Hz */ 957 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 958 795, 864, 0, 576, 580, 586, 625, 0, 959 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 960 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 961 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 962 /* 55 - 720(1440)x576i@200Hz */ 963 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 964 795, 864, 0, 576, 580, 586, 625, 0, 965 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 966 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 967 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 968 /* 56 - 720x480@240Hz */ 969 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 970 798, 858, 0, 480, 489, 495, 525, 0, 971 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 972 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 973 /* 57 - 720x480@240Hz */ 974 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 975 798, 858, 0, 480, 489, 495, 525, 0, 976 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 977 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 978 /* 58 - 720(1440)x480i@240 */ 979 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 980 801, 858, 0, 480, 488, 494, 525, 0, 981 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 982 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 983 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 984 /* 59 - 720(1440)x480i@240 */ 985 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 986 801, 858, 0, 480, 488, 494, 525, 0, 987 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 988 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 989 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 /* 60 - 1280x720@24Hz */ 991 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 992 3080, 3300, 0, 720, 725, 730, 750, 0, 993 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 994 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 995 /* 61 - 1280x720@25Hz */ 996 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 997 3740, 3960, 0, 720, 725, 730, 750, 0, 998 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 999 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1000 /* 62 - 1280x720@30Hz */ 1001 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1002 3080, 3300, 0, 720, 725, 730, 750, 0, 1003 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1004 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1005 /* 63 - 1920x1080@120Hz */ 1006 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1007 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1008 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1009 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1010 /* 64 - 1920x1080@100Hz */ 1011 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1012 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 1013 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1014 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1015 }; 1016 1017 /* 1018 * HDMI 1.4 4k modes. 1019 */ 1020 static const struct drm_display_mode edid_4k_modes[] = { 1021 /* 1 - 3840x2160@30Hz */ 1022 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1023 3840, 4016, 4104, 4400, 0, 1024 2160, 2168, 2178, 2250, 0, 1025 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1026 .vrefresh = 30, }, 1027 /* 2 - 3840x2160@25Hz */ 1028 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1029 3840, 4896, 4984, 5280, 0, 1030 2160, 2168, 2178, 2250, 0, 1031 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1032 .vrefresh = 25, }, 1033 /* 3 - 3840x2160@24Hz */ 1034 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1035 3840, 5116, 5204, 5500, 0, 1036 2160, 2168, 2178, 2250, 0, 1037 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1038 .vrefresh = 24, }, 1039 /* 4 - 4096x2160@24Hz (SMPTE) */ 1040 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1041 4096, 5116, 5204, 5500, 0, 1042 2160, 2168, 2178, 2250, 0, 1043 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1044 .vrefresh = 24, }, 1045 }; 1046 1047 /*** DDC fetch and block validation ***/ 1048 1049 static const u8 edid_header[] = { 1050 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1051 }; 1052 1053 /** 1054 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1055 * @raw_edid: pointer to raw base EDID block 1056 * 1057 * Sanity check the header of the base EDID block. 1058 * 1059 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1060 */ 1061 int drm_edid_header_is_valid(const u8 *raw_edid) 1062 { 1063 int i, score = 0; 1064 1065 for (i = 0; i < sizeof(edid_header); i++) 1066 if (raw_edid[i] == edid_header[i]) 1067 score++; 1068 1069 return score; 1070 } 1071 EXPORT_SYMBOL(drm_edid_header_is_valid); 1072 1073 static int edid_fixup __read_mostly = 6; 1074 module_param_named(edid_fixup, edid_fixup, int, 0400); 1075 MODULE_PARM_DESC(edid_fixup, 1076 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1077 1078 static void drm_get_displayid(struct drm_connector *connector, 1079 struct edid *edid); 1080 1081 static int drm_edid_block_checksum(const u8 *raw_edid) 1082 { 1083 int i; 1084 u8 csum = 0; 1085 for (i = 0; i < EDID_LENGTH; i++) 1086 csum += raw_edid[i]; 1087 1088 return csum; 1089 } 1090 1091 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1092 { 1093 if (memchr_inv(in_edid, 0, length)) 1094 return false; 1095 1096 return true; 1097 } 1098 1099 /** 1100 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1101 * @raw_edid: pointer to raw EDID block 1102 * @block: type of block to validate (0 for base, extension otherwise) 1103 * @print_bad_edid: if true, dump bad EDID blocks to the console 1104 * @edid_corrupt: if true, the header or checksum is invalid 1105 * 1106 * Validate a base or extension EDID block and optionally dump bad blocks to 1107 * the console. 1108 * 1109 * Return: True if the block is valid, false otherwise. 1110 */ 1111 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1112 bool *edid_corrupt) 1113 { 1114 u8 csum; 1115 struct edid *edid = (struct edid *)raw_edid; 1116 1117 if (WARN_ON(!raw_edid)) 1118 return false; 1119 1120 if (edid_fixup > 8 || edid_fixup < 0) 1121 edid_fixup = 6; 1122 1123 if (block == 0) { 1124 int score = drm_edid_header_is_valid(raw_edid); 1125 if (score == 8) { 1126 if (edid_corrupt) 1127 *edid_corrupt = false; 1128 } else if (score >= edid_fixup) { 1129 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1130 * The corrupt flag needs to be set here otherwise, the 1131 * fix-up code here will correct the problem, the 1132 * checksum is correct and the test fails 1133 */ 1134 if (edid_corrupt) 1135 *edid_corrupt = true; 1136 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1137 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1138 } else { 1139 if (edid_corrupt) 1140 *edid_corrupt = true; 1141 goto bad; 1142 } 1143 } 1144 1145 csum = drm_edid_block_checksum(raw_edid); 1146 if (csum) { 1147 if (print_bad_edid) { 1148 DRM_ERROR("EDID checksum is invalid, remainder is %d\n", csum); 1149 } 1150 1151 if (edid_corrupt) 1152 *edid_corrupt = true; 1153 1154 /* allow CEA to slide through, switches mangle this */ 1155 if (raw_edid[0] != 0x02) 1156 goto bad; 1157 } 1158 1159 /* per-block-type checks */ 1160 switch (raw_edid[0]) { 1161 case 0: /* base */ 1162 if (edid->version != 1) { 1163 DRM_ERROR("EDID has major version %d, instead of 1\n", edid->version); 1164 goto bad; 1165 } 1166 1167 if (edid->revision > 4) 1168 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1169 break; 1170 1171 default: 1172 break; 1173 } 1174 1175 return true; 1176 1177 bad: 1178 if (print_bad_edid) { 1179 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1180 printk(KERN_ERR "EDID block is all zeroes\n"); 1181 } else { 1182 printk(KERN_ERR "Raw EDID:\n"); 1183 print_hex_dump(KERN_ERR, " \t", DUMP_PREFIX_NONE, 16, 1, 1184 raw_edid, EDID_LENGTH, false); 1185 } 1186 } 1187 return false; 1188 } 1189 EXPORT_SYMBOL(drm_edid_block_valid); 1190 1191 /** 1192 * drm_edid_is_valid - sanity check EDID data 1193 * @edid: EDID data 1194 * 1195 * Sanity-check an entire EDID record (including extensions) 1196 * 1197 * Return: True if the EDID data is valid, false otherwise. 1198 */ 1199 bool drm_edid_is_valid(struct edid *edid) 1200 { 1201 int i; 1202 u8 *raw = (u8 *)edid; 1203 1204 if (!edid) 1205 return false; 1206 1207 for (i = 0; i <= edid->extensions; i++) 1208 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1209 return false; 1210 1211 return true; 1212 } 1213 EXPORT_SYMBOL(drm_edid_is_valid); 1214 1215 #define DDC_SEGMENT_ADDR 0x30 1216 /** 1217 * drm_do_probe_ddc_edid() - get EDID information via I2C 1218 * @data: I2C device adapter 1219 * @buf: EDID data buffer to be filled 1220 * @block: 128 byte EDID block to start fetching from 1221 * @len: EDID data buffer length to fetch 1222 * 1223 * Try to fetch EDID information by calling I2C driver functions. 1224 * 1225 * Return: 0 on success or -1 on failure. 1226 */ 1227 static int 1228 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1229 { 1230 struct i2c_adapter *adapter = data; 1231 unsigned char start = block * EDID_LENGTH; 1232 unsigned char segment = block >> 1; 1233 unsigned char xfers = segment ? 3 : 2; 1234 int ret, retries = 5; 1235 1236 /* 1237 * The core I2C driver will automatically retry the transfer if the 1238 * adapter reports EAGAIN. However, we find that bit-banging transfers 1239 * are susceptible to errors under a heavily loaded machine and 1240 * generate spurious NAKs and timeouts. Retrying the transfer 1241 * of the individual block a few times seems to overcome this. 1242 */ 1243 do { 1244 struct i2c_msg msgs[] = { 1245 { 1246 .addr = DDC_SEGMENT_ADDR, 1247 .flags = 0, 1248 .len = 1, 1249 .buf = &segment, 1250 }, { 1251 .addr = DDC_ADDR, 1252 .flags = 0, 1253 .len = 1, 1254 .buf = &start, 1255 }, { 1256 .addr = DDC_ADDR, 1257 .flags = I2C_M_RD, 1258 .len = len, 1259 .buf = buf, 1260 } 1261 }; 1262 1263 /* 1264 * Avoid sending the segment addr to not upset non-compliant 1265 * DDC monitors. 1266 */ 1267 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1268 1269 if (ret == -ENXIO) { 1270 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1271 adapter->name); 1272 break; 1273 } 1274 } while (ret != xfers && --retries); 1275 1276 return ret == xfers ? 0 : -1; 1277 } 1278 1279 /** 1280 * drm_do_get_edid - get EDID data using a custom EDID block read function 1281 * @connector: connector we're probing 1282 * @get_edid_block: EDID block read function 1283 * @data: private data passed to the block read function 1284 * 1285 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1286 * exposes a different interface to read EDID blocks this function can be used 1287 * to get EDID data using a custom block read function. 1288 * 1289 * As in the general case the DDC bus is accessible by the kernel at the I2C 1290 * level, drivers must make all reasonable efforts to expose it as an I2C 1291 * adapter and use drm_get_edid() instead of abusing this function. 1292 * 1293 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1294 */ 1295 struct edid *drm_do_get_edid(struct drm_connector *connector, 1296 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1297 size_t len), 1298 void *data) 1299 { 1300 int i, j = 0, valid_extensions = 0; 1301 u8 *block, *new; 1302 bool print_bad_edid = !connector->bad_edid_counter || (drm_debug & DRM_UT_KMS); 1303 1304 if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1305 return NULL; 1306 1307 /* base block fetch */ 1308 for (i = 0; i < 4; i++) { 1309 if (get_edid_block(data, block, 0, EDID_LENGTH)) 1310 goto out; 1311 if (drm_edid_block_valid(block, 0, print_bad_edid, 1312 &connector->edid_corrupt)) 1313 break; 1314 if (i == 0 && drm_edid_is_zero(block, EDID_LENGTH)) { 1315 connector->null_edid_counter++; 1316 goto carp; 1317 } 1318 } 1319 if (i == 4) 1320 goto carp; 1321 1322 /* if there's no extensions, we're done */ 1323 if (block[0x7e] == 0) 1324 return (struct edid *)block; 1325 1326 new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); 1327 if (!new) 1328 goto out; 1329 block = new; 1330 1331 for (j = 1; j <= block[0x7e]; j++) { 1332 for (i = 0; i < 4; i++) { 1333 if (get_edid_block(data, 1334 block + (valid_extensions + 1) * EDID_LENGTH, 1335 j, EDID_LENGTH)) 1336 goto out; 1337 if (drm_edid_block_valid(block + (valid_extensions + 1) 1338 * EDID_LENGTH, j, 1339 print_bad_edid, 1340 NULL)) { 1341 valid_extensions++; 1342 break; 1343 } 1344 } 1345 1346 if (i == 4 && print_bad_edid) { 1347 dev_warn(connector->dev->dev, 1348 "%s: Ignoring invalid EDID block %d.\n", 1349 connector->name, j); 1350 1351 connector->bad_edid_counter++; 1352 } 1353 } 1354 1355 if (valid_extensions != block[0x7e]) { 1356 block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; 1357 block[0x7e] = valid_extensions; 1358 new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1359 if (!new) 1360 goto out; 1361 block = new; 1362 } 1363 1364 return (struct edid *)block; 1365 1366 carp: 1367 if (print_bad_edid) { 1368 dev_warn(connector->dev->dev, "%s: EDID block %d invalid.\n", 1369 connector->name, j); 1370 } 1371 connector->bad_edid_counter++; 1372 1373 out: 1374 kfree(block); 1375 return NULL; 1376 } 1377 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1378 1379 /** 1380 * drm_probe_ddc() - probe DDC presence 1381 * @adapter: I2C adapter to probe 1382 * 1383 * Return: True on success, false on failure. 1384 */ 1385 bool 1386 drm_probe_ddc(struct i2c_adapter *adapter) 1387 { 1388 unsigned char out; 1389 1390 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1391 } 1392 EXPORT_SYMBOL(drm_probe_ddc); 1393 1394 /** 1395 * drm_get_edid - get EDID data, if available 1396 * @connector: connector we're probing 1397 * @adapter: I2C adapter to use for DDC 1398 * 1399 * Poke the given I2C channel to grab EDID data if possible. If found, 1400 * attach it to the connector. 1401 * 1402 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1403 */ 1404 struct edid *drm_get_edid(struct drm_connector *connector, 1405 struct i2c_adapter *adapter) 1406 { 1407 struct edid *edid; 1408 1409 if (!drm_probe_ddc(adapter)) 1410 return NULL; 1411 1412 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 1413 if (edid) 1414 drm_get_displayid(connector, edid); 1415 return edid; 1416 } 1417 EXPORT_SYMBOL(drm_get_edid); 1418 1419 /** 1420 * drm_edid_duplicate - duplicate an EDID and the extensions 1421 * @edid: EDID to duplicate 1422 * 1423 * Return: Pointer to duplicated EDID or NULL on allocation failure. 1424 */ 1425 struct edid *drm_edid_duplicate(const struct edid *edid) 1426 { 1427 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1428 } 1429 EXPORT_SYMBOL(drm_edid_duplicate); 1430 1431 /*** EDID parsing ***/ 1432 1433 /** 1434 * edid_vendor - match a string against EDID's obfuscated vendor field 1435 * @edid: EDID to match 1436 * @vendor: vendor string 1437 * 1438 * Returns true if @vendor is in @edid, false otherwise 1439 */ 1440 static bool edid_vendor(struct edid *edid, char *vendor) 1441 { 1442 char edid_vendor[3]; 1443 1444 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 1445 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 1446 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 1447 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 1448 1449 return !strncmp(edid_vendor, vendor, 3); 1450 } 1451 1452 /** 1453 * edid_get_quirks - return quirk flags for a given EDID 1454 * @edid: EDID to process 1455 * 1456 * This tells subsequent routines what fixes they need to apply. 1457 */ 1458 static u32 edid_get_quirks(struct edid *edid) 1459 { 1460 struct edid_quirk *quirk; 1461 int i; 1462 1463 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 1464 quirk = &edid_quirk_list[i]; 1465 1466 if (edid_vendor(edid, quirk->vendor) && 1467 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 1468 return quirk->quirks; 1469 } 1470 1471 return 0; 1472 } 1473 1474 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 1475 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 1476 1477 /** 1478 * edid_fixup_preferred - set preferred modes based on quirk list 1479 * @connector: has mode list to fix up 1480 * @quirks: quirks list 1481 * 1482 * Walk the mode list for @connector, clearing the preferred status 1483 * on existing modes and setting it anew for the right mode ala @quirks. 1484 */ 1485 static void edid_fixup_preferred(struct drm_connector *connector, 1486 u32 quirks) 1487 { 1488 struct drm_display_mode *t, *cur_mode, *preferred_mode; 1489 int target_refresh = 0; 1490 int cur_vrefresh, preferred_vrefresh; 1491 1492 if (list_empty(&connector->probed_modes)) 1493 return; 1494 1495 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 1496 target_refresh = 60; 1497 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 1498 target_refresh = 75; 1499 1500 preferred_mode = list_first_entry(&connector->probed_modes, 1501 struct drm_display_mode, head); 1502 1503 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 1504 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 1505 1506 if (cur_mode == preferred_mode) 1507 continue; 1508 1509 /* Largest mode is preferred */ 1510 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 1511 preferred_mode = cur_mode; 1512 1513 cur_vrefresh = cur_mode->vrefresh ? 1514 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 1515 preferred_vrefresh = preferred_mode->vrefresh ? 1516 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 1517 /* At a given size, try to get closest to target refresh */ 1518 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 1519 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 1520 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 1521 preferred_mode = cur_mode; 1522 } 1523 } 1524 1525 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 1526 } 1527 1528 static bool 1529 mode_is_rb(const struct drm_display_mode *mode) 1530 { 1531 return (mode->htotal - mode->hdisplay == 160) && 1532 (mode->hsync_end - mode->hdisplay == 80) && 1533 (mode->hsync_end - mode->hsync_start == 32) && 1534 (mode->vsync_start - mode->vdisplay == 3); 1535 } 1536 1537 /* 1538 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 1539 * @dev: Device to duplicate against 1540 * @hsize: Mode width 1541 * @vsize: Mode height 1542 * @fresh: Mode refresh rate 1543 * @rb: Mode reduced-blanking-ness 1544 * 1545 * Walk the DMT mode list looking for a match for the given parameters. 1546 * 1547 * Return: A newly allocated copy of the mode, or NULL if not found. 1548 */ 1549 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 1550 int hsize, int vsize, int fresh, 1551 bool rb) 1552 { 1553 int i; 1554 1555 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 1556 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 1557 if (hsize != ptr->hdisplay) 1558 continue; 1559 if (vsize != ptr->vdisplay) 1560 continue; 1561 if (fresh != drm_mode_vrefresh(ptr)) 1562 continue; 1563 if (rb != mode_is_rb(ptr)) 1564 continue; 1565 1566 return drm_mode_duplicate(dev, ptr); 1567 } 1568 1569 return NULL; 1570 } 1571 EXPORT_SYMBOL(drm_mode_find_dmt); 1572 1573 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 1574 1575 static void 1576 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1577 { 1578 int i, n = 0; 1579 u8 d = ext[0x02]; 1580 u8 *det_base = ext + d; 1581 1582 n = (127 - d) / 18; 1583 for (i = 0; i < n; i++) 1584 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1585 } 1586 1587 static void 1588 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 1589 { 1590 unsigned int i, n = min((int)ext[0x02], 6); 1591 u8 *det_base = ext + 5; 1592 1593 if (ext[0x01] != 1) 1594 return; /* unknown version */ 1595 1596 for (i = 0; i < n; i++) 1597 cb((struct detailed_timing *)(det_base + 18 * i), closure); 1598 } 1599 1600 static void 1601 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 1602 { 1603 int i; 1604 struct edid *edid = (struct edid *)raw_edid; 1605 1606 if (edid == NULL) 1607 return; 1608 1609 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 1610 cb(&(edid->detailed_timings[i]), closure); 1611 1612 for (i = 1; i <= raw_edid[0x7e]; i++) { 1613 u8 *ext = raw_edid + (i * EDID_LENGTH); 1614 switch (*ext) { 1615 case CEA_EXT: 1616 cea_for_each_detailed_block(ext, cb, closure); 1617 break; 1618 case VTB_EXT: 1619 vtb_for_each_detailed_block(ext, cb, closure); 1620 break; 1621 default: 1622 break; 1623 } 1624 } 1625 } 1626 1627 static void 1628 is_rb(struct detailed_timing *t, void *data) 1629 { 1630 u8 *r = (u8 *)t; 1631 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 1632 if (r[15] & 0x10) 1633 *(bool *)data = true; 1634 } 1635 1636 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 1637 static bool 1638 drm_monitor_supports_rb(struct edid *edid) 1639 { 1640 if (edid->revision >= 4) { 1641 bool ret = false; 1642 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 1643 return ret; 1644 } 1645 1646 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 1647 } 1648 1649 static void 1650 find_gtf2(struct detailed_timing *t, void *data) 1651 { 1652 u8 *r = (u8 *)t; 1653 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 1654 *(u8 **)data = r; 1655 } 1656 1657 /* Secondary GTF curve kicks in above some break frequency */ 1658 static int 1659 drm_gtf2_hbreak(struct edid *edid) 1660 { 1661 u8 *r = NULL; 1662 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1663 return r ? (r[12] * 2) : 0; 1664 } 1665 1666 static int 1667 drm_gtf2_2c(struct edid *edid) 1668 { 1669 u8 *r = NULL; 1670 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1671 return r ? r[13] : 0; 1672 } 1673 1674 static int 1675 drm_gtf2_m(struct edid *edid) 1676 { 1677 u8 *r = NULL; 1678 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1679 return r ? (r[15] << 8) + r[14] : 0; 1680 } 1681 1682 static int 1683 drm_gtf2_k(struct edid *edid) 1684 { 1685 u8 *r = NULL; 1686 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1687 return r ? r[16] : 0; 1688 } 1689 1690 static int 1691 drm_gtf2_2j(struct edid *edid) 1692 { 1693 u8 *r = NULL; 1694 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 1695 return r ? r[17] : 0; 1696 } 1697 1698 /** 1699 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 1700 * @edid: EDID block to scan 1701 */ 1702 static int standard_timing_level(struct edid *edid) 1703 { 1704 if (edid->revision >= 2) { 1705 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 1706 return LEVEL_CVT; 1707 if (drm_gtf2_hbreak(edid)) 1708 return LEVEL_GTF2; 1709 return LEVEL_GTF; 1710 } 1711 return LEVEL_DMT; 1712 } 1713 1714 /* 1715 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 1716 * monitors fill with ascii space (0x20) instead. 1717 */ 1718 static int 1719 bad_std_timing(u8 a, u8 b) 1720 { 1721 return (a == 0x00 && b == 0x00) || 1722 (a == 0x01 && b == 0x01) || 1723 (a == 0x20 && b == 0x20); 1724 } 1725 1726 /** 1727 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 1728 * @connector: connector of for the EDID block 1729 * @edid: EDID block to scan 1730 * @t: standard timing params 1731 * 1732 * Take the standard timing params (in this case width, aspect, and refresh) 1733 * and convert them into a real mode using CVT/GTF/DMT. 1734 */ 1735 static struct drm_display_mode * 1736 drm_mode_std(struct drm_connector *connector, struct edid *edid, 1737 struct std_timing *t) 1738 { 1739 struct drm_device *dev = connector->dev; 1740 struct drm_display_mode *m, *mode = NULL; 1741 int hsize, vsize; 1742 int vrefresh_rate; 1743 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 1744 >> EDID_TIMING_ASPECT_SHIFT; 1745 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 1746 >> EDID_TIMING_VFREQ_SHIFT; 1747 int timing_level = standard_timing_level(edid); 1748 1749 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 1750 return NULL; 1751 1752 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 1753 hsize = t->hsize * 8 + 248; 1754 /* vrefresh_rate = vfreq + 60 */ 1755 vrefresh_rate = vfreq + 60; 1756 /* the vdisplay is calculated based on the aspect ratio */ 1757 if (aspect_ratio == 0) { 1758 if (edid->revision < 3) 1759 vsize = hsize; 1760 else 1761 vsize = (hsize * 10) / 16; 1762 } else if (aspect_ratio == 1) 1763 vsize = (hsize * 3) / 4; 1764 else if (aspect_ratio == 2) 1765 vsize = (hsize * 4) / 5; 1766 else 1767 vsize = (hsize * 9) / 16; 1768 1769 /* HDTV hack, part 1 */ 1770 if (vrefresh_rate == 60 && 1771 ((hsize == 1360 && vsize == 765) || 1772 (hsize == 1368 && vsize == 769))) { 1773 hsize = 1366; 1774 vsize = 768; 1775 } 1776 1777 /* 1778 * If this connector already has a mode for this size and refresh 1779 * rate (because it came from detailed or CVT info), use that 1780 * instead. This way we don't have to guess at interlace or 1781 * reduced blanking. 1782 */ 1783 list_for_each_entry(m, &connector->probed_modes, head) 1784 if (m->hdisplay == hsize && m->vdisplay == vsize && 1785 drm_mode_vrefresh(m) == vrefresh_rate) 1786 return NULL; 1787 1788 /* HDTV hack, part 2 */ 1789 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 1790 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 1791 false); 1792 mode->hdisplay = 1366; 1793 mode->hsync_start = mode->hsync_start - 1; 1794 mode->hsync_end = mode->hsync_end - 1; 1795 return mode; 1796 } 1797 1798 /* check whether it can be found in default mode table */ 1799 if (drm_monitor_supports_rb(edid)) { 1800 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 1801 true); 1802 if (mode) 1803 return mode; 1804 } 1805 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 1806 if (mode) 1807 return mode; 1808 1809 /* okay, generate it */ 1810 switch (timing_level) { 1811 case LEVEL_DMT: 1812 break; 1813 case LEVEL_GTF: 1814 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1815 break; 1816 case LEVEL_GTF2: 1817 /* 1818 * This is potentially wrong if there's ever a monitor with 1819 * more than one ranges section, each claiming a different 1820 * secondary GTF curve. Please don't do that. 1821 */ 1822 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 1823 if (!mode) 1824 return NULL; 1825 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 1826 drm_mode_destroy(dev, mode); 1827 mode = drm_gtf_mode_complex(dev, hsize, vsize, 1828 vrefresh_rate, 0, 0, 1829 drm_gtf2_m(edid), 1830 drm_gtf2_2c(edid), 1831 drm_gtf2_k(edid), 1832 drm_gtf2_2j(edid)); 1833 } 1834 break; 1835 case LEVEL_CVT: 1836 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 1837 false); 1838 break; 1839 } 1840 return mode; 1841 } 1842 1843 /* 1844 * EDID is delightfully ambiguous about how interlaced modes are to be 1845 * encoded. Our internal representation is of frame height, but some 1846 * HDTV detailed timings are encoded as field height. 1847 * 1848 * The format list here is from CEA, in frame size. Technically we 1849 * should be checking refresh rate too. Whatever. 1850 */ 1851 static void 1852 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 1853 struct detailed_pixel_timing *pt) 1854 { 1855 int i; 1856 static const struct { 1857 int w, h; 1858 } cea_interlaced[] = { 1859 { 1920, 1080 }, 1860 { 720, 480 }, 1861 { 1440, 480 }, 1862 { 2880, 480 }, 1863 { 720, 576 }, 1864 { 1440, 576 }, 1865 { 2880, 576 }, 1866 }; 1867 1868 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 1869 return; 1870 1871 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 1872 if ((mode->hdisplay == cea_interlaced[i].w) && 1873 (mode->vdisplay == cea_interlaced[i].h / 2)) { 1874 mode->vdisplay *= 2; 1875 mode->vsync_start *= 2; 1876 mode->vsync_end *= 2; 1877 mode->vtotal *= 2; 1878 mode->vtotal |= 1; 1879 } 1880 } 1881 1882 mode->flags |= DRM_MODE_FLAG_INTERLACE; 1883 } 1884 1885 /** 1886 * drm_mode_detailed - create a new mode from an EDID detailed timing section 1887 * @dev: DRM device (needed to create new mode) 1888 * @edid: EDID block 1889 * @timing: EDID detailed timing info 1890 * @quirks: quirks to apply 1891 * 1892 * An EDID detailed timing block contains enough info for us to create and 1893 * return a new struct drm_display_mode. 1894 */ 1895 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 1896 struct edid *edid, 1897 struct detailed_timing *timing, 1898 u32 quirks) 1899 { 1900 struct drm_display_mode *mode; 1901 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 1902 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 1903 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 1904 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 1905 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 1906 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 1907 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 1908 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 1909 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 1910 1911 /* ignore tiny modes */ 1912 if (hactive < 64 || vactive < 64) 1913 return NULL; 1914 1915 if (pt->misc & DRM_EDID_PT_STEREO) { 1916 DRM_DEBUG_KMS("stereo mode not supported\n"); 1917 return NULL; 1918 } 1919 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 1920 DRM_DEBUG_KMS("composite sync not supported\n"); 1921 } 1922 1923 /* it is incorrect if hsync/vsync width is zero */ 1924 if (!hsync_pulse_width || !vsync_pulse_width) { 1925 DRM_DEBUG_KMS("Incorrect Detailed timing. " 1926 "Wrong Hsync/Vsync pulse width\n"); 1927 return NULL; 1928 } 1929 1930 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 1931 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 1932 if (!mode) 1933 return NULL; 1934 1935 goto set_size; 1936 } 1937 1938 mode = drm_mode_create(dev); 1939 if (!mode) 1940 return NULL; 1941 1942 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 1943 timing->pixel_clock = cpu_to_le16(1088); 1944 1945 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 1946 1947 mode->hdisplay = hactive; 1948 mode->hsync_start = mode->hdisplay + hsync_offset; 1949 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 1950 mode->htotal = mode->hdisplay + hblank; 1951 1952 mode->vdisplay = vactive; 1953 mode->vsync_start = mode->vdisplay + vsync_offset; 1954 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 1955 mode->vtotal = mode->vdisplay + vblank; 1956 1957 /* Some EDIDs have bogus h/vtotal values */ 1958 if (mode->hsync_end > mode->htotal) 1959 mode->htotal = mode->hsync_end + 1; 1960 if (mode->vsync_end > mode->vtotal) 1961 mode->vtotal = mode->vsync_end + 1; 1962 1963 drm_mode_do_interlace_quirk(mode, pt); 1964 1965 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 1966 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 1967 } 1968 1969 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 1970 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 1971 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 1972 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 1973 1974 set_size: 1975 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 1976 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 1977 1978 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 1979 mode->width_mm *= 10; 1980 mode->height_mm *= 10; 1981 } 1982 1983 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 1984 mode->width_mm = edid->width_cm * 10; 1985 mode->height_mm = edid->height_cm * 10; 1986 } 1987 1988 mode->type = DRM_MODE_TYPE_DRIVER; 1989 mode->vrefresh = drm_mode_vrefresh(mode); 1990 drm_mode_set_name(mode); 1991 1992 return mode; 1993 } 1994 1995 static bool 1996 mode_in_hsync_range(const struct drm_display_mode *mode, 1997 struct edid *edid, u8 *t) 1998 { 1999 int hsync, hmin, hmax; 2000 2001 hmin = t[7]; 2002 if (edid->revision >= 4) 2003 hmin += ((t[4] & 0x04) ? 255 : 0); 2004 hmax = t[8]; 2005 if (edid->revision >= 4) 2006 hmax += ((t[4] & 0x08) ? 255 : 0); 2007 hsync = drm_mode_hsync(mode); 2008 2009 return (hsync <= hmax && hsync >= hmin); 2010 } 2011 2012 static bool 2013 mode_in_vsync_range(const struct drm_display_mode *mode, 2014 struct edid *edid, u8 *t) 2015 { 2016 int vsync, vmin, vmax; 2017 2018 vmin = t[5]; 2019 if (edid->revision >= 4) 2020 vmin += ((t[4] & 0x01) ? 255 : 0); 2021 vmax = t[6]; 2022 if (edid->revision >= 4) 2023 vmax += ((t[4] & 0x02) ? 255 : 0); 2024 vsync = drm_mode_vrefresh(mode); 2025 2026 return (vsync <= vmax && vsync >= vmin); 2027 } 2028 2029 static u32 2030 range_pixel_clock(struct edid *edid, u8 *t) 2031 { 2032 /* unspecified */ 2033 if (t[9] == 0 || t[9] == 255) 2034 return 0; 2035 2036 /* 1.4 with CVT support gives us real precision, yay */ 2037 if (edid->revision >= 4 && t[10] == 0x04) 2038 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2039 2040 /* 1.3 is pathetic, so fuzz up a bit */ 2041 return t[9] * 10000 + 5001; 2042 } 2043 2044 static bool 2045 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2046 struct detailed_timing *timing) 2047 { 2048 u32 max_clock; 2049 u8 *t = (u8 *)timing; 2050 2051 if (!mode_in_hsync_range(mode, edid, t)) 2052 return false; 2053 2054 if (!mode_in_vsync_range(mode, edid, t)) 2055 return false; 2056 2057 if ((max_clock = range_pixel_clock(edid, t))) 2058 if (mode->clock > max_clock) 2059 return false; 2060 2061 /* 1.4 max horizontal check */ 2062 if (edid->revision >= 4 && t[10] == 0x04) 2063 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2064 return false; 2065 2066 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2067 return false; 2068 2069 return true; 2070 } 2071 2072 static bool valid_inferred_mode(const struct drm_connector *connector, 2073 const struct drm_display_mode *mode) 2074 { 2075 const struct drm_display_mode *m; 2076 bool ok = false; 2077 2078 list_for_each_entry(m, &connector->probed_modes, head) { 2079 if (mode->hdisplay == m->hdisplay && 2080 mode->vdisplay == m->vdisplay && 2081 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2082 return false; /* duplicated */ 2083 if (mode->hdisplay <= m->hdisplay && 2084 mode->vdisplay <= m->vdisplay) 2085 ok = true; 2086 } 2087 return ok; 2088 } 2089 2090 static int 2091 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2092 struct detailed_timing *timing) 2093 { 2094 int i, modes = 0; 2095 struct drm_display_mode *newmode; 2096 struct drm_device *dev = connector->dev; 2097 2098 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2099 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2100 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2101 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2102 if (newmode) { 2103 drm_mode_probed_add(connector, newmode); 2104 modes++; 2105 } 2106 } 2107 } 2108 2109 return modes; 2110 } 2111 2112 /* fix up 1366x768 mode from 1368x768; 2113 * GFT/CVT can't express 1366 width which isn't dividable by 8 2114 */ 2115 static void fixup_mode_1366x768(struct drm_display_mode *mode) 2116 { 2117 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2118 mode->hdisplay = 1366; 2119 mode->hsync_start--; 2120 mode->hsync_end--; 2121 drm_mode_set_name(mode); 2122 } 2123 } 2124 2125 static int 2126 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2127 struct detailed_timing *timing) 2128 { 2129 int i, modes = 0; 2130 struct drm_display_mode *newmode; 2131 struct drm_device *dev = connector->dev; 2132 2133 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2134 const struct minimode *m = &extra_modes[i]; 2135 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2136 if (!newmode) 2137 return modes; 2138 2139 fixup_mode_1366x768(newmode); 2140 if (!mode_in_range(newmode, edid, timing) || 2141 !valid_inferred_mode(connector, newmode)) { 2142 drm_mode_destroy(dev, newmode); 2143 continue; 2144 } 2145 2146 drm_mode_probed_add(connector, newmode); 2147 modes++; 2148 } 2149 2150 return modes; 2151 } 2152 2153 static int 2154 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2155 struct detailed_timing *timing) 2156 { 2157 int i, modes = 0; 2158 struct drm_display_mode *newmode; 2159 struct drm_device *dev = connector->dev; 2160 bool rb = drm_monitor_supports_rb(edid); 2161 2162 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2163 const struct minimode *m = &extra_modes[i]; 2164 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2165 if (!newmode) 2166 return modes; 2167 2168 fixup_mode_1366x768(newmode); 2169 if (!mode_in_range(newmode, edid, timing) || 2170 !valid_inferred_mode(connector, newmode)) { 2171 drm_mode_destroy(dev, newmode); 2172 continue; 2173 } 2174 2175 drm_mode_probed_add(connector, newmode); 2176 modes++; 2177 } 2178 2179 return modes; 2180 } 2181 2182 static void 2183 do_inferred_modes(struct detailed_timing *timing, void *c) 2184 { 2185 struct detailed_mode_closure *closure = c; 2186 struct detailed_non_pixel *data = &timing->data.other_data; 2187 struct detailed_data_monitor_range *range = &data->data.range; 2188 2189 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2190 return; 2191 2192 closure->modes += drm_dmt_modes_for_range(closure->connector, 2193 closure->edid, 2194 timing); 2195 2196 if (!version_greater(closure->edid, 1, 1)) 2197 return; /* GTF not defined yet */ 2198 2199 switch (range->flags) { 2200 case 0x02: /* secondary gtf, XXX could do more */ 2201 case 0x00: /* default gtf */ 2202 closure->modes += drm_gtf_modes_for_range(closure->connector, 2203 closure->edid, 2204 timing); 2205 break; 2206 case 0x04: /* cvt, only in 1.4+ */ 2207 if (!version_greater(closure->edid, 1, 3)) 2208 break; 2209 2210 closure->modes += drm_cvt_modes_for_range(closure->connector, 2211 closure->edid, 2212 timing); 2213 break; 2214 case 0x01: /* just the ranges, no formula */ 2215 default: 2216 break; 2217 } 2218 } 2219 2220 static int 2221 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2222 { 2223 struct detailed_mode_closure closure = { 2224 .connector = connector, 2225 .edid = edid, 2226 }; 2227 2228 if (version_greater(edid, 1, 0)) 2229 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2230 &closure); 2231 2232 return closure.modes; 2233 } 2234 2235 static int 2236 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2237 { 2238 int i, j, m, modes = 0; 2239 struct drm_display_mode *mode; 2240 u8 *est = ((u8 *)timing) + 5; 2241 2242 for (i = 0; i < 6; i++) { 2243 for (j = 7; j >= 0; j--) { 2244 m = (i * 8) + (7 - j); 2245 if (m >= ARRAY_SIZE(est3_modes)) 2246 break; 2247 if (est[i] & (1 << j)) { 2248 mode = drm_mode_find_dmt(connector->dev, 2249 est3_modes[m].w, 2250 est3_modes[m].h, 2251 est3_modes[m].r, 2252 est3_modes[m].rb); 2253 if (mode) { 2254 drm_mode_probed_add(connector, mode); 2255 modes++; 2256 } 2257 } 2258 } 2259 } 2260 2261 return modes; 2262 } 2263 2264 static void 2265 do_established_modes(struct detailed_timing *timing, void *c) 2266 { 2267 struct detailed_mode_closure *closure = c; 2268 struct detailed_non_pixel *data = &timing->data.other_data; 2269 2270 if (data->type == EDID_DETAIL_EST_TIMINGS) 2271 closure->modes += drm_est3_modes(closure->connector, timing); 2272 } 2273 2274 /** 2275 * add_established_modes - get est. modes from EDID and add them 2276 * @connector: connector to add mode(s) to 2277 * @edid: EDID block to scan 2278 * 2279 * Each EDID block contains a bitmap of the supported "established modes" list 2280 * (defined above). Tease them out and add them to the global modes list. 2281 */ 2282 static int 2283 add_established_modes(struct drm_connector *connector, struct edid *edid) 2284 { 2285 struct drm_device *dev = connector->dev; 2286 unsigned long est_bits = edid->established_timings.t1 | 2287 (edid->established_timings.t2 << 8) | 2288 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2289 int i, modes = 0; 2290 struct detailed_mode_closure closure = { 2291 .connector = connector, 2292 .edid = edid, 2293 }; 2294 2295 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2296 if (est_bits & (1<<i)) { 2297 struct drm_display_mode *newmode; 2298 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2299 if (newmode) { 2300 drm_mode_probed_add(connector, newmode); 2301 modes++; 2302 } 2303 } 2304 } 2305 2306 if (version_greater(edid, 1, 0)) 2307 drm_for_each_detailed_block((u8 *)edid, 2308 do_established_modes, &closure); 2309 2310 return modes + closure.modes; 2311 } 2312 2313 static void 2314 do_standard_modes(struct detailed_timing *timing, void *c) 2315 { 2316 struct detailed_mode_closure *closure = c; 2317 struct detailed_non_pixel *data = &timing->data.other_data; 2318 struct drm_connector *connector = closure->connector; 2319 struct edid *edid = closure->edid; 2320 2321 if (data->type == EDID_DETAIL_STD_MODES) { 2322 int i; 2323 for (i = 0; i < 6; i++) { 2324 struct std_timing *std; 2325 struct drm_display_mode *newmode; 2326 2327 std = &data->data.timings[i]; 2328 newmode = drm_mode_std(connector, edid, std); 2329 if (newmode) { 2330 drm_mode_probed_add(connector, newmode); 2331 closure->modes++; 2332 } 2333 } 2334 } 2335 } 2336 2337 /** 2338 * add_standard_modes - get std. modes from EDID and add them 2339 * @connector: connector to add mode(s) to 2340 * @edid: EDID block to scan 2341 * 2342 * Standard modes can be calculated using the appropriate standard (DMT, 2343 * GTF or CVT. Grab them from @edid and add them to the list. 2344 */ 2345 static int 2346 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2347 { 2348 int i, modes = 0; 2349 struct detailed_mode_closure closure = { 2350 .connector = connector, 2351 .edid = edid, 2352 }; 2353 2354 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2355 struct drm_display_mode *newmode; 2356 2357 newmode = drm_mode_std(connector, edid, 2358 &edid->standard_timings[i]); 2359 if (newmode) { 2360 drm_mode_probed_add(connector, newmode); 2361 modes++; 2362 } 2363 } 2364 2365 if (version_greater(edid, 1, 0)) 2366 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 2367 &closure); 2368 2369 /* XXX should also look for standard codes in VTB blocks */ 2370 2371 return modes + closure.modes; 2372 } 2373 2374 static int drm_cvt_modes(struct drm_connector *connector, 2375 struct detailed_timing *timing) 2376 { 2377 int i, j, modes = 0; 2378 struct drm_display_mode *newmode; 2379 struct drm_device *dev = connector->dev; 2380 struct cvt_timing *cvt; 2381 const int rates[] = { 60, 85, 75, 60, 50 }; 2382 const u8 empty[3] = { 0, 0, 0 }; 2383 2384 for (i = 0; i < 4; i++) { 2385 int uninitialized_var(width), height; 2386 cvt = &(timing->data.other_data.data.cvt[i]); 2387 2388 if (!memcmp(cvt->code, empty, 3)) 2389 continue; 2390 2391 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 2392 switch (cvt->code[1] & 0x0c) { 2393 case 0x00: 2394 width = height * 4 / 3; 2395 break; 2396 case 0x04: 2397 width = height * 16 / 9; 2398 break; 2399 case 0x08: 2400 width = height * 16 / 10; 2401 break; 2402 case 0x0c: 2403 width = height * 15 / 9; 2404 break; 2405 } 2406 2407 for (j = 1; j < 5; j++) { 2408 if (cvt->code[2] & (1 << j)) { 2409 newmode = drm_cvt_mode(dev, width, height, 2410 rates[j], j == 0, 2411 false, false); 2412 if (newmode) { 2413 drm_mode_probed_add(connector, newmode); 2414 modes++; 2415 } 2416 } 2417 } 2418 } 2419 2420 return modes; 2421 } 2422 2423 static void 2424 do_cvt_mode(struct detailed_timing *timing, void *c) 2425 { 2426 struct detailed_mode_closure *closure = c; 2427 struct detailed_non_pixel *data = &timing->data.other_data; 2428 2429 if (data->type == EDID_DETAIL_CVT_3BYTE) 2430 closure->modes += drm_cvt_modes(closure->connector, timing); 2431 } 2432 2433 static int 2434 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 2435 { 2436 struct detailed_mode_closure closure = { 2437 .connector = connector, 2438 .edid = edid, 2439 }; 2440 2441 if (version_greater(edid, 1, 2)) 2442 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 2443 2444 /* XXX should also look for CVT codes in VTB blocks */ 2445 2446 return closure.modes; 2447 } 2448 2449 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 2450 2451 static void 2452 do_detailed_mode(struct detailed_timing *timing, void *c) 2453 { 2454 struct detailed_mode_closure *closure = c; 2455 struct drm_display_mode *newmode; 2456 2457 if (timing->pixel_clock) { 2458 newmode = drm_mode_detailed(closure->connector->dev, 2459 closure->edid, timing, 2460 closure->quirks); 2461 if (!newmode) 2462 return; 2463 2464 if (closure->preferred) 2465 newmode->type |= DRM_MODE_TYPE_PREFERRED; 2466 2467 /* 2468 * Detailed modes are limited to 10kHz pixel clock resolution, 2469 * so fix up anything that looks like CEA/HDMI mode, but the clock 2470 * is just slightly off. 2471 */ 2472 fixup_detailed_cea_mode_clock(newmode); 2473 2474 drm_mode_probed_add(closure->connector, newmode); 2475 closure->modes++; 2476 closure->preferred = 0; 2477 } 2478 } 2479 2480 /* 2481 * add_detailed_modes - Add modes from detailed timings 2482 * @connector: attached connector 2483 * @edid: EDID block to scan 2484 * @quirks: quirks to apply 2485 */ 2486 static int 2487 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 2488 u32 quirks) 2489 { 2490 struct detailed_mode_closure closure = { 2491 .connector = connector, 2492 .edid = edid, 2493 .preferred = 1, 2494 .quirks = quirks, 2495 }; 2496 2497 if (closure.preferred && !version_greater(edid, 1, 3)) 2498 closure.preferred = 2499 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 2500 2501 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 2502 2503 return closure.modes; 2504 } 2505 2506 #define AUDIO_BLOCK 0x01 2507 #define VIDEO_BLOCK 0x02 2508 #define VENDOR_BLOCK 0x03 2509 #define SPEAKER_BLOCK 0x04 2510 #define VIDEO_CAPABILITY_BLOCK 0x07 2511 #define EDID_BASIC_AUDIO (1 << 6) 2512 #define EDID_CEA_YCRCB444 (1 << 5) 2513 #define EDID_CEA_YCRCB422 (1 << 4) 2514 #define EDID_CEA_VCDB_QS (1 << 6) 2515 2516 /* 2517 * Search EDID for CEA extension block. 2518 */ 2519 static u8 *drm_find_edid_extension(struct edid *edid, int ext_id) 2520 { 2521 u8 *edid_ext = NULL; 2522 int i; 2523 2524 /* No EDID or EDID extensions */ 2525 if (edid == NULL || edid->extensions == 0) 2526 return NULL; 2527 2528 /* Find CEA extension */ 2529 for (i = 0; i < edid->extensions; i++) { 2530 edid_ext = (u8 *)edid + EDID_LENGTH * (i + 1); 2531 if (edid_ext[0] == ext_id) 2532 break; 2533 } 2534 2535 if (i == edid->extensions) 2536 return NULL; 2537 2538 return edid_ext; 2539 } 2540 2541 static u8 *drm_find_cea_extension(struct edid *edid) 2542 { 2543 return drm_find_edid_extension(edid, CEA_EXT); 2544 } 2545 2546 static u8 *drm_find_displayid_extension(struct edid *edid) 2547 { 2548 return drm_find_edid_extension(edid, DISPLAYID_EXT); 2549 } 2550 2551 /* 2552 * Calculate the alternate clock for the CEA mode 2553 * (60Hz vs. 59.94Hz etc.) 2554 */ 2555 static unsigned int 2556 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 2557 { 2558 unsigned int clock = cea_mode->clock; 2559 2560 if (cea_mode->vrefresh % 6 != 0) 2561 return clock; 2562 2563 /* 2564 * edid_cea_modes contains the 59.94Hz 2565 * variant for 240 and 480 line modes, 2566 * and the 60Hz variant otherwise. 2567 */ 2568 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 2569 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 2570 else 2571 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 2572 2573 return clock; 2574 } 2575 2576 /** 2577 * drm_match_cea_mode - look for a CEA mode matching given mode 2578 * @to_match: display mode 2579 * 2580 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 2581 * mode. 2582 */ 2583 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 2584 { 2585 u8 mode; 2586 2587 if (!to_match->clock) 2588 return 0; 2589 2590 for (mode = 0; mode < ARRAY_SIZE(edid_cea_modes); mode++) { 2591 const struct drm_display_mode *cea_mode = &edid_cea_modes[mode]; 2592 unsigned int clock1, clock2; 2593 2594 /* Check both 60Hz and 59.94Hz */ 2595 clock1 = cea_mode->clock; 2596 clock2 = cea_mode_alternate_clock(cea_mode); 2597 2598 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2599 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2600 drm_mode_equal_no_clocks_no_stereo(to_match, cea_mode)) 2601 return mode + 1; 2602 } 2603 return 0; 2604 } 2605 EXPORT_SYMBOL(drm_match_cea_mode); 2606 2607 /** 2608 * drm_get_cea_aspect_ratio - get the picture aspect ratio corresponding to 2609 * the input VIC from the CEA mode list 2610 * @video_code: ID given to each of the CEA modes 2611 * 2612 * Returns picture aspect ratio 2613 */ 2614 enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 2615 { 2616 /* return picture aspect ratio for video_code - 1 to access the 2617 * right array element 2618 */ 2619 return edid_cea_modes[video_code-1].picture_aspect_ratio; 2620 } 2621 EXPORT_SYMBOL(drm_get_cea_aspect_ratio); 2622 2623 /* 2624 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 2625 * specific block). 2626 * 2627 * It's almost like cea_mode_alternate_clock(), we just need to add an 2628 * exception for the VIC 4 mode (4096x2160@24Hz): no alternate clock for this 2629 * one. 2630 */ 2631 static unsigned int 2632 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 2633 { 2634 if (hdmi_mode->vdisplay == 4096 && hdmi_mode->hdisplay == 2160) 2635 return hdmi_mode->clock; 2636 2637 return cea_mode_alternate_clock(hdmi_mode); 2638 } 2639 2640 /* 2641 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 2642 * @to_match: display mode 2643 * 2644 * An HDMI mode is one defined in the HDMI vendor specific block. 2645 * 2646 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 2647 */ 2648 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 2649 { 2650 u8 mode; 2651 2652 if (!to_match->clock) 2653 return 0; 2654 2655 for (mode = 0; mode < ARRAY_SIZE(edid_4k_modes); mode++) { 2656 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[mode]; 2657 unsigned int clock1, clock2; 2658 2659 /* Make sure to also match alternate clocks */ 2660 clock1 = hdmi_mode->clock; 2661 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 2662 2663 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 2664 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 2665 drm_mode_equal_no_clocks_no_stereo(to_match, hdmi_mode)) 2666 return mode + 1; 2667 } 2668 return 0; 2669 } 2670 2671 static int 2672 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 2673 { 2674 struct drm_device *dev = connector->dev; 2675 struct drm_display_mode *mode, *tmp; 2676 struct list_head list = LIST_HEAD_INIT(list); 2677 int modes = 0; 2678 2679 /* Don't add CEA modes if the CEA extension block is missing */ 2680 if (!drm_find_cea_extension(edid)) 2681 return 0; 2682 2683 /* 2684 * Go through all probed modes and create a new mode 2685 * with the alternate clock for certain CEA modes. 2686 */ 2687 list_for_each_entry(mode, &connector->probed_modes, head) { 2688 const struct drm_display_mode *cea_mode = NULL; 2689 struct drm_display_mode *newmode; 2690 u8 mode_idx = drm_match_cea_mode(mode) - 1; 2691 unsigned int clock1, clock2; 2692 2693 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 2694 cea_mode = &edid_cea_modes[mode_idx]; 2695 clock2 = cea_mode_alternate_clock(cea_mode); 2696 } else { 2697 mode_idx = drm_match_hdmi_mode(mode) - 1; 2698 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 2699 cea_mode = &edid_4k_modes[mode_idx]; 2700 clock2 = hdmi_mode_alternate_clock(cea_mode); 2701 } 2702 } 2703 2704 if (!cea_mode) 2705 continue; 2706 2707 clock1 = cea_mode->clock; 2708 2709 if (clock1 == clock2) 2710 continue; 2711 2712 if (mode->clock != clock1 && mode->clock != clock2) 2713 continue; 2714 2715 newmode = drm_mode_duplicate(dev, cea_mode); 2716 if (!newmode) 2717 continue; 2718 2719 /* Carry over the stereo flags */ 2720 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 2721 2722 /* 2723 * The current mode could be either variant. Make 2724 * sure to pick the "other" clock for the new mode. 2725 */ 2726 if (mode->clock != clock1) 2727 newmode->clock = clock1; 2728 else 2729 newmode->clock = clock2; 2730 2731 list_add_tail(&newmode->head, &list); 2732 } 2733 2734 list_for_each_entry_safe(mode, tmp, &list, head) { 2735 list_del(&mode->head); 2736 drm_mode_probed_add(connector, mode); 2737 modes++; 2738 } 2739 2740 return modes; 2741 } 2742 2743 static struct drm_display_mode * 2744 drm_display_mode_from_vic_index(struct drm_connector *connector, 2745 const u8 *video_db, u8 video_len, 2746 u8 video_index) 2747 { 2748 struct drm_device *dev = connector->dev; 2749 struct drm_display_mode *newmode; 2750 u8 cea_mode; 2751 2752 if (video_db == NULL || video_index >= video_len) 2753 return NULL; 2754 2755 /* CEA modes are numbered 1..127 */ 2756 cea_mode = (video_db[video_index] & 127) - 1; 2757 if (cea_mode >= ARRAY_SIZE(edid_cea_modes)) 2758 return NULL; 2759 2760 newmode = drm_mode_duplicate(dev, &edid_cea_modes[cea_mode]); 2761 if (!newmode) 2762 return NULL; 2763 2764 newmode->vrefresh = 0; 2765 2766 return newmode; 2767 } 2768 2769 static int 2770 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 2771 { 2772 int i, modes = 0; 2773 2774 for (i = 0; i < len; i++) { 2775 struct drm_display_mode *mode; 2776 mode = drm_display_mode_from_vic_index(connector, db, len, i); 2777 if (mode) { 2778 drm_mode_probed_add(connector, mode); 2779 modes++; 2780 } 2781 } 2782 2783 return modes; 2784 } 2785 2786 struct stereo_mandatory_mode { 2787 int width, height, vrefresh; 2788 unsigned int flags; 2789 }; 2790 2791 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 2792 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2793 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2794 { 1920, 1080, 50, 2795 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2796 { 1920, 1080, 60, 2797 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 2798 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2799 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 2800 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 2801 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 2802 }; 2803 2804 static bool 2805 stereo_match_mandatory(const struct drm_display_mode *mode, 2806 const struct stereo_mandatory_mode *stereo_mode) 2807 { 2808 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 2809 2810 return mode->hdisplay == stereo_mode->width && 2811 mode->vdisplay == stereo_mode->height && 2812 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 2813 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 2814 } 2815 2816 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 2817 { 2818 struct drm_device *dev = connector->dev; 2819 const struct drm_display_mode *mode; 2820 struct list_head stereo_modes; 2821 int modes = 0, i; 2822 2823 INIT_LIST_HEAD(&stereo_modes); 2824 2825 list_for_each_entry(mode, &connector->probed_modes, head) { 2826 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 2827 const struct stereo_mandatory_mode *mandatory; 2828 struct drm_display_mode *new_mode; 2829 2830 if (!stereo_match_mandatory(mode, 2831 &stereo_mandatory_modes[i])) 2832 continue; 2833 2834 mandatory = &stereo_mandatory_modes[i]; 2835 new_mode = drm_mode_duplicate(dev, mode); 2836 if (!new_mode) 2837 continue; 2838 2839 new_mode->flags |= mandatory->flags; 2840 list_add_tail(&new_mode->head, &stereo_modes); 2841 modes++; 2842 } 2843 } 2844 2845 list_splice_tail(&stereo_modes, &connector->probed_modes); 2846 2847 return modes; 2848 } 2849 2850 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 2851 { 2852 struct drm_device *dev = connector->dev; 2853 struct drm_display_mode *newmode; 2854 2855 vic--; /* VICs start at 1 */ 2856 if (vic >= ARRAY_SIZE(edid_4k_modes)) { 2857 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 2858 return 0; 2859 } 2860 2861 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 2862 if (!newmode) 2863 return 0; 2864 2865 drm_mode_probed_add(connector, newmode); 2866 2867 return 1; 2868 } 2869 2870 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 2871 const u8 *video_db, u8 video_len, u8 video_index) 2872 { 2873 struct drm_display_mode *newmode; 2874 int modes = 0; 2875 2876 if (structure & (1 << 0)) { 2877 newmode = drm_display_mode_from_vic_index(connector, video_db, 2878 video_len, 2879 video_index); 2880 if (newmode) { 2881 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 2882 drm_mode_probed_add(connector, newmode); 2883 modes++; 2884 } 2885 } 2886 if (structure & (1 << 6)) { 2887 newmode = drm_display_mode_from_vic_index(connector, video_db, 2888 video_len, 2889 video_index); 2890 if (newmode) { 2891 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 2892 drm_mode_probed_add(connector, newmode); 2893 modes++; 2894 } 2895 } 2896 if (structure & (1 << 8)) { 2897 newmode = drm_display_mode_from_vic_index(connector, video_db, 2898 video_len, 2899 video_index); 2900 if (newmode) { 2901 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 2902 drm_mode_probed_add(connector, newmode); 2903 modes++; 2904 } 2905 } 2906 2907 return modes; 2908 } 2909 2910 /* 2911 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 2912 * @connector: connector corresponding to the HDMI sink 2913 * @db: start of the CEA vendor specific block 2914 * @len: length of the CEA block payload, ie. one can access up to db[len] 2915 * 2916 * Parses the HDMI VSDB looking for modes to add to @connector. This function 2917 * also adds the stereo 3d modes when applicable. 2918 */ 2919 static int 2920 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 2921 const u8 *video_db, u8 video_len) 2922 { 2923 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 2924 u8 vic_len, hdmi_3d_len = 0; 2925 u16 mask; 2926 u16 structure_all; 2927 2928 if (len < 8) 2929 goto out; 2930 2931 /* no HDMI_Video_Present */ 2932 if (!(db[8] & (1 << 5))) 2933 goto out; 2934 2935 /* Latency_Fields_Present */ 2936 if (db[8] & (1 << 7)) 2937 offset += 2; 2938 2939 /* I_Latency_Fields_Present */ 2940 if (db[8] & (1 << 6)) 2941 offset += 2; 2942 2943 /* the declared length is not long enough for the 2 first bytes 2944 * of additional video format capabilities */ 2945 if (len < (8 + offset + 2)) 2946 goto out; 2947 2948 /* 3D_Present */ 2949 offset++; 2950 if (db[8 + offset] & (1 << 7)) { 2951 modes += add_hdmi_mandatory_stereo_modes(connector); 2952 2953 /* 3D_Multi_present */ 2954 multi_present = (db[8 + offset] & 0x60) >> 5; 2955 } 2956 2957 offset++; 2958 vic_len = db[8 + offset] >> 5; 2959 hdmi_3d_len = db[8 + offset] & 0x1f; 2960 2961 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 2962 u8 vic; 2963 2964 vic = db[9 + offset + i]; 2965 modes += add_hdmi_mode(connector, vic); 2966 } 2967 offset += 1 + vic_len; 2968 2969 if (multi_present == 1) 2970 multi_len = 2; 2971 else if (multi_present == 2) 2972 multi_len = 4; 2973 else 2974 multi_len = 0; 2975 2976 if (len < (8 + offset + hdmi_3d_len - 1)) 2977 goto out; 2978 2979 if (hdmi_3d_len < multi_len) 2980 goto out; 2981 2982 if (multi_present == 1 || multi_present == 2) { 2983 /* 3D_Structure_ALL */ 2984 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 2985 2986 /* check if 3D_MASK is present */ 2987 if (multi_present == 2) 2988 mask = (db[10 + offset] << 8) | db[11 + offset]; 2989 else 2990 mask = 0xffff; 2991 2992 for (i = 0; i < 16; i++) { 2993 if (mask & (1 << i)) 2994 modes += add_3d_struct_modes(connector, 2995 structure_all, 2996 video_db, 2997 video_len, i); 2998 } 2999 } 3000 3001 offset += multi_len; 3002 3003 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3004 int vic_index; 3005 struct drm_display_mode *newmode = NULL; 3006 unsigned int newflag = 0; 3007 bool detail_present; 3008 3009 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3010 3011 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3012 break; 3013 3014 /* 2D_VIC_order_X */ 3015 vic_index = db[8 + offset + i] >> 4; 3016 3017 /* 3D_Structure_X */ 3018 switch (db[8 + offset + i] & 0x0f) { 3019 case 0: 3020 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3021 break; 3022 case 6: 3023 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3024 break; 3025 case 8: 3026 /* 3D_Detail_X */ 3027 if ((db[9 + offset + i] >> 4) == 1) 3028 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3029 break; 3030 } 3031 3032 if (newflag != 0) { 3033 newmode = drm_display_mode_from_vic_index(connector, 3034 video_db, 3035 video_len, 3036 vic_index); 3037 3038 if (newmode) { 3039 newmode->flags |= newflag; 3040 drm_mode_probed_add(connector, newmode); 3041 modes++; 3042 } 3043 } 3044 3045 if (detail_present) 3046 i++; 3047 } 3048 3049 out: 3050 return modes; 3051 } 3052 3053 static int 3054 cea_db_payload_len(const u8 *db) 3055 { 3056 return db[0] & 0x1f; 3057 } 3058 3059 static int 3060 cea_db_tag(const u8 *db) 3061 { 3062 return db[0] >> 5; 3063 } 3064 3065 static int 3066 cea_revision(const u8 *cea) 3067 { 3068 return cea[1]; 3069 } 3070 3071 static int 3072 cea_db_offsets(const u8 *cea, int *start, int *end) 3073 { 3074 /* Data block offset in CEA extension block */ 3075 *start = 4; 3076 *end = cea[2]; 3077 if (*end == 0) 3078 *end = 127; 3079 if (*end < 4 || *end > 127) 3080 return -ERANGE; 3081 return 0; 3082 } 3083 3084 static bool cea_db_is_hdmi_vsdb(const u8 *db) 3085 { 3086 int hdmi_id; 3087 3088 if (cea_db_tag(db) != VENDOR_BLOCK) 3089 return false; 3090 3091 if (cea_db_payload_len(db) < 5) 3092 return false; 3093 3094 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 3095 3096 return hdmi_id == HDMI_IEEE_OUI; 3097 } 3098 3099 #define for_each_cea_db(cea, i, start, end) \ 3100 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 3101 3102 static int 3103 add_cea_modes(struct drm_connector *connector, struct edid *edid) 3104 { 3105 const u8 *cea = drm_find_cea_extension(edid); 3106 const u8 *db, *hdmi = NULL, *video = NULL; 3107 u8 dbl, hdmi_len, video_len = 0; 3108 int modes = 0; 3109 3110 if (cea && cea_revision(cea) >= 3) { 3111 int i, start, end; 3112 3113 if (cea_db_offsets(cea, &start, &end)) 3114 return 0; 3115 3116 for_each_cea_db(cea, i, start, end) { 3117 db = &cea[i]; 3118 dbl = cea_db_payload_len(db); 3119 3120 if (cea_db_tag(db) == VIDEO_BLOCK) { 3121 video = db + 1; 3122 video_len = dbl; 3123 modes += do_cea_modes(connector, video, dbl); 3124 } 3125 else if (cea_db_is_hdmi_vsdb(db)) { 3126 hdmi = db; 3127 hdmi_len = dbl; 3128 } 3129 } 3130 } 3131 3132 /* 3133 * We parse the HDMI VSDB after having added the cea modes as we will 3134 * be patching their flags when the sink supports stereo 3D. 3135 */ 3136 if (hdmi) 3137 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 3138 video_len); 3139 3140 return modes; 3141 } 3142 3143 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 3144 { 3145 const struct drm_display_mode *cea_mode; 3146 int clock1, clock2, clock; 3147 u8 mode_idx; 3148 const char *type; 3149 3150 mode_idx = drm_match_cea_mode(mode) - 1; 3151 if (mode_idx < ARRAY_SIZE(edid_cea_modes)) { 3152 type = "CEA"; 3153 cea_mode = &edid_cea_modes[mode_idx]; 3154 clock1 = cea_mode->clock; 3155 clock2 = cea_mode_alternate_clock(cea_mode); 3156 } else { 3157 mode_idx = drm_match_hdmi_mode(mode) - 1; 3158 if (mode_idx < ARRAY_SIZE(edid_4k_modes)) { 3159 type = "HDMI"; 3160 cea_mode = &edid_4k_modes[mode_idx]; 3161 clock1 = cea_mode->clock; 3162 clock2 = hdmi_mode_alternate_clock(cea_mode); 3163 } else { 3164 return; 3165 } 3166 } 3167 3168 /* pick whichever is closest */ 3169 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 3170 clock = clock1; 3171 else 3172 clock = clock2; 3173 3174 if (mode->clock == clock) 3175 return; 3176 3177 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 3178 type, mode_idx + 1, mode->clock, clock); 3179 mode->clock = clock; 3180 } 3181 3182 static void 3183 parse_hdmi_vsdb(struct drm_connector *connector, const u8 *db) 3184 { 3185 u8 len = cea_db_payload_len(db); 3186 3187 if (len >= 5) { 3188 connector->physical_address = (db[4] << 8) | db[5]; 3189 } 3190 if (len >= 6) { 3191 connector->eld[5] |= (db[6] >> 7) << 1; /* Supports_AI */ 3192 connector->dvi_dual = db[6] & 1; 3193 } 3194 if (len >= 7) 3195 connector->max_tmds_clock = db[7] * 5; 3196 if (len >= 8) { 3197 connector->latency_present[0] = db[8] >> 7; 3198 connector->latency_present[1] = (db[8] >> 6) & 1; 3199 } 3200 if (len >= 9) 3201 connector->video_latency[0] = db[9]; 3202 if (len >= 10) 3203 connector->audio_latency[0] = db[10]; 3204 if (len >= 11) 3205 connector->video_latency[1] = db[11]; 3206 if (len >= 12) 3207 connector->audio_latency[1] = db[12]; 3208 3209 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 3210 "max TMDS clock %d, " 3211 "latency present %d %d, " 3212 "video latency %d %d, " 3213 "audio latency %d %d\n", 3214 connector->dvi_dual, 3215 connector->max_tmds_clock, 3216 (int) connector->latency_present[0], 3217 (int) connector->latency_present[1], 3218 connector->video_latency[0], 3219 connector->video_latency[1], 3220 connector->audio_latency[0], 3221 connector->audio_latency[1]); 3222 } 3223 3224 static void 3225 monitor_name(struct detailed_timing *t, void *data) 3226 { 3227 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 3228 *(u8 **)data = t->data.other_data.data.str.str; 3229 } 3230 3231 /** 3232 * drm_edid_to_eld - build ELD from EDID 3233 * @connector: connector corresponding to the HDMI/DP sink 3234 * @edid: EDID to parse 3235 * 3236 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 3237 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 3238 */ 3239 void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 3240 { 3241 uint8_t *eld = connector->eld; 3242 u8 *cea; 3243 u8 *name; 3244 u8 *db; 3245 int sad_count = 0; 3246 int mnl; 3247 int dbl; 3248 3249 memset(eld, 0, sizeof(connector->eld)); 3250 3251 cea = drm_find_cea_extension(edid); 3252 if (!cea) { 3253 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 3254 return; 3255 } 3256 3257 name = NULL; 3258 drm_for_each_detailed_block((u8 *)edid, monitor_name, &name); 3259 for (mnl = 0; name && mnl < 13; mnl++) { 3260 if (name[mnl] == 0x0a) 3261 break; 3262 eld[20 + mnl] = name[mnl]; 3263 } 3264 eld[4] = (cea[1] << 5) | mnl; 3265 DRM_DEBUG_KMS("ELD monitor %s\n", eld + 20); 3266 3267 eld[0] = 2 << 3; /* ELD version: 2 */ 3268 3269 eld[16] = edid->mfg_id[0]; 3270 eld[17] = edid->mfg_id[1]; 3271 eld[18] = edid->prod_code[0]; 3272 eld[19] = edid->prod_code[1]; 3273 3274 if (cea_revision(cea) >= 3) { 3275 int i, start, end; 3276 3277 if (cea_db_offsets(cea, &start, &end)) { 3278 start = 0; 3279 end = 0; 3280 } 3281 3282 for_each_cea_db(cea, i, start, end) { 3283 db = &cea[i]; 3284 dbl = cea_db_payload_len(db); 3285 3286 switch (cea_db_tag(db)) { 3287 case AUDIO_BLOCK: 3288 /* Audio Data Block, contains SADs */ 3289 sad_count = dbl / 3; 3290 if (dbl >= 1) 3291 memcpy(eld + 20 + mnl, &db[1], dbl); 3292 break; 3293 case SPEAKER_BLOCK: 3294 /* Speaker Allocation Data Block */ 3295 if (dbl >= 1) 3296 eld[7] = db[1]; 3297 break; 3298 case VENDOR_BLOCK: 3299 /* HDMI Vendor-Specific Data Block */ 3300 if (cea_db_is_hdmi_vsdb(db)) 3301 parse_hdmi_vsdb(connector, db); 3302 break; 3303 default: 3304 break; 3305 } 3306 } 3307 } 3308 eld[5] |= sad_count << 4; 3309 3310 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3311 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 3312 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 3313 else 3314 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 3315 3316 eld[DRM_ELD_BASELINE_ELD_LEN] = 3317 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 3318 3319 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 3320 drm_eld_size(eld), sad_count); 3321 } 3322 EXPORT_SYMBOL(drm_edid_to_eld); 3323 3324 /** 3325 * drm_edid_to_sad - extracts SADs from EDID 3326 * @edid: EDID to parse 3327 * @sads: pointer that will be set to the extracted SADs 3328 * 3329 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 3330 * 3331 * Note: The returned pointer needs to be freed using kfree(). 3332 * 3333 * Return: The number of found SADs or negative number on error. 3334 */ 3335 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 3336 { 3337 int count = 0; 3338 int i, start, end, dbl; 3339 u8 *cea; 3340 3341 cea = drm_find_cea_extension(edid); 3342 if (!cea) { 3343 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3344 return -ENOENT; 3345 } 3346 3347 if (cea_revision(cea) < 3) { 3348 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3349 return -ENOTSUPP; 3350 } 3351 3352 if (cea_db_offsets(cea, &start, &end)) { 3353 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3354 return -EPROTO; 3355 } 3356 3357 for_each_cea_db(cea, i, start, end) { 3358 u8 *db = &cea[i]; 3359 3360 if (cea_db_tag(db) == AUDIO_BLOCK) { 3361 int j; 3362 dbl = cea_db_payload_len(db); 3363 3364 count = dbl / 3; /* SAD is 3B */ 3365 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 3366 if (!*sads) 3367 return -ENOMEM; 3368 for (j = 0; j < count; j++) { 3369 u8 *sad = &db[1 + j * 3]; 3370 3371 (*sads)[j].format = (sad[0] & 0x78) >> 3; 3372 (*sads)[j].channels = sad[0] & 0x7; 3373 (*sads)[j].freq = sad[1] & 0x7F; 3374 (*sads)[j].byte2 = sad[2]; 3375 } 3376 break; 3377 } 3378 } 3379 3380 return count; 3381 } 3382 EXPORT_SYMBOL(drm_edid_to_sad); 3383 3384 /** 3385 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 3386 * @edid: EDID to parse 3387 * @sadb: pointer to the speaker block 3388 * 3389 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 3390 * 3391 * Note: The returned pointer needs to be freed using kfree(). 3392 * 3393 * Return: The number of found Speaker Allocation Blocks or negative number on 3394 * error. 3395 */ 3396 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 3397 { 3398 int count = 0; 3399 int i, start, end, dbl; 3400 const u8 *cea; 3401 3402 cea = drm_find_cea_extension(edid); 3403 if (!cea) { 3404 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 3405 return -ENOENT; 3406 } 3407 3408 if (cea_revision(cea) < 3) { 3409 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 3410 return -ENOTSUPP; 3411 } 3412 3413 if (cea_db_offsets(cea, &start, &end)) { 3414 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 3415 return -EPROTO; 3416 } 3417 3418 for_each_cea_db(cea, i, start, end) { 3419 const u8 *db = &cea[i]; 3420 3421 if (cea_db_tag(db) == SPEAKER_BLOCK) { 3422 dbl = cea_db_payload_len(db); 3423 3424 /* Speaker Allocation Data Block */ 3425 if (dbl == 3) { 3426 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 3427 if (!*sadb) 3428 return -ENOMEM; 3429 count = dbl; 3430 break; 3431 } 3432 } 3433 } 3434 3435 return count; 3436 } 3437 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 3438 3439 /** 3440 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 3441 * @connector: connector associated with the HDMI/DP sink 3442 * @mode: the display mode 3443 * 3444 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 3445 * the sink doesn't support audio or video. 3446 */ 3447 int drm_av_sync_delay(struct drm_connector *connector, 3448 const struct drm_display_mode *mode) 3449 { 3450 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 3451 int a, v; 3452 3453 if (!connector->latency_present[0]) 3454 return 0; 3455 if (!connector->latency_present[1]) 3456 i = 0; 3457 3458 a = connector->audio_latency[i]; 3459 v = connector->video_latency[i]; 3460 3461 /* 3462 * HDMI/DP sink doesn't support audio or video? 3463 */ 3464 if (a == 255 || v == 255) 3465 return 0; 3466 3467 /* 3468 * Convert raw EDID values to millisecond. 3469 * Treat unknown latency as 0ms. 3470 */ 3471 if (a) 3472 a = min(2 * (a - 1), 500); 3473 if (v) 3474 v = min(2 * (v - 1), 500); 3475 3476 return max(v - a, 0); 3477 } 3478 EXPORT_SYMBOL(drm_av_sync_delay); 3479 3480 /** 3481 * drm_select_eld - select one ELD from multiple HDMI/DP sinks 3482 * @encoder: the encoder just changed display mode 3483 * 3484 * It's possible for one encoder to be associated with multiple HDMI/DP sinks. 3485 * The policy is now hard coded to simply use the first HDMI/DP sink's ELD. 3486 * 3487 * Return: The connector associated with the first HDMI/DP sink that has ELD 3488 * attached to it. 3489 */ 3490 struct drm_connector *drm_select_eld(struct drm_encoder *encoder) 3491 { 3492 struct drm_connector *connector; 3493 struct drm_device *dev = encoder->dev; 3494 3495 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); 3496 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); 3497 3498 drm_for_each_connector(connector, dev) 3499 if (connector->encoder == encoder && connector->eld[0]) 3500 return connector; 3501 3502 return NULL; 3503 } 3504 EXPORT_SYMBOL(drm_select_eld); 3505 3506 /** 3507 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 3508 * @edid: monitor EDID information 3509 * 3510 * Parse the CEA extension according to CEA-861-B. 3511 * 3512 * Return: True if the monitor is HDMI, false if not or unknown. 3513 */ 3514 bool drm_detect_hdmi_monitor(struct edid *edid) 3515 { 3516 u8 *edid_ext; 3517 int i; 3518 int start_offset, end_offset; 3519 3520 edid_ext = drm_find_cea_extension(edid); 3521 if (!edid_ext) 3522 return false; 3523 3524 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3525 return false; 3526 3527 /* 3528 * Because HDMI identifier is in Vendor Specific Block, 3529 * search it from all data blocks of CEA extension. 3530 */ 3531 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3532 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 3533 return true; 3534 } 3535 3536 return false; 3537 } 3538 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 3539 3540 /** 3541 * drm_detect_monitor_audio - check monitor audio capability 3542 * @edid: EDID block to scan 3543 * 3544 * Monitor should have CEA extension block. 3545 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 3546 * audio' only. If there is any audio extension block and supported 3547 * audio format, assume at least 'basic audio' support, even if 'basic 3548 * audio' is not defined in EDID. 3549 * 3550 * Return: True if the monitor supports audio, false otherwise. 3551 */ 3552 bool drm_detect_monitor_audio(struct edid *edid) 3553 { 3554 u8 *edid_ext; 3555 int i, j; 3556 bool has_audio = false; 3557 int start_offset, end_offset; 3558 3559 edid_ext = drm_find_cea_extension(edid); 3560 if (!edid_ext) 3561 goto end; 3562 3563 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 3564 3565 if (has_audio) { 3566 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 3567 goto end; 3568 } 3569 3570 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3571 goto end; 3572 3573 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3574 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 3575 has_audio = true; 3576 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 3577 DRM_DEBUG_KMS("CEA audio format %d\n", 3578 (edid_ext[i + j] >> 3) & 0xf); 3579 goto end; 3580 } 3581 } 3582 end: 3583 return has_audio; 3584 } 3585 EXPORT_SYMBOL(drm_detect_monitor_audio); 3586 3587 /** 3588 * drm_rgb_quant_range_selectable - is RGB quantization range selectable? 3589 * @edid: EDID block to scan 3590 * 3591 * Check whether the monitor reports the RGB quantization range selection 3592 * as supported. The AVI infoframe can then be used to inform the monitor 3593 * which quantization range (full or limited) is used. 3594 * 3595 * Return: True if the RGB quantization range is selectable, false otherwise. 3596 */ 3597 bool drm_rgb_quant_range_selectable(struct edid *edid) 3598 { 3599 u8 *edid_ext; 3600 int i, start, end; 3601 3602 edid_ext = drm_find_cea_extension(edid); 3603 if (!edid_ext) 3604 return false; 3605 3606 if (cea_db_offsets(edid_ext, &start, &end)) 3607 return false; 3608 3609 for_each_cea_db(edid_ext, i, start, end) { 3610 if (cea_db_tag(&edid_ext[i]) == VIDEO_CAPABILITY_BLOCK && 3611 cea_db_payload_len(&edid_ext[i]) == 2) { 3612 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", edid_ext[i + 2]); 3613 return edid_ext[i + 2] & EDID_CEA_VCDB_QS; 3614 } 3615 } 3616 3617 return false; 3618 } 3619 EXPORT_SYMBOL(drm_rgb_quant_range_selectable); 3620 3621 /** 3622 * drm_assign_hdmi_deep_color_info - detect whether monitor supports 3623 * hdmi deep color modes and update drm_display_info if so. 3624 * @edid: monitor EDID information 3625 * @info: Updated with maximum supported deep color bpc and color format 3626 * if deep color supported. 3627 * @connector: DRM connector, used only for debug output 3628 * 3629 * Parse the CEA extension according to CEA-861-B. 3630 * Return true if HDMI deep color supported, false if not or unknown. 3631 */ 3632 static bool drm_assign_hdmi_deep_color_info(struct edid *edid, 3633 struct drm_display_info *info, 3634 struct drm_connector *connector) 3635 { 3636 u8 *edid_ext, *hdmi; 3637 int i; 3638 int start_offset, end_offset; 3639 unsigned int dc_bpc = 0; 3640 3641 edid_ext = drm_find_cea_extension(edid); 3642 if (!edid_ext) 3643 return false; 3644 3645 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 3646 return false; 3647 3648 /* 3649 * Because HDMI identifier is in Vendor Specific Block, 3650 * search it from all data blocks of CEA extension. 3651 */ 3652 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 3653 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) { 3654 /* HDMI supports at least 8 bpc */ 3655 info->bpc = 8; 3656 3657 hdmi = &edid_ext[i]; 3658 if (cea_db_payload_len(hdmi) < 6) 3659 return false; 3660 3661 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 3662 dc_bpc = 10; 3663 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 3664 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 3665 connector->name); 3666 } 3667 3668 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 3669 dc_bpc = 12; 3670 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 3671 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 3672 connector->name); 3673 } 3674 3675 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 3676 dc_bpc = 16; 3677 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 3678 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 3679 connector->name); 3680 } 3681 3682 if (dc_bpc > 0) { 3683 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 3684 connector->name, dc_bpc); 3685 info->bpc = dc_bpc; 3686 3687 /* 3688 * Deep color support mandates RGB444 support for all video 3689 * modes and forbids YCRCB422 support for all video modes per 3690 * HDMI 1.3 spec. 3691 */ 3692 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3693 3694 /* YCRCB444 is optional according to spec. */ 3695 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 3696 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3697 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 3698 connector->name); 3699 } 3700 3701 /* 3702 * Spec says that if any deep color mode is supported at all, 3703 * then deep color 36 bit must be supported. 3704 */ 3705 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 3706 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 3707 connector->name); 3708 } 3709 3710 return true; 3711 } 3712 else { 3713 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 3714 connector->name); 3715 } 3716 } 3717 } 3718 3719 return false; 3720 } 3721 3722 /** 3723 * drm_add_display_info - pull display info out if present 3724 * @edid: EDID data 3725 * @info: display info (attached to connector) 3726 * @connector: connector whose edid is used to build display info 3727 * 3728 * Grab any available display info and stuff it into the drm_display_info 3729 * structure that's part of the connector. Useful for tracking bpp and 3730 * color spaces. 3731 */ 3732 static void drm_add_display_info(struct edid *edid, 3733 struct drm_display_info *info, 3734 struct drm_connector *connector) 3735 { 3736 u8 *edid_ext; 3737 3738 info->width_mm = edid->width_cm * 10; 3739 info->height_mm = edid->height_cm * 10; 3740 3741 /* driver figures it out in this case */ 3742 info->bpc = 0; 3743 info->color_formats = 0; 3744 3745 if (edid->revision < 3) 3746 return; 3747 3748 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 3749 return; 3750 3751 /* Get data from CEA blocks if present */ 3752 edid_ext = drm_find_cea_extension(edid); 3753 if (edid_ext) { 3754 info->cea_rev = edid_ext[1]; 3755 3756 /* The existence of a CEA block should imply RGB support */ 3757 info->color_formats = DRM_COLOR_FORMAT_RGB444; 3758 if (edid_ext[3] & EDID_CEA_YCRCB444) 3759 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3760 if (edid_ext[3] & EDID_CEA_YCRCB422) 3761 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3762 } 3763 3764 /* HDMI deep color modes supported? Assign to info, if so */ 3765 drm_assign_hdmi_deep_color_info(edid, info, connector); 3766 3767 /* Only defined for 1.4 with digital displays */ 3768 if (edid->revision < 4) 3769 return; 3770 3771 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 3772 case DRM_EDID_DIGITAL_DEPTH_6: 3773 info->bpc = 6; 3774 break; 3775 case DRM_EDID_DIGITAL_DEPTH_8: 3776 info->bpc = 8; 3777 break; 3778 case DRM_EDID_DIGITAL_DEPTH_10: 3779 info->bpc = 10; 3780 break; 3781 case DRM_EDID_DIGITAL_DEPTH_12: 3782 info->bpc = 12; 3783 break; 3784 case DRM_EDID_DIGITAL_DEPTH_14: 3785 info->bpc = 14; 3786 break; 3787 case DRM_EDID_DIGITAL_DEPTH_16: 3788 info->bpc = 16; 3789 break; 3790 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 3791 default: 3792 info->bpc = 0; 3793 break; 3794 } 3795 3796 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 3797 connector->name, info->bpc); 3798 3799 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 3800 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 3801 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 3802 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 3803 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 3804 } 3805 3806 /** 3807 * drm_add_edid_modes - add modes from EDID data, if available 3808 * @connector: connector we're probing 3809 * @edid: EDID data 3810 * 3811 * Add the specified modes to the connector's mode list. 3812 * 3813 * Return: The number of modes added or 0 if we couldn't find any. 3814 */ 3815 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 3816 { 3817 int num_modes = 0; 3818 u32 quirks; 3819 3820 if (edid == NULL) { 3821 return 0; 3822 } 3823 if (!drm_edid_is_valid(edid)) { 3824 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 3825 connector->name); 3826 return 0; 3827 } 3828 3829 quirks = edid_get_quirks(edid); 3830 3831 /* 3832 * EDID spec says modes should be preferred in this order: 3833 * - preferred detailed mode 3834 * - other detailed modes from base block 3835 * - detailed modes from extension blocks 3836 * - CVT 3-byte code modes 3837 * - standard timing codes 3838 * - established timing codes 3839 * - modes inferred from GTF or CVT range information 3840 * 3841 * We get this pretty much right. 3842 * 3843 * XXX order for additional mode types in extension blocks? 3844 */ 3845 num_modes += add_detailed_modes(connector, edid, quirks); 3846 num_modes += add_cvt_modes(connector, edid); 3847 num_modes += add_standard_modes(connector, edid); 3848 num_modes += add_established_modes(connector, edid); 3849 num_modes += add_cea_modes(connector, edid); 3850 num_modes += add_alternate_cea_modes(connector, edid); 3851 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 3852 num_modes += add_inferred_modes(connector, edid); 3853 3854 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 3855 edid_fixup_preferred(connector, quirks); 3856 3857 drm_add_display_info(edid, &connector->display_info, connector); 3858 3859 if (quirks & EDID_QUIRK_FORCE_6BPC) 3860 connector->display_info.bpc = 6; 3861 3862 if (quirks & EDID_QUIRK_FORCE_8BPC) 3863 connector->display_info.bpc = 8; 3864 3865 if (quirks & EDID_QUIRK_FORCE_10BPC) 3866 connector->display_info.bpc = 10; 3867 3868 if (quirks & EDID_QUIRK_FORCE_12BPC) 3869 connector->display_info.bpc = 12; 3870 3871 return num_modes; 3872 } 3873 EXPORT_SYMBOL(drm_add_edid_modes); 3874 3875 /** 3876 * drm_add_modes_noedid - add modes for the connectors without EDID 3877 * @connector: connector we're probing 3878 * @hdisplay: the horizontal display limit 3879 * @vdisplay: the vertical display limit 3880 * 3881 * Add the specified modes to the connector's mode list. Only when the 3882 * hdisplay/vdisplay is not beyond the given limit, it will be added. 3883 * 3884 * Return: The number of modes added or 0 if we couldn't find any. 3885 */ 3886 int drm_add_modes_noedid(struct drm_connector *connector, 3887 int hdisplay, int vdisplay) 3888 { 3889 int i, count, num_modes = 0; 3890 struct drm_display_mode *mode; 3891 struct drm_device *dev = connector->dev; 3892 3893 count = ARRAY_SIZE(drm_dmt_modes); 3894 if (hdisplay < 0) 3895 hdisplay = 0; 3896 if (vdisplay < 0) 3897 vdisplay = 0; 3898 3899 for (i = 0; i < count; i++) { 3900 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3901 if (hdisplay && vdisplay) { 3902 /* 3903 * Only when two are valid, they will be used to check 3904 * whether the mode should be added to the mode list of 3905 * the connector. 3906 */ 3907 if (ptr->hdisplay > hdisplay || 3908 ptr->vdisplay > vdisplay) 3909 continue; 3910 } 3911 if (drm_mode_vrefresh(ptr) > 61) 3912 continue; 3913 mode = drm_mode_duplicate(dev, ptr); 3914 if (mode) { 3915 drm_mode_probed_add(connector, mode); 3916 num_modes++; 3917 } 3918 } 3919 return num_modes; 3920 } 3921 EXPORT_SYMBOL(drm_add_modes_noedid); 3922 3923 /** 3924 * drm_set_preferred_mode - Sets the preferred mode of a connector 3925 * @connector: connector whose mode list should be processed 3926 * @hpref: horizontal resolution of preferred mode 3927 * @vpref: vertical resolution of preferred mode 3928 * 3929 * Marks a mode as preferred if it matches the resolution specified by @hpref 3930 * and @vpref. 3931 */ 3932 void drm_set_preferred_mode(struct drm_connector *connector, 3933 int hpref, int vpref) 3934 { 3935 struct drm_display_mode *mode; 3936 3937 list_for_each_entry(mode, &connector->probed_modes, head) { 3938 if (mode->hdisplay == hpref && 3939 mode->vdisplay == vpref) 3940 mode->type |= DRM_MODE_TYPE_PREFERRED; 3941 } 3942 } 3943 EXPORT_SYMBOL(drm_set_preferred_mode); 3944 3945 /** 3946 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 3947 * data from a DRM display mode 3948 * @frame: HDMI AVI infoframe 3949 * @mode: DRM display mode 3950 * 3951 * Return: 0 on success or a negative error code on failure. 3952 */ 3953 int 3954 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 3955 const struct drm_display_mode *mode) 3956 { 3957 int err; 3958 3959 if (!frame || !mode) 3960 return -EINVAL; 3961 3962 err = hdmi_avi_infoframe_init(frame); 3963 if (err < 0) 3964 return err; 3965 3966 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 3967 frame->pixel_repeat = 1; 3968 3969 frame->video_code = drm_match_cea_mode(mode); 3970 3971 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 3972 3973 /* 3974 * Populate picture aspect ratio from either 3975 * user input (if specified) or from the CEA mode list. 3976 */ 3977 if (mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_4_3 || 3978 mode->picture_aspect_ratio == HDMI_PICTURE_ASPECT_16_9) 3979 frame->picture_aspect = mode->picture_aspect_ratio; 3980 else if (frame->video_code > 0) 3981 frame->picture_aspect = drm_get_cea_aspect_ratio( 3982 frame->video_code); 3983 3984 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 3985 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 3986 3987 return 0; 3988 } 3989 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 3990 3991 static enum hdmi_3d_structure 3992 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 3993 { 3994 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 3995 3996 switch (layout) { 3997 case DRM_MODE_FLAG_3D_FRAME_PACKING: 3998 return HDMI_3D_STRUCTURE_FRAME_PACKING; 3999 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 4000 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 4001 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 4002 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 4003 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 4004 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 4005 case DRM_MODE_FLAG_3D_L_DEPTH: 4006 return HDMI_3D_STRUCTURE_L_DEPTH; 4007 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 4008 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 4009 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 4010 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 4011 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 4012 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 4013 default: 4014 return HDMI_3D_STRUCTURE_INVALID; 4015 } 4016 } 4017 4018 /** 4019 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 4020 * data from a DRM display mode 4021 * @frame: HDMI vendor infoframe 4022 * @mode: DRM display mode 4023 * 4024 * Note that there's is a need to send HDMI vendor infoframes only when using a 4025 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 4026 * function will return -EINVAL, error that can be safely ignored. 4027 * 4028 * Return: 0 on success or a negative error code on failure. 4029 */ 4030 int 4031 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 4032 const struct drm_display_mode *mode) 4033 { 4034 int err; 4035 u32 s3d_flags; 4036 u8 vic; 4037 4038 if (!frame || !mode) 4039 return -EINVAL; 4040 4041 vic = drm_match_hdmi_mode(mode); 4042 s3d_flags = mode->flags & DRM_MODE_FLAG_3D_MASK; 4043 4044 if (!vic && !s3d_flags) 4045 return -EINVAL; 4046 4047 if (vic && s3d_flags) 4048 return -EINVAL; 4049 4050 err = hdmi_vendor_infoframe_init(frame); 4051 if (err < 0) 4052 return err; 4053 4054 if (vic) 4055 frame->vic = vic; 4056 else 4057 frame->s3d_struct = s3d_structure_from_display_mode(mode); 4058 4059 return 0; 4060 } 4061 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 4062 4063 static int drm_parse_display_id(struct drm_connector *connector, 4064 u8 *displayid, int length, 4065 bool is_edid_extension) 4066 { 4067 /* if this is an EDID extension the first byte will be 0x70 */ 4068 int idx = 0; 4069 struct displayid_hdr *base; 4070 struct displayid_block *block; 4071 u8 csum = 0; 4072 int i; 4073 4074 if (is_edid_extension) 4075 idx = 1; 4076 4077 base = (struct displayid_hdr *)&displayid[idx]; 4078 4079 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 4080 base->rev, base->bytes, base->prod_id, base->ext_count); 4081 4082 if (base->bytes + 5 > length - idx) 4083 return -EINVAL; 4084 4085 for (i = idx; i <= base->bytes + 5; i++) { 4086 csum += displayid[i]; 4087 } 4088 if (csum) { 4089 DRM_ERROR("DisplayID checksum invalid, remainder is %d\n", csum); 4090 return -EINVAL; 4091 } 4092 4093 block = (struct displayid_block *)&displayid[idx + 4]; 4094 DRM_DEBUG_KMS("block id %d, rev %d, len %d\n", 4095 block->tag, block->rev, block->num_bytes); 4096 4097 switch (block->tag) { 4098 case DATA_BLOCK_TILED_DISPLAY: { 4099 struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 4100 4101 u16 w, h; 4102 u8 tile_v_loc, tile_h_loc; 4103 u8 num_v_tile, num_h_tile; 4104 struct drm_tile_group *tg; 4105 4106 w = tile->tile_size[0] | tile->tile_size[1] << 8; 4107 h = tile->tile_size[2] | tile->tile_size[3] << 8; 4108 4109 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 4110 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 4111 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 4112 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 4113 4114 connector->has_tile = true; 4115 if (tile->tile_cap & 0x80) 4116 connector->tile_is_single_monitor = true; 4117 4118 connector->num_h_tile = num_h_tile + 1; 4119 connector->num_v_tile = num_v_tile + 1; 4120 connector->tile_h_loc = tile_h_loc; 4121 connector->tile_v_loc = tile_v_loc; 4122 connector->tile_h_size = w + 1; 4123 connector->tile_v_size = h + 1; 4124 4125 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 4126 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 4127 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 4128 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 4129 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 4130 4131 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 4132 if (!tg) { 4133 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 4134 } 4135 if (!tg) 4136 return -ENOMEM; 4137 4138 if (connector->tile_group != tg) { 4139 /* if we haven't got a pointer, 4140 take the reference, drop ref to old tile group */ 4141 if (connector->tile_group) { 4142 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4143 } 4144 connector->tile_group = tg; 4145 } else 4146 /* if same tile group, then release the ref we just took. */ 4147 drm_mode_put_tile_group(connector->dev, tg); 4148 } 4149 break; 4150 default: 4151 printk("unknown displayid tag %d\n", block->tag); 4152 break; 4153 } 4154 return 0; 4155 } 4156 4157 static void drm_get_displayid(struct drm_connector *connector, 4158 struct edid *edid) 4159 { 4160 void *displayid = NULL; 4161 int ret; 4162 connector->has_tile = false; 4163 displayid = drm_find_displayid_extension(edid); 4164 if (!displayid) { 4165 /* drop reference to any tile group we had */ 4166 goto out_drop_ref; 4167 } 4168 4169 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 4170 if (ret < 0) 4171 goto out_drop_ref; 4172 if (!connector->has_tile) 4173 goto out_drop_ref; 4174 return; 4175 out_drop_ref: 4176 if (connector->tile_group) { 4177 drm_mode_put_tile_group(connector->dev, connector->tile_group); 4178 connector->tile_group = NULL; 4179 } 4180 return; 4181 } 4182
Indexes created Fri Sep 26 20:09:58 GMT 2025