11.1Sriastradconfig DRM_I915_USERFAULT_AUTOSUSPEND 21.1Sriastrad int "Runtime autosuspend delay for userspace GGTT mmaps (ms)" 31.1Sriastrad default 250 # milliseconds 41.1Sriastrad help 51.1Sriastrad On runtime suspend, as we suspend the device, we have to revoke 61.1Sriastrad userspace GGTT mmaps and force userspace to take a pagefault on 71.1Sriastrad their next access. The revocation and subsequent recreation of 81.1Sriastrad the GGTT mmap can be very slow and so we impose a small hysteris 91.1Sriastrad that complements the runtime-pm autosuspend and provides a lower 101.1Sriastrad floor on the autosuspend delay. 111.1Sriastrad 121.1Sriastrad May be 0 to disable the extra delay and solely use the device level 131.1Sriastrad runtime pm autosuspend delay tunable. 141.1Sriastrad 151.1Sriastradconfig DRM_I915_HEARTBEAT_INTERVAL 161.1Sriastrad int "Interval between heartbeat pulses (ms)" 171.1Sriastrad default 2500 # milliseconds 181.1Sriastrad help 191.1Sriastrad The driver sends a periodic heartbeat down all active engines to 201.1Sriastrad check the health of the GPU and undertake regular house-keeping of 211.1Sriastrad internal driver state. 221.1Sriastrad 231.1Sriastrad May be 0 to disable heartbeats and therefore disable automatic GPU 241.1Sriastrad hang detection. 251.1Sriastrad 261.1Sriastradconfig DRM_I915_PREEMPT_TIMEOUT 271.1Sriastrad int "Preempt timeout (ms, jiffy granularity)" 281.1Sriastrad default 640 # milliseconds 291.1Sriastrad help 301.1Sriastrad How long to wait (in milliseconds) for a preemption event to occur 311.1Sriastrad when submitting a new context via execlists. If the current context 321.1Sriastrad does not hit an arbitration point and yield to HW before the timer 331.1Sriastrad expires, the HW will be reset to allow the more important context 341.1Sriastrad to execute. 351.1Sriastrad 361.1Sriastrad May be 0 to disable the timeout. 371.1Sriastrad 381.1Sriastradconfig DRM_I915_SPIN_REQUEST 391.1Sriastrad int "Busywait for request completion (us)" 401.1Sriastrad default 5 # microseconds 411.1Sriastrad help 421.1Sriastrad Before sleeping waiting for a request (GPU operation) to complete, 431.1Sriastrad we may spend some time polling for its completion. As the IRQ may 441.1Sriastrad take a non-negligible time to setup, we do a short spin first to 451.1Sriastrad check if the request will complete in the time it would have taken 461.1Sriastrad us to enable the interrupt. 471.1Sriastrad 481.1Sriastrad May be 0 to disable the initial spin. In practice, we estimate 491.1Sriastrad the cost of enabling the interrupt (if currently disabled) to be 501.1Sriastrad a few microseconds. 511.1Sriastrad 521.1Sriastradconfig DRM_I915_STOP_TIMEOUT 531.1Sriastrad int "How long to wait for an engine to quiesce gracefully before reset (ms)" 541.1Sriastrad default 100 # milliseconds 551.1Sriastrad help 561.1Sriastrad By stopping submission and sleeping for a short time before resetting 571.1Sriastrad the GPU, we allow the innocent contexts also on the system to quiesce. 581.1Sriastrad It is then less likely for a hanging context to cause collateral 591.1Sriastrad damage as the system is reset in order to recover. The corollary is 601.1Sriastrad that the reset itself may take longer and so be more disruptive to 611.1Sriastrad interactive or low latency workloads. 621.1Sriastrad 631.1Sriastradconfig DRM_I915_TIMESLICE_DURATION 641.1Sriastrad int "Scheduling quantum for userspace batches (ms, jiffy granularity)" 651.1Sriastrad default 1 # milliseconds 661.1Sriastrad help 671.1Sriastrad When two user batches of equal priority are executing, we will 681.1Sriastrad alternate execution of each batch to ensure forward progress of 691.1Sriastrad all users. This is necessary in some cases where there may be 701.1Sriastrad an implicit dependency between those batches that requires 711.1Sriastrad concurrent execution in order for them to proceed, e.g. they 721.1Sriastrad interact with each other via userspace semaphores. Each context 731.1Sriastrad is scheduled for execution for the timeslice duration, before 741.1Sriastrad switching to the next context. 751.1Sriastrad 761.1Sriastrad May be 0 to disable timeslicing. 77