intel_dp.h revision 1.3 1 /* $NetBSD: intel_dp.h,v 1.3 2021/12/19 11:38:03 riastradh Exp $ */
2
3 /* SPDX-License-Identifier: MIT */
4 /*
5 * Copyright 2019 Intel Corporation
6 */
7
8 #ifndef __INTEL_DP_H__
9 #define __INTEL_DP_H__
10
11 #include <linux/types.h>
12
13 #include <drm/i915_drm.h>
14
15 #include "i915_reg.h"
16
17 #include <sys/file.h>
18 #define pipe pipe_drmhack /* see intel_display.h */
19
20 enum pipe;
21 enum port;
22 struct drm_connector_state;
23 struct drm_encoder;
24 struct drm_i915_private;
25 struct drm_modeset_acquire_ctx;
26 struct intel_connector;
27 struct intel_crtc_state;
28 struct intel_digital_port;
29 struct intel_dp;
30 struct intel_encoder;
31
32 struct link_config_limits {
33 int min_clock, max_clock;
34 int min_lane_count, max_lane_count;
35 int min_bpp, max_bpp;
36 };
37
38 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
39 struct intel_crtc_state *pipe_config,
40 struct link_config_limits *limits);
41 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state,
42 const struct drm_connector_state *conn_state);
43 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state);
44 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv,
45 i915_reg_t dp_reg, enum port port,
46 enum pipe *pipe);
47 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg,
48 enum port port);
49 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
50 struct intel_connector *intel_connector);
51 void intel_dp_set_link_params(struct intel_dp *intel_dp,
52 int link_rate, u8 lane_count,
53 bool link_mst);
54 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
55 int link_rate, u8 lane_count);
56 int intel_dp_retrain_link(struct intel_encoder *encoder,
57 struct drm_modeset_acquire_ctx *ctx);
58 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode);
59 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
60 const struct intel_crtc_state *crtc_state,
61 bool enable);
62 void intel_dp_encoder_reset(struct drm_encoder *encoder);
63 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder);
64 void intel_dp_encoder_flush_work(struct drm_encoder *encoder);
65 int intel_dp_compute_config(struct intel_encoder *encoder,
66 struct intel_crtc_state *pipe_config,
67 struct drm_connector_state *conn_state);
68 bool intel_dp_is_edp(struct intel_dp *intel_dp);
69 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
70 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port,
71 bool long_hpd);
72 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state,
73 const struct drm_connector_state *conn_state);
74 void intel_edp_backlight_off(const struct drm_connector_state *conn_state);
75 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
76 void intel_edp_panel_on(struct intel_dp *intel_dp);
77 void intel_edp_panel_off(struct intel_dp *intel_dp);
78 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv);
79 void intel_dp_mst_resume(struct drm_i915_private *dev_priv);
80 int intel_dp_max_link_rate(struct intel_dp *intel_dp);
81 int intel_dp_max_lane_count(struct intel_dp *intel_dp);
82 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate);
83 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv);
84 u32 intel_dp_pack_aux(const u8 *src, int src_bytes);
85
86 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
87 const struct intel_crtc_state *crtc_state);
88 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
89 const struct intel_crtc_state *crtc_state);
90 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
91 unsigned int frontbuffer_bits);
92 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
93 unsigned int frontbuffer_bits);
94
95 void
96 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
97 u8 dp_train_pat);
98 void
99 intel_dp_set_signal_levels(struct intel_dp *intel_dp);
100 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp);
101 u8
102 intel_dp_voltage_max(struct intel_dp *intel_dp);
103 u8
104 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing);
105 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
106 u8 *link_bw, u8 *rate_select);
107 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp);
108 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp);
109 bool
110 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status);
111
112 bool intel_dp_read_dpcd(struct intel_dp *intel_dp);
113 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp);
114 int intel_dp_link_required(int pixel_clock, int bpp);
115 int intel_dp_max_data_rate(int max_link_clock, int max_lanes);
116 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
117 const struct drm_connector_state *conn_state);
118 void intel_dp_vsc_enable(struct intel_dp *intel_dp,
119 const struct intel_crtc_state *crtc_state,
120 const struct drm_connector_state *conn_state);
121 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
122 const struct intel_crtc_state *crtc_state,
123 const struct drm_connector_state *conn_state);
124 bool intel_digital_port_connected(struct intel_encoder *encoder);
125
126 static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
127 {
128 return ~((1 << lane_count) - 1) & 0xf;
129 }
130
131 u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
132
133 #endif /* __INTEL_DP_H__ */
134