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      1  1.3  riastrad /*	$NetBSD: intel_fbc.c,v 1.3 2021/12/19 12:32:15 riastradh Exp $	*/
      2  1.1  riastrad 
      3  1.1  riastrad /*
      4  1.1  riastrad  * Copyright  2014 Intel Corporation
      5  1.1  riastrad  *
      6  1.1  riastrad  * Permission is hereby granted, free of charge, to any person obtaining a
      7  1.1  riastrad  * copy of this software and associated documentation files (the "Software"),
      8  1.1  riastrad  * to deal in the Software without restriction, including without limitation
      9  1.1  riastrad  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  1.1  riastrad  * and/or sell copies of the Software, and to permit persons to whom the
     11  1.1  riastrad  * Software is furnished to do so, subject to the following conditions:
     12  1.1  riastrad  *
     13  1.1  riastrad  * The above copyright notice and this permission notice (including the next
     14  1.1  riastrad  * paragraph) shall be included in all copies or substantial portions of the
     15  1.1  riastrad  * Software.
     16  1.1  riastrad  *
     17  1.1  riastrad  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  1.1  riastrad  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  1.1  riastrad  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  1.1  riastrad  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  1.1  riastrad  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
     22  1.1  riastrad  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
     23  1.1  riastrad  * DEALINGS IN THE SOFTWARE.
     24  1.1  riastrad  */
     25  1.1  riastrad 
     26  1.1  riastrad /**
     27  1.1  riastrad  * DOC: Frame Buffer Compression (FBC)
     28  1.1  riastrad  *
     29  1.1  riastrad  * FBC tries to save memory bandwidth (and so power consumption) by
     30  1.1  riastrad  * compressing the amount of memory used by the display. It is total
     31  1.1  riastrad  * transparent to user space and completely handled in the kernel.
     32  1.1  riastrad  *
     33  1.1  riastrad  * The benefits of FBC are mostly visible with solid backgrounds and
     34  1.1  riastrad  * variation-less patterns. It comes from keeping the memory footprint small
     35  1.1  riastrad  * and having fewer memory pages opened and accessed for refreshing the display.
     36  1.1  riastrad  *
     37  1.1  riastrad  * i915 is responsible to reserve stolen memory for FBC and configure its
     38  1.1  riastrad  * offset on proper registers. The hardware takes care of all
     39  1.1  riastrad  * compress/decompress. However there are many known cases where we have to
     40  1.1  riastrad  * forcibly disable it to allow proper screen updates.
     41  1.1  riastrad  */
     42  1.1  riastrad 
     43  1.1  riastrad #include <sys/cdefs.h>
     44  1.3  riastrad __KERNEL_RCSID(0, "$NetBSD: intel_fbc.c,v 1.3 2021/12/19 12:32:15 riastradh Exp $");
     45  1.1  riastrad 
     46  1.1  riastrad #include <drm/drm_fourcc.h>
     47  1.1  riastrad 
     48  1.1  riastrad #include "i915_drv.h"
     49  1.1  riastrad #include "intel_display_types.h"
     50  1.1  riastrad #include "intel_fbc.h"
     51  1.1  riastrad #include "intel_frontbuffer.h"
     52  1.1  riastrad 
     53  1.2  riastrad #include <linux/nbsd-namespace.h>
     54  1.2  riastrad 
     55  1.1  riastrad static inline bool fbc_supported(struct drm_i915_private *dev_priv)
     56  1.1  riastrad {
     57  1.1  riastrad 	return HAS_FBC(dev_priv);
     58  1.1  riastrad }
     59  1.1  riastrad 
     60  1.1  riastrad /*
     61  1.1  riastrad  * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
     62  1.1  riastrad  * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
     63  1.1  riastrad  * origin so the x and y offsets can actually fit the registers. As a
     64  1.1  riastrad  * consequence, the fence doesn't really start exactly at the display plane
     65  1.1  riastrad  * address we program because it starts at the real start of the buffer, so we
     66  1.1  riastrad  * have to take this into consideration here.
     67  1.1  riastrad  */
     68  1.1  riastrad static unsigned int get_crtc_fence_y_offset(struct intel_fbc *fbc)
     69  1.1  riastrad {
     70  1.1  riastrad 	return fbc->state_cache.plane.y - fbc->state_cache.plane.adjusted_y;
     71  1.1  riastrad }
     72  1.1  riastrad 
     73  1.1  riastrad /*
     74  1.1  riastrad  * For SKL+, the plane source size used by the hardware is based on the value we
     75  1.1  riastrad  * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
     76  1.1  riastrad  * we wrote to PIPESRC.
     77  1.1  riastrad  */
     78  1.1  riastrad static void intel_fbc_get_plane_source_size(const struct intel_fbc_state_cache *cache,
     79  1.1  riastrad 					    int *width, int *height)
     80  1.1  riastrad {
     81  1.1  riastrad 	if (width)
     82  1.1  riastrad 		*width = cache->plane.src_w;
     83  1.1  riastrad 	if (height)
     84  1.1  riastrad 		*height = cache->plane.src_h;
     85  1.1  riastrad }
     86  1.1  riastrad 
     87  1.1  riastrad static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
     88  1.1  riastrad 					const struct intel_fbc_state_cache *cache)
     89  1.1  riastrad {
     90  1.1  riastrad 	int lines;
     91  1.1  riastrad 
     92  1.1  riastrad 	intel_fbc_get_plane_source_size(cache, NULL, &lines);
     93  1.1  riastrad 	if (IS_GEN(dev_priv, 7))
     94  1.1  riastrad 		lines = min(lines, 2048);
     95  1.1  riastrad 	else if (INTEL_GEN(dev_priv) >= 8)
     96  1.1  riastrad 		lines = min(lines, 2560);
     97  1.1  riastrad 
     98  1.1  riastrad 	/* Hardware needs the full buffer stride, not just the active area. */
     99  1.1  riastrad 	return lines * cache->fb.stride;
    100  1.1  riastrad }
    101  1.1  riastrad 
    102  1.1  riastrad static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
    103  1.1  riastrad {
    104  1.1  riastrad 	u32 fbc_ctl;
    105  1.1  riastrad 
    106  1.1  riastrad 	/* Disable compression */
    107  1.1  riastrad 	fbc_ctl = I915_READ(FBC_CONTROL);
    108  1.1  riastrad 	if ((fbc_ctl & FBC_CTL_EN) == 0)
    109  1.1  riastrad 		return;
    110  1.1  riastrad 
    111  1.1  riastrad 	fbc_ctl &= ~FBC_CTL_EN;
    112  1.1  riastrad 	I915_WRITE(FBC_CONTROL, fbc_ctl);
    113  1.1  riastrad 
    114  1.1  riastrad 	/* Wait for compressing bit to clear */
    115  1.1  riastrad 	if (intel_de_wait_for_clear(dev_priv, FBC_STATUS,
    116  1.1  riastrad 				    FBC_STAT_COMPRESSING, 10)) {
    117  1.1  riastrad 		DRM_DEBUG_KMS("FBC idle timed out\n");
    118  1.1  riastrad 		return;
    119  1.1  riastrad 	}
    120  1.1  riastrad }
    121  1.1  riastrad 
    122  1.1  riastrad static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
    123  1.1  riastrad {
    124  1.1  riastrad 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
    125  1.1  riastrad 	int cfb_pitch;
    126  1.1  riastrad 	int i;
    127  1.1  riastrad 	u32 fbc_ctl;
    128  1.1  riastrad 
    129  1.1  riastrad 	/* Note: fbc.threshold == 1 for i8xx */
    130  1.1  riastrad 	cfb_pitch = params->cfb_size / FBC_LL_SIZE;
    131  1.1  riastrad 	if (params->fb.stride < cfb_pitch)
    132  1.1  riastrad 		cfb_pitch = params->fb.stride;
    133  1.1  riastrad 
    134  1.1  riastrad 	/* FBC_CTL wants 32B or 64B units */
    135  1.1  riastrad 	if (IS_GEN(dev_priv, 2))
    136  1.1  riastrad 		cfb_pitch = (cfb_pitch / 32) - 1;
    137  1.1  riastrad 	else
    138  1.1  riastrad 		cfb_pitch = (cfb_pitch / 64) - 1;
    139  1.1  riastrad 
    140  1.1  riastrad 	/* Clear old tags */
    141  1.1  riastrad 	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
    142  1.1  riastrad 		I915_WRITE(FBC_TAG(i), 0);
    143  1.1  riastrad 
    144  1.1  riastrad 	if (IS_GEN(dev_priv, 4)) {
    145  1.1  riastrad 		u32 fbc_ctl2;
    146  1.1  riastrad 
    147  1.1  riastrad 		/* Set it up... */
    148  1.1  riastrad 		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM;
    149  1.1  riastrad 		fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.i9xx_plane);
    150  1.1  riastrad 		if (params->fence_id >= 0)
    151  1.1  riastrad 			fbc_ctl2 |= FBC_CTL_CPU_FENCE;
    152  1.1  riastrad 		I915_WRITE(FBC_CONTROL2, fbc_ctl2);
    153  1.1  riastrad 		I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
    154  1.1  riastrad 	}
    155  1.1  riastrad 
    156  1.1  riastrad 	/* enable it... */
    157  1.1  riastrad 	fbc_ctl = I915_READ(FBC_CONTROL);
    158  1.1  riastrad 	fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
    159  1.1  riastrad 	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
    160  1.1  riastrad 	if (IS_I945GM(dev_priv))
    161  1.1  riastrad 		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
    162  1.1  riastrad 	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
    163  1.1  riastrad 	if (params->fence_id >= 0)
    164  1.1  riastrad 		fbc_ctl |= params->fence_id;
    165  1.1  riastrad 	I915_WRITE(FBC_CONTROL, fbc_ctl);
    166  1.1  riastrad }
    167  1.1  riastrad 
    168  1.1  riastrad static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
    169  1.1  riastrad {
    170  1.1  riastrad 	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
    171  1.1  riastrad }
    172  1.1  riastrad 
    173  1.1  riastrad static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
    174  1.1  riastrad {
    175  1.1  riastrad 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
    176  1.1  riastrad 	u32 dpfc_ctl;
    177  1.1  riastrad 
    178  1.1  riastrad 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane) | DPFC_SR_EN;
    179  1.1  riastrad 	if (params->fb.format->cpp[0] == 2)
    180  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
    181  1.1  riastrad 	else
    182  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
    183  1.1  riastrad 
    184  1.1  riastrad 	if (params->fence_id >= 0) {
    185  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fence_id;
    186  1.1  riastrad 		I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
    187  1.1  riastrad 	} else {
    188  1.1  riastrad 		I915_WRITE(DPFC_FENCE_YOFF, 0);
    189  1.1  riastrad 	}
    190  1.1  riastrad 
    191  1.1  riastrad 	/* enable it... */
    192  1.1  riastrad 	I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
    193  1.1  riastrad }
    194  1.1  riastrad 
    195  1.1  riastrad static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
    196  1.1  riastrad {
    197  1.1  riastrad 	u32 dpfc_ctl;
    198  1.1  riastrad 
    199  1.1  riastrad 	/* Disable compression */
    200  1.1  riastrad 	dpfc_ctl = I915_READ(DPFC_CONTROL);
    201  1.1  riastrad 	if (dpfc_ctl & DPFC_CTL_EN) {
    202  1.1  riastrad 		dpfc_ctl &= ~DPFC_CTL_EN;
    203  1.1  riastrad 		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
    204  1.1  riastrad 	}
    205  1.1  riastrad }
    206  1.1  riastrad 
    207  1.1  riastrad static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
    208  1.1  riastrad {
    209  1.1  riastrad 	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
    210  1.1  riastrad }
    211  1.1  riastrad 
    212  1.1  riastrad /* This function forces a CFB recompression through the nuke operation. */
    213  1.1  riastrad static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
    214  1.1  riastrad {
    215  1.1  riastrad 	I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
    216  1.1  riastrad 	POSTING_READ(MSG_FBC_REND_STATE);
    217  1.1  riastrad }
    218  1.1  riastrad 
    219  1.1  riastrad static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
    220  1.1  riastrad {
    221  1.1  riastrad 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
    222  1.1  riastrad 	u32 dpfc_ctl;
    223  1.1  riastrad 	int threshold = dev_priv->fbc.threshold;
    224  1.1  riastrad 
    225  1.1  riastrad 	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.i9xx_plane);
    226  1.1  riastrad 	if (params->fb.format->cpp[0] == 2)
    227  1.1  riastrad 		threshold++;
    228  1.1  riastrad 
    229  1.1  riastrad 	switch (threshold) {
    230  1.1  riastrad 	case 4:
    231  1.1  riastrad 	case 3:
    232  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
    233  1.1  riastrad 		break;
    234  1.1  riastrad 	case 2:
    235  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
    236  1.1  riastrad 		break;
    237  1.1  riastrad 	case 1:
    238  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
    239  1.1  riastrad 		break;
    240  1.1  riastrad 	}
    241  1.1  riastrad 
    242  1.1  riastrad 	if (params->fence_id >= 0) {
    243  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_FENCE_EN;
    244  1.1  riastrad 		if (IS_GEN(dev_priv, 5))
    245  1.1  riastrad 			dpfc_ctl |= params->fence_id;
    246  1.1  riastrad 		if (IS_GEN(dev_priv, 6)) {
    247  1.1  riastrad 			I915_WRITE(SNB_DPFC_CTL_SA,
    248  1.1  riastrad 				   SNB_CPU_FENCE_ENABLE |
    249  1.1  riastrad 				   params->fence_id);
    250  1.1  riastrad 			I915_WRITE(DPFC_CPU_FENCE_OFFSET,
    251  1.1  riastrad 				   params->crtc.fence_y_offset);
    252  1.1  riastrad 		}
    253  1.1  riastrad 	} else {
    254  1.1  riastrad 		if (IS_GEN(dev_priv, 6)) {
    255  1.1  riastrad 			I915_WRITE(SNB_DPFC_CTL_SA, 0);
    256  1.1  riastrad 			I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
    257  1.1  riastrad 		}
    258  1.1  riastrad 	}
    259  1.1  riastrad 
    260  1.1  riastrad 	I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
    261  1.1  riastrad 	/* enable it... */
    262  1.1  riastrad 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
    263  1.1  riastrad 
    264  1.1  riastrad 	intel_fbc_recompress(dev_priv);
    265  1.1  riastrad }
    266  1.1  riastrad 
    267  1.1  riastrad static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
    268  1.1  riastrad {
    269  1.1  riastrad 	u32 dpfc_ctl;
    270  1.1  riastrad 
    271  1.1  riastrad 	/* Disable compression */
    272  1.1  riastrad 	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
    273  1.1  riastrad 	if (dpfc_ctl & DPFC_CTL_EN) {
    274  1.1  riastrad 		dpfc_ctl &= ~DPFC_CTL_EN;
    275  1.1  riastrad 		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
    276  1.1  riastrad 	}
    277  1.1  riastrad }
    278  1.1  riastrad 
    279  1.1  riastrad static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
    280  1.1  riastrad {
    281  1.1  riastrad 	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
    282  1.1  riastrad }
    283  1.1  riastrad 
    284  1.1  riastrad static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
    285  1.1  riastrad {
    286  1.1  riastrad 	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
    287  1.1  riastrad 	u32 dpfc_ctl;
    288  1.1  riastrad 	int threshold = dev_priv->fbc.threshold;
    289  1.1  riastrad 
    290  1.1  riastrad 	/* Display WA #0529: skl, kbl, bxt. */
    291  1.1  riastrad 	if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) {
    292  1.1  riastrad 		u32 val = I915_READ(CHICKEN_MISC_4);
    293  1.1  riastrad 
    294  1.1  riastrad 		val &= ~(FBC_STRIDE_OVERRIDE | FBC_STRIDE_MASK);
    295  1.1  riastrad 
    296  1.1  riastrad 		if (params->gen9_wa_cfb_stride)
    297  1.1  riastrad 			val |= FBC_STRIDE_OVERRIDE | params->gen9_wa_cfb_stride;
    298  1.1  riastrad 
    299  1.1  riastrad 		I915_WRITE(CHICKEN_MISC_4, val);
    300  1.1  riastrad 	}
    301  1.1  riastrad 
    302  1.1  riastrad 	dpfc_ctl = 0;
    303  1.1  riastrad 	if (IS_IVYBRIDGE(dev_priv))
    304  1.1  riastrad 		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.i9xx_plane);
    305  1.1  riastrad 
    306  1.1  riastrad 	if (params->fb.format->cpp[0] == 2)
    307  1.1  riastrad 		threshold++;
    308  1.1  riastrad 
    309  1.1  riastrad 	switch (threshold) {
    310  1.1  riastrad 	case 4:
    311  1.1  riastrad 	case 3:
    312  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
    313  1.1  riastrad 		break;
    314  1.1  riastrad 	case 2:
    315  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
    316  1.1  riastrad 		break;
    317  1.1  riastrad 	case 1:
    318  1.1  riastrad 		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
    319  1.1  riastrad 		break;
    320  1.1  riastrad 	}
    321  1.1  riastrad 
    322  1.1  riastrad 	if (params->fence_id >= 0) {
    323  1.1  riastrad 		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
    324  1.1  riastrad 		I915_WRITE(SNB_DPFC_CTL_SA,
    325  1.1  riastrad 			   SNB_CPU_FENCE_ENABLE |
    326  1.1  riastrad 			   params->fence_id);
    327  1.1  riastrad 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
    328  1.1  riastrad 	} else {
    329  1.1  riastrad 		I915_WRITE(SNB_DPFC_CTL_SA,0);
    330  1.1  riastrad 		I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
    331  1.1  riastrad 	}
    332  1.1  riastrad 
    333  1.1  riastrad 	if (dev_priv->fbc.false_color)
    334  1.1  riastrad 		dpfc_ctl |= FBC_CTL_FALSE_COLOR;
    335  1.1  riastrad 
    336  1.1  riastrad 	if (IS_IVYBRIDGE(dev_priv)) {
    337  1.1  riastrad 		/* WaFbcAsynchFlipDisableFbcQueue:ivb */
    338  1.1  riastrad 		I915_WRITE(ILK_DISPLAY_CHICKEN1,
    339  1.1  riastrad 			   I915_READ(ILK_DISPLAY_CHICKEN1) |
    340  1.1  riastrad 			   ILK_FBCQ_DIS);
    341  1.1  riastrad 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
    342  1.1  riastrad 		/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
    343  1.1  riastrad 		I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
    344  1.1  riastrad 			   I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
    345  1.1  riastrad 			   HSW_FBCQ_DIS);
    346  1.1  riastrad 	}
    347  1.1  riastrad 
    348  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 11)
    349  1.1  riastrad 		/* Wa_1409120013:icl,ehl,tgl */
    350  1.1  riastrad 		I915_WRITE(ILK_DPFC_CHICKEN, ILK_DPFC_CHICKEN_COMP_DUMMY_PIXEL);
    351  1.1  riastrad 
    352  1.1  riastrad 	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
    353  1.1  riastrad 
    354  1.1  riastrad 	intel_fbc_recompress(dev_priv);
    355  1.1  riastrad }
    356  1.1  riastrad 
    357  1.1  riastrad static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
    358  1.1  riastrad {
    359  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 5)
    360  1.1  riastrad 		return ilk_fbc_is_active(dev_priv);
    361  1.1  riastrad 	else if (IS_GM45(dev_priv))
    362  1.1  riastrad 		return g4x_fbc_is_active(dev_priv);
    363  1.1  riastrad 	else
    364  1.1  riastrad 		return i8xx_fbc_is_active(dev_priv);
    365  1.1  riastrad }
    366  1.1  riastrad 
    367  1.1  riastrad static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
    368  1.1  riastrad {
    369  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    370  1.1  riastrad 
    371  1.1  riastrad 	fbc->active = true;
    372  1.1  riastrad 	fbc->activated = true;
    373  1.1  riastrad 
    374  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 7)
    375  1.1  riastrad 		gen7_fbc_activate(dev_priv);
    376  1.1  riastrad 	else if (INTEL_GEN(dev_priv) >= 5)
    377  1.1  riastrad 		ilk_fbc_activate(dev_priv);
    378  1.1  riastrad 	else if (IS_GM45(dev_priv))
    379  1.1  riastrad 		g4x_fbc_activate(dev_priv);
    380  1.1  riastrad 	else
    381  1.1  riastrad 		i8xx_fbc_activate(dev_priv);
    382  1.1  riastrad }
    383  1.1  riastrad 
    384  1.1  riastrad static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
    385  1.1  riastrad {
    386  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    387  1.1  riastrad 
    388  1.1  riastrad 	fbc->active = false;
    389  1.1  riastrad 
    390  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 5)
    391  1.1  riastrad 		ilk_fbc_deactivate(dev_priv);
    392  1.1  riastrad 	else if (IS_GM45(dev_priv))
    393  1.1  riastrad 		g4x_fbc_deactivate(dev_priv);
    394  1.1  riastrad 	else
    395  1.1  riastrad 		i8xx_fbc_deactivate(dev_priv);
    396  1.1  riastrad }
    397  1.1  riastrad 
    398  1.1  riastrad /**
    399  1.1  riastrad  * intel_fbc_is_active - Is FBC active?
    400  1.1  riastrad  * @dev_priv: i915 device instance
    401  1.1  riastrad  *
    402  1.1  riastrad  * This function is used to verify the current state of FBC.
    403  1.1  riastrad  *
    404  1.1  riastrad  * FIXME: This should be tracked in the plane config eventually
    405  1.1  riastrad  * instead of queried at runtime for most callers.
    406  1.1  riastrad  */
    407  1.1  riastrad bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
    408  1.1  riastrad {
    409  1.1  riastrad 	return dev_priv->fbc.active;
    410  1.1  riastrad }
    411  1.1  riastrad 
    412  1.1  riastrad static void intel_fbc_deactivate(struct drm_i915_private *dev_priv,
    413  1.1  riastrad 				 const char *reason)
    414  1.1  riastrad {
    415  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    416  1.1  riastrad 
    417  1.1  riastrad 	WARN_ON(!mutex_is_locked(&fbc->lock));
    418  1.1  riastrad 
    419  1.1  riastrad 	if (fbc->active)
    420  1.1  riastrad 		intel_fbc_hw_deactivate(dev_priv);
    421  1.1  riastrad 
    422  1.1  riastrad 	fbc->no_fbc_reason = reason;
    423  1.1  riastrad }
    424  1.1  riastrad 
    425  1.1  riastrad static int find_compression_threshold(struct drm_i915_private *dev_priv,
    426  1.1  riastrad 				      struct drm_mm_node *node,
    427  1.1  riastrad 				      unsigned int size,
    428  1.1  riastrad 				      unsigned int fb_cpp)
    429  1.1  riastrad {
    430  1.1  riastrad 	int compression_threshold = 1;
    431  1.1  riastrad 	int ret;
    432  1.1  riastrad 	u64 end;
    433  1.1  riastrad 
    434  1.1  riastrad 	/* The FBC hardware for BDW/SKL doesn't have access to the stolen
    435  1.1  riastrad 	 * reserved range size, so it always assumes the maximum (8mb) is used.
    436  1.1  riastrad 	 * If we enable FBC using a CFB on that memory range we'll get FIFO
    437  1.1  riastrad 	 * underruns, even if that range is not reserved by the BIOS. */
    438  1.1  riastrad 	if (IS_BROADWELL(dev_priv) || IS_GEN9_BC(dev_priv))
    439  1.1  riastrad 		end = resource_size(&dev_priv->dsm) - 8 * 1024 * 1024;
    440  1.1  riastrad 	else
    441  1.1  riastrad 		end = U64_MAX;
    442  1.1  riastrad 
    443  1.1  riastrad 	/* HACK: This code depends on what we will do in *_enable_fbc. If that
    444  1.1  riastrad 	 * code changes, this code needs to change as well.
    445  1.1  riastrad 	 *
    446  1.1  riastrad 	 * The enable_fbc code will attempt to use one of our 2 compression
    447  1.1  riastrad 	 * thresholds, therefore, in that case, we only have 1 resort.
    448  1.1  riastrad 	 */
    449  1.1  riastrad 
    450  1.1  riastrad 	/* Try to over-allocate to reduce reallocations and fragmentation. */
    451  1.1  riastrad 	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
    452  1.1  riastrad 						   4096, 0, end);
    453  1.1  riastrad 	if (ret == 0)
    454  1.1  riastrad 		return compression_threshold;
    455  1.1  riastrad 
    456  1.1  riastrad again:
    457  1.1  riastrad 	/* HW's ability to limit the CFB is 1:4 */
    458  1.1  riastrad 	if (compression_threshold > 4 ||
    459  1.1  riastrad 	    (fb_cpp == 2 && compression_threshold == 2))
    460  1.1  riastrad 		return 0;
    461  1.1  riastrad 
    462  1.1  riastrad 	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
    463  1.1  riastrad 						   4096, 0, end);
    464  1.1  riastrad 	if (ret && INTEL_GEN(dev_priv) <= 4) {
    465  1.1  riastrad 		return 0;
    466  1.1  riastrad 	} else if (ret) {
    467  1.1  riastrad 		compression_threshold <<= 1;
    468  1.1  riastrad 		goto again;
    469  1.1  riastrad 	} else {
    470  1.1  riastrad 		return compression_threshold;
    471  1.1  riastrad 	}
    472  1.1  riastrad }
    473  1.1  riastrad 
    474  1.1  riastrad static int intel_fbc_alloc_cfb(struct drm_i915_private *dev_priv,
    475  1.1  riastrad 			       unsigned int size, unsigned int fb_cpp)
    476  1.1  riastrad {
    477  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    478  1.1  riastrad 	struct drm_mm_node *uninitialized_var(compressed_llb);
    479  1.1  riastrad 	int ret;
    480  1.1  riastrad 
    481  1.1  riastrad 	WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
    482  1.1  riastrad 
    483  1.1  riastrad 	ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
    484  1.1  riastrad 					 size, fb_cpp);
    485  1.1  riastrad 	if (!ret)
    486  1.1  riastrad 		goto err_llb;
    487  1.1  riastrad 	else if (ret > 1) {
    488  1.1  riastrad 		DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");
    489  1.1  riastrad 
    490  1.1  riastrad 	}
    491  1.1  riastrad 
    492  1.1  riastrad 	fbc->threshold = ret;
    493  1.1  riastrad 
    494  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 5)
    495  1.1  riastrad 		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
    496  1.1  riastrad 	else if (IS_GM45(dev_priv)) {
    497  1.1  riastrad 		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
    498  1.1  riastrad 	} else {
    499  1.1  riastrad 		compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
    500  1.1  riastrad 		if (!compressed_llb)
    501  1.1  riastrad 			goto err_fb;
    502  1.1  riastrad 
    503  1.1  riastrad 		ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
    504  1.1  riastrad 						  4096, 4096);
    505  1.1  riastrad 		if (ret)
    506  1.1  riastrad 			goto err_fb;
    507  1.1  riastrad 
    508  1.1  riastrad 		fbc->compressed_llb = compressed_llb;
    509  1.1  riastrad 
    510  1.1  riastrad 		GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
    511  1.1  riastrad 					     fbc->compressed_fb.start,
    512  1.1  riastrad 					     U32_MAX));
    513  1.1  riastrad 		GEM_BUG_ON(range_overflows_t(u64, dev_priv->dsm.start,
    514  1.1  riastrad 					     fbc->compressed_llb->start,
    515  1.1  riastrad 					     U32_MAX));
    516  1.1  riastrad 		I915_WRITE(FBC_CFB_BASE,
    517  1.1  riastrad 			   dev_priv->dsm.start + fbc->compressed_fb.start);
    518  1.1  riastrad 		I915_WRITE(FBC_LL_BASE,
    519  1.1  riastrad 			   dev_priv->dsm.start + compressed_llb->start);
    520  1.1  riastrad 	}
    521  1.1  riastrad 
    522  1.2  riastrad 	DRM_DEBUG_KMS("reserved %"PRIu64" bytes of contiguous stolen space for FBC, threshold: %d\n",
    523  1.1  riastrad 		      fbc->compressed_fb.size, fbc->threshold);
    524  1.1  riastrad 
    525  1.1  riastrad 	return 0;
    526  1.1  riastrad 
    527  1.1  riastrad err_fb:
    528  1.1  riastrad 	kfree(compressed_llb);
    529  1.1  riastrad 	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
    530  1.1  riastrad err_llb:
    531  1.1  riastrad 	if (drm_mm_initialized(&dev_priv->mm.stolen))
    532  1.1  riastrad 		pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
    533  1.1  riastrad 	return -ENOSPC;
    534  1.1  riastrad }
    535  1.1  riastrad 
    536  1.1  riastrad static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
    537  1.1  riastrad {
    538  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    539  1.1  riastrad 
    540  1.1  riastrad 	if (drm_mm_node_allocated(&fbc->compressed_fb))
    541  1.1  riastrad 		i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
    542  1.1  riastrad 
    543  1.1  riastrad 	if (fbc->compressed_llb) {
    544  1.1  riastrad 		i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
    545  1.1  riastrad 		kfree(fbc->compressed_llb);
    546  1.1  riastrad 	}
    547  1.1  riastrad }
    548  1.1  riastrad 
    549  1.1  riastrad void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
    550  1.1  riastrad {
    551  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    552  1.1  riastrad 
    553  1.1  riastrad 	if (!fbc_supported(dev_priv))
    554  1.1  riastrad 		return;
    555  1.1  riastrad 
    556  1.1  riastrad 	mutex_lock(&fbc->lock);
    557  1.1  riastrad 	__intel_fbc_cleanup_cfb(dev_priv);
    558  1.1  riastrad 	mutex_unlock(&fbc->lock);
    559  1.1  riastrad }
    560  1.1  riastrad 
    561  1.1  riastrad static bool stride_is_valid(struct drm_i915_private *dev_priv,
    562  1.1  riastrad 			    unsigned int stride)
    563  1.1  riastrad {
    564  1.1  riastrad 	/* This should have been caught earlier. */
    565  1.1  riastrad 	if (WARN_ON_ONCE((stride & (64 - 1)) != 0))
    566  1.1  riastrad 		return false;
    567  1.1  riastrad 
    568  1.1  riastrad 	/* Below are the additional FBC restrictions. */
    569  1.1  riastrad 	if (stride < 512)
    570  1.1  riastrad 		return false;
    571  1.1  riastrad 
    572  1.1  riastrad 	if (IS_GEN(dev_priv, 2) || IS_GEN(dev_priv, 3))
    573  1.1  riastrad 		return stride == 4096 || stride == 8192;
    574  1.1  riastrad 
    575  1.1  riastrad 	if (IS_GEN(dev_priv, 4) && !IS_G4X(dev_priv) && stride < 2048)
    576  1.1  riastrad 		return false;
    577  1.1  riastrad 
    578  1.1  riastrad 	if (stride > 16384)
    579  1.1  riastrad 		return false;
    580  1.1  riastrad 
    581  1.1  riastrad 	return true;
    582  1.1  riastrad }
    583  1.1  riastrad 
    584  1.1  riastrad static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
    585  1.1  riastrad 				  u32 pixel_format)
    586  1.1  riastrad {
    587  1.1  riastrad 	switch (pixel_format) {
    588  1.1  riastrad 	case DRM_FORMAT_XRGB8888:
    589  1.1  riastrad 	case DRM_FORMAT_XBGR8888:
    590  1.1  riastrad 		return true;
    591  1.1  riastrad 	case DRM_FORMAT_XRGB1555:
    592  1.1  riastrad 	case DRM_FORMAT_RGB565:
    593  1.1  riastrad 		/* 16bpp not supported on gen2 */
    594  1.1  riastrad 		if (IS_GEN(dev_priv, 2))
    595  1.1  riastrad 			return false;
    596  1.1  riastrad 		/* WaFbcOnly1to1Ratio:ctg */
    597  1.1  riastrad 		if (IS_G4X(dev_priv))
    598  1.1  riastrad 			return false;
    599  1.1  riastrad 		return true;
    600  1.1  riastrad 	default:
    601  1.1  riastrad 		return false;
    602  1.1  riastrad 	}
    603  1.1  riastrad }
    604  1.1  riastrad 
    605  1.1  riastrad /*
    606  1.1  riastrad  * For some reason, the hardware tracking starts looking at whatever we
    607  1.1  riastrad  * programmed as the display plane base address register. It does not look at
    608  1.1  riastrad  * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
    609  1.1  riastrad  * variables instead of just looking at the pipe/plane size.
    610  1.1  riastrad  */
    611  1.1  riastrad static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
    612  1.1  riastrad {
    613  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    614  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    615  1.1  riastrad 	unsigned int effective_w, effective_h, max_w, max_h;
    616  1.1  riastrad 
    617  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
    618  1.1  riastrad 		max_w = 5120;
    619  1.1  riastrad 		max_h = 4096;
    620  1.1  riastrad 	} else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
    621  1.1  riastrad 		max_w = 4096;
    622  1.1  riastrad 		max_h = 4096;
    623  1.1  riastrad 	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
    624  1.1  riastrad 		max_w = 4096;
    625  1.1  riastrad 		max_h = 2048;
    626  1.1  riastrad 	} else {
    627  1.1  riastrad 		max_w = 2048;
    628  1.1  riastrad 		max_h = 1536;
    629  1.1  riastrad 	}
    630  1.1  riastrad 
    631  1.1  riastrad 	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
    632  1.1  riastrad 					&effective_h);
    633  1.1  riastrad 	effective_w += fbc->state_cache.plane.adjusted_x;
    634  1.1  riastrad 	effective_h += fbc->state_cache.plane.adjusted_y;
    635  1.1  riastrad 
    636  1.1  riastrad 	return effective_w <= max_w && effective_h <= max_h;
    637  1.1  riastrad }
    638  1.1  riastrad 
    639  1.1  riastrad static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
    640  1.1  riastrad 					 const struct intel_crtc_state *crtc_state,
    641  1.1  riastrad 					 const struct intel_plane_state *plane_state)
    642  1.1  riastrad {
    643  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    644  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    645  1.1  riastrad 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
    646  1.1  riastrad 	struct drm_framebuffer *fb = plane_state->hw.fb;
    647  1.1  riastrad 
    648  1.1  riastrad 	cache->plane.visible = plane_state->uapi.visible;
    649  1.1  riastrad 	if (!cache->plane.visible)
    650  1.1  riastrad 		return;
    651  1.1  riastrad 
    652  1.1  riastrad 	cache->crtc.mode_flags = crtc_state->hw.adjusted_mode.flags;
    653  1.1  riastrad 	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
    654  1.1  riastrad 		cache->crtc.hsw_bdw_pixel_rate = crtc_state->pixel_rate;
    655  1.1  riastrad 
    656  1.1  riastrad 	cache->plane.rotation = plane_state->hw.rotation;
    657  1.1  riastrad 	/*
    658  1.1  riastrad 	 * Src coordinates are already rotated by 270 degrees for
    659  1.1  riastrad 	 * the 90/270 degree plane rotation cases (to match the
    660  1.1  riastrad 	 * GTT mapping), hence no need to account for rotation here.
    661  1.1  riastrad 	 */
    662  1.1  riastrad 	cache->plane.src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
    663  1.1  riastrad 	cache->plane.src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
    664  1.1  riastrad 	cache->plane.adjusted_x = plane_state->color_plane[0].x;
    665  1.1  riastrad 	cache->plane.adjusted_y = plane_state->color_plane[0].y;
    666  1.1  riastrad 	cache->plane.y = plane_state->uapi.src.y1 >> 16;
    667  1.1  riastrad 
    668  1.1  riastrad 	cache->plane.pixel_blend_mode = plane_state->hw.pixel_blend_mode;
    669  1.1  riastrad 
    670  1.1  riastrad 	cache->fb.format = fb->format;
    671  1.1  riastrad 	cache->fb.stride = fb->pitches[0];
    672  1.1  riastrad 
    673  1.1  riastrad 	WARN_ON(plane_state->flags & PLANE_HAS_FENCE &&
    674  1.1  riastrad 		!plane_state->vma->fence);
    675  1.1  riastrad 
    676  1.1  riastrad 	if (plane_state->flags & PLANE_HAS_FENCE &&
    677  1.1  riastrad 	    plane_state->vma->fence)
    678  1.1  riastrad 		cache->fence_id = plane_state->vma->fence->id;
    679  1.1  riastrad 	else
    680  1.1  riastrad 		cache->fence_id = -1;
    681  1.1  riastrad }
    682  1.1  riastrad 
    683  1.1  riastrad static bool intel_fbc_cfb_size_changed(struct drm_i915_private *dev_priv)
    684  1.1  riastrad {
    685  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    686  1.1  riastrad 
    687  1.1  riastrad 	return intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
    688  1.1  riastrad 		fbc->compressed_fb.size * fbc->threshold;
    689  1.1  riastrad }
    690  1.1  riastrad 
    691  1.1  riastrad static bool intel_fbc_can_activate(struct intel_crtc *crtc)
    692  1.1  riastrad {
    693  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    694  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    695  1.1  riastrad 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
    696  1.1  riastrad 
    697  1.1  riastrad 	if (!cache->plane.visible) {
    698  1.1  riastrad 		fbc->no_fbc_reason = "primary plane not visible";
    699  1.1  riastrad 		return false;
    700  1.1  riastrad 	}
    701  1.1  riastrad 
    702  1.1  riastrad 	/* We don't need to use a state cache here since this information is
    703  1.1  riastrad 	 * global for all CRTC.
    704  1.1  riastrad 	 */
    705  1.1  riastrad 	if (fbc->underrun_detected) {
    706  1.1  riastrad 		fbc->no_fbc_reason = "underrun detected";
    707  1.1  riastrad 		return false;
    708  1.1  riastrad 	}
    709  1.1  riastrad 
    710  1.1  riastrad 	if (cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) {
    711  1.1  riastrad 		fbc->no_fbc_reason = "incompatible mode";
    712  1.1  riastrad 		return false;
    713  1.1  riastrad 	}
    714  1.1  riastrad 
    715  1.1  riastrad 	if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
    716  1.1  riastrad 		fbc->no_fbc_reason = "mode too large for compression";
    717  1.1  riastrad 		return false;
    718  1.1  riastrad 	}
    719  1.1  riastrad 
    720  1.1  riastrad 	/* The use of a CPU fence is mandatory in order to detect writes
    721  1.1  riastrad 	 * by the CPU to the scanout and trigger updates to the FBC.
    722  1.1  riastrad 	 *
    723  1.1  riastrad 	 * Note that is possible for a tiled surface to be unmappable (and
    724  1.1  riastrad 	 * so have no fence associated with it) due to aperture constaints
    725  1.1  riastrad 	 * at the time of pinning.
    726  1.1  riastrad 	 *
    727  1.1  riastrad 	 * FIXME with 90/270 degree rotation we should use the fence on
    728  1.1  riastrad 	 * the normal GTT view (the rotated view doesn't even have a
    729  1.1  riastrad 	 * fence). Would need changes to the FBC fence Y offset as well.
    730  1.1  riastrad 	 * For now this will effecively disable FBC with 90/270 degree
    731  1.1  riastrad 	 * rotation.
    732  1.1  riastrad 	 */
    733  1.1  riastrad 	if (cache->fence_id < 0) {
    734  1.1  riastrad 		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
    735  1.1  riastrad 		return false;
    736  1.1  riastrad 	}
    737  1.1  riastrad 	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
    738  1.1  riastrad 	    cache->plane.rotation != DRM_MODE_ROTATE_0) {
    739  1.1  riastrad 		fbc->no_fbc_reason = "rotation unsupported";
    740  1.1  riastrad 		return false;
    741  1.1  riastrad 	}
    742  1.1  riastrad 
    743  1.1  riastrad 	if (!stride_is_valid(dev_priv, cache->fb.stride)) {
    744  1.1  riastrad 		fbc->no_fbc_reason = "framebuffer stride not supported";
    745  1.1  riastrad 		return false;
    746  1.1  riastrad 	}
    747  1.1  riastrad 
    748  1.1  riastrad 	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
    749  1.1  riastrad 		fbc->no_fbc_reason = "pixel format is invalid";
    750  1.1  riastrad 		return false;
    751  1.1  riastrad 	}
    752  1.1  riastrad 
    753  1.1  riastrad 	if (cache->plane.pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
    754  1.1  riastrad 	    cache->fb.format->has_alpha) {
    755  1.1  riastrad 		fbc->no_fbc_reason = "per-pixel alpha blending is incompatible with FBC";
    756  1.1  riastrad 		return false;
    757  1.1  riastrad 	}
    758  1.1  riastrad 
    759  1.1  riastrad 	/* WaFbcExceedCdClockThreshold:hsw,bdw */
    760  1.1  riastrad 	if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
    761  1.1  riastrad 	    cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk.hw.cdclk * 95 / 100) {
    762  1.1  riastrad 		fbc->no_fbc_reason = "pixel rate is too big";
    763  1.1  riastrad 		return false;
    764  1.1  riastrad 	}
    765  1.1  riastrad 
    766  1.1  riastrad 	/* It is possible for the required CFB size change without a
    767  1.1  riastrad 	 * crtc->disable + crtc->enable since it is possible to change the
    768  1.1  riastrad 	 * stride without triggering a full modeset. Since we try to
    769  1.1  riastrad 	 * over-allocate the CFB, there's a chance we may keep FBC enabled even
    770  1.1  riastrad 	 * if this happens, but if we exceed the current CFB size we'll have to
    771  1.1  riastrad 	 * disable FBC. Notice that it would be possible to disable FBC, wait
    772  1.1  riastrad 	 * for a frame, free the stolen node, then try to reenable FBC in case
    773  1.1  riastrad 	 * we didn't get any invalidate/deactivate calls, but this would require
    774  1.1  riastrad 	 * a lot of tracking just for a specific case. If we conclude it's an
    775  1.1  riastrad 	 * important case, we can implement it later. */
    776  1.1  riastrad 	if (intel_fbc_cfb_size_changed(dev_priv)) {
    777  1.1  riastrad 		fbc->no_fbc_reason = "CFB requirements changed";
    778  1.1  riastrad 		return false;
    779  1.1  riastrad 	}
    780  1.1  riastrad 
    781  1.1  riastrad 	/*
    782  1.1  riastrad 	 * Work around a problem on GEN9+ HW, where enabling FBC on a plane
    783  1.1  riastrad 	 * having a Y offset that isn't divisible by 4 causes FIFO underrun
    784  1.1  riastrad 	 * and screen flicker.
    785  1.1  riastrad 	 */
    786  1.1  riastrad 	if (INTEL_GEN(dev_priv) >= 9 &&
    787  1.1  riastrad 	    (fbc->state_cache.plane.adjusted_y & 3)) {
    788  1.1  riastrad 		fbc->no_fbc_reason = "plane Y offset is misaligned";
    789  1.1  riastrad 		return false;
    790  1.1  riastrad 	}
    791  1.1  riastrad 
    792  1.1  riastrad 	return true;
    793  1.1  riastrad }
    794  1.1  riastrad 
    795  1.1  riastrad static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
    796  1.1  riastrad {
    797  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    798  1.1  riastrad 
    799  1.1  riastrad 	if (intel_vgpu_active(dev_priv)) {
    800  1.1  riastrad 		fbc->no_fbc_reason = "VGPU is active";
    801  1.1  riastrad 		return false;
    802  1.1  riastrad 	}
    803  1.1  riastrad 
    804  1.1  riastrad 	if (!i915_modparams.enable_fbc) {
    805  1.1  riastrad 		fbc->no_fbc_reason = "disabled per module param or by default";
    806  1.1  riastrad 		return false;
    807  1.1  riastrad 	}
    808  1.1  riastrad 
    809  1.1  riastrad 	if (fbc->underrun_detected) {
    810  1.1  riastrad 		fbc->no_fbc_reason = "underrun detected";
    811  1.1  riastrad 		return false;
    812  1.1  riastrad 	}
    813  1.1  riastrad 
    814  1.1  riastrad 	return true;
    815  1.1  riastrad }
    816  1.1  riastrad 
    817  1.1  riastrad static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
    818  1.1  riastrad 				     struct intel_fbc_reg_params *params)
    819  1.1  riastrad {
    820  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    821  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    822  1.1  riastrad 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
    823  1.1  riastrad 
    824  1.1  riastrad 	/* Since all our fields are integer types, use memset here so the
    825  1.1  riastrad 	 * comparison function can rely on memcmp because the padding will be
    826  1.1  riastrad 	 * zero. */
    827  1.1  riastrad 	memset(params, 0, sizeof(*params));
    828  1.1  riastrad 
    829  1.1  riastrad 	params->fence_id = cache->fence_id;
    830  1.1  riastrad 
    831  1.1  riastrad 	params->crtc.pipe = crtc->pipe;
    832  1.1  riastrad 	params->crtc.i9xx_plane = to_intel_plane(crtc->base.primary)->i9xx_plane;
    833  1.1  riastrad 	params->crtc.fence_y_offset = get_crtc_fence_y_offset(fbc);
    834  1.1  riastrad 
    835  1.1  riastrad 	params->fb.format = cache->fb.format;
    836  1.1  riastrad 	params->fb.stride = cache->fb.stride;
    837  1.1  riastrad 
    838  1.1  riastrad 	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
    839  1.1  riastrad 
    840  1.1  riastrad 	params->gen9_wa_cfb_stride = cache->gen9_wa_cfb_stride;
    841  1.1  riastrad 
    842  1.1  riastrad 	params->plane_visible = cache->plane.visible;
    843  1.1  riastrad }
    844  1.1  riastrad 
    845  1.1  riastrad static bool intel_fbc_can_flip_nuke(const struct intel_crtc_state *crtc_state)
    846  1.1  riastrad {
    847  1.1  riastrad 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
    848  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    849  1.1  riastrad 	const struct intel_fbc *fbc = &dev_priv->fbc;
    850  1.1  riastrad 	const struct intel_fbc_state_cache *cache = &fbc->state_cache;
    851  1.1  riastrad 	const struct intel_fbc_reg_params *params = &fbc->params;
    852  1.1  riastrad 
    853  1.1  riastrad 	if (drm_atomic_crtc_needs_modeset(&crtc_state->uapi))
    854  1.1  riastrad 		return false;
    855  1.1  riastrad 
    856  1.1  riastrad 	if (!params->plane_visible)
    857  1.1  riastrad 		return false;
    858  1.1  riastrad 
    859  1.1  riastrad 	if (!intel_fbc_can_activate(crtc))
    860  1.1  riastrad 		return false;
    861  1.1  riastrad 
    862  1.1  riastrad 	if (params->fb.format != cache->fb.format)
    863  1.1  riastrad 		return false;
    864  1.1  riastrad 
    865  1.1  riastrad 	if (params->fb.stride != cache->fb.stride)
    866  1.1  riastrad 		return false;
    867  1.1  riastrad 
    868  1.1  riastrad 	if (params->cfb_size != intel_fbc_calculate_cfb_size(dev_priv, cache))
    869  1.1  riastrad 		return false;
    870  1.1  riastrad 
    871  1.1  riastrad 	if (params->gen9_wa_cfb_stride != cache->gen9_wa_cfb_stride)
    872  1.1  riastrad 		return false;
    873  1.1  riastrad 
    874  1.1  riastrad 	return true;
    875  1.1  riastrad }
    876  1.1  riastrad 
    877  1.1  riastrad bool intel_fbc_pre_update(struct intel_crtc *crtc,
    878  1.1  riastrad 			  const struct intel_crtc_state *crtc_state,
    879  1.1  riastrad 			  const struct intel_plane_state *plane_state)
    880  1.1  riastrad {
    881  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    882  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    883  1.1  riastrad 	const char *reason = "update pending";
    884  1.1  riastrad 	bool need_vblank_wait = false;
    885  1.1  riastrad 
    886  1.1  riastrad 	if (!fbc_supported(dev_priv))
    887  1.1  riastrad 		return need_vblank_wait;
    888  1.1  riastrad 
    889  1.1  riastrad 	mutex_lock(&fbc->lock);
    890  1.1  riastrad 
    891  1.1  riastrad 	if (fbc->crtc != crtc)
    892  1.1  riastrad 		goto unlock;
    893  1.1  riastrad 
    894  1.1  riastrad 	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
    895  1.1  riastrad 	fbc->flip_pending = true;
    896  1.1  riastrad 
    897  1.1  riastrad 	if (!intel_fbc_can_flip_nuke(crtc_state)) {
    898  1.1  riastrad 		intel_fbc_deactivate(dev_priv, reason);
    899  1.1  riastrad 
    900  1.1  riastrad 		/*
    901  1.1  riastrad 		 * Display WA #1198: glk+
    902  1.1  riastrad 		 * Need an extra vblank wait between FBC disable and most plane
    903  1.1  riastrad 		 * updates. Bspec says this is only needed for plane disable, but
    904  1.1  riastrad 		 * that is not true. Touching most plane registers will cause the
    905  1.1  riastrad 		 * corruption to appear. Also SKL/derivatives do not seem to be
    906  1.1  riastrad 		 * affected.
    907  1.1  riastrad 		 *
    908  1.1  riastrad 		 * TODO: could optimize this a bit by sampling the frame
    909  1.1  riastrad 		 * counter when we disable FBC (if it was already done earlier)
    910  1.1  riastrad 		 * and skipping the extra vblank wait before the plane update
    911  1.1  riastrad 		 * if at least one frame has already passed.
    912  1.1  riastrad 		 */
    913  1.1  riastrad 		if (fbc->activated &&
    914  1.1  riastrad 		    (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)))
    915  1.1  riastrad 			need_vblank_wait = true;
    916  1.1  riastrad 		fbc->activated = false;
    917  1.1  riastrad 	}
    918  1.1  riastrad unlock:
    919  1.1  riastrad 	mutex_unlock(&fbc->lock);
    920  1.1  riastrad 
    921  1.1  riastrad 	return need_vblank_wait;
    922  1.1  riastrad }
    923  1.1  riastrad 
    924  1.1  riastrad /**
    925  1.1  riastrad  * __intel_fbc_disable - disable FBC
    926  1.1  riastrad  * @dev_priv: i915 device instance
    927  1.1  riastrad  *
    928  1.1  riastrad  * This is the low level function that actually disables FBC. Callers should
    929  1.1  riastrad  * grab the FBC lock.
    930  1.1  riastrad  */
    931  1.1  riastrad static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
    932  1.1  riastrad {
    933  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    934  1.1  riastrad 	struct intel_crtc *crtc = fbc->crtc;
    935  1.1  riastrad 
    936  1.1  riastrad 	WARN_ON(!mutex_is_locked(&fbc->lock));
    937  1.1  riastrad 	WARN_ON(!fbc->crtc);
    938  1.1  riastrad 	WARN_ON(fbc->active);
    939  1.1  riastrad 
    940  1.1  riastrad 	DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));
    941  1.1  riastrad 
    942  1.1  riastrad 	__intel_fbc_cleanup_cfb(dev_priv);
    943  1.1  riastrad 
    944  1.1  riastrad 	fbc->crtc = NULL;
    945  1.1  riastrad }
    946  1.1  riastrad 
    947  1.1  riastrad static void __intel_fbc_post_update(struct intel_crtc *crtc)
    948  1.1  riastrad {
    949  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    950  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    951  1.1  riastrad 
    952  1.1  riastrad 	WARN_ON(!mutex_is_locked(&fbc->lock));
    953  1.1  riastrad 
    954  1.1  riastrad 	if (fbc->crtc != crtc)
    955  1.1  riastrad 		return;
    956  1.1  riastrad 
    957  1.1  riastrad 	fbc->flip_pending = false;
    958  1.1  riastrad 
    959  1.1  riastrad 	if (!i915_modparams.enable_fbc) {
    960  1.1  riastrad 		intel_fbc_deactivate(dev_priv, "disabled at runtime per module param");
    961  1.1  riastrad 		__intel_fbc_disable(dev_priv);
    962  1.1  riastrad 
    963  1.1  riastrad 		return;
    964  1.1  riastrad 	}
    965  1.1  riastrad 
    966  1.1  riastrad 	intel_fbc_get_reg_params(crtc, &fbc->params);
    967  1.1  riastrad 
    968  1.1  riastrad 	if (!intel_fbc_can_activate(crtc))
    969  1.1  riastrad 		return;
    970  1.1  riastrad 
    971  1.1  riastrad 	if (!fbc->busy_bits)
    972  1.1  riastrad 		intel_fbc_hw_activate(dev_priv);
    973  1.1  riastrad 	else
    974  1.1  riastrad 		intel_fbc_deactivate(dev_priv, "frontbuffer write");
    975  1.1  riastrad }
    976  1.1  riastrad 
    977  1.1  riastrad void intel_fbc_post_update(struct intel_crtc *crtc)
    978  1.1  riastrad {
    979  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
    980  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
    981  1.1  riastrad 
    982  1.1  riastrad 	if (!fbc_supported(dev_priv))
    983  1.1  riastrad 		return;
    984  1.1  riastrad 
    985  1.1  riastrad 	mutex_lock(&fbc->lock);
    986  1.1  riastrad 	__intel_fbc_post_update(crtc);
    987  1.1  riastrad 	mutex_unlock(&fbc->lock);
    988  1.1  riastrad }
    989  1.1  riastrad 
    990  1.1  riastrad static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
    991  1.1  riastrad {
    992  1.1  riastrad 	if (fbc->crtc)
    993  1.1  riastrad 		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
    994  1.1  riastrad 	else
    995  1.1  riastrad 		return fbc->possible_framebuffer_bits;
    996  1.1  riastrad }
    997  1.1  riastrad 
    998  1.1  riastrad void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
    999  1.1  riastrad 			  unsigned int frontbuffer_bits,
   1000  1.1  riastrad 			  enum fb_op_origin origin)
   1001  1.1  riastrad {
   1002  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1003  1.1  riastrad 
   1004  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1005  1.1  riastrad 		return;
   1006  1.1  riastrad 
   1007  1.1  riastrad 	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
   1008  1.1  riastrad 		return;
   1009  1.1  riastrad 
   1010  1.1  riastrad 	mutex_lock(&fbc->lock);
   1011  1.1  riastrad 
   1012  1.1  riastrad 	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
   1013  1.1  riastrad 
   1014  1.1  riastrad 	if (fbc->crtc && fbc->busy_bits)
   1015  1.1  riastrad 		intel_fbc_deactivate(dev_priv, "frontbuffer write");
   1016  1.1  riastrad 
   1017  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1018  1.1  riastrad }
   1019  1.1  riastrad 
   1020  1.1  riastrad void intel_fbc_flush(struct drm_i915_private *dev_priv,
   1021  1.1  riastrad 		     unsigned int frontbuffer_bits, enum fb_op_origin origin)
   1022  1.1  riastrad {
   1023  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1024  1.1  riastrad 
   1025  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1026  1.1  riastrad 		return;
   1027  1.1  riastrad 
   1028  1.1  riastrad 	mutex_lock(&fbc->lock);
   1029  1.1  riastrad 
   1030  1.1  riastrad 	fbc->busy_bits &= ~frontbuffer_bits;
   1031  1.1  riastrad 
   1032  1.1  riastrad 	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
   1033  1.1  riastrad 		goto out;
   1034  1.1  riastrad 
   1035  1.1  riastrad 	if (!fbc->busy_bits && fbc->crtc &&
   1036  1.1  riastrad 	    (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
   1037  1.1  riastrad 		if (fbc->active)
   1038  1.1  riastrad 			intel_fbc_recompress(dev_priv);
   1039  1.1  riastrad 		else if (!fbc->flip_pending)
   1040  1.1  riastrad 			__intel_fbc_post_update(fbc->crtc);
   1041  1.1  riastrad 	}
   1042  1.1  riastrad 
   1043  1.1  riastrad out:
   1044  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1045  1.1  riastrad }
   1046  1.1  riastrad 
   1047  1.1  riastrad /**
   1048  1.1  riastrad  * intel_fbc_choose_crtc - select a CRTC to enable FBC on
   1049  1.1  riastrad  * @dev_priv: i915 device instance
   1050  1.1  riastrad  * @state: the atomic state structure
   1051  1.1  riastrad  *
   1052  1.1  riastrad  * This function looks at the proposed state for CRTCs and planes, then chooses
   1053  1.1  riastrad  * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
   1054  1.1  riastrad  * true.
   1055  1.1  riastrad  *
   1056  1.1  riastrad  * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
   1057  1.1  riastrad  * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
   1058  1.1  riastrad  */
   1059  1.1  riastrad void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
   1060  1.1  riastrad 			   struct intel_atomic_state *state)
   1061  1.1  riastrad {
   1062  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1063  1.1  riastrad 	struct intel_plane *plane;
   1064  1.1  riastrad 	struct intel_plane_state *plane_state;
   1065  1.1  riastrad 	bool crtc_chosen = false;
   1066  1.1  riastrad 	int i;
   1067  1.1  riastrad 
   1068  1.1  riastrad 	mutex_lock(&fbc->lock);
   1069  1.1  riastrad 
   1070  1.1  riastrad 	/* Does this atomic commit involve the CRTC currently tied to FBC? */
   1071  1.1  riastrad 	if (fbc->crtc &&
   1072  1.1  riastrad 	    !intel_atomic_get_new_crtc_state(state, fbc->crtc))
   1073  1.1  riastrad 		goto out;
   1074  1.1  riastrad 
   1075  1.1  riastrad 	if (!intel_fbc_can_enable(dev_priv))
   1076  1.1  riastrad 		goto out;
   1077  1.1  riastrad 
   1078  1.1  riastrad 	/* Simply choose the first CRTC that is compatible and has a visible
   1079  1.1  riastrad 	 * plane. We could go for fancier schemes such as checking the plane
   1080  1.1  riastrad 	 * size, but this would just affect the few platforms that don't tie FBC
   1081  1.1  riastrad 	 * to pipe or plane A. */
   1082  1.1  riastrad 	for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
   1083  1.1  riastrad 		struct intel_crtc_state *crtc_state;
   1084  1.1  riastrad 		struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
   1085  1.1  riastrad 
   1086  1.1  riastrad 		if (!plane->has_fbc)
   1087  1.1  riastrad 			continue;
   1088  1.1  riastrad 
   1089  1.1  riastrad 		if (!plane_state->uapi.visible)
   1090  1.1  riastrad 			continue;
   1091  1.1  riastrad 
   1092  1.1  riastrad 		crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
   1093  1.1  riastrad 
   1094  1.1  riastrad 		crtc_state->enable_fbc = true;
   1095  1.1  riastrad 		crtc_chosen = true;
   1096  1.1  riastrad 		break;
   1097  1.1  riastrad 	}
   1098  1.1  riastrad 
   1099  1.1  riastrad 	if (!crtc_chosen)
   1100  1.1  riastrad 		fbc->no_fbc_reason = "no suitable CRTC for FBC";
   1101  1.1  riastrad 
   1102  1.1  riastrad out:
   1103  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1104  1.1  riastrad }
   1105  1.1  riastrad 
   1106  1.1  riastrad /**
   1107  1.1  riastrad  * intel_fbc_enable: tries to enable FBC on the CRTC
   1108  1.1  riastrad  * @crtc: the CRTC
   1109  1.1  riastrad  * @crtc_state: corresponding &drm_crtc_state for @crtc
   1110  1.1  riastrad  * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
   1111  1.1  riastrad  *
   1112  1.1  riastrad  * This function checks if the given CRTC was chosen for FBC, then enables it if
   1113  1.1  riastrad  * possible. Notice that it doesn't activate FBC. It is valid to call
   1114  1.1  riastrad  * intel_fbc_enable multiple times for the same pipe without an
   1115  1.1  riastrad  * intel_fbc_disable in the middle, as long as it is deactivated.
   1116  1.1  riastrad  */
   1117  1.1  riastrad void intel_fbc_enable(struct intel_crtc *crtc,
   1118  1.1  riastrad 		      const struct intel_crtc_state *crtc_state,
   1119  1.1  riastrad 		      const struct intel_plane_state *plane_state)
   1120  1.1  riastrad {
   1121  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
   1122  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1123  1.1  riastrad 	struct intel_fbc_state_cache *cache = &fbc->state_cache;
   1124  1.1  riastrad 	const struct drm_framebuffer *fb = plane_state->hw.fb;
   1125  1.1  riastrad 
   1126  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1127  1.1  riastrad 		return;
   1128  1.1  riastrad 
   1129  1.1  riastrad 	mutex_lock(&fbc->lock);
   1130  1.1  riastrad 
   1131  1.1  riastrad 	if (fbc->crtc) {
   1132  1.1  riastrad 		if (fbc->crtc != crtc ||
   1133  1.1  riastrad 		    !intel_fbc_cfb_size_changed(dev_priv))
   1134  1.1  riastrad 			goto out;
   1135  1.1  riastrad 
   1136  1.1  riastrad 		__intel_fbc_disable(dev_priv);
   1137  1.1  riastrad 	}
   1138  1.1  riastrad 
   1139  1.1  riastrad 	WARN_ON(fbc->active);
   1140  1.1  riastrad 
   1141  1.1  riastrad 	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
   1142  1.1  riastrad 
   1143  1.1  riastrad 	/* FIXME crtc_state->enable_fbc lies :( */
   1144  1.1  riastrad 	if (!cache->plane.visible)
   1145  1.1  riastrad 		goto out;
   1146  1.1  riastrad 
   1147  1.1  riastrad 	if (intel_fbc_alloc_cfb(dev_priv,
   1148  1.1  riastrad 				intel_fbc_calculate_cfb_size(dev_priv, cache),
   1149  1.1  riastrad 				fb->format->cpp[0])) {
   1150  1.1  riastrad 		cache->plane.visible = false;
   1151  1.1  riastrad 		fbc->no_fbc_reason = "not enough stolen memory";
   1152  1.1  riastrad 		goto out;
   1153  1.1  riastrad 	}
   1154  1.1  riastrad 
   1155  1.1  riastrad 	if ((IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) &&
   1156  1.1  riastrad 	    fb->modifier != I915_FORMAT_MOD_X_TILED)
   1157  1.1  riastrad 		cache->gen9_wa_cfb_stride =
   1158  1.1  riastrad 			DIV_ROUND_UP(cache->plane.src_w, 32 * fbc->threshold) * 8;
   1159  1.1  riastrad 	else
   1160  1.1  riastrad 		cache->gen9_wa_cfb_stride = 0;
   1161  1.1  riastrad 
   1162  1.1  riastrad 	DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
   1163  1.1  riastrad 	fbc->no_fbc_reason = "FBC enabled but not active yet\n";
   1164  1.1  riastrad 
   1165  1.1  riastrad 	fbc->crtc = crtc;
   1166  1.1  riastrad out:
   1167  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1168  1.1  riastrad }
   1169  1.1  riastrad 
   1170  1.1  riastrad /**
   1171  1.1  riastrad  * intel_fbc_disable - disable FBC if it's associated with crtc
   1172  1.1  riastrad  * @crtc: the CRTC
   1173  1.1  riastrad  *
   1174  1.1  riastrad  * This function disables FBC if it's associated with the provided CRTC.
   1175  1.1  riastrad  */
   1176  1.1  riastrad void intel_fbc_disable(struct intel_crtc *crtc)
   1177  1.1  riastrad {
   1178  1.1  riastrad 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
   1179  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1180  1.1  riastrad 
   1181  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1182  1.1  riastrad 		return;
   1183  1.1  riastrad 
   1184  1.1  riastrad 	mutex_lock(&fbc->lock);
   1185  1.1  riastrad 	if (fbc->crtc == crtc)
   1186  1.1  riastrad 		__intel_fbc_disable(dev_priv);
   1187  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1188  1.1  riastrad }
   1189  1.1  riastrad 
   1190  1.1  riastrad /**
   1191  1.1  riastrad  * intel_fbc_global_disable - globally disable FBC
   1192  1.1  riastrad  * @dev_priv: i915 device instance
   1193  1.1  riastrad  *
   1194  1.1  riastrad  * This function disables FBC regardless of which CRTC is associated with it.
   1195  1.1  riastrad  */
   1196  1.1  riastrad void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
   1197  1.1  riastrad {
   1198  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1199  1.1  riastrad 
   1200  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1201  1.1  riastrad 		return;
   1202  1.1  riastrad 
   1203  1.1  riastrad 	mutex_lock(&fbc->lock);
   1204  1.1  riastrad 	if (fbc->crtc) {
   1205  1.1  riastrad 		WARN_ON(fbc->crtc->active);
   1206  1.1  riastrad 		__intel_fbc_disable(dev_priv);
   1207  1.1  riastrad 	}
   1208  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1209  1.1  riastrad }
   1210  1.1  riastrad 
   1211  1.1  riastrad static void intel_fbc_underrun_work_fn(struct work_struct *work)
   1212  1.1  riastrad {
   1213  1.1  riastrad 	struct drm_i915_private *dev_priv =
   1214  1.1  riastrad 		container_of(work, struct drm_i915_private, fbc.underrun_work);
   1215  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1216  1.1  riastrad 
   1217  1.1  riastrad 	mutex_lock(&fbc->lock);
   1218  1.1  riastrad 
   1219  1.1  riastrad 	/* Maybe we were scheduled twice. */
   1220  1.1  riastrad 	if (fbc->underrun_detected || !fbc->crtc)
   1221  1.1  riastrad 		goto out;
   1222  1.1  riastrad 
   1223  1.1  riastrad 	DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
   1224  1.1  riastrad 	fbc->underrun_detected = true;
   1225  1.1  riastrad 
   1226  1.1  riastrad 	intel_fbc_deactivate(dev_priv, "FIFO underrun");
   1227  1.1  riastrad out:
   1228  1.1  riastrad 	mutex_unlock(&fbc->lock);
   1229  1.1  riastrad }
   1230  1.1  riastrad 
   1231  1.1  riastrad /*
   1232  1.1  riastrad  * intel_fbc_reset_underrun - reset FBC fifo underrun status.
   1233  1.1  riastrad  * @dev_priv: i915 device instance
   1234  1.1  riastrad  *
   1235  1.1  riastrad  * See intel_fbc_handle_fifo_underrun_irq(). For automated testing we
   1236  1.1  riastrad  * want to re-enable FBC after an underrun to increase test coverage.
   1237  1.1  riastrad  */
   1238  1.1  riastrad int intel_fbc_reset_underrun(struct drm_i915_private *dev_priv)
   1239  1.1  riastrad {
   1240  1.1  riastrad 	int ret;
   1241  1.1  riastrad 
   1242  1.1  riastrad 	cancel_work_sync(&dev_priv->fbc.underrun_work);
   1243  1.1  riastrad 
   1244  1.1  riastrad 	ret = mutex_lock_interruptible(&dev_priv->fbc.lock);
   1245  1.1  riastrad 	if (ret)
   1246  1.1  riastrad 		return ret;
   1247  1.1  riastrad 
   1248  1.1  riastrad 	if (dev_priv->fbc.underrun_detected) {
   1249  1.1  riastrad 		DRM_DEBUG_KMS("Re-allowing FBC after fifo underrun\n");
   1250  1.1  riastrad 		dev_priv->fbc.no_fbc_reason = "FIFO underrun cleared";
   1251  1.1  riastrad 	}
   1252  1.1  riastrad 
   1253  1.1  riastrad 	dev_priv->fbc.underrun_detected = false;
   1254  1.1  riastrad 	mutex_unlock(&dev_priv->fbc.lock);
   1255  1.1  riastrad 
   1256  1.1  riastrad 	return 0;
   1257  1.1  riastrad }
   1258  1.1  riastrad 
   1259  1.1  riastrad /**
   1260  1.1  riastrad  * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
   1261  1.1  riastrad  * @dev_priv: i915 device instance
   1262  1.1  riastrad  *
   1263  1.1  riastrad  * Without FBC, most underruns are harmless and don't really cause too many
   1264  1.1  riastrad  * problems, except for an annoying message on dmesg. With FBC, underruns can
   1265  1.1  riastrad  * become black screens or even worse, especially when paired with bad
   1266  1.1  riastrad  * watermarks. So in order for us to be on the safe side, completely disable FBC
   1267  1.1  riastrad  * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
   1268  1.1  riastrad  * already suggests that watermarks may be bad, so try to be as safe as
   1269  1.1  riastrad  * possible.
   1270  1.1  riastrad  *
   1271  1.1  riastrad  * This function is called from the IRQ handler.
   1272  1.1  riastrad  */
   1273  1.1  riastrad void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
   1274  1.1  riastrad {
   1275  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1276  1.1  riastrad 
   1277  1.1  riastrad 	if (!fbc_supported(dev_priv))
   1278  1.1  riastrad 		return;
   1279  1.1  riastrad 
   1280  1.1  riastrad 	/* There's no guarantee that underrun_detected won't be set to true
   1281  1.1  riastrad 	 * right after this check and before the work is scheduled, but that's
   1282  1.1  riastrad 	 * not a problem since we'll check it again under the work function
   1283  1.1  riastrad 	 * while FBC is locked. This check here is just to prevent us from
   1284  1.1  riastrad 	 * unnecessarily scheduling the work, and it relies on the fact that we
   1285  1.1  riastrad 	 * never switch underrun_detect back to false after it's true. */
   1286  1.1  riastrad 	if (READ_ONCE(fbc->underrun_detected))
   1287  1.1  riastrad 		return;
   1288  1.1  riastrad 
   1289  1.1  riastrad 	schedule_work(&fbc->underrun_work);
   1290  1.1  riastrad }
   1291  1.1  riastrad 
   1292  1.1  riastrad /*
   1293  1.1  riastrad  * The DDX driver changes its behavior depending on the value it reads from
   1294  1.1  riastrad  * i915.enable_fbc, so sanitize it by translating the default value into either
   1295  1.1  riastrad  * 0 or 1 in order to allow it to know what's going on.
   1296  1.1  riastrad  *
   1297  1.1  riastrad  * Notice that this is done at driver initialization and we still allow user
   1298  1.1  riastrad  * space to change the value during runtime without sanitizing it again. IGT
   1299  1.1  riastrad  * relies on being able to change i915.enable_fbc at runtime.
   1300  1.1  riastrad  */
   1301  1.1  riastrad static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
   1302  1.1  riastrad {
   1303  1.1  riastrad 	if (i915_modparams.enable_fbc >= 0)
   1304  1.1  riastrad 		return !!i915_modparams.enable_fbc;
   1305  1.1  riastrad 
   1306  1.1  riastrad 	if (!HAS_FBC(dev_priv))
   1307  1.1  riastrad 		return 0;
   1308  1.1  riastrad 
   1309  1.1  riastrad 	if (IS_BROADWELL(dev_priv) || INTEL_GEN(dev_priv) >= 9)
   1310  1.1  riastrad 		return 1;
   1311  1.1  riastrad 
   1312  1.1  riastrad 	return 0;
   1313  1.1  riastrad }
   1314  1.1  riastrad 
   1315  1.1  riastrad static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
   1316  1.1  riastrad {
   1317  1.1  riastrad 	/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
   1318  1.1  riastrad 	if (intel_vtd_active() &&
   1319  1.1  riastrad 	    (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
   1320  1.1  riastrad 		DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
   1321  1.1  riastrad 		return true;
   1322  1.1  riastrad 	}
   1323  1.1  riastrad 
   1324  1.1  riastrad 	return false;
   1325  1.1  riastrad }
   1326  1.1  riastrad 
   1327  1.1  riastrad /**
   1328  1.1  riastrad  * intel_fbc_init - Initialize FBC
   1329  1.1  riastrad  * @dev_priv: the i915 device
   1330  1.1  riastrad  *
   1331  1.1  riastrad  * This function might be called during PM init process.
   1332  1.1  riastrad  */
   1333  1.1  riastrad void intel_fbc_init(struct drm_i915_private *dev_priv)
   1334  1.1  riastrad {
   1335  1.1  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1336  1.1  riastrad 
   1337  1.1  riastrad 	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
   1338  1.1  riastrad 	mutex_init(&fbc->lock);
   1339  1.1  riastrad 	fbc->active = false;
   1340  1.1  riastrad 
   1341  1.1  riastrad 	if (!drm_mm_initialized(&dev_priv->mm.stolen))
   1342  1.1  riastrad 		mkwrite_device_info(dev_priv)->display.has_fbc = false;
   1343  1.1  riastrad 
   1344  1.1  riastrad 	if (need_fbc_vtd_wa(dev_priv))
   1345  1.1  riastrad 		mkwrite_device_info(dev_priv)->display.has_fbc = false;
   1346  1.1  riastrad 
   1347  1.1  riastrad 	i915_modparams.enable_fbc = intel_sanitize_fbc_option(dev_priv);
   1348  1.1  riastrad 	DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n",
   1349  1.1  riastrad 		      i915_modparams.enable_fbc);
   1350  1.1  riastrad 
   1351  1.1  riastrad 	if (!HAS_FBC(dev_priv)) {
   1352  1.1  riastrad 		fbc->no_fbc_reason = "unsupported by this chipset";
   1353  1.1  riastrad 		return;
   1354  1.1  riastrad 	}
   1355  1.1  riastrad 
   1356  1.1  riastrad 	/* This value was pulled out of someone's hat */
   1357  1.1  riastrad 	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
   1358  1.1  riastrad 		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);
   1359  1.1  riastrad 
   1360  1.1  riastrad 	/* We still don't have any sort of hardware state readout for FBC, so
   1361  1.1  riastrad 	 * deactivate it in case the BIOS activated it to make sure software
   1362  1.1  riastrad 	 * matches the hardware state. */
   1363  1.1  riastrad 	if (intel_fbc_hw_is_active(dev_priv))
   1364  1.1  riastrad 		intel_fbc_hw_deactivate(dev_priv);
   1365  1.1  riastrad }
   1366  1.3  riastrad 
   1367  1.3  riastrad void
   1368  1.3  riastrad intel_fbc_cleanup(struct drm_i915_private *dev_priv)
   1369  1.3  riastrad {
   1370  1.3  riastrad 	struct intel_fbc *fbc = &dev_priv->fbc;
   1371  1.3  riastrad 
   1372  1.3  riastrad 	mutex_destroy(&fbc->lock);
   1373  1.3  riastrad }
   1374