intel_sprite.c revision 1.1.1.1
1 /* $NetBSD: intel_sprite.c,v 1.1.1.1 2021/12/18 20:15:31 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Jesse Barnes <jbarnes (at) virtuousgeek.org> 27 * 28 * New plane/sprite handling. 29 * 30 * The older chips had a separate interface for programming plane related 31 * registers; newer ones are much simpler and we can use the new DRM plane 32 * support. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: intel_sprite.c,v 1.1.1.1 2021/12/18 20:15:31 riastradh Exp $"); 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_color_mgmt.h> 41 #include <drm/drm_crtc.h> 42 #include <drm/drm_fourcc.h> 43 #include <drm/drm_plane_helper.h> 44 #include <drm/drm_rect.h> 45 #include <drm/i915_drm.h> 46 47 #include "i915_drv.h" 48 #include "i915_trace.h" 49 #include "intel_atomic_plane.h" 50 #include "intel_display_types.h" 51 #include "intel_frontbuffer.h" 52 #include "intel_pm.h" 53 #include "intel_psr.h" 54 #include "intel_sprite.h" 55 56 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 57 int usecs) 58 { 59 /* paranoia */ 60 if (!adjusted_mode->crtc_htotal) 61 return 1; 62 63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 64 1000 * adjusted_mode->crtc_htotal); 65 } 66 67 /* FIXME: We should instead only take spinlocks once for the entire update 68 * instead of once per mmio. */ 69 #if IS_ENABLED(CONFIG_PROVE_LOCKING) 70 #define VBLANK_EVASION_TIME_US 250 71 #else 72 #define VBLANK_EVASION_TIME_US 100 73 #endif 74 75 /** 76 * intel_pipe_update_start() - start update of a set of display registers 77 * @new_crtc_state: the new crtc state 78 * 79 * Mark the start of an update to pipe registers that should be updated 80 * atomically regarding vblank. If the next vblank will happens within 81 * the next 100 us, this function waits until the vblank passes. 82 * 83 * After a successful call to this function, interrupts will be disabled 84 * until a subsequent call to intel_pipe_update_end(). That is done to 85 * avoid random delays. 86 */ 87 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) 88 { 89 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 90 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 91 const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; 92 long timeout = msecs_to_jiffies_timeout(1); 93 int scanline, min, max, vblank_start; 94 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 95 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 96 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI); 97 DEFINE_WAIT(wait); 98 u32 psr_status; 99 100 vblank_start = adjusted_mode->crtc_vblank_start; 101 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 102 vblank_start = DIV_ROUND_UP(vblank_start, 2); 103 104 /* FIXME needs to be calibrated sensibly */ 105 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 106 VBLANK_EVASION_TIME_US); 107 max = vblank_start - 1; 108 109 if (min <= 0 || max <= 0) 110 goto irq_disable; 111 112 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 113 goto irq_disable; 114 115 /* 116 * Wait for psr to idle out after enabling the VBL interrupts 117 * VBL interrupts will start the PSR exit and prevent a PSR 118 * re-entry as well. 119 */ 120 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status)) 121 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n", 122 psr_status); 123 124 local_irq_disable(); 125 126 crtc->debug.min_vbl = min; 127 crtc->debug.max_vbl = max; 128 trace_intel_pipe_update_start(crtc); 129 130 for (;;) { 131 /* 132 * prepare_to_wait() has a memory barrier, which guarantees 133 * other CPUs can see the task state update by the time we 134 * read the scanline. 135 */ 136 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 137 138 scanline = intel_get_crtc_scanline(crtc); 139 if (scanline < min || scanline > max) 140 break; 141 142 if (!timeout) { 143 DRM_ERROR("Potential atomic update failure on pipe %c\n", 144 pipe_name(crtc->pipe)); 145 break; 146 } 147 148 local_irq_enable(); 149 150 timeout = schedule_timeout(timeout); 151 152 local_irq_disable(); 153 } 154 155 finish_wait(wq, &wait); 156 157 drm_crtc_vblank_put(&crtc->base); 158 159 /* 160 * On VLV/CHV DSI the scanline counter would appear to 161 * increment approx. 1/3 of a scanline before start of vblank. 162 * The registers still get latched at start of vblank however. 163 * This means we must not write any registers on the first 164 * line of vblank (since not the whole line is actually in 165 * vblank). And unfortunately we can't use the interrupt to 166 * wait here since it will fire too soon. We could use the 167 * frame start interrupt instead since it will fire after the 168 * critical scanline, but that would require more changes 169 * in the interrupt code. So for now we'll just do the nasty 170 * thing and poll for the bad scanline to pass us by. 171 * 172 * FIXME figure out if BXT+ DSI suffers from this as well 173 */ 174 while (need_vlv_dsi_wa && scanline == vblank_start) 175 scanline = intel_get_crtc_scanline(crtc); 176 177 crtc->debug.scanline_start = scanline; 178 crtc->debug.start_vbl_time = ktime_get(); 179 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 180 181 trace_intel_pipe_update_vblank_evaded(crtc); 182 return; 183 184 irq_disable: 185 local_irq_disable(); 186 } 187 188 /** 189 * intel_pipe_update_end() - end update of a set of display registers 190 * @new_crtc_state: the new crtc state 191 * 192 * Mark the end of an update started with intel_pipe_update_start(). This 193 * re-enables interrupts and verifies the update was actually completed 194 * before a vblank. 195 */ 196 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) 197 { 198 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 199 enum pipe pipe = crtc->pipe; 200 int scanline_end = intel_get_crtc_scanline(crtc); 201 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 202 ktime_t end_vbl_time = ktime_get(); 203 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 204 205 trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); 206 207 /* We're still in the vblank-evade critical section, this can't race. 208 * Would be slightly nice to just grab the vblank count and arm the 209 * event outside of the critical section - the spinlock might spin for a 210 * while ... */ 211 if (new_crtc_state->uapi.event) { 212 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 213 214 spin_lock(&crtc->base.dev->event_lock); 215 drm_crtc_arm_vblank_event(&crtc->base, 216 new_crtc_state->uapi.event); 217 spin_unlock(&crtc->base.dev->event_lock); 218 219 new_crtc_state->uapi.event = NULL; 220 } 221 222 local_irq_enable(); 223 224 if (intel_vgpu_active(dev_priv)) 225 return; 226 227 if (crtc->debug.start_vbl_count && 228 crtc->debug.start_vbl_count != end_vbl_count) { 229 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n", 230 pipe_name(pipe), crtc->debug.start_vbl_count, 231 end_vbl_count, 232 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 233 crtc->debug.min_vbl, crtc->debug.max_vbl, 234 crtc->debug.scanline_start, scanline_end); 235 } 236 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 237 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) > 238 VBLANK_EVASION_TIME_US) 239 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n", 240 pipe_name(pipe), 241 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 242 VBLANK_EVASION_TIME_US); 243 #endif 244 } 245 246 int intel_plane_check_stride(const struct intel_plane_state *plane_state) 247 { 248 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 249 const struct drm_framebuffer *fb = plane_state->hw.fb; 250 unsigned int rotation = plane_state->hw.rotation; 251 u32 stride, max_stride; 252 253 /* 254 * We ignore stride for all invisible planes that 255 * can be remapped. Otherwise we could end up 256 * with a false positive when the remapping didn't 257 * kick in due the plane being invisible. 258 */ 259 if (intel_plane_can_remap(plane_state) && 260 !plane_state->uapi.visible) 261 return 0; 262 263 /* FIXME other color planes? */ 264 stride = plane_state->color_plane[0].stride; 265 max_stride = plane->max_stride(plane, fb->format->format, 266 fb->modifier, rotation); 267 268 if (stride > max_stride) { 269 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 270 fb->base.id, stride, 271 plane->base.base.id, plane->base.name, max_stride); 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) 279 { 280 const struct drm_framebuffer *fb = plane_state->hw.fb; 281 struct drm_rect *src = &plane_state->uapi.src; 282 u32 src_x, src_y, src_w, src_h, hsub, vsub; 283 bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation); 284 285 /* 286 * Hardware doesn't handle subpixel coordinates. 287 * Adjust to (macro)pixel boundary, but be careful not to 288 * increase the source viewport size, because that could 289 * push the downscaling factor out of bounds. 290 */ 291 src_x = src->x1 >> 16; 292 src_w = drm_rect_width(src) >> 16; 293 src_y = src->y1 >> 16; 294 src_h = drm_rect_height(src) >> 16; 295 296 drm_rect_init(src, src_x << 16, src_y << 16, 297 src_w << 16, src_h << 16); 298 299 if (!fb->format->is_yuv) 300 return 0; 301 302 /* YUV specific checks */ 303 if (!rotated) { 304 hsub = fb->format->hsub; 305 vsub = fb->format->vsub; 306 } else { 307 hsub = vsub = max(fb->format->hsub, fb->format->vsub); 308 } 309 310 if (src_x % hsub || src_w % hsub) { 311 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n", 312 src_x, src_w, hsub, rotated ? "rotated " : ""); 313 return -EINVAL; 314 } 315 316 if (src_y % vsub || src_h % vsub) { 317 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n", 318 src_y, src_h, vsub, rotated ? "rotated " : ""); 319 return -EINVAL; 320 } 321 322 return 0; 323 } 324 325 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 326 { 327 return INTEL_GEN(dev_priv) >= 11 && 328 icl_hdr_plane_mask() & BIT(plane_id); 329 } 330 331 static void 332 skl_plane_ratio(const struct intel_crtc_state *crtc_state, 333 const struct intel_plane_state *plane_state, 334 unsigned int *num, unsigned int *den) 335 { 336 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 337 const struct drm_framebuffer *fb = plane_state->hw.fb; 338 339 if (fb->format->cpp[0] == 8) { 340 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 341 *num = 10; 342 *den = 8; 343 } else { 344 *num = 9; 345 *den = 8; 346 } 347 } else { 348 *num = 1; 349 *den = 1; 350 } 351 } 352 353 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 354 const struct intel_plane_state *plane_state) 355 { 356 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 357 unsigned int pixel_rate = crtc_state->pixel_rate; 358 unsigned int src_w, src_h, dst_w, dst_h; 359 unsigned int num, den; 360 361 skl_plane_ratio(crtc_state, plane_state, &num, &den); 362 363 /* two pixels per clock on glk+ */ 364 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 365 den *= 2; 366 367 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 368 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 369 dst_w = drm_rect_width(&plane_state->uapi.dst); 370 dst_h = drm_rect_height(&plane_state->uapi.dst); 371 372 /* Downscaling limits the maximum pixel rate */ 373 dst_w = min(src_w, dst_w); 374 dst_h = min(src_h, dst_h); 375 376 return DIV64_U64_ROUND_UP(mul_u32_u32(pixel_rate * num, src_w * src_h), 377 mul_u32_u32(den, dst_w * dst_h)); 378 } 379 380 static unsigned int 381 skl_plane_max_stride(struct intel_plane *plane, 382 u32 pixel_format, u64 modifier, 383 unsigned int rotation) 384 { 385 const struct drm_format_info *info = drm_format_info(pixel_format); 386 int cpp = info->cpp[0]; 387 388 /* 389 * "The stride in bytes must not exceed the 390 * of the size of 8K pixels and 32K bytes." 391 */ 392 if (drm_rotation_90_or_270(rotation)) 393 return min(8192, 32768 / cpp); 394 else 395 return min(8192 * cpp, 32768); 396 } 397 398 static void 399 skl_program_scaler(struct intel_plane *plane, 400 const struct intel_crtc_state *crtc_state, 401 const struct intel_plane_state *plane_state) 402 { 403 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 404 const struct drm_framebuffer *fb = plane_state->hw.fb; 405 enum pipe pipe = plane->pipe; 406 int scaler_id = plane_state->scaler_id; 407 const struct intel_scaler *scaler = 408 &crtc_state->scaler_state.scalers[scaler_id]; 409 int crtc_x = plane_state->uapi.dst.x1; 410 int crtc_y = plane_state->uapi.dst.y1; 411 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 412 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 413 u16 y_hphase, uv_rgb_hphase; 414 u16 y_vphase, uv_rgb_vphase; 415 int hscale, vscale; 416 417 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 418 &plane_state->uapi.dst, 419 0, INT_MAX); 420 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 421 &plane_state->uapi.dst, 422 0, INT_MAX); 423 424 /* TODO: handle sub-pixel coordinates */ 425 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 426 !icl_is_hdr_plane(dev_priv, plane->id)) { 427 y_hphase = skl_scaler_calc_phase(1, hscale, false); 428 y_vphase = skl_scaler_calc_phase(1, vscale, false); 429 430 /* MPEG2 chroma siting convention */ 431 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 432 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 433 } else { 434 /* not used */ 435 y_hphase = 0; 436 y_vphase = 0; 437 438 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 439 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 440 } 441 442 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), 443 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); 444 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), 445 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 446 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), 447 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 448 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 449 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); 450 } 451 452 /* Preoffset values for YUV to RGB Conversion */ 453 #define PREOFF_YUV_TO_RGB_HI 0x1800 454 #define PREOFF_YUV_TO_RGB_ME 0x1F00 455 #define PREOFF_YUV_TO_RGB_LO 0x1800 456 457 #define ROFF(x) (((x) & 0xffff) << 16) 458 #define GOFF(x) (((x) & 0xffff) << 0) 459 #define BOFF(x) (((x) & 0xffff) << 16) 460 461 static void 462 icl_program_input_csc(struct intel_plane *plane, 463 const struct intel_crtc_state *crtc_state, 464 const struct intel_plane_state *plane_state) 465 { 466 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 467 enum pipe pipe = plane->pipe; 468 enum plane_id plane_id = plane->id; 469 470 static const u16 input_csc_matrix[][9] = { 471 /* 472 * BT.601 full range YCbCr -> full range RGB 473 * The matrix required is : 474 * [1.000, 0.000, 1.371, 475 * 1.000, -0.336, -0.698, 476 * 1.000, 1.732, 0.0000] 477 */ 478 [DRM_COLOR_YCBCR_BT601] = { 479 0x7AF8, 0x7800, 0x0, 480 0x8B28, 0x7800, 0x9AC0, 481 0x0, 0x7800, 0x7DD8, 482 }, 483 /* 484 * BT.709 full range YCbCr -> full range RGB 485 * The matrix required is : 486 * [1.000, 0.000, 1.574, 487 * 1.000, -0.187, -0.468, 488 * 1.000, 1.855, 0.0000] 489 */ 490 [DRM_COLOR_YCBCR_BT709] = { 491 0x7C98, 0x7800, 0x0, 492 0x9EF8, 0x7800, 0xAC00, 493 0x0, 0x7800, 0x7ED8, 494 }, 495 /* 496 * BT.2020 full range YCbCr -> full range RGB 497 * The matrix required is : 498 * [1.000, 0.000, 1.474, 499 * 1.000, -0.1645, -0.5713, 500 * 1.000, 1.8814, 0.0000] 501 */ 502 [DRM_COLOR_YCBCR_BT2020] = { 503 0x7BC8, 0x7800, 0x0, 504 0x8928, 0x7800, 0xAA88, 505 0x0, 0x7800, 0x7F10, 506 }, 507 }; 508 509 /* Matrix for Limited Range to Full Range Conversion */ 510 static const u16 input_csc_matrix_lr[][9] = { 511 /* 512 * BT.601 Limted range YCbCr -> full range RGB 513 * The matrix required is : 514 * [1.164384, 0.000, 1.596027, 515 * 1.164384, -0.39175, -0.812813, 516 * 1.164384, 2.017232, 0.0000] 517 */ 518 [DRM_COLOR_YCBCR_BT601] = { 519 0x7CC8, 0x7950, 0x0, 520 0x8D00, 0x7950, 0x9C88, 521 0x0, 0x7950, 0x6810, 522 }, 523 /* 524 * BT.709 Limited range YCbCr -> full range RGB 525 * The matrix required is : 526 * [1.164384, 0.000, 1.792741, 527 * 1.164384, -0.213249, -0.532909, 528 * 1.164384, 2.112402, 0.0000] 529 */ 530 [DRM_COLOR_YCBCR_BT709] = { 531 0x7E58, 0x7950, 0x0, 532 0x8888, 0x7950, 0xADA8, 533 0x0, 0x7950, 0x6870, 534 }, 535 /* 536 * BT.2020 Limited range YCbCr -> full range RGB 537 * The matrix required is : 538 * [1.164, 0.000, 1.678, 539 * 1.164, -0.1873, -0.6504, 540 * 1.164, 2.1417, 0.0000] 541 */ 542 [DRM_COLOR_YCBCR_BT2020] = { 543 0x7D70, 0x7950, 0x0, 544 0x8A68, 0x7950, 0xAC00, 545 0x0, 0x7950, 0x6890, 546 }, 547 }; 548 const u16 *csc; 549 550 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 551 csc = input_csc_matrix[plane_state->hw.color_encoding]; 552 else 553 csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; 554 555 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | 556 GOFF(csc[1])); 557 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); 558 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | 559 GOFF(csc[4])); 560 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); 561 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | 562 GOFF(csc[7])); 563 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); 564 565 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 566 PREOFF_YUV_TO_RGB_HI); 567 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 568 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); 569 else 570 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 571 PREOFF_YUV_TO_RGB_ME); 572 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 573 PREOFF_YUV_TO_RGB_LO); 574 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 575 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 576 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 577 } 578 579 static void 580 skl_program_plane(struct intel_plane *plane, 581 const struct intel_crtc_state *crtc_state, 582 const struct intel_plane_state *plane_state, 583 int color_plane) 584 { 585 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 586 enum plane_id plane_id = plane->id; 587 enum pipe pipe = plane->pipe; 588 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 589 u32 surf_addr = plane_state->color_plane[color_plane].offset; 590 u32 stride = skl_plane_stride(plane_state, color_plane); 591 const struct drm_framebuffer *fb = plane_state->hw.fb; 592 int aux_plane = intel_main_to_aux_plane(fb, color_plane); 593 u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr; 594 u32 aux_stride = skl_plane_stride(plane_state, aux_plane); 595 int crtc_x = plane_state->uapi.dst.x1; 596 int crtc_y = plane_state->uapi.dst.y1; 597 u32 x = plane_state->color_plane[color_plane].x; 598 u32 y = plane_state->color_plane[color_plane].y; 599 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 600 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 601 u8 alpha = plane_state->hw.alpha >> 8; 602 u32 plane_color_ctl = 0; 603 unsigned long irqflags; 604 u32 keymsk, keymax; 605 u32 plane_ctl = plane_state->ctl; 606 607 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 608 609 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 610 plane_color_ctl = plane_state->color_ctl | 611 glk_plane_color_ctl_crtc(crtc_state); 612 613 /* Sizes are 0 based */ 614 src_w--; 615 src_h--; 616 617 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 618 619 keymsk = key->channel_mask & 0x7ffffff; 620 if (alpha < 0xff) 621 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 622 623 /* The scaler will handle the output position */ 624 if (plane_state->scaler_id >= 0) { 625 crtc_x = 0; 626 crtc_y = 0; 627 } 628 629 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 630 631 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); 632 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); 633 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); 634 635 if (INTEL_GEN(dev_priv) < 12) 636 aux_dist |= aux_stride; 637 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); 638 639 if (icl_is_hdr_plane(dev_priv, plane_id)) 640 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); 641 642 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 643 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 644 645 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 646 icl_program_input_csc(plane, crtc_state, plane_state); 647 648 skl_write_plane_wm(plane, crtc_state); 649 650 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); 651 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); 652 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); 653 654 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); 655 656 if (INTEL_GEN(dev_priv) < 11) 657 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), 658 (plane_state->color_plane[1].y << 16) | 659 plane_state->color_plane[1].x); 660 661 /* 662 * The control register self-arms if the plane was previously 663 * disabled. Try to make the plane enable atomic by writing 664 * the control register just before the surface register. 665 */ 666 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); 667 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 668 intel_plane_ggtt_offset(plane_state) + surf_addr); 669 670 if (plane_state->scaler_id >= 0) 671 skl_program_scaler(plane, crtc_state, plane_state); 672 673 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 674 } 675 676 static void 677 skl_update_plane(struct intel_plane *plane, 678 const struct intel_crtc_state *crtc_state, 679 const struct intel_plane_state *plane_state) 680 { 681 int color_plane = 0; 682 683 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 684 /* Program the UV plane on planar master */ 685 color_plane = 1; 686 687 skl_program_plane(plane, crtc_state, plane_state, color_plane); 688 } 689 static void 690 skl_disable_plane(struct intel_plane *plane, 691 const struct intel_crtc_state *crtc_state) 692 { 693 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 694 enum plane_id plane_id = plane->id; 695 enum pipe pipe = plane->pipe; 696 unsigned long irqflags; 697 698 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 699 700 if (icl_is_hdr_plane(dev_priv, plane_id)) 701 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); 702 703 skl_write_plane_wm(plane, crtc_state); 704 705 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); 706 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); 707 708 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 709 } 710 711 static bool 712 skl_plane_get_hw_state(struct intel_plane *plane, 713 enum pipe *pipe) 714 { 715 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 716 enum intel_display_power_domain power_domain; 717 enum plane_id plane_id = plane->id; 718 intel_wakeref_t wakeref; 719 bool ret; 720 721 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 722 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 723 if (!wakeref) 724 return false; 725 726 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 727 728 *pipe = plane->pipe; 729 730 intel_display_power_put(dev_priv, power_domain, wakeref); 731 732 return ret; 733 } 734 735 static void i9xx_plane_linear_gamma(u16 gamma[8]) 736 { 737 /* The points are not evenly spaced. */ 738 static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 }; 739 int i; 740 741 for (i = 0; i < 8; i++) 742 gamma[i] = (in[i] << 8) / 32; 743 } 744 745 static void 746 chv_update_csc(const struct intel_plane_state *plane_state) 747 { 748 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 749 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 750 const struct drm_framebuffer *fb = plane_state->hw.fb; 751 enum plane_id plane_id = plane->id; 752 /* 753 * |r| | c0 c1 c2 | |cr| 754 * |g| = | c3 c4 c5 | x |y | 755 * |b| | c6 c7 c8 | |cb| 756 * 757 * Coefficients are s3.12. 758 * 759 * Cb and Cr apparently come in as signed already, and 760 * we always get full range data in on account of CLRC0/1. 761 */ 762 static const s16 csc_matrix[][9] = { 763 /* BT.601 full range YCbCr -> full range RGB */ 764 [DRM_COLOR_YCBCR_BT601] = { 765 5743, 4096, 0, 766 -2925, 4096, -1410, 767 0, 4096, 7258, 768 }, 769 /* BT.709 full range YCbCr -> full range RGB */ 770 [DRM_COLOR_YCBCR_BT709] = { 771 6450, 4096, 0, 772 -1917, 4096, -767, 773 0, 4096, 7601, 774 }, 775 }; 776 const s16 *csc = csc_matrix[plane_state->hw.color_encoding]; 777 778 /* Seems RGB data bypasses the CSC always */ 779 if (!fb->format->is_yuv) 780 return; 781 782 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 783 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 784 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 785 786 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 787 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 788 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 789 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 790 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); 791 792 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 793 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 794 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 795 796 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 797 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 798 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 799 } 800 801 #define SIN_0 0 802 #define COS_0 1 803 804 static void 805 vlv_update_clrc(const struct intel_plane_state *plane_state) 806 { 807 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 808 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 809 const struct drm_framebuffer *fb = plane_state->hw.fb; 810 enum pipe pipe = plane->pipe; 811 enum plane_id plane_id = plane->id; 812 int contrast, brightness, sh_scale, sh_sin, sh_cos; 813 814 if (fb->format->is_yuv && 815 plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { 816 /* 817 * Expand limited range to full range: 818 * Contrast is applied first and is used to expand Y range. 819 * Brightness is applied second and is used to remove the 820 * offset from Y. Saturation/hue is used to expand CbCr range. 821 */ 822 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16); 823 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16); 824 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128); 825 sh_sin = SIN_0 * sh_scale; 826 sh_cos = COS_0 * sh_scale; 827 } else { 828 /* Pass-through everything. */ 829 contrast = 1 << 6; 830 brightness = 0; 831 sh_scale = 1 << 7; 832 sh_sin = SIN_0 * sh_scale; 833 sh_cos = COS_0 * sh_scale; 834 } 835 836 /* FIXME these register are single buffered :( */ 837 I915_WRITE_FW(SPCLRC0(pipe, plane_id), 838 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 839 I915_WRITE_FW(SPCLRC1(pipe, plane_id), 840 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 841 } 842 843 static void 844 vlv_plane_ratio(const struct intel_crtc_state *crtc_state, 845 const struct intel_plane_state *plane_state, 846 unsigned int *num, unsigned int *den) 847 { 848 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 849 const struct drm_framebuffer *fb = plane_state->hw.fb; 850 unsigned int cpp = fb->format->cpp[0]; 851 852 /* 853 * VLV bspec only considers cases where all three planes are 854 * enabled, and cases where the primary and one sprite is enabled. 855 * Let's assume the case with just two sprites enabled also 856 * maps to the latter case. 857 */ 858 if (hweight8(active_planes) == 3) { 859 switch (cpp) { 860 case 8: 861 *num = 11; 862 *den = 8; 863 break; 864 case 4: 865 *num = 18; 866 *den = 16; 867 break; 868 default: 869 *num = 1; 870 *den = 1; 871 break; 872 } 873 } else if (hweight8(active_planes) == 2) { 874 switch (cpp) { 875 case 8: 876 *num = 10; 877 *den = 8; 878 break; 879 case 4: 880 *num = 17; 881 *den = 16; 882 break; 883 default: 884 *num = 1; 885 *den = 1; 886 break; 887 } 888 } else { 889 switch (cpp) { 890 case 8: 891 *num = 10; 892 *den = 8; 893 break; 894 default: 895 *num = 1; 896 *den = 1; 897 break; 898 } 899 } 900 } 901 902 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 903 const struct intel_plane_state *plane_state) 904 { 905 unsigned int pixel_rate; 906 unsigned int num, den; 907 908 /* 909 * Note that crtc_state->pixel_rate accounts for both 910 * horizontal and vertical panel fitter downscaling factors. 911 * Pre-HSW bspec tells us to only consider the horizontal 912 * downscaling factor here. We ignore that and just consider 913 * both for simplicity. 914 */ 915 pixel_rate = crtc_state->pixel_rate; 916 917 vlv_plane_ratio(crtc_state, plane_state, &num, &den); 918 919 return DIV_ROUND_UP(pixel_rate * num, den); 920 } 921 922 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 923 { 924 u32 sprctl = 0; 925 926 if (crtc_state->gamma_enable) 927 sprctl |= SP_GAMMA_ENABLE; 928 929 return sprctl; 930 } 931 932 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, 933 const struct intel_plane_state *plane_state) 934 { 935 const struct drm_framebuffer *fb = plane_state->hw.fb; 936 unsigned int rotation = plane_state->hw.rotation; 937 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 938 u32 sprctl; 939 940 sprctl = SP_ENABLE; 941 942 switch (fb->format->format) { 943 case DRM_FORMAT_YUYV: 944 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 945 break; 946 case DRM_FORMAT_YVYU: 947 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 948 break; 949 case DRM_FORMAT_UYVY: 950 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 951 break; 952 case DRM_FORMAT_VYUY: 953 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 954 break; 955 case DRM_FORMAT_C8: 956 sprctl |= SP_FORMAT_8BPP; 957 break; 958 case DRM_FORMAT_RGB565: 959 sprctl |= SP_FORMAT_BGR565; 960 break; 961 case DRM_FORMAT_XRGB8888: 962 sprctl |= SP_FORMAT_BGRX8888; 963 break; 964 case DRM_FORMAT_ARGB8888: 965 sprctl |= SP_FORMAT_BGRA8888; 966 break; 967 case DRM_FORMAT_XBGR2101010: 968 sprctl |= SP_FORMAT_RGBX1010102; 969 break; 970 case DRM_FORMAT_ABGR2101010: 971 sprctl |= SP_FORMAT_RGBA1010102; 972 break; 973 case DRM_FORMAT_XRGB2101010: 974 sprctl |= SP_FORMAT_BGRX1010102; 975 break; 976 case DRM_FORMAT_ARGB2101010: 977 sprctl |= SP_FORMAT_BGRA1010102; 978 break; 979 case DRM_FORMAT_XBGR8888: 980 sprctl |= SP_FORMAT_RGBX8888; 981 break; 982 case DRM_FORMAT_ABGR8888: 983 sprctl |= SP_FORMAT_RGBA8888; 984 break; 985 default: 986 MISSING_CASE(fb->format->format); 987 return 0; 988 } 989 990 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 991 sprctl |= SP_YUV_FORMAT_BT709; 992 993 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 994 sprctl |= SP_TILED; 995 996 if (rotation & DRM_MODE_ROTATE_180) 997 sprctl |= SP_ROTATE_180; 998 999 if (rotation & DRM_MODE_REFLECT_X) 1000 sprctl |= SP_MIRROR; 1001 1002 if (key->flags & I915_SET_COLORKEY_SOURCE) 1003 sprctl |= SP_SOURCE_KEY; 1004 1005 return sprctl; 1006 } 1007 1008 static void vlv_update_gamma(const struct intel_plane_state *plane_state) 1009 { 1010 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1011 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1012 const struct drm_framebuffer *fb = plane_state->hw.fb; 1013 enum pipe pipe = plane->pipe; 1014 enum plane_id plane_id = plane->id; 1015 u16 gamma[8]; 1016 int i; 1017 1018 /* Seems RGB data bypasses the gamma always */ 1019 if (!fb->format->is_yuv) 1020 return; 1021 1022 i9xx_plane_linear_gamma(gamma); 1023 1024 /* FIXME these register are single buffered :( */ 1025 /* The two end points are implicit (0.0 and 1.0) */ 1026 for (i = 1; i < 8 - 1; i++) 1027 I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), 1028 gamma[i] << 16 | 1029 gamma[i] << 8 | 1030 gamma[i]); 1031 } 1032 1033 static void 1034 vlv_update_plane(struct intel_plane *plane, 1035 const struct intel_crtc_state *crtc_state, 1036 const struct intel_plane_state *plane_state) 1037 { 1038 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1039 enum pipe pipe = plane->pipe; 1040 enum plane_id plane_id = plane->id; 1041 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1042 u32 linear_offset; 1043 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1044 int crtc_x = plane_state->uapi.dst.x1; 1045 int crtc_y = plane_state->uapi.dst.y1; 1046 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1047 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1048 u32 x = plane_state->color_plane[0].x; 1049 u32 y = plane_state->color_plane[0].y; 1050 unsigned long irqflags; 1051 u32 sprctl; 1052 1053 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); 1054 1055 /* Sizes are 0 based */ 1056 crtc_w--; 1057 crtc_h--; 1058 1059 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1060 1061 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1062 1063 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), 1064 plane_state->color_plane[0].stride); 1065 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); 1066 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); 1067 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); 1068 1069 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) 1070 chv_update_csc(plane_state); 1071 1072 if (key->flags) { 1073 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); 1074 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); 1075 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); 1076 } 1077 1078 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); 1079 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); 1080 1081 /* 1082 * The control register self-arms if the plane was previously 1083 * disabled. Try to make the plane enable atomic by writing 1084 * the control register just before the surface register. 1085 */ 1086 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); 1087 I915_WRITE_FW(SPSURF(pipe, plane_id), 1088 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1089 1090 vlv_update_clrc(plane_state); 1091 vlv_update_gamma(plane_state); 1092 1093 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1094 } 1095 1096 static void 1097 vlv_disable_plane(struct intel_plane *plane, 1098 const struct intel_crtc_state *crtc_state) 1099 { 1100 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1101 enum pipe pipe = plane->pipe; 1102 enum plane_id plane_id = plane->id; 1103 unsigned long irqflags; 1104 1105 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1106 1107 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); 1108 I915_WRITE_FW(SPSURF(pipe, plane_id), 0); 1109 1110 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1111 } 1112 1113 static bool 1114 vlv_plane_get_hw_state(struct intel_plane *plane, 1115 enum pipe *pipe) 1116 { 1117 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1118 enum intel_display_power_domain power_domain; 1119 enum plane_id plane_id = plane->id; 1120 intel_wakeref_t wakeref; 1121 bool ret; 1122 1123 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1124 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1125 if (!wakeref) 1126 return false; 1127 1128 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 1129 1130 *pipe = plane->pipe; 1131 1132 intel_display_power_put(dev_priv, power_domain, wakeref); 1133 1134 return ret; 1135 } 1136 1137 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state, 1138 const struct intel_plane_state *plane_state, 1139 unsigned int *num, unsigned int *den) 1140 { 1141 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1142 const struct drm_framebuffer *fb = plane_state->hw.fb; 1143 unsigned int cpp = fb->format->cpp[0]; 1144 1145 if (hweight8(active_planes) == 2) { 1146 switch (cpp) { 1147 case 8: 1148 *num = 10; 1149 *den = 8; 1150 break; 1151 case 4: 1152 *num = 17; 1153 *den = 16; 1154 break; 1155 default: 1156 *num = 1; 1157 *den = 1; 1158 break; 1159 } 1160 } else { 1161 switch (cpp) { 1162 case 8: 1163 *num = 9; 1164 *den = 8; 1165 break; 1166 default: 1167 *num = 1; 1168 *den = 1; 1169 break; 1170 } 1171 } 1172 } 1173 1174 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state, 1175 const struct intel_plane_state *plane_state, 1176 unsigned int *num, unsigned int *den) 1177 { 1178 const struct drm_framebuffer *fb = plane_state->hw.fb; 1179 unsigned int cpp = fb->format->cpp[0]; 1180 1181 switch (cpp) { 1182 case 8: 1183 *num = 12; 1184 *den = 8; 1185 break; 1186 case 4: 1187 *num = 19; 1188 *den = 16; 1189 break; 1190 case 2: 1191 *num = 33; 1192 *den = 32; 1193 break; 1194 default: 1195 *num = 1; 1196 *den = 1; 1197 break; 1198 } 1199 } 1200 1201 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1202 const struct intel_plane_state *plane_state) 1203 { 1204 unsigned int pixel_rate; 1205 unsigned int num, den; 1206 1207 /* 1208 * Note that crtc_state->pixel_rate accounts for both 1209 * horizontal and vertical panel fitter downscaling factors. 1210 * Pre-HSW bspec tells us to only consider the horizontal 1211 * downscaling factor here. We ignore that and just consider 1212 * both for simplicity. 1213 */ 1214 pixel_rate = crtc_state->pixel_rate; 1215 1216 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1217 1218 return DIV_ROUND_UP(pixel_rate * num, den); 1219 } 1220 1221 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1222 const struct intel_plane_state *plane_state) 1223 { 1224 unsigned int src_w, dst_w, pixel_rate; 1225 unsigned int num, den; 1226 1227 /* 1228 * Note that crtc_state->pixel_rate accounts for both 1229 * horizontal and vertical panel fitter downscaling factors. 1230 * Pre-HSW bspec tells us to only consider the horizontal 1231 * downscaling factor here. We ignore that and just consider 1232 * both for simplicity. 1233 */ 1234 pixel_rate = crtc_state->pixel_rate; 1235 1236 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1237 dst_w = drm_rect_width(&plane_state->uapi.dst); 1238 1239 if (src_w != dst_w) 1240 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den); 1241 else 1242 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1243 1244 /* Horizontal downscaling limits the maximum pixel rate */ 1245 dst_w = min(src_w, dst_w); 1246 1247 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), 1248 den * dst_w); 1249 } 1250 1251 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state, 1252 const struct intel_plane_state *plane_state, 1253 unsigned int *num, unsigned int *den) 1254 { 1255 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1256 const struct drm_framebuffer *fb = plane_state->hw.fb; 1257 unsigned int cpp = fb->format->cpp[0]; 1258 1259 if (hweight8(active_planes) == 2) { 1260 switch (cpp) { 1261 case 8: 1262 *num = 10; 1263 *den = 8; 1264 break; 1265 default: 1266 *num = 1; 1267 *den = 1; 1268 break; 1269 } 1270 } else { 1271 switch (cpp) { 1272 case 8: 1273 *num = 9; 1274 *den = 8; 1275 break; 1276 default: 1277 *num = 1; 1278 *den = 1; 1279 break; 1280 } 1281 } 1282 } 1283 1284 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1285 const struct intel_plane_state *plane_state) 1286 { 1287 unsigned int pixel_rate = crtc_state->pixel_rate; 1288 unsigned int num, den; 1289 1290 hsw_plane_ratio(crtc_state, plane_state, &num, &den); 1291 1292 return DIV_ROUND_UP(pixel_rate * num, den); 1293 } 1294 1295 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1296 { 1297 u32 sprctl = 0; 1298 1299 if (crtc_state->gamma_enable) 1300 sprctl |= SPRITE_GAMMA_ENABLE; 1301 1302 if (crtc_state->csc_enable) 1303 sprctl |= SPRITE_PIPE_CSC_ENABLE; 1304 1305 return sprctl; 1306 } 1307 1308 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) 1309 { 1310 struct drm_i915_private *dev_priv = 1311 to_i915(plane_state->uapi.plane->dev); 1312 const struct drm_framebuffer *fb = plane_state->hw.fb; 1313 1314 return fb->format->cpp[0] == 8 && 1315 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); 1316 } 1317 1318 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, 1319 const struct intel_plane_state *plane_state) 1320 { 1321 struct drm_i915_private *dev_priv = 1322 to_i915(plane_state->uapi.plane->dev); 1323 const struct drm_framebuffer *fb = plane_state->hw.fb; 1324 unsigned int rotation = plane_state->hw.rotation; 1325 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1326 u32 sprctl; 1327 1328 sprctl = SPRITE_ENABLE; 1329 1330 if (IS_IVYBRIDGE(dev_priv)) 1331 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 1332 1333 switch (fb->format->format) { 1334 case DRM_FORMAT_XBGR8888: 1335 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 1336 break; 1337 case DRM_FORMAT_XRGB8888: 1338 sprctl |= SPRITE_FORMAT_RGBX888; 1339 break; 1340 case DRM_FORMAT_XBGR2101010: 1341 sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX; 1342 break; 1343 case DRM_FORMAT_XRGB2101010: 1344 sprctl |= SPRITE_FORMAT_RGBX101010; 1345 break; 1346 case DRM_FORMAT_XBGR16161616F: 1347 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX; 1348 break; 1349 case DRM_FORMAT_XRGB16161616F: 1350 sprctl |= SPRITE_FORMAT_RGBX161616; 1351 break; 1352 case DRM_FORMAT_YUYV: 1353 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 1354 break; 1355 case DRM_FORMAT_YVYU: 1356 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 1357 break; 1358 case DRM_FORMAT_UYVY: 1359 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 1360 break; 1361 case DRM_FORMAT_VYUY: 1362 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 1363 break; 1364 default: 1365 MISSING_CASE(fb->format->format); 1366 return 0; 1367 } 1368 1369 if (!ivb_need_sprite_gamma(plane_state)) 1370 sprctl |= SPRITE_INT_GAMMA_DISABLE; 1371 1372 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1373 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709; 1374 1375 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1376 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE; 1377 1378 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1379 sprctl |= SPRITE_TILED; 1380 1381 if (rotation & DRM_MODE_ROTATE_180) 1382 sprctl |= SPRITE_ROTATE_180; 1383 1384 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1385 sprctl |= SPRITE_DEST_KEY; 1386 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1387 sprctl |= SPRITE_SOURCE_KEY; 1388 1389 return sprctl; 1390 } 1391 1392 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, 1393 u16 gamma[18]) 1394 { 1395 int scale, i; 1396 1397 /* 1398 * WaFP16GammaEnabling:ivb,hsw 1399 * "Workaround : When using the 64-bit format, the sprite output 1400 * on each color channel has one quarter amplitude. It can be 1401 * brought up to full amplitude by using sprite internal gamma 1402 * correction, pipe gamma correction, or pipe color space 1403 * conversion to multiply the sprite output by four." 1404 */ 1405 scale = 4; 1406 1407 for (i = 0; i < 16; i++) 1408 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1); 1409 1410 gamma[i] = min((scale * i << 10) / 16, 1 << 10); 1411 i++; 1412 1413 gamma[i] = 3 << 10; 1414 i++; 1415 } 1416 1417 static void ivb_update_gamma(const struct intel_plane_state *plane_state) 1418 { 1419 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1420 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1421 enum pipe pipe = plane->pipe; 1422 u16 gamma[18]; 1423 int i; 1424 1425 if (!ivb_need_sprite_gamma(plane_state)) 1426 return; 1427 1428 ivb_sprite_linear_gamma(plane_state, gamma); 1429 1430 /* FIXME these register are single buffered :( */ 1431 for (i = 0; i < 16; i++) 1432 I915_WRITE_FW(SPRGAMC(pipe, i), 1433 gamma[i] << 20 | 1434 gamma[i] << 10 | 1435 gamma[i]); 1436 1437 I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); 1438 I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); 1439 I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); 1440 i++; 1441 1442 I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); 1443 I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); 1444 I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); 1445 i++; 1446 } 1447 1448 static void 1449 ivb_update_plane(struct intel_plane *plane, 1450 const struct intel_crtc_state *crtc_state, 1451 const struct intel_plane_state *plane_state) 1452 { 1453 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1454 enum pipe pipe = plane->pipe; 1455 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1456 u32 linear_offset; 1457 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1458 int crtc_x = plane_state->uapi.dst.x1; 1459 int crtc_y = plane_state->uapi.dst.y1; 1460 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1461 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1462 u32 x = plane_state->color_plane[0].x; 1463 u32 y = plane_state->color_plane[0].y; 1464 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1465 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1466 u32 sprctl, sprscale = 0; 1467 unsigned long irqflags; 1468 1469 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); 1470 1471 /* Sizes are 0 based */ 1472 src_w--; 1473 src_h--; 1474 crtc_w--; 1475 crtc_h--; 1476 1477 if (crtc_w != src_w || crtc_h != src_h) 1478 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 1479 1480 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1481 1482 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1483 1484 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); 1485 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 1486 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 1487 if (IS_IVYBRIDGE(dev_priv)) 1488 I915_WRITE_FW(SPRSCALE(pipe), sprscale); 1489 1490 if (key->flags) { 1491 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); 1492 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); 1493 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); 1494 } 1495 1496 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 1497 * register */ 1498 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1499 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); 1500 } else { 1501 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); 1502 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); 1503 } 1504 1505 /* 1506 * The control register self-arms if the plane was previously 1507 * disabled. Try to make the plane enable atomic by writing 1508 * the control register just before the surface register. 1509 */ 1510 I915_WRITE_FW(SPRCTL(pipe), sprctl); 1511 I915_WRITE_FW(SPRSURF(pipe), 1512 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1513 1514 ivb_update_gamma(plane_state); 1515 1516 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1517 } 1518 1519 static void 1520 ivb_disable_plane(struct intel_plane *plane, 1521 const struct intel_crtc_state *crtc_state) 1522 { 1523 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1524 enum pipe pipe = plane->pipe; 1525 unsigned long irqflags; 1526 1527 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1528 1529 I915_WRITE_FW(SPRCTL(pipe), 0); 1530 /* Disable the scaler */ 1531 if (IS_IVYBRIDGE(dev_priv)) 1532 I915_WRITE_FW(SPRSCALE(pipe), 0); 1533 I915_WRITE_FW(SPRSURF(pipe), 0); 1534 1535 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1536 } 1537 1538 static bool 1539 ivb_plane_get_hw_state(struct intel_plane *plane, 1540 enum pipe *pipe) 1541 { 1542 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1543 enum intel_display_power_domain power_domain; 1544 intel_wakeref_t wakeref; 1545 bool ret; 1546 1547 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1548 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1549 if (!wakeref) 1550 return false; 1551 1552 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; 1553 1554 *pipe = plane->pipe; 1555 1556 intel_display_power_put(dev_priv, power_domain, wakeref); 1557 1558 return ret; 1559 } 1560 1561 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1562 const struct intel_plane_state *plane_state) 1563 { 1564 const struct drm_framebuffer *fb = plane_state->hw.fb; 1565 unsigned int hscale, pixel_rate; 1566 unsigned int limit, decimate; 1567 1568 /* 1569 * Note that crtc_state->pixel_rate accounts for both 1570 * horizontal and vertical panel fitter downscaling factors. 1571 * Pre-HSW bspec tells us to only consider the horizontal 1572 * downscaling factor here. We ignore that and just consider 1573 * both for simplicity. 1574 */ 1575 pixel_rate = crtc_state->pixel_rate; 1576 1577 /* Horizontal downscaling limits the maximum pixel rate */ 1578 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 1579 &plane_state->uapi.dst, 1580 0, INT_MAX); 1581 if (hscale < 0x10000) 1582 return pixel_rate; 1583 1584 /* Decimation steps at 2x,4x,8x,16x */ 1585 decimate = ilog2(hscale >> 16); 1586 hscale >>= decimate; 1587 1588 /* Starting limit is 90% of cdclk */ 1589 limit = 9; 1590 1591 /* -10% per decimation step */ 1592 limit -= decimate; 1593 1594 /* -10% for RGB */ 1595 if (fb->format->cpp[0] >= 4) 1596 limit--; /* -10% for RGB */ 1597 1598 /* 1599 * We should also do -10% if sprite scaling is enabled 1600 * on the other pipe, but we can't really check for that, 1601 * so we ignore it. 1602 */ 1603 1604 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale), 1605 limit << 16); 1606 } 1607 1608 static unsigned int 1609 g4x_sprite_max_stride(struct intel_plane *plane, 1610 u32 pixel_format, u64 modifier, 1611 unsigned int rotation) 1612 { 1613 return 16384; 1614 } 1615 1616 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1617 { 1618 u32 dvscntr = 0; 1619 1620 if (crtc_state->gamma_enable) 1621 dvscntr |= DVS_GAMMA_ENABLE; 1622 1623 if (crtc_state->csc_enable) 1624 dvscntr |= DVS_PIPE_CSC_ENABLE; 1625 1626 return dvscntr; 1627 } 1628 1629 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, 1630 const struct intel_plane_state *plane_state) 1631 { 1632 struct drm_i915_private *dev_priv = 1633 to_i915(plane_state->uapi.plane->dev); 1634 const struct drm_framebuffer *fb = plane_state->hw.fb; 1635 unsigned int rotation = plane_state->hw.rotation; 1636 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1637 u32 dvscntr; 1638 1639 dvscntr = DVS_ENABLE; 1640 1641 if (IS_GEN(dev_priv, 6)) 1642 dvscntr |= DVS_TRICKLE_FEED_DISABLE; 1643 1644 switch (fb->format->format) { 1645 case DRM_FORMAT_XBGR8888: 1646 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 1647 break; 1648 case DRM_FORMAT_XRGB8888: 1649 dvscntr |= DVS_FORMAT_RGBX888; 1650 break; 1651 case DRM_FORMAT_XBGR2101010: 1652 dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR; 1653 break; 1654 case DRM_FORMAT_XRGB2101010: 1655 dvscntr |= DVS_FORMAT_RGBX101010; 1656 break; 1657 case DRM_FORMAT_XBGR16161616F: 1658 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR; 1659 break; 1660 case DRM_FORMAT_XRGB16161616F: 1661 dvscntr |= DVS_FORMAT_RGBX161616; 1662 break; 1663 case DRM_FORMAT_YUYV: 1664 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 1665 break; 1666 case DRM_FORMAT_YVYU: 1667 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 1668 break; 1669 case DRM_FORMAT_UYVY: 1670 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 1671 break; 1672 case DRM_FORMAT_VYUY: 1673 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 1674 break; 1675 default: 1676 MISSING_CASE(fb->format->format); 1677 return 0; 1678 } 1679 1680 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1681 dvscntr |= DVS_YUV_FORMAT_BT709; 1682 1683 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1684 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE; 1685 1686 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1687 dvscntr |= DVS_TILED; 1688 1689 if (rotation & DRM_MODE_ROTATE_180) 1690 dvscntr |= DVS_ROTATE_180; 1691 1692 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1693 dvscntr |= DVS_DEST_KEY; 1694 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1695 dvscntr |= DVS_SOURCE_KEY; 1696 1697 return dvscntr; 1698 } 1699 1700 static void g4x_update_gamma(const struct intel_plane_state *plane_state) 1701 { 1702 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1703 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1704 const struct drm_framebuffer *fb = plane_state->hw.fb; 1705 enum pipe pipe = plane->pipe; 1706 u16 gamma[8]; 1707 int i; 1708 1709 /* Seems RGB data bypasses the gamma always */ 1710 if (!fb->format->is_yuv) 1711 return; 1712 1713 i9xx_plane_linear_gamma(gamma); 1714 1715 /* FIXME these register are single buffered :( */ 1716 /* The two end points are implicit (0.0 and 1.0) */ 1717 for (i = 1; i < 8 - 1; i++) 1718 I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), 1719 gamma[i] << 16 | 1720 gamma[i] << 8 | 1721 gamma[i]); 1722 } 1723 1724 static void ilk_sprite_linear_gamma(u16 gamma[17]) 1725 { 1726 int i; 1727 1728 for (i = 0; i < 17; i++) 1729 gamma[i] = (i << 10) / 16; 1730 } 1731 1732 static void ilk_update_gamma(const struct intel_plane_state *plane_state) 1733 { 1734 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1735 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1736 const struct drm_framebuffer *fb = plane_state->hw.fb; 1737 enum pipe pipe = plane->pipe; 1738 u16 gamma[17]; 1739 int i; 1740 1741 /* Seems RGB data bypasses the gamma always */ 1742 if (!fb->format->is_yuv) 1743 return; 1744 1745 ilk_sprite_linear_gamma(gamma); 1746 1747 /* FIXME these register are single buffered :( */ 1748 for (i = 0; i < 16; i++) 1749 I915_WRITE_FW(DVSGAMC_ILK(pipe, i), 1750 gamma[i] << 20 | 1751 gamma[i] << 10 | 1752 gamma[i]); 1753 1754 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1755 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1756 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1757 i++; 1758 } 1759 1760 static void 1761 g4x_update_plane(struct intel_plane *plane, 1762 const struct intel_crtc_state *crtc_state, 1763 const struct intel_plane_state *plane_state) 1764 { 1765 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1766 enum pipe pipe = plane->pipe; 1767 u32 dvssurf_offset = plane_state->color_plane[0].offset; 1768 u32 linear_offset; 1769 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1770 int crtc_x = plane_state->uapi.dst.x1; 1771 int crtc_y = plane_state->uapi.dst.y1; 1772 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1773 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1774 u32 x = plane_state->color_plane[0].x; 1775 u32 y = plane_state->color_plane[0].y; 1776 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1777 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1778 u32 dvscntr, dvsscale = 0; 1779 unsigned long irqflags; 1780 1781 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); 1782 1783 /* Sizes are 0 based */ 1784 src_w--; 1785 src_h--; 1786 crtc_w--; 1787 crtc_h--; 1788 1789 if (crtc_w != src_w || crtc_h != src_h) 1790 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 1791 1792 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1793 1794 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1795 1796 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); 1797 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 1798 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 1799 I915_WRITE_FW(DVSSCALE(pipe), dvsscale); 1800 1801 if (key->flags) { 1802 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); 1803 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); 1804 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); 1805 } 1806 1807 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); 1808 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); 1809 1810 /* 1811 * The control register self-arms if the plane was previously 1812 * disabled. Try to make the plane enable atomic by writing 1813 * the control register just before the surface register. 1814 */ 1815 I915_WRITE_FW(DVSCNTR(pipe), dvscntr); 1816 I915_WRITE_FW(DVSSURF(pipe), 1817 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 1818 1819 if (IS_G4X(dev_priv)) 1820 g4x_update_gamma(plane_state); 1821 else 1822 ilk_update_gamma(plane_state); 1823 1824 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1825 } 1826 1827 static void 1828 g4x_disable_plane(struct intel_plane *plane, 1829 const struct intel_crtc_state *crtc_state) 1830 { 1831 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1832 enum pipe pipe = plane->pipe; 1833 unsigned long irqflags; 1834 1835 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1836 1837 I915_WRITE_FW(DVSCNTR(pipe), 0); 1838 /* Disable the scaler */ 1839 I915_WRITE_FW(DVSSCALE(pipe), 0); 1840 I915_WRITE_FW(DVSSURF(pipe), 0); 1841 1842 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1843 } 1844 1845 static bool 1846 g4x_plane_get_hw_state(struct intel_plane *plane, 1847 enum pipe *pipe) 1848 { 1849 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1850 enum intel_display_power_domain power_domain; 1851 intel_wakeref_t wakeref; 1852 bool ret; 1853 1854 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1855 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1856 if (!wakeref) 1857 return false; 1858 1859 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; 1860 1861 *pipe = plane->pipe; 1862 1863 intel_display_power_put(dev_priv, power_domain, wakeref); 1864 1865 return ret; 1866 } 1867 1868 static bool intel_fb_scalable(const struct drm_framebuffer *fb) 1869 { 1870 if (!fb) 1871 return false; 1872 1873 switch (fb->format->format) { 1874 case DRM_FORMAT_C8: 1875 return false; 1876 case DRM_FORMAT_XRGB16161616F: 1877 case DRM_FORMAT_ARGB16161616F: 1878 case DRM_FORMAT_XBGR16161616F: 1879 case DRM_FORMAT_ABGR16161616F: 1880 return INTEL_GEN(to_i915(fb->dev)) >= 11; 1881 default: 1882 return true; 1883 } 1884 } 1885 1886 static int 1887 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 1888 struct intel_plane_state *plane_state) 1889 { 1890 const struct drm_framebuffer *fb = plane_state->hw.fb; 1891 const struct drm_rect *src = &plane_state->uapi.src; 1892 const struct drm_rect *dst = &plane_state->uapi.dst; 1893 int src_x, src_w, src_h, crtc_w, crtc_h; 1894 const struct drm_display_mode *adjusted_mode = 1895 &crtc_state->hw.adjusted_mode; 1896 unsigned int stride = plane_state->color_plane[0].stride; 1897 unsigned int cpp = fb->format->cpp[0]; 1898 unsigned int width_bytes; 1899 int min_width, min_height; 1900 1901 crtc_w = drm_rect_width(dst); 1902 crtc_h = drm_rect_height(dst); 1903 1904 src_x = src->x1 >> 16; 1905 src_w = drm_rect_width(src) >> 16; 1906 src_h = drm_rect_height(src) >> 16; 1907 1908 if (src_w == crtc_w && src_h == crtc_h) 1909 return 0; 1910 1911 min_width = 3; 1912 1913 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1914 if (src_h & 1) { 1915 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n"); 1916 return -EINVAL; 1917 } 1918 min_height = 6; 1919 } else { 1920 min_height = 3; 1921 } 1922 1923 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 1924 1925 if (src_w < min_width || src_h < min_height || 1926 src_w > 2048 || src_h > 2048) { 1927 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1928 src_w, src_h, min_width, min_height, 2048, 2048); 1929 return -EINVAL; 1930 } 1931 1932 if (width_bytes > 4096) { 1933 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1934 width_bytes, 4096); 1935 return -EINVAL; 1936 } 1937 1938 if (stride > 4096) { 1939 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n", 1940 stride, 4096); 1941 return -EINVAL; 1942 } 1943 1944 return 0; 1945 } 1946 1947 static int 1948 g4x_sprite_check(struct intel_crtc_state *crtc_state, 1949 struct intel_plane_state *plane_state) 1950 { 1951 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1952 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1953 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 1954 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 1955 int ret; 1956 1957 if (intel_fb_scalable(plane_state->hw.fb)) { 1958 if (INTEL_GEN(dev_priv) < 7) { 1959 min_scale = 1; 1960 max_scale = 16 << 16; 1961 } else if (IS_IVYBRIDGE(dev_priv)) { 1962 min_scale = 1; 1963 max_scale = 2 << 16; 1964 } 1965 } 1966 1967 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 1968 &crtc_state->uapi, 1969 min_scale, max_scale, 1970 true, true); 1971 if (ret) 1972 return ret; 1973 1974 ret = i9xx_check_plane_surface(plane_state); 1975 if (ret) 1976 return ret; 1977 1978 if (!plane_state->uapi.visible) 1979 return 0; 1980 1981 ret = intel_plane_check_src_coordinates(plane_state); 1982 if (ret) 1983 return ret; 1984 1985 ret = g4x_sprite_check_scaling(crtc_state, plane_state); 1986 if (ret) 1987 return ret; 1988 1989 if (INTEL_GEN(dev_priv) >= 7) 1990 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 1991 else 1992 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); 1993 1994 return 0; 1995 } 1996 1997 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 1998 { 1999 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2000 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2001 unsigned int rotation = plane_state->hw.rotation; 2002 2003 /* CHV ignores the mirror bit when the rotate bit is set :( */ 2004 if (IS_CHERRYVIEW(dev_priv) && 2005 rotation & DRM_MODE_ROTATE_180 && 2006 rotation & DRM_MODE_REFLECT_X) { 2007 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n"); 2008 return -EINVAL; 2009 } 2010 2011 return 0; 2012 } 2013 2014 static int 2015 vlv_sprite_check(struct intel_crtc_state *crtc_state, 2016 struct intel_plane_state *plane_state) 2017 { 2018 int ret; 2019 2020 ret = chv_plane_check_rotation(plane_state); 2021 if (ret) 2022 return ret; 2023 2024 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 2025 &crtc_state->uapi, 2026 DRM_PLANE_HELPER_NO_SCALING, 2027 DRM_PLANE_HELPER_NO_SCALING, 2028 true, true); 2029 if (ret) 2030 return ret; 2031 2032 ret = i9xx_check_plane_surface(plane_state); 2033 if (ret) 2034 return ret; 2035 2036 if (!plane_state->uapi.visible) 2037 return 0; 2038 2039 ret = intel_plane_check_src_coordinates(plane_state); 2040 if (ret) 2041 return ret; 2042 2043 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); 2044 2045 return 0; 2046 } 2047 2048 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 2049 const struct intel_plane_state *plane_state) 2050 { 2051 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2052 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2053 const struct drm_framebuffer *fb = plane_state->hw.fb; 2054 unsigned int rotation = plane_state->hw.rotation; 2055 struct drm_format_name_buf format_name; 2056 2057 if (!fb) 2058 return 0; 2059 2060 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 2061 is_ccs_modifier(fb->modifier)) { 2062 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n", 2063 rotation); 2064 return -EINVAL; 2065 } 2066 2067 if (rotation & DRM_MODE_REFLECT_X && 2068 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 2069 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n"); 2070 return -EINVAL; 2071 } 2072 2073 if (drm_rotation_90_or_270(rotation)) { 2074 if (fb->modifier != I915_FORMAT_MOD_Y_TILED && 2075 fb->modifier != I915_FORMAT_MOD_Yf_TILED) { 2076 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n"); 2077 return -EINVAL; 2078 } 2079 2080 /* 2081 * 90/270 is not allowed with RGB64 16:16:16:16 and 2082 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 2083 */ 2084 switch (fb->format->format) { 2085 case DRM_FORMAT_RGB565: 2086 if (INTEL_GEN(dev_priv) >= 11) 2087 break; 2088 /* fall through */ 2089 case DRM_FORMAT_C8: 2090 case DRM_FORMAT_XRGB16161616F: 2091 case DRM_FORMAT_XBGR16161616F: 2092 case DRM_FORMAT_ARGB16161616F: 2093 case DRM_FORMAT_ABGR16161616F: 2094 case DRM_FORMAT_Y210: 2095 case DRM_FORMAT_Y212: 2096 case DRM_FORMAT_Y216: 2097 case DRM_FORMAT_XVYU12_16161616: 2098 case DRM_FORMAT_XVYU16161616: 2099 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n", 2100 drm_get_format_name(fb->format->format, 2101 &format_name)); 2102 return -EINVAL; 2103 default: 2104 break; 2105 } 2106 } 2107 2108 /* Y-tiling is not supported in IF-ID Interlace mode */ 2109 if (crtc_state->hw.enable && 2110 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 2111 (fb->modifier == I915_FORMAT_MOD_Y_TILED || 2112 fb->modifier == I915_FORMAT_MOD_Yf_TILED || 2113 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || 2114 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || 2115 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2116 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { 2117 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); 2118 return -EINVAL; 2119 } 2120 2121 return 0; 2122 } 2123 2124 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 2125 const struct intel_plane_state *plane_state) 2126 { 2127 struct drm_i915_private *dev_priv = 2128 to_i915(plane_state->uapi.plane->dev); 2129 int crtc_x = plane_state->uapi.dst.x1; 2130 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 2131 int pipe_src_w = crtc_state->pipe_src_w; 2132 2133 /* 2134 * Display WA #1175: cnl,glk 2135 * Planes other than the cursor may cause FIFO underflow and display 2136 * corruption if starting less than 4 pixels from the right edge of 2137 * the screen. 2138 * Besides the above WA fix the similar problem, where planes other 2139 * than the cursor ending less than 4 pixels from the left edge of the 2140 * screen may cause FIFO underflow and display corruption. 2141 */ 2142 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && 2143 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 2144 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n", 2145 crtc_x + crtc_w < 4 ? "end" : "start", 2146 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 2147 4, pipe_src_w - 4); 2148 return -ERANGE; 2149 } 2150 2151 return 0; 2152 } 2153 2154 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 2155 { 2156 const struct drm_framebuffer *fb = plane_state->hw.fb; 2157 unsigned int rotation = plane_state->hw.rotation; 2158 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 2159 2160 /* Display WA #1106 */ 2161 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2162 src_w & 3 && 2163 (rotation == DRM_MODE_ROTATE_270 || 2164 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 2165 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n"); 2166 return -EINVAL; 2167 } 2168 2169 return 0; 2170 } 2171 2172 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 2173 const struct drm_framebuffer *fb) 2174 { 2175 /* 2176 * We don't yet know the final source width nor 2177 * whether we can use the HQ scaler mode. Assume 2178 * the best case. 2179 * FIXME need to properly check this later. 2180 */ 2181 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || 2182 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 2183 return 0x30000 - 1; 2184 else 2185 return 0x20000 - 1; 2186 } 2187 2188 static int skl_plane_check(struct intel_crtc_state *crtc_state, 2189 struct intel_plane_state *plane_state) 2190 { 2191 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2192 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2193 const struct drm_framebuffer *fb = plane_state->hw.fb; 2194 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 2195 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 2196 int ret; 2197 2198 ret = skl_plane_check_fb(crtc_state, plane_state); 2199 if (ret) 2200 return ret; 2201 2202 /* use scaler when colorkey is not required */ 2203 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) { 2204 min_scale = 1; 2205 max_scale = skl_plane_max_scale(dev_priv, fb); 2206 } 2207 2208 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 2209 &crtc_state->uapi, 2210 min_scale, max_scale, 2211 true, true); 2212 if (ret) 2213 return ret; 2214 2215 ret = skl_check_plane_surface(plane_state); 2216 if (ret) 2217 return ret; 2218 2219 if (!plane_state->uapi.visible) 2220 return 0; 2221 2222 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 2223 if (ret) 2224 return ret; 2225 2226 ret = intel_plane_check_src_coordinates(plane_state); 2227 if (ret) 2228 return ret; 2229 2230 ret = skl_plane_check_nv12_rotation(plane_state); 2231 if (ret) 2232 return ret; 2233 2234 /* HW only has 8 bits pixel precision, disable plane if invisible */ 2235 if (!(plane_state->hw.alpha >> 8)) 2236 plane_state->uapi.visible = false; 2237 2238 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 2239 2240 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2241 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 2242 plane_state); 2243 2244 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2245 icl_is_hdr_plane(dev_priv, plane->id)) 2246 /* Enable and use MPEG-2 chroma siting */ 2247 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2248 PLANE_CUS_HPHASE_0 | 2249 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2250 else 2251 plane_state->cus_ctl = 0; 2252 2253 return 0; 2254 } 2255 2256 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) 2257 { 2258 return INTEL_GEN(dev_priv) >= 9; 2259 } 2260 2261 static void intel_plane_set_ckey(struct intel_plane_state *plane_state, 2262 const struct drm_intel_sprite_colorkey *set) 2263 { 2264 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2265 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2266 struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 2267 2268 *key = *set; 2269 2270 /* 2271 * We want src key enabled on the 2272 * sprite and not on the primary. 2273 */ 2274 if (plane->id == PLANE_PRIMARY && 2275 set->flags & I915_SET_COLORKEY_SOURCE) 2276 key->flags = 0; 2277 2278 /* 2279 * On SKL+ we want dst key enabled on 2280 * the primary and not on the sprite. 2281 */ 2282 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && 2283 set->flags & I915_SET_COLORKEY_DESTINATION) 2284 key->flags = 0; 2285 } 2286 2287 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, 2288 struct drm_file *file_priv) 2289 { 2290 struct drm_i915_private *dev_priv = to_i915(dev); 2291 struct drm_intel_sprite_colorkey *set = data; 2292 struct drm_plane *plane; 2293 struct drm_plane_state *plane_state; 2294 struct drm_atomic_state *state; 2295 struct drm_modeset_acquire_ctx ctx; 2296 int ret = 0; 2297 2298 /* ignore the pointless "none" flag */ 2299 set->flags &= ~I915_SET_COLORKEY_NONE; 2300 2301 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2302 return -EINVAL; 2303 2304 /* Make sure we don't try to enable both src & dest simultaneously */ 2305 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2306 return -EINVAL; 2307 2308 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2309 set->flags & I915_SET_COLORKEY_DESTINATION) 2310 return -EINVAL; 2311 2312 plane = drm_plane_find(dev, file_priv, set->plane_id); 2313 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 2314 return -ENOENT; 2315 2316 /* 2317 * SKL+ only plane 2 can do destination keying against plane 1. 2318 * Also multiple planes can't do destination keying on the same 2319 * pipe simultaneously. 2320 */ 2321 if (INTEL_GEN(dev_priv) >= 9 && 2322 to_intel_plane(plane)->id >= PLANE_SPRITE1 && 2323 set->flags & I915_SET_COLORKEY_DESTINATION) 2324 return -EINVAL; 2325 2326 drm_modeset_acquire_init(&ctx, 0); 2327 2328 state = drm_atomic_state_alloc(plane->dev); 2329 if (!state) { 2330 ret = -ENOMEM; 2331 goto out; 2332 } 2333 state->acquire_ctx = &ctx; 2334 2335 while (1) { 2336 plane_state = drm_atomic_get_plane_state(state, plane); 2337 ret = PTR_ERR_OR_ZERO(plane_state); 2338 if (!ret) 2339 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2340 2341 /* 2342 * On some platforms we have to configure 2343 * the dst colorkey on the primary plane. 2344 */ 2345 if (!ret && has_dst_key_in_primary_plane(dev_priv)) { 2346 struct intel_crtc *crtc = 2347 intel_get_crtc_for_pipe(dev_priv, 2348 to_intel_plane(plane)->pipe); 2349 2350 plane_state = drm_atomic_get_plane_state(state, 2351 crtc->base.primary); 2352 ret = PTR_ERR_OR_ZERO(plane_state); 2353 if (!ret) 2354 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2355 } 2356 2357 if (!ret) 2358 ret = drm_atomic_commit(state); 2359 2360 if (ret != -EDEADLK) 2361 break; 2362 2363 drm_atomic_state_clear(state); 2364 drm_modeset_backoff(&ctx); 2365 } 2366 2367 drm_atomic_state_put(state); 2368 out: 2369 drm_modeset_drop_locks(&ctx); 2370 drm_modeset_acquire_fini(&ctx); 2371 return ret; 2372 } 2373 2374 static const u32 g4x_plane_formats[] = { 2375 DRM_FORMAT_XRGB8888, 2376 DRM_FORMAT_YUYV, 2377 DRM_FORMAT_YVYU, 2378 DRM_FORMAT_UYVY, 2379 DRM_FORMAT_VYUY, 2380 }; 2381 2382 static const u64 i9xx_plane_format_modifiers[] = { 2383 I915_FORMAT_MOD_X_TILED, 2384 DRM_FORMAT_MOD_LINEAR, 2385 DRM_FORMAT_MOD_INVALID 2386 }; 2387 2388 static const u32 snb_plane_formats[] = { 2389 DRM_FORMAT_XRGB8888, 2390 DRM_FORMAT_XBGR8888, 2391 DRM_FORMAT_XRGB2101010, 2392 DRM_FORMAT_XBGR2101010, 2393 DRM_FORMAT_XRGB16161616F, 2394 DRM_FORMAT_XBGR16161616F, 2395 DRM_FORMAT_YUYV, 2396 DRM_FORMAT_YVYU, 2397 DRM_FORMAT_UYVY, 2398 DRM_FORMAT_VYUY, 2399 }; 2400 2401 static const u32 vlv_plane_formats[] = { 2402 DRM_FORMAT_C8, 2403 DRM_FORMAT_RGB565, 2404 DRM_FORMAT_XRGB8888, 2405 DRM_FORMAT_XBGR8888, 2406 DRM_FORMAT_ARGB8888, 2407 DRM_FORMAT_ABGR8888, 2408 DRM_FORMAT_XBGR2101010, 2409 DRM_FORMAT_ABGR2101010, 2410 DRM_FORMAT_YUYV, 2411 DRM_FORMAT_YVYU, 2412 DRM_FORMAT_UYVY, 2413 DRM_FORMAT_VYUY, 2414 }; 2415 2416 static const u32 chv_pipe_b_sprite_formats[] = { 2417 DRM_FORMAT_C8, 2418 DRM_FORMAT_RGB565, 2419 DRM_FORMAT_XRGB8888, 2420 DRM_FORMAT_XBGR8888, 2421 DRM_FORMAT_ARGB8888, 2422 DRM_FORMAT_ABGR8888, 2423 DRM_FORMAT_XRGB2101010, 2424 DRM_FORMAT_XBGR2101010, 2425 DRM_FORMAT_ARGB2101010, 2426 DRM_FORMAT_ABGR2101010, 2427 DRM_FORMAT_YUYV, 2428 DRM_FORMAT_YVYU, 2429 DRM_FORMAT_UYVY, 2430 DRM_FORMAT_VYUY, 2431 }; 2432 2433 static const u32 skl_plane_formats[] = { 2434 DRM_FORMAT_C8, 2435 DRM_FORMAT_RGB565, 2436 DRM_FORMAT_XRGB8888, 2437 DRM_FORMAT_XBGR8888, 2438 DRM_FORMAT_ARGB8888, 2439 DRM_FORMAT_ABGR8888, 2440 DRM_FORMAT_XRGB2101010, 2441 DRM_FORMAT_XBGR2101010, 2442 DRM_FORMAT_XRGB16161616F, 2443 DRM_FORMAT_XBGR16161616F, 2444 DRM_FORMAT_YUYV, 2445 DRM_FORMAT_YVYU, 2446 DRM_FORMAT_UYVY, 2447 DRM_FORMAT_VYUY, 2448 }; 2449 2450 static const u32 skl_planar_formats[] = { 2451 DRM_FORMAT_C8, 2452 DRM_FORMAT_RGB565, 2453 DRM_FORMAT_XRGB8888, 2454 DRM_FORMAT_XBGR8888, 2455 DRM_FORMAT_ARGB8888, 2456 DRM_FORMAT_ABGR8888, 2457 DRM_FORMAT_XRGB2101010, 2458 DRM_FORMAT_XBGR2101010, 2459 DRM_FORMAT_XRGB16161616F, 2460 DRM_FORMAT_XBGR16161616F, 2461 DRM_FORMAT_YUYV, 2462 DRM_FORMAT_YVYU, 2463 DRM_FORMAT_UYVY, 2464 DRM_FORMAT_VYUY, 2465 DRM_FORMAT_NV12, 2466 }; 2467 2468 static const u32 glk_planar_formats[] = { 2469 DRM_FORMAT_C8, 2470 DRM_FORMAT_RGB565, 2471 DRM_FORMAT_XRGB8888, 2472 DRM_FORMAT_XBGR8888, 2473 DRM_FORMAT_ARGB8888, 2474 DRM_FORMAT_ABGR8888, 2475 DRM_FORMAT_XRGB2101010, 2476 DRM_FORMAT_XBGR2101010, 2477 DRM_FORMAT_XRGB16161616F, 2478 DRM_FORMAT_XBGR16161616F, 2479 DRM_FORMAT_YUYV, 2480 DRM_FORMAT_YVYU, 2481 DRM_FORMAT_UYVY, 2482 DRM_FORMAT_VYUY, 2483 DRM_FORMAT_NV12, 2484 DRM_FORMAT_P010, 2485 DRM_FORMAT_P012, 2486 DRM_FORMAT_P016, 2487 }; 2488 2489 static const u32 icl_sdr_y_plane_formats[] = { 2490 DRM_FORMAT_C8, 2491 DRM_FORMAT_RGB565, 2492 DRM_FORMAT_XRGB8888, 2493 DRM_FORMAT_XBGR8888, 2494 DRM_FORMAT_ARGB8888, 2495 DRM_FORMAT_ABGR8888, 2496 DRM_FORMAT_XRGB2101010, 2497 DRM_FORMAT_XBGR2101010, 2498 DRM_FORMAT_ARGB2101010, 2499 DRM_FORMAT_ABGR2101010, 2500 DRM_FORMAT_YUYV, 2501 DRM_FORMAT_YVYU, 2502 DRM_FORMAT_UYVY, 2503 DRM_FORMAT_VYUY, 2504 DRM_FORMAT_Y210, 2505 DRM_FORMAT_Y212, 2506 DRM_FORMAT_Y216, 2507 DRM_FORMAT_XVYU2101010, 2508 DRM_FORMAT_XVYU12_16161616, 2509 DRM_FORMAT_XVYU16161616, 2510 }; 2511 2512 static const u32 icl_sdr_uv_plane_formats[] = { 2513 DRM_FORMAT_C8, 2514 DRM_FORMAT_RGB565, 2515 DRM_FORMAT_XRGB8888, 2516 DRM_FORMAT_XBGR8888, 2517 DRM_FORMAT_ARGB8888, 2518 DRM_FORMAT_ABGR8888, 2519 DRM_FORMAT_XRGB2101010, 2520 DRM_FORMAT_XBGR2101010, 2521 DRM_FORMAT_ARGB2101010, 2522 DRM_FORMAT_ABGR2101010, 2523 DRM_FORMAT_YUYV, 2524 DRM_FORMAT_YVYU, 2525 DRM_FORMAT_UYVY, 2526 DRM_FORMAT_VYUY, 2527 DRM_FORMAT_NV12, 2528 DRM_FORMAT_P010, 2529 DRM_FORMAT_P012, 2530 DRM_FORMAT_P016, 2531 DRM_FORMAT_Y210, 2532 DRM_FORMAT_Y212, 2533 DRM_FORMAT_Y216, 2534 DRM_FORMAT_XVYU2101010, 2535 DRM_FORMAT_XVYU12_16161616, 2536 DRM_FORMAT_XVYU16161616, 2537 }; 2538 2539 static const u32 icl_hdr_plane_formats[] = { 2540 DRM_FORMAT_C8, 2541 DRM_FORMAT_RGB565, 2542 DRM_FORMAT_XRGB8888, 2543 DRM_FORMAT_XBGR8888, 2544 DRM_FORMAT_ARGB8888, 2545 DRM_FORMAT_ABGR8888, 2546 DRM_FORMAT_XRGB2101010, 2547 DRM_FORMAT_XBGR2101010, 2548 DRM_FORMAT_ARGB2101010, 2549 DRM_FORMAT_ABGR2101010, 2550 DRM_FORMAT_XRGB16161616F, 2551 DRM_FORMAT_XBGR16161616F, 2552 DRM_FORMAT_ARGB16161616F, 2553 DRM_FORMAT_ABGR16161616F, 2554 DRM_FORMAT_YUYV, 2555 DRM_FORMAT_YVYU, 2556 DRM_FORMAT_UYVY, 2557 DRM_FORMAT_VYUY, 2558 DRM_FORMAT_NV12, 2559 DRM_FORMAT_P010, 2560 DRM_FORMAT_P012, 2561 DRM_FORMAT_P016, 2562 DRM_FORMAT_Y210, 2563 DRM_FORMAT_Y212, 2564 DRM_FORMAT_Y216, 2565 DRM_FORMAT_XVYU2101010, 2566 DRM_FORMAT_XVYU12_16161616, 2567 DRM_FORMAT_XVYU16161616, 2568 }; 2569 2570 static const u64 skl_plane_format_modifiers_noccs[] = { 2571 I915_FORMAT_MOD_Yf_TILED, 2572 I915_FORMAT_MOD_Y_TILED, 2573 I915_FORMAT_MOD_X_TILED, 2574 DRM_FORMAT_MOD_LINEAR, 2575 DRM_FORMAT_MOD_INVALID 2576 }; 2577 2578 static const u64 skl_plane_format_modifiers_ccs[] = { 2579 I915_FORMAT_MOD_Yf_TILED_CCS, 2580 I915_FORMAT_MOD_Y_TILED_CCS, 2581 I915_FORMAT_MOD_Yf_TILED, 2582 I915_FORMAT_MOD_Y_TILED, 2583 I915_FORMAT_MOD_X_TILED, 2584 DRM_FORMAT_MOD_LINEAR, 2585 DRM_FORMAT_MOD_INVALID 2586 }; 2587 2588 static const u64 gen12_plane_format_modifiers_mc_ccs[] = { 2589 I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 2590 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2591 I915_FORMAT_MOD_Y_TILED, 2592 I915_FORMAT_MOD_X_TILED, 2593 DRM_FORMAT_MOD_LINEAR, 2594 DRM_FORMAT_MOD_INVALID 2595 }; 2596 2597 static const u64 gen12_plane_format_modifiers_rc_ccs[] = { 2598 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2599 I915_FORMAT_MOD_Y_TILED, 2600 I915_FORMAT_MOD_X_TILED, 2601 DRM_FORMAT_MOD_LINEAR, 2602 DRM_FORMAT_MOD_INVALID 2603 }; 2604 2605 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, 2606 u32 format, u64 modifier) 2607 { 2608 switch (modifier) { 2609 case DRM_FORMAT_MOD_LINEAR: 2610 case I915_FORMAT_MOD_X_TILED: 2611 break; 2612 default: 2613 return false; 2614 } 2615 2616 switch (format) { 2617 case DRM_FORMAT_XRGB8888: 2618 case DRM_FORMAT_YUYV: 2619 case DRM_FORMAT_YVYU: 2620 case DRM_FORMAT_UYVY: 2621 case DRM_FORMAT_VYUY: 2622 if (modifier == DRM_FORMAT_MOD_LINEAR || 2623 modifier == I915_FORMAT_MOD_X_TILED) 2624 return true; 2625 /* fall through */ 2626 default: 2627 return false; 2628 } 2629 } 2630 2631 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, 2632 u32 format, u64 modifier) 2633 { 2634 switch (modifier) { 2635 case DRM_FORMAT_MOD_LINEAR: 2636 case I915_FORMAT_MOD_X_TILED: 2637 break; 2638 default: 2639 return false; 2640 } 2641 2642 switch (format) { 2643 case DRM_FORMAT_XRGB8888: 2644 case DRM_FORMAT_XBGR8888: 2645 case DRM_FORMAT_XRGB2101010: 2646 case DRM_FORMAT_XBGR2101010: 2647 case DRM_FORMAT_XRGB16161616F: 2648 case DRM_FORMAT_XBGR16161616F: 2649 case DRM_FORMAT_YUYV: 2650 case DRM_FORMAT_YVYU: 2651 case DRM_FORMAT_UYVY: 2652 case DRM_FORMAT_VYUY: 2653 if (modifier == DRM_FORMAT_MOD_LINEAR || 2654 modifier == I915_FORMAT_MOD_X_TILED) 2655 return true; 2656 /* fall through */ 2657 default: 2658 return false; 2659 } 2660 } 2661 2662 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, 2663 u32 format, u64 modifier) 2664 { 2665 switch (modifier) { 2666 case DRM_FORMAT_MOD_LINEAR: 2667 case I915_FORMAT_MOD_X_TILED: 2668 break; 2669 default: 2670 return false; 2671 } 2672 2673 switch (format) { 2674 case DRM_FORMAT_C8: 2675 case DRM_FORMAT_RGB565: 2676 case DRM_FORMAT_ABGR8888: 2677 case DRM_FORMAT_ARGB8888: 2678 case DRM_FORMAT_XBGR8888: 2679 case DRM_FORMAT_XRGB8888: 2680 case DRM_FORMAT_XBGR2101010: 2681 case DRM_FORMAT_ABGR2101010: 2682 case DRM_FORMAT_XRGB2101010: 2683 case DRM_FORMAT_ARGB2101010: 2684 case DRM_FORMAT_YUYV: 2685 case DRM_FORMAT_YVYU: 2686 case DRM_FORMAT_UYVY: 2687 case DRM_FORMAT_VYUY: 2688 if (modifier == DRM_FORMAT_MOD_LINEAR || 2689 modifier == I915_FORMAT_MOD_X_TILED) 2690 return true; 2691 /* fall through */ 2692 default: 2693 return false; 2694 } 2695 } 2696 2697 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2698 u32 format, u64 modifier) 2699 { 2700 struct intel_plane *plane = to_intel_plane(_plane); 2701 2702 switch (modifier) { 2703 case DRM_FORMAT_MOD_LINEAR: 2704 case I915_FORMAT_MOD_X_TILED: 2705 case I915_FORMAT_MOD_Y_TILED: 2706 case I915_FORMAT_MOD_Yf_TILED: 2707 break; 2708 case I915_FORMAT_MOD_Y_TILED_CCS: 2709 case I915_FORMAT_MOD_Yf_TILED_CCS: 2710 if (!plane->has_ccs) 2711 return false; 2712 break; 2713 default: 2714 return false; 2715 } 2716 2717 switch (format) { 2718 case DRM_FORMAT_XRGB8888: 2719 case DRM_FORMAT_XBGR8888: 2720 case DRM_FORMAT_ARGB8888: 2721 case DRM_FORMAT_ABGR8888: 2722 if (is_ccs_modifier(modifier)) 2723 return true; 2724 /* fall through */ 2725 case DRM_FORMAT_RGB565: 2726 case DRM_FORMAT_XRGB2101010: 2727 case DRM_FORMAT_XBGR2101010: 2728 case DRM_FORMAT_ARGB2101010: 2729 case DRM_FORMAT_ABGR2101010: 2730 case DRM_FORMAT_YUYV: 2731 case DRM_FORMAT_YVYU: 2732 case DRM_FORMAT_UYVY: 2733 case DRM_FORMAT_VYUY: 2734 case DRM_FORMAT_NV12: 2735 case DRM_FORMAT_P010: 2736 case DRM_FORMAT_P012: 2737 case DRM_FORMAT_P016: 2738 case DRM_FORMAT_XVYU2101010: 2739 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2740 return true; 2741 /* fall through */ 2742 case DRM_FORMAT_C8: 2743 case DRM_FORMAT_XBGR16161616F: 2744 case DRM_FORMAT_ABGR16161616F: 2745 case DRM_FORMAT_XRGB16161616F: 2746 case DRM_FORMAT_ARGB16161616F: 2747 case DRM_FORMAT_Y210: 2748 case DRM_FORMAT_Y212: 2749 case DRM_FORMAT_Y216: 2750 case DRM_FORMAT_XVYU12_16161616: 2751 case DRM_FORMAT_XVYU16161616: 2752 if (modifier == DRM_FORMAT_MOD_LINEAR || 2753 modifier == I915_FORMAT_MOD_X_TILED || 2754 modifier == I915_FORMAT_MOD_Y_TILED) 2755 return true; 2756 /* fall through */ 2757 default: 2758 return false; 2759 } 2760 } 2761 2762 static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id) 2763 { 2764 return plane_id < PLANE_SPRITE4; 2765 } 2766 2767 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2768 u32 format, u64 modifier) 2769 { 2770 struct intel_plane *plane = to_intel_plane(_plane); 2771 2772 switch (modifier) { 2773 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 2774 if (!gen12_plane_supports_mc_ccs(plane->id)) 2775 return false; 2776 /* fall through */ 2777 case DRM_FORMAT_MOD_LINEAR: 2778 case I915_FORMAT_MOD_X_TILED: 2779 case I915_FORMAT_MOD_Y_TILED: 2780 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 2781 break; 2782 default: 2783 return false; 2784 } 2785 2786 switch (format) { 2787 case DRM_FORMAT_XRGB8888: 2788 case DRM_FORMAT_XBGR8888: 2789 case DRM_FORMAT_ARGB8888: 2790 case DRM_FORMAT_ABGR8888: 2791 if (is_ccs_modifier(modifier)) 2792 return true; 2793 /* fall through */ 2794 case DRM_FORMAT_YUYV: 2795 case DRM_FORMAT_YVYU: 2796 case DRM_FORMAT_UYVY: 2797 case DRM_FORMAT_VYUY: 2798 case DRM_FORMAT_NV12: 2799 case DRM_FORMAT_P010: 2800 case DRM_FORMAT_P012: 2801 case DRM_FORMAT_P016: 2802 if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) 2803 return true; 2804 /* fall through */ 2805 case DRM_FORMAT_RGB565: 2806 case DRM_FORMAT_XRGB2101010: 2807 case DRM_FORMAT_XBGR2101010: 2808 case DRM_FORMAT_ARGB2101010: 2809 case DRM_FORMAT_ABGR2101010: 2810 case DRM_FORMAT_XVYU2101010: 2811 case DRM_FORMAT_C8: 2812 case DRM_FORMAT_XBGR16161616F: 2813 case DRM_FORMAT_ABGR16161616F: 2814 case DRM_FORMAT_XRGB16161616F: 2815 case DRM_FORMAT_ARGB16161616F: 2816 case DRM_FORMAT_Y210: 2817 case DRM_FORMAT_Y212: 2818 case DRM_FORMAT_Y216: 2819 case DRM_FORMAT_XVYU12_16161616: 2820 case DRM_FORMAT_XVYU16161616: 2821 if (modifier == DRM_FORMAT_MOD_LINEAR || 2822 modifier == I915_FORMAT_MOD_X_TILED || 2823 modifier == I915_FORMAT_MOD_Y_TILED) 2824 return true; 2825 /* fall through */ 2826 default: 2827 return false; 2828 } 2829 } 2830 2831 static const struct drm_plane_funcs g4x_sprite_funcs = { 2832 .update_plane = drm_atomic_helper_update_plane, 2833 .disable_plane = drm_atomic_helper_disable_plane, 2834 .destroy = intel_plane_destroy, 2835 .atomic_duplicate_state = intel_plane_duplicate_state, 2836 .atomic_destroy_state = intel_plane_destroy_state, 2837 .format_mod_supported = g4x_sprite_format_mod_supported, 2838 }; 2839 2840 static const struct drm_plane_funcs snb_sprite_funcs = { 2841 .update_plane = drm_atomic_helper_update_plane, 2842 .disable_plane = drm_atomic_helper_disable_plane, 2843 .destroy = intel_plane_destroy, 2844 .atomic_duplicate_state = intel_plane_duplicate_state, 2845 .atomic_destroy_state = intel_plane_destroy_state, 2846 .format_mod_supported = snb_sprite_format_mod_supported, 2847 }; 2848 2849 static const struct drm_plane_funcs vlv_sprite_funcs = { 2850 .update_plane = drm_atomic_helper_update_plane, 2851 .disable_plane = drm_atomic_helper_disable_plane, 2852 .destroy = intel_plane_destroy, 2853 .atomic_duplicate_state = intel_plane_duplicate_state, 2854 .atomic_destroy_state = intel_plane_destroy_state, 2855 .format_mod_supported = vlv_sprite_format_mod_supported, 2856 }; 2857 2858 static const struct drm_plane_funcs skl_plane_funcs = { 2859 .update_plane = drm_atomic_helper_update_plane, 2860 .disable_plane = drm_atomic_helper_disable_plane, 2861 .destroy = intel_plane_destroy, 2862 .atomic_duplicate_state = intel_plane_duplicate_state, 2863 .atomic_destroy_state = intel_plane_destroy_state, 2864 .format_mod_supported = skl_plane_format_mod_supported, 2865 }; 2866 2867 static const struct drm_plane_funcs gen12_plane_funcs = { 2868 .update_plane = drm_atomic_helper_update_plane, 2869 .disable_plane = drm_atomic_helper_disable_plane, 2870 .destroy = intel_plane_destroy, 2871 .atomic_duplicate_state = intel_plane_duplicate_state, 2872 .atomic_destroy_state = intel_plane_destroy_state, 2873 .format_mod_supported = gen12_plane_format_mod_supported, 2874 }; 2875 2876 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 2877 enum pipe pipe, enum plane_id plane_id) 2878 { 2879 if (!HAS_FBC(dev_priv)) 2880 return false; 2881 2882 return pipe == PIPE_A && plane_id == PLANE_PRIMARY; 2883 } 2884 2885 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2886 enum pipe pipe, enum plane_id plane_id) 2887 { 2888 /* Display WA #0870: skl, bxt */ 2889 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 2890 return false; 2891 2892 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) 2893 return false; 2894 2895 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 2896 return false; 2897 2898 return true; 2899 } 2900 2901 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 2902 enum pipe pipe, enum plane_id plane_id, 2903 int *num_formats) 2904 { 2905 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2906 *num_formats = ARRAY_SIZE(skl_planar_formats); 2907 return skl_planar_formats; 2908 } else { 2909 *num_formats = ARRAY_SIZE(skl_plane_formats); 2910 return skl_plane_formats; 2911 } 2912 } 2913 2914 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 2915 enum pipe pipe, enum plane_id plane_id, 2916 int *num_formats) 2917 { 2918 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2919 *num_formats = ARRAY_SIZE(glk_planar_formats); 2920 return glk_planar_formats; 2921 } else { 2922 *num_formats = ARRAY_SIZE(skl_plane_formats); 2923 return skl_plane_formats; 2924 } 2925 } 2926 2927 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2928 enum pipe pipe, enum plane_id plane_id, 2929 int *num_formats) 2930 { 2931 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2932 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2933 return icl_hdr_plane_formats; 2934 } else if (icl_is_nv12_y_plane(plane_id)) { 2935 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2936 return icl_sdr_y_plane_formats; 2937 } else { 2938 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2939 return icl_sdr_uv_plane_formats; 2940 } 2941 } 2942 2943 static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id) 2944 { 2945 if (gen12_plane_supports_mc_ccs(plane_id)) 2946 return gen12_plane_format_modifiers_mc_ccs; 2947 else 2948 return gen12_plane_format_modifiers_rc_ccs; 2949 } 2950 2951 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, 2952 enum pipe pipe, enum plane_id plane_id) 2953 { 2954 if (plane_id == PLANE_CURSOR) 2955 return false; 2956 2957 if (INTEL_GEN(dev_priv) >= 10) 2958 return true; 2959 2960 if (IS_GEMINILAKE(dev_priv)) 2961 return pipe != PIPE_C; 2962 2963 return pipe != PIPE_C && 2964 (plane_id == PLANE_PRIMARY || 2965 plane_id == PLANE_SPRITE0); 2966 } 2967 2968 struct intel_plane * 2969 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2970 enum pipe pipe, enum plane_id plane_id) 2971 { 2972 const struct drm_plane_funcs *plane_funcs; 2973 struct intel_plane *plane; 2974 enum drm_plane_type plane_type; 2975 unsigned int supported_rotations; 2976 unsigned int possible_crtcs; 2977 const u64 *modifiers; 2978 const u32 *formats; 2979 int num_formats; 2980 int ret; 2981 2982 plane = intel_plane_alloc(); 2983 if (IS_ERR(plane)) 2984 return plane; 2985 2986 plane->pipe = pipe; 2987 plane->id = plane_id; 2988 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 2989 2990 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id); 2991 if (plane->has_fbc) { 2992 struct intel_fbc *fbc = &dev_priv->fbc; 2993 2994 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 2995 } 2996 2997 plane->max_stride = skl_plane_max_stride; 2998 plane->update_plane = skl_update_plane; 2999 plane->disable_plane = skl_disable_plane; 3000 plane->get_hw_state = skl_plane_get_hw_state; 3001 plane->check_plane = skl_plane_check; 3002 plane->min_cdclk = skl_plane_min_cdclk; 3003 3004 if (INTEL_GEN(dev_priv) >= 11) 3005 formats = icl_get_plane_formats(dev_priv, pipe, 3006 plane_id, &num_formats); 3007 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3008 formats = glk_get_plane_formats(dev_priv, pipe, 3009 plane_id, &num_formats); 3010 else 3011 formats = skl_get_plane_formats(dev_priv, pipe, 3012 plane_id, &num_formats); 3013 3014 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); 3015 if (INTEL_GEN(dev_priv) >= 12) { 3016 modifiers = gen12_get_plane_modifiers(plane_id); 3017 plane_funcs = &gen12_plane_funcs; 3018 } else { 3019 if (plane->has_ccs) 3020 modifiers = skl_plane_format_modifiers_ccs; 3021 else 3022 modifiers = skl_plane_format_modifiers_noccs; 3023 plane_funcs = &skl_plane_funcs; 3024 } 3025 3026 if (plane_id == PLANE_PRIMARY) 3027 plane_type = DRM_PLANE_TYPE_PRIMARY; 3028 else 3029 plane_type = DRM_PLANE_TYPE_OVERLAY; 3030 3031 possible_crtcs = BIT(pipe); 3032 3033 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3034 possible_crtcs, plane_funcs, 3035 formats, num_formats, modifiers, 3036 plane_type, 3037 "plane %d%c", plane_id + 1, 3038 pipe_name(pipe)); 3039 if (ret) 3040 goto fail; 3041 3042 supported_rotations = 3043 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 3044 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 3045 3046 if (INTEL_GEN(dev_priv) >= 10) 3047 supported_rotations |= DRM_MODE_REFLECT_X; 3048 3049 drm_plane_create_rotation_property(&plane->base, 3050 DRM_MODE_ROTATE_0, 3051 supported_rotations); 3052 3053 drm_plane_create_color_properties(&plane->base, 3054 BIT(DRM_COLOR_YCBCR_BT601) | 3055 BIT(DRM_COLOR_YCBCR_BT709), 3056 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3057 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3058 DRM_COLOR_YCBCR_BT709, 3059 DRM_COLOR_YCBCR_LIMITED_RANGE); 3060 3061 drm_plane_create_alpha_property(&plane->base); 3062 drm_plane_create_blend_mode_property(&plane->base, 3063 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 3064 BIT(DRM_MODE_BLEND_PREMULTI) | 3065 BIT(DRM_MODE_BLEND_COVERAGE)); 3066 3067 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 3068 3069 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3070 3071 return plane; 3072 3073 fail: 3074 intel_plane_free(plane); 3075 3076 return ERR_PTR(ret); 3077 } 3078 3079 struct intel_plane * 3080 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 3081 enum pipe pipe, int sprite) 3082 { 3083 struct intel_plane *plane; 3084 const struct drm_plane_funcs *plane_funcs; 3085 unsigned long possible_crtcs; 3086 unsigned int supported_rotations; 3087 const u64 *modifiers; 3088 const u32 *formats; 3089 int num_formats; 3090 int ret, zpos; 3091 3092 if (INTEL_GEN(dev_priv) >= 9) 3093 return skl_universal_plane_create(dev_priv, pipe, 3094 PLANE_SPRITE0 + sprite); 3095 3096 plane = intel_plane_alloc(); 3097 if (IS_ERR(plane)) 3098 return plane; 3099 3100 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3101 plane->max_stride = i9xx_plane_max_stride; 3102 plane->update_plane = vlv_update_plane; 3103 plane->disable_plane = vlv_disable_plane; 3104 plane->get_hw_state = vlv_plane_get_hw_state; 3105 plane->check_plane = vlv_sprite_check; 3106 plane->min_cdclk = vlv_plane_min_cdclk; 3107 3108 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3109 formats = chv_pipe_b_sprite_formats; 3110 num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); 3111 } else { 3112 formats = vlv_plane_formats; 3113 num_formats = ARRAY_SIZE(vlv_plane_formats); 3114 } 3115 modifiers = i9xx_plane_format_modifiers; 3116 3117 plane_funcs = &vlv_sprite_funcs; 3118 } else if (INTEL_GEN(dev_priv) >= 7) { 3119 plane->max_stride = g4x_sprite_max_stride; 3120 plane->update_plane = ivb_update_plane; 3121 plane->disable_plane = ivb_disable_plane; 3122 plane->get_hw_state = ivb_plane_get_hw_state; 3123 plane->check_plane = g4x_sprite_check; 3124 3125 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3126 plane->min_cdclk = hsw_plane_min_cdclk; 3127 else 3128 plane->min_cdclk = ivb_sprite_min_cdclk; 3129 3130 formats = snb_plane_formats; 3131 num_formats = ARRAY_SIZE(snb_plane_formats); 3132 modifiers = i9xx_plane_format_modifiers; 3133 3134 plane_funcs = &snb_sprite_funcs; 3135 } else { 3136 plane->max_stride = g4x_sprite_max_stride; 3137 plane->update_plane = g4x_update_plane; 3138 plane->disable_plane = g4x_disable_plane; 3139 plane->get_hw_state = g4x_plane_get_hw_state; 3140 plane->check_plane = g4x_sprite_check; 3141 plane->min_cdclk = g4x_sprite_min_cdclk; 3142 3143 modifiers = i9xx_plane_format_modifiers; 3144 if (IS_GEN(dev_priv, 6)) { 3145 formats = snb_plane_formats; 3146 num_formats = ARRAY_SIZE(snb_plane_formats); 3147 3148 plane_funcs = &snb_sprite_funcs; 3149 } else { 3150 formats = g4x_plane_formats; 3151 num_formats = ARRAY_SIZE(g4x_plane_formats); 3152 3153 plane_funcs = &g4x_sprite_funcs; 3154 } 3155 } 3156 3157 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3158 supported_rotations = 3159 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 3160 DRM_MODE_REFLECT_X; 3161 } else { 3162 supported_rotations = 3163 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 3164 } 3165 3166 plane->pipe = pipe; 3167 plane->id = PLANE_SPRITE0 + sprite; 3168 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 3169 3170 possible_crtcs = BIT(pipe); 3171 3172 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3173 possible_crtcs, plane_funcs, 3174 formats, num_formats, modifiers, 3175 DRM_PLANE_TYPE_OVERLAY, 3176 "sprite %c", sprite_name(pipe, sprite)); 3177 if (ret) 3178 goto fail; 3179 3180 drm_plane_create_rotation_property(&plane->base, 3181 DRM_MODE_ROTATE_0, 3182 supported_rotations); 3183 3184 drm_plane_create_color_properties(&plane->base, 3185 BIT(DRM_COLOR_YCBCR_BT601) | 3186 BIT(DRM_COLOR_YCBCR_BT709), 3187 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3188 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3189 DRM_COLOR_YCBCR_BT709, 3190 DRM_COLOR_YCBCR_LIMITED_RANGE); 3191 3192 zpos = sprite + 1; 3193 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 3194 3195 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3196 3197 return plane; 3198 3199 fail: 3200 intel_plane_free(plane); 3201 3202 return ERR_PTR(ret); 3203 } 3204
Indexes created Thu Oct 02 07:10:07 GMT 2025