intel_sprite.c revision 1.2
1 /* $NetBSD: intel_sprite.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Intel Corporation 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the next 14 * paragraph) shall be included in all copies or substantial portions of the 15 * Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 * SOFTWARE. 24 * 25 * Authors: 26 * Jesse Barnes <jbarnes (at) virtuousgeek.org> 27 * 28 * New plane/sprite handling. 29 * 30 * The older chips had a separate interface for programming plane related 31 * registers; newer ones are much simpler and we can use the new DRM plane 32 * support. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: intel_sprite.c,v 1.2 2021/12/18 23:45:30 riastradh Exp $"); 37 38 #include <drm/drm_atomic.h> 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_color_mgmt.h> 41 #include <drm/drm_crtc.h> 42 #include <drm/drm_fourcc.h> 43 #include <drm/drm_plane_helper.h> 44 #include <drm/drm_rect.h> 45 #include <drm/i915_drm.h> 46 47 #include "i915_drv.h" 48 #include "i915_trace.h" 49 #include "intel_atomic_plane.h" 50 #include "intel_display_types.h" 51 #include "intel_frontbuffer.h" 52 #include "intel_pm.h" 53 #include "intel_psr.h" 54 #include "intel_sprite.h" 55 56 int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, 57 int usecs) 58 { 59 /* paranoia */ 60 if (!adjusted_mode->crtc_htotal) 61 return 1; 62 63 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, 64 1000 * adjusted_mode->crtc_htotal); 65 } 66 67 /* FIXME: We should instead only take spinlocks once for the entire update 68 * instead of once per mmio. */ 69 #if IS_ENABLED(CONFIG_PROVE_LOCKING) 70 #define VBLANK_EVASION_TIME_US 250 71 #else 72 #define VBLANK_EVASION_TIME_US 100 73 #endif 74 75 /** 76 * intel_pipe_update_start() - start update of a set of display registers 77 * @new_crtc_state: the new crtc state 78 * 79 * Mark the start of an update to pipe registers that should be updated 80 * atomically regarding vblank. If the next vblank will happens within 81 * the next 100 us, this function waits until the vblank passes. 82 * 83 * After a successful call to this function, interrupts will be disabled 84 * until a subsequent call to intel_pipe_update_end(). That is done to 85 * avoid random delays. 86 */ 87 void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state) 88 { 89 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 90 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 91 const struct drm_display_mode *adjusted_mode = &new_crtc_state->hw.adjusted_mode; 92 long timeout = msecs_to_jiffies_timeout(1); 93 int scanline, min, max, vblank_start; 94 #ifdef __NetBSD__ 95 drm_waitqueue_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 96 int ret; 97 #else 98 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 99 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 100 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI); 101 DEFINE_WAIT(wait); 102 #endif 103 u32 psr_status; 104 105 vblank_start = adjusted_mode->crtc_vblank_start; 106 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 107 vblank_start = DIV_ROUND_UP(vblank_start, 2); 108 109 /* FIXME needs to be calibrated sensibly */ 110 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode, 111 VBLANK_EVASION_TIME_US); 112 max = vblank_start - 1; 113 114 if (min <= 0 || max <= 0) 115 goto irq_disable; 116 117 if (WARN_ON(drm_crtc_vblank_get(&crtc->base))) 118 goto irq_disable; 119 120 /* 121 * Wait for psr to idle out after enabling the VBL interrupts 122 * VBL interrupts will start the PSR exit and prevent a PSR 123 * re-entry as well. 124 */ 125 if (intel_psr_wait_for_idle(new_crtc_state, &psr_status)) 126 DRM_ERROR("PSR idle timed out 0x%x, atomic update may fail\n", 127 psr_status); 128 129 #ifdef __NetBSD__ 130 spin_lock(&dev->vbl_lock); 131 #else 132 local_irq_disable(); 133 #endif 134 135 crtc->debug.min_vbl = min; 136 crtc->debug.max_vbl = max; 137 trace_intel_pipe_update_start(crtc); 138 139 #ifdef __NetBSD__ 140 DRM_SPIN_TIMED_WAIT_NOINTR_UNTIL(ret, wq, &dev->vbl_lock, timeout, 141 (scanline = intel_get_crtc_scanline(crtc), 142 scanline < min || scanline > max)); 143 if (ret <= 0) 144 DRM_ERROR("Potential atomic update failure on pipe %c: %d\n", 145 pipe_name(crtc->pipe), ret ? ret : -EWOULDBLOCK); 146 drm_crtc_vblank_put_locked(&crtc->base); 147 #else 148 for (;;) { 149 /* 150 * prepare_to_wait() has a memory barrier, which guarantees 151 * other CPUs can see the task state update by the time we 152 * read the scanline. 153 */ 154 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE); 155 156 scanline = intel_get_crtc_scanline(crtc); 157 if (scanline < min || scanline > max) 158 break; 159 160 if (!timeout) { 161 DRM_ERROR("Potential atomic update failure on pipe %c\n", 162 pipe_name(crtc->pipe)); 163 break; 164 } 165 166 local_irq_enable(); 167 168 timeout = schedule_timeout(timeout); 169 170 local_irq_disable(); 171 } 172 173 finish_wait(wq, &wait); 174 175 drm_crtc_vblank_put(&crtc->base); 176 #endif 177 178 /* 179 * On VLV/CHV DSI the scanline counter would appear to 180 * increment approx. 1/3 of a scanline before start of vblank. 181 * The registers still get latched at start of vblank however. 182 * This means we must not write any registers on the first 183 * line of vblank (since not the whole line is actually in 184 * vblank). And unfortunately we can't use the interrupt to 185 * wait here since it will fire too soon. We could use the 186 * frame start interrupt instead since it will fire after the 187 * critical scanline, but that would require more changes 188 * in the interrupt code. So for now we'll just do the nasty 189 * thing and poll for the bad scanline to pass us by. 190 * 191 * FIXME figure out if BXT+ DSI suffers from this as well 192 */ 193 while (need_vlv_dsi_wa && scanline == vblank_start) 194 scanline = intel_get_crtc_scanline(crtc); 195 196 crtc->debug.scanline_start = scanline; 197 crtc->debug.start_vbl_time = ktime_get(); 198 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc); 199 200 trace_intel_pipe_update_vblank_evaded(crtc); 201 return; 202 203 irq_disable: 204 local_irq_disable(); 205 } 206 207 /** 208 * intel_pipe_update_end() - end update of a set of display registers 209 * @new_crtc_state: the new crtc state 210 * 211 * Mark the end of an update started with intel_pipe_update_start(). This 212 * re-enables interrupts and verifies the update was actually completed 213 * before a vblank. 214 */ 215 void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state) 216 { 217 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); 218 enum pipe pipe = crtc->pipe; 219 int scanline_end = intel_get_crtc_scanline(crtc); 220 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc); 221 ktime_t end_vbl_time = ktime_get(); 222 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 223 224 trace_intel_pipe_update_end(crtc, end_vbl_count, scanline_end); 225 226 /* We're still in the vblank-evade critical section, this can't race. 227 * Would be slightly nice to just grab the vblank count and arm the 228 * event outside of the critical section - the spinlock might spin for a 229 * while ... */ 230 if (new_crtc_state->uapi.event) { 231 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0); 232 233 spin_lock(&crtc->base.dev->event_lock); 234 drm_crtc_arm_vblank_event(&crtc->base, 235 new_crtc_state->uapi.event); 236 spin_unlock(&crtc->base.dev->event_lock); 237 238 new_crtc_state->uapi.event = NULL; 239 } 240 241 #ifdef __NetBSD__ 242 spin_unlock(&dev->vbl_lock); 243 #else 244 local_irq_enable(); 245 #endif 246 247 if (intel_vgpu_active(dev_priv)) 248 return; 249 250 if (crtc->debug.start_vbl_count && 251 crtc->debug.start_vbl_count != end_vbl_count) { 252 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %"PRIdMAX" us, min %d, max %d, scanline start %d, end %d\n", 253 pipe_name(pipe), crtc->debug.start_vbl_count, 254 end_vbl_count, 255 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 256 crtc->debug.min_vbl, crtc->debug.max_vbl, 257 crtc->debug.scanline_start, scanline_end); 258 } 259 #ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE 260 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) > 261 VBLANK_EVASION_TIME_US) 262 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n", 263 pipe_name(pipe), 264 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time), 265 VBLANK_EVASION_TIME_US); 266 #endif 267 } 268 269 int intel_plane_check_stride(const struct intel_plane_state *plane_state) 270 { 271 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 272 const struct drm_framebuffer *fb = plane_state->hw.fb; 273 unsigned int rotation = plane_state->hw.rotation; 274 u32 stride, max_stride; 275 276 /* 277 * We ignore stride for all invisible planes that 278 * can be remapped. Otherwise we could end up 279 * with a false positive when the remapping didn't 280 * kick in due the plane being invisible. 281 */ 282 if (intel_plane_can_remap(plane_state) && 283 !plane_state->uapi.visible) 284 return 0; 285 286 /* FIXME other color planes? */ 287 stride = plane_state->color_plane[0].stride; 288 max_stride = plane->max_stride(plane, fb->format->format, 289 fb->modifier, rotation); 290 291 if (stride > max_stride) { 292 DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n", 293 fb->base.id, stride, 294 plane->base.base.id, plane->base.name, max_stride); 295 return -EINVAL; 296 } 297 298 return 0; 299 } 300 301 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state) 302 { 303 const struct drm_framebuffer *fb = plane_state->hw.fb; 304 struct drm_rect *src = &plane_state->uapi.src; 305 u32 src_x, src_y, src_w, src_h, hsub, vsub; 306 bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation); 307 308 /* 309 * Hardware doesn't handle subpixel coordinates. 310 * Adjust to (macro)pixel boundary, but be careful not to 311 * increase the source viewport size, because that could 312 * push the downscaling factor out of bounds. 313 */ 314 src_x = src->x1 >> 16; 315 src_w = drm_rect_width(src) >> 16; 316 src_y = src->y1 >> 16; 317 src_h = drm_rect_height(src) >> 16; 318 319 drm_rect_init(src, src_x << 16, src_y << 16, 320 src_w << 16, src_h << 16); 321 322 if (!fb->format->is_yuv) 323 return 0; 324 325 /* YUV specific checks */ 326 if (!rotated) { 327 hsub = fb->format->hsub; 328 vsub = fb->format->vsub; 329 } else { 330 hsub = vsub = max(fb->format->hsub, fb->format->vsub); 331 } 332 333 if (src_x % hsub || src_w % hsub) { 334 DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of %u for %sYUV planes\n", 335 src_x, src_w, hsub, rotated ? "rotated " : ""); 336 return -EINVAL; 337 } 338 339 if (src_y % vsub || src_h % vsub) { 340 DRM_DEBUG_KMS("src y/h (%u, %u) must be a multiple of %u for %sYUV planes\n", 341 src_y, src_h, vsub, rotated ? "rotated " : ""); 342 return -EINVAL; 343 } 344 345 return 0; 346 } 347 348 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) 349 { 350 return INTEL_GEN(dev_priv) >= 11 && 351 icl_hdr_plane_mask() & BIT(plane_id); 352 } 353 354 static void 355 skl_plane_ratio(const struct intel_crtc_state *crtc_state, 356 const struct intel_plane_state *plane_state, 357 unsigned int *num, unsigned int *den) 358 { 359 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 360 const struct drm_framebuffer *fb = plane_state->hw.fb; 361 362 if (fb->format->cpp[0] == 8) { 363 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { 364 *num = 10; 365 *den = 8; 366 } else { 367 *num = 9; 368 *den = 8; 369 } 370 } else { 371 *num = 1; 372 *den = 1; 373 } 374 } 375 376 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 377 const struct intel_plane_state *plane_state) 378 { 379 struct drm_i915_private *dev_priv = to_i915(plane_state->uapi.plane->dev); 380 unsigned int pixel_rate = crtc_state->pixel_rate; 381 unsigned int src_w, src_h, dst_w, dst_h; 382 unsigned int num, den; 383 384 skl_plane_ratio(crtc_state, plane_state, &num, &den); 385 386 /* two pixels per clock on glk+ */ 387 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 388 den *= 2; 389 390 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 391 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 392 dst_w = drm_rect_width(&plane_state->uapi.dst); 393 dst_h = drm_rect_height(&plane_state->uapi.dst); 394 395 /* Downscaling limits the maximum pixel rate */ 396 dst_w = min(src_w, dst_w); 397 dst_h = min(src_h, dst_h); 398 399 return DIV64_U64_ROUND_UP(mul_u32_u32(pixel_rate * num, src_w * src_h), 400 mul_u32_u32(den, dst_w * dst_h)); 401 } 402 403 static unsigned int 404 skl_plane_max_stride(struct intel_plane *plane, 405 u32 pixel_format, u64 modifier, 406 unsigned int rotation) 407 { 408 const struct drm_format_info *info = drm_format_info(pixel_format); 409 int cpp = info->cpp[0]; 410 411 /* 412 * "The stride in bytes must not exceed the 413 * of the size of 8K pixels and 32K bytes." 414 */ 415 if (drm_rotation_90_or_270(rotation)) 416 return min(8192, 32768 / cpp); 417 else 418 return min(8192 * cpp, 32768); 419 } 420 421 static void 422 skl_program_scaler(struct intel_plane *plane, 423 const struct intel_crtc_state *crtc_state, 424 const struct intel_plane_state *plane_state) 425 { 426 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 427 const struct drm_framebuffer *fb = plane_state->hw.fb; 428 enum pipe pipe = plane->pipe; 429 int scaler_id = plane_state->scaler_id; 430 const struct intel_scaler *scaler = 431 &crtc_state->scaler_state.scalers[scaler_id]; 432 int crtc_x = plane_state->uapi.dst.x1; 433 int crtc_y = plane_state->uapi.dst.y1; 434 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 435 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 436 u16 y_hphase, uv_rgb_hphase; 437 u16 y_vphase, uv_rgb_vphase; 438 int hscale, vscale; 439 440 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 441 &plane_state->uapi.dst, 442 0, INT_MAX); 443 vscale = drm_rect_calc_vscale(&plane_state->uapi.src, 444 &plane_state->uapi.dst, 445 0, INT_MAX); 446 447 /* TODO: handle sub-pixel coordinates */ 448 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 449 !icl_is_hdr_plane(dev_priv, plane->id)) { 450 y_hphase = skl_scaler_calc_phase(1, hscale, false); 451 y_vphase = skl_scaler_calc_phase(1, vscale, false); 452 453 /* MPEG2 chroma siting convention */ 454 uv_rgb_hphase = skl_scaler_calc_phase(2, hscale, true); 455 uv_rgb_vphase = skl_scaler_calc_phase(2, vscale, false); 456 } else { 457 /* not used */ 458 y_hphase = 0; 459 y_vphase = 0; 460 461 uv_rgb_hphase = skl_scaler_calc_phase(1, hscale, false); 462 uv_rgb_vphase = skl_scaler_calc_phase(1, vscale, false); 463 } 464 465 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), 466 PS_SCALER_EN | PS_PLANE_SEL(plane->id) | scaler->mode); 467 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), 468 PS_Y_PHASE(y_vphase) | PS_UV_RGB_PHASE(uv_rgb_vphase)); 469 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), 470 PS_Y_PHASE(y_hphase) | PS_UV_RGB_PHASE(uv_rgb_hphase)); 471 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); 472 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); 473 } 474 475 /* Preoffset values for YUV to RGB Conversion */ 476 #define PREOFF_YUV_TO_RGB_HI 0x1800 477 #define PREOFF_YUV_TO_RGB_ME 0x1F00 478 #define PREOFF_YUV_TO_RGB_LO 0x1800 479 480 #define ROFF(x) (((x) & 0xffff) << 16) 481 #define GOFF(x) (((x) & 0xffff) << 0) 482 #define BOFF(x) (((x) & 0xffff) << 16) 483 484 static void 485 icl_program_input_csc(struct intel_plane *plane, 486 const struct intel_crtc_state *crtc_state, 487 const struct intel_plane_state *plane_state) 488 { 489 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 490 enum pipe pipe = plane->pipe; 491 enum plane_id plane_id = plane->id; 492 493 static const u16 input_csc_matrix[][9] = { 494 /* 495 * BT.601 full range YCbCr -> full range RGB 496 * The matrix required is : 497 * [1.000, 0.000, 1.371, 498 * 1.000, -0.336, -0.698, 499 * 1.000, 1.732, 0.0000] 500 */ 501 [DRM_COLOR_YCBCR_BT601] = { 502 0x7AF8, 0x7800, 0x0, 503 0x8B28, 0x7800, 0x9AC0, 504 0x0, 0x7800, 0x7DD8, 505 }, 506 /* 507 * BT.709 full range YCbCr -> full range RGB 508 * The matrix required is : 509 * [1.000, 0.000, 1.574, 510 * 1.000, -0.187, -0.468, 511 * 1.000, 1.855, 0.0000] 512 */ 513 [DRM_COLOR_YCBCR_BT709] = { 514 0x7C98, 0x7800, 0x0, 515 0x9EF8, 0x7800, 0xAC00, 516 0x0, 0x7800, 0x7ED8, 517 }, 518 /* 519 * BT.2020 full range YCbCr -> full range RGB 520 * The matrix required is : 521 * [1.000, 0.000, 1.474, 522 * 1.000, -0.1645, -0.5713, 523 * 1.000, 1.8814, 0.0000] 524 */ 525 [DRM_COLOR_YCBCR_BT2020] = { 526 0x7BC8, 0x7800, 0x0, 527 0x8928, 0x7800, 0xAA88, 528 0x0, 0x7800, 0x7F10, 529 }, 530 }; 531 532 /* Matrix for Limited Range to Full Range Conversion */ 533 static const u16 input_csc_matrix_lr[][9] = { 534 /* 535 * BT.601 Limted range YCbCr -> full range RGB 536 * The matrix required is : 537 * [1.164384, 0.000, 1.596027, 538 * 1.164384, -0.39175, -0.812813, 539 * 1.164384, 2.017232, 0.0000] 540 */ 541 [DRM_COLOR_YCBCR_BT601] = { 542 0x7CC8, 0x7950, 0x0, 543 0x8D00, 0x7950, 0x9C88, 544 0x0, 0x7950, 0x6810, 545 }, 546 /* 547 * BT.709 Limited range YCbCr -> full range RGB 548 * The matrix required is : 549 * [1.164384, 0.000, 1.792741, 550 * 1.164384, -0.213249, -0.532909, 551 * 1.164384, 2.112402, 0.0000] 552 */ 553 [DRM_COLOR_YCBCR_BT709] = { 554 0x7E58, 0x7950, 0x0, 555 0x8888, 0x7950, 0xADA8, 556 0x0, 0x7950, 0x6870, 557 }, 558 /* 559 * BT.2020 Limited range YCbCr -> full range RGB 560 * The matrix required is : 561 * [1.164, 0.000, 1.678, 562 * 1.164, -0.1873, -0.6504, 563 * 1.164, 2.1417, 0.0000] 564 */ 565 [DRM_COLOR_YCBCR_BT2020] = { 566 0x7D70, 0x7950, 0x0, 567 0x8A68, 0x7950, 0xAC00, 568 0x0, 0x7950, 0x6890, 569 }, 570 }; 571 const u16 *csc; 572 573 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 574 csc = input_csc_matrix[plane_state->hw.color_encoding]; 575 else 576 csc = input_csc_matrix_lr[plane_state->hw.color_encoding]; 577 578 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0), ROFF(csc[0]) | 579 GOFF(csc[1])); 580 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1), BOFF(csc[2])); 581 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2), ROFF(csc[3]) | 582 GOFF(csc[4])); 583 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3), BOFF(csc[5])); 584 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4), ROFF(csc[6]) | 585 GOFF(csc[7])); 586 I915_WRITE_FW(PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5), BOFF(csc[8])); 587 588 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0), 589 PREOFF_YUV_TO_RGB_HI); 590 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 591 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 0); 592 else 593 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1), 594 PREOFF_YUV_TO_RGB_ME); 595 I915_WRITE_FW(PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2), 596 PREOFF_YUV_TO_RGB_LO); 597 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0); 598 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0); 599 I915_WRITE_FW(PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0); 600 } 601 602 static void 603 skl_program_plane(struct intel_plane *plane, 604 const struct intel_crtc_state *crtc_state, 605 const struct intel_plane_state *plane_state, 606 int color_plane) 607 { 608 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 609 enum plane_id plane_id = plane->id; 610 enum pipe pipe = plane->pipe; 611 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 612 u32 surf_addr = plane_state->color_plane[color_plane].offset; 613 u32 stride = skl_plane_stride(plane_state, color_plane); 614 const struct drm_framebuffer *fb = plane_state->hw.fb; 615 int aux_plane = intel_main_to_aux_plane(fb, color_plane); 616 u32 aux_dist = plane_state->color_plane[aux_plane].offset - surf_addr; 617 u32 aux_stride = skl_plane_stride(plane_state, aux_plane); 618 int crtc_x = plane_state->uapi.dst.x1; 619 int crtc_y = plane_state->uapi.dst.y1; 620 u32 x = plane_state->color_plane[color_plane].x; 621 u32 y = plane_state->color_plane[color_plane].y; 622 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 623 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 624 u8 alpha = plane_state->hw.alpha >> 8; 625 u32 plane_color_ctl = 0; 626 unsigned long irqflags; 627 u32 keymsk, keymax; 628 u32 plane_ctl = plane_state->ctl; 629 630 plane_ctl |= skl_plane_ctl_crtc(crtc_state); 631 632 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 633 plane_color_ctl = plane_state->color_ctl | 634 glk_plane_color_ctl_crtc(crtc_state); 635 636 /* Sizes are 0 based */ 637 src_w--; 638 src_h--; 639 640 keymax = (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha); 641 642 keymsk = key->channel_mask & 0x7ffffff; 643 if (alpha < 0xff) 644 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE; 645 646 /* The scaler will handle the output position */ 647 if (plane_state->scaler_id >= 0) { 648 crtc_x = 0; 649 crtc_y = 0; 650 } 651 652 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 653 654 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); 655 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x); 656 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); 657 658 if (INTEL_GEN(dev_priv) < 12) 659 aux_dist |= aux_stride; 660 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), aux_dist); 661 662 if (icl_is_hdr_plane(dev_priv, plane_id)) 663 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), plane_state->cus_ctl); 664 665 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 666 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl); 667 668 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id)) 669 icl_program_input_csc(plane, crtc_state, plane_state); 670 671 skl_write_plane_wm(plane, crtc_state); 672 673 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value); 674 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), keymsk); 675 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), keymax); 676 677 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x); 678 679 if (INTEL_GEN(dev_priv) < 11) 680 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), 681 (plane_state->color_plane[1].y << 16) | 682 plane_state->color_plane[1].x); 683 684 /* 685 * The control register self-arms if the plane was previously 686 * disabled. Try to make the plane enable atomic by writing 687 * the control register just before the surface register. 688 */ 689 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); 690 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 691 intel_plane_ggtt_offset(plane_state) + surf_addr); 692 693 if (plane_state->scaler_id >= 0) 694 skl_program_scaler(plane, crtc_state, plane_state); 695 696 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 697 } 698 699 static void 700 skl_update_plane(struct intel_plane *plane, 701 const struct intel_crtc_state *crtc_state, 702 const struct intel_plane_state *plane_state) 703 { 704 int color_plane = 0; 705 706 if (plane_state->planar_linked_plane && !plane_state->planar_slave) 707 /* Program the UV plane on planar master */ 708 color_plane = 1; 709 710 skl_program_plane(plane, crtc_state, plane_state, color_plane); 711 } 712 static void 713 skl_disable_plane(struct intel_plane *plane, 714 const struct intel_crtc_state *crtc_state) 715 { 716 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 717 enum plane_id plane_id = plane->id; 718 enum pipe pipe = plane->pipe; 719 unsigned long irqflags; 720 721 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 722 723 if (icl_is_hdr_plane(dev_priv, plane_id)) 724 I915_WRITE_FW(PLANE_CUS_CTL(pipe, plane_id), 0); 725 726 skl_write_plane_wm(plane, crtc_state); 727 728 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); 729 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); 730 731 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 732 } 733 734 static bool 735 skl_plane_get_hw_state(struct intel_plane *plane, 736 enum pipe *pipe) 737 { 738 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 739 enum intel_display_power_domain power_domain; 740 enum plane_id plane_id = plane->id; 741 intel_wakeref_t wakeref; 742 bool ret; 743 744 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 745 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 746 if (!wakeref) 747 return false; 748 749 ret = I915_READ(PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE; 750 751 *pipe = plane->pipe; 752 753 intel_display_power_put(dev_priv, power_domain, wakeref); 754 755 return ret; 756 } 757 758 static void i9xx_plane_linear_gamma(u16 gamma[8]) 759 { 760 /* The points are not evenly spaced. */ 761 static const u8 in[8] = { 0, 1, 2, 4, 8, 16, 24, 32 }; 762 int i; 763 764 for (i = 0; i < 8; i++) 765 gamma[i] = (in[i] << 8) / 32; 766 } 767 768 static void 769 chv_update_csc(const struct intel_plane_state *plane_state) 770 { 771 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 772 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 773 const struct drm_framebuffer *fb = plane_state->hw.fb; 774 enum plane_id plane_id = plane->id; 775 /* 776 * |r| | c0 c1 c2 | |cr| 777 * |g| = | c3 c4 c5 | x |y | 778 * |b| | c6 c7 c8 | |cb| 779 * 780 * Coefficients are s3.12. 781 * 782 * Cb and Cr apparently come in as signed already, and 783 * we always get full range data in on account of CLRC0/1. 784 */ 785 static const s16 csc_matrix[][9] = { 786 /* BT.601 full range YCbCr -> full range RGB */ 787 [DRM_COLOR_YCBCR_BT601] = { 788 5743, 4096, 0, 789 -2925, 4096, -1410, 790 0, 4096, 7258, 791 }, 792 /* BT.709 full range YCbCr -> full range RGB */ 793 [DRM_COLOR_YCBCR_BT709] = { 794 6450, 4096, 0, 795 -1917, 4096, -767, 796 0, 4096, 7601, 797 }, 798 }; 799 const s16 *csc = csc_matrix[plane_state->hw.color_encoding]; 800 801 /* Seems RGB data bypasses the CSC always */ 802 if (!fb->format->is_yuv) 803 return; 804 805 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 806 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 807 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0)); 808 809 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 810 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 811 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 812 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 813 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(csc[8])); 814 815 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 816 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 817 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 818 819 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 820 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 821 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 822 } 823 824 #define SIN_0 0 825 #define COS_0 1 826 827 static void 828 vlv_update_clrc(const struct intel_plane_state *plane_state) 829 { 830 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 831 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 832 const struct drm_framebuffer *fb = plane_state->hw.fb; 833 enum pipe pipe = plane->pipe; 834 enum plane_id plane_id = plane->id; 835 int contrast, brightness, sh_scale, sh_sin, sh_cos; 836 837 if (fb->format->is_yuv && 838 plane_state->hw.color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) { 839 /* 840 * Expand limited range to full range: 841 * Contrast is applied first and is used to expand Y range. 842 * Brightness is applied second and is used to remove the 843 * offset from Y. Saturation/hue is used to expand CbCr range. 844 */ 845 contrast = DIV_ROUND_CLOSEST(255 << 6, 235 - 16); 846 brightness = -DIV_ROUND_CLOSEST(16 * 255, 235 - 16); 847 sh_scale = DIV_ROUND_CLOSEST(128 << 7, 240 - 128); 848 sh_sin = SIN_0 * sh_scale; 849 sh_cos = COS_0 * sh_scale; 850 } else { 851 /* Pass-through everything. */ 852 contrast = 1 << 6; 853 brightness = 0; 854 sh_scale = 1 << 7; 855 sh_sin = SIN_0 * sh_scale; 856 sh_cos = COS_0 * sh_scale; 857 } 858 859 /* FIXME these register are single buffered :( */ 860 I915_WRITE_FW(SPCLRC0(pipe, plane_id), 861 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 862 I915_WRITE_FW(SPCLRC1(pipe, plane_id), 863 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 864 } 865 866 static void 867 vlv_plane_ratio(const struct intel_crtc_state *crtc_state, 868 const struct intel_plane_state *plane_state, 869 unsigned int *num, unsigned int *den) 870 { 871 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 872 const struct drm_framebuffer *fb = plane_state->hw.fb; 873 unsigned int cpp = fb->format->cpp[0]; 874 875 /* 876 * VLV bspec only considers cases where all three planes are 877 * enabled, and cases where the primary and one sprite is enabled. 878 * Let's assume the case with just two sprites enabled also 879 * maps to the latter case. 880 */ 881 if (hweight8(active_planes) == 3) { 882 switch (cpp) { 883 case 8: 884 *num = 11; 885 *den = 8; 886 break; 887 case 4: 888 *num = 18; 889 *den = 16; 890 break; 891 default: 892 *num = 1; 893 *den = 1; 894 break; 895 } 896 } else if (hweight8(active_planes) == 2) { 897 switch (cpp) { 898 case 8: 899 *num = 10; 900 *den = 8; 901 break; 902 case 4: 903 *num = 17; 904 *den = 16; 905 break; 906 default: 907 *num = 1; 908 *den = 1; 909 break; 910 } 911 } else { 912 switch (cpp) { 913 case 8: 914 *num = 10; 915 *den = 8; 916 break; 917 default: 918 *num = 1; 919 *den = 1; 920 break; 921 } 922 } 923 } 924 925 int vlv_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 926 const struct intel_plane_state *plane_state) 927 { 928 unsigned int pixel_rate; 929 unsigned int num, den; 930 931 /* 932 * Note that crtc_state->pixel_rate accounts for both 933 * horizontal and vertical panel fitter downscaling factors. 934 * Pre-HSW bspec tells us to only consider the horizontal 935 * downscaling factor here. We ignore that and just consider 936 * both for simplicity. 937 */ 938 pixel_rate = crtc_state->pixel_rate; 939 940 vlv_plane_ratio(crtc_state, plane_state, &num, &den); 941 942 return DIV_ROUND_UP(pixel_rate * num, den); 943 } 944 945 static u32 vlv_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 946 { 947 u32 sprctl = 0; 948 949 if (crtc_state->gamma_enable) 950 sprctl |= SP_GAMMA_ENABLE; 951 952 return sprctl; 953 } 954 955 static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state, 956 const struct intel_plane_state *plane_state) 957 { 958 const struct drm_framebuffer *fb = plane_state->hw.fb; 959 unsigned int rotation = plane_state->hw.rotation; 960 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 961 u32 sprctl; 962 963 sprctl = SP_ENABLE; 964 965 switch (fb->format->format) { 966 case DRM_FORMAT_YUYV: 967 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV; 968 break; 969 case DRM_FORMAT_YVYU: 970 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU; 971 break; 972 case DRM_FORMAT_UYVY: 973 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY; 974 break; 975 case DRM_FORMAT_VYUY: 976 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY; 977 break; 978 case DRM_FORMAT_C8: 979 sprctl |= SP_FORMAT_8BPP; 980 break; 981 case DRM_FORMAT_RGB565: 982 sprctl |= SP_FORMAT_BGR565; 983 break; 984 case DRM_FORMAT_XRGB8888: 985 sprctl |= SP_FORMAT_BGRX8888; 986 break; 987 case DRM_FORMAT_ARGB8888: 988 sprctl |= SP_FORMAT_BGRA8888; 989 break; 990 case DRM_FORMAT_XBGR2101010: 991 sprctl |= SP_FORMAT_RGBX1010102; 992 break; 993 case DRM_FORMAT_ABGR2101010: 994 sprctl |= SP_FORMAT_RGBA1010102; 995 break; 996 case DRM_FORMAT_XRGB2101010: 997 sprctl |= SP_FORMAT_BGRX1010102; 998 break; 999 case DRM_FORMAT_ARGB2101010: 1000 sprctl |= SP_FORMAT_BGRA1010102; 1001 break; 1002 case DRM_FORMAT_XBGR8888: 1003 sprctl |= SP_FORMAT_RGBX8888; 1004 break; 1005 case DRM_FORMAT_ABGR8888: 1006 sprctl |= SP_FORMAT_RGBA8888; 1007 break; 1008 default: 1009 MISSING_CASE(fb->format->format); 1010 return 0; 1011 } 1012 1013 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1014 sprctl |= SP_YUV_FORMAT_BT709; 1015 1016 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1017 sprctl |= SP_TILED; 1018 1019 if (rotation & DRM_MODE_ROTATE_180) 1020 sprctl |= SP_ROTATE_180; 1021 1022 if (rotation & DRM_MODE_REFLECT_X) 1023 sprctl |= SP_MIRROR; 1024 1025 if (key->flags & I915_SET_COLORKEY_SOURCE) 1026 sprctl |= SP_SOURCE_KEY; 1027 1028 return sprctl; 1029 } 1030 1031 static void vlv_update_gamma(const struct intel_plane_state *plane_state) 1032 { 1033 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1034 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1035 const struct drm_framebuffer *fb = plane_state->hw.fb; 1036 enum pipe pipe = plane->pipe; 1037 enum plane_id plane_id = plane->id; 1038 u16 gamma[8]; 1039 int i; 1040 1041 /* Seems RGB data bypasses the gamma always */ 1042 if (!fb->format->is_yuv) 1043 return; 1044 1045 i9xx_plane_linear_gamma(gamma); 1046 1047 /* FIXME these register are single buffered :( */ 1048 /* The two end points are implicit (0.0 and 1.0) */ 1049 for (i = 1; i < 8 - 1; i++) 1050 I915_WRITE_FW(SPGAMC(pipe, plane_id, i - 1), 1051 gamma[i] << 16 | 1052 gamma[i] << 8 | 1053 gamma[i]); 1054 } 1055 1056 static void 1057 vlv_update_plane(struct intel_plane *plane, 1058 const struct intel_crtc_state *crtc_state, 1059 const struct intel_plane_state *plane_state) 1060 { 1061 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1062 enum pipe pipe = plane->pipe; 1063 enum plane_id plane_id = plane->id; 1064 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1065 u32 linear_offset; 1066 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1067 int crtc_x = plane_state->uapi.dst.x1; 1068 int crtc_y = plane_state->uapi.dst.y1; 1069 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1070 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1071 u32 x = plane_state->color_plane[0].x; 1072 u32 y = plane_state->color_plane[0].y; 1073 unsigned long irqflags; 1074 u32 sprctl; 1075 1076 sprctl = plane_state->ctl | vlv_sprite_ctl_crtc(crtc_state); 1077 1078 /* Sizes are 0 based */ 1079 crtc_w--; 1080 crtc_h--; 1081 1082 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1083 1084 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1085 1086 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), 1087 plane_state->color_plane[0].stride); 1088 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x); 1089 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w); 1090 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0); 1091 1092 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) 1093 chv_update_csc(plane_state); 1094 1095 if (key->flags) { 1096 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value); 1097 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask); 1098 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value); 1099 } 1100 1101 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset); 1102 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x); 1103 1104 /* 1105 * The control register self-arms if the plane was previously 1106 * disabled. Try to make the plane enable atomic by writing 1107 * the control register just before the surface register. 1108 */ 1109 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl); 1110 I915_WRITE_FW(SPSURF(pipe, plane_id), 1111 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1112 1113 vlv_update_clrc(plane_state); 1114 vlv_update_gamma(plane_state); 1115 1116 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1117 } 1118 1119 static void 1120 vlv_disable_plane(struct intel_plane *plane, 1121 const struct intel_crtc_state *crtc_state) 1122 { 1123 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1124 enum pipe pipe = plane->pipe; 1125 enum plane_id plane_id = plane->id; 1126 unsigned long irqflags; 1127 1128 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1129 1130 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0); 1131 I915_WRITE_FW(SPSURF(pipe, plane_id), 0); 1132 1133 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1134 } 1135 1136 static bool 1137 vlv_plane_get_hw_state(struct intel_plane *plane, 1138 enum pipe *pipe) 1139 { 1140 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1141 enum intel_display_power_domain power_domain; 1142 enum plane_id plane_id = plane->id; 1143 intel_wakeref_t wakeref; 1144 bool ret; 1145 1146 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1147 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1148 if (!wakeref) 1149 return false; 1150 1151 ret = I915_READ(SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 1152 1153 *pipe = plane->pipe; 1154 1155 intel_display_power_put(dev_priv, power_domain, wakeref); 1156 1157 return ret; 1158 } 1159 1160 static void ivb_plane_ratio(const struct intel_crtc_state *crtc_state, 1161 const struct intel_plane_state *plane_state, 1162 unsigned int *num, unsigned int *den) 1163 { 1164 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1165 const struct drm_framebuffer *fb = plane_state->hw.fb; 1166 unsigned int cpp = fb->format->cpp[0]; 1167 1168 if (hweight8(active_planes) == 2) { 1169 switch (cpp) { 1170 case 8: 1171 *num = 10; 1172 *den = 8; 1173 break; 1174 case 4: 1175 *num = 17; 1176 *den = 16; 1177 break; 1178 default: 1179 *num = 1; 1180 *den = 1; 1181 break; 1182 } 1183 } else { 1184 switch (cpp) { 1185 case 8: 1186 *num = 9; 1187 *den = 8; 1188 break; 1189 default: 1190 *num = 1; 1191 *den = 1; 1192 break; 1193 } 1194 } 1195 } 1196 1197 static void ivb_plane_ratio_scaling(const struct intel_crtc_state *crtc_state, 1198 const struct intel_plane_state *plane_state, 1199 unsigned int *num, unsigned int *den) 1200 { 1201 const struct drm_framebuffer *fb = plane_state->hw.fb; 1202 unsigned int cpp = fb->format->cpp[0]; 1203 1204 switch (cpp) { 1205 case 8: 1206 *num = 12; 1207 *den = 8; 1208 break; 1209 case 4: 1210 *num = 19; 1211 *den = 16; 1212 break; 1213 case 2: 1214 *num = 33; 1215 *den = 32; 1216 break; 1217 default: 1218 *num = 1; 1219 *den = 1; 1220 break; 1221 } 1222 } 1223 1224 int ivb_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1225 const struct intel_plane_state *plane_state) 1226 { 1227 unsigned int pixel_rate; 1228 unsigned int num, den; 1229 1230 /* 1231 * Note that crtc_state->pixel_rate accounts for both 1232 * horizontal and vertical panel fitter downscaling factors. 1233 * Pre-HSW bspec tells us to only consider the horizontal 1234 * downscaling factor here. We ignore that and just consider 1235 * both for simplicity. 1236 */ 1237 pixel_rate = crtc_state->pixel_rate; 1238 1239 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1240 1241 return DIV_ROUND_UP(pixel_rate * num, den); 1242 } 1243 1244 static int ivb_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1245 const struct intel_plane_state *plane_state) 1246 { 1247 unsigned int src_w, dst_w, pixel_rate; 1248 unsigned int num, den; 1249 1250 /* 1251 * Note that crtc_state->pixel_rate accounts for both 1252 * horizontal and vertical panel fitter downscaling factors. 1253 * Pre-HSW bspec tells us to only consider the horizontal 1254 * downscaling factor here. We ignore that and just consider 1255 * both for simplicity. 1256 */ 1257 pixel_rate = crtc_state->pixel_rate; 1258 1259 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1260 dst_w = drm_rect_width(&plane_state->uapi.dst); 1261 1262 if (src_w != dst_w) 1263 ivb_plane_ratio_scaling(crtc_state, plane_state, &num, &den); 1264 else 1265 ivb_plane_ratio(crtc_state, plane_state, &num, &den); 1266 1267 /* Horizontal downscaling limits the maximum pixel rate */ 1268 dst_w = min(src_w, dst_w); 1269 1270 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, num * src_w), 1271 den * dst_w); 1272 } 1273 1274 static void hsw_plane_ratio(const struct intel_crtc_state *crtc_state, 1275 const struct intel_plane_state *plane_state, 1276 unsigned int *num, unsigned int *den) 1277 { 1278 u8 active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); 1279 const struct drm_framebuffer *fb = plane_state->hw.fb; 1280 unsigned int cpp = fb->format->cpp[0]; 1281 1282 if (hweight8(active_planes) == 2) { 1283 switch (cpp) { 1284 case 8: 1285 *num = 10; 1286 *den = 8; 1287 break; 1288 default: 1289 *num = 1; 1290 *den = 1; 1291 break; 1292 } 1293 } else { 1294 switch (cpp) { 1295 case 8: 1296 *num = 9; 1297 *den = 8; 1298 break; 1299 default: 1300 *num = 1; 1301 *den = 1; 1302 break; 1303 } 1304 } 1305 } 1306 1307 int hsw_plane_min_cdclk(const struct intel_crtc_state *crtc_state, 1308 const struct intel_plane_state *plane_state) 1309 { 1310 unsigned int pixel_rate = crtc_state->pixel_rate; 1311 unsigned int num, den; 1312 1313 hsw_plane_ratio(crtc_state, plane_state, &num, &den); 1314 1315 return DIV_ROUND_UP(pixel_rate * num, den); 1316 } 1317 1318 static u32 ivb_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1319 { 1320 u32 sprctl = 0; 1321 1322 if (crtc_state->gamma_enable) 1323 sprctl |= SPRITE_GAMMA_ENABLE; 1324 1325 if (crtc_state->csc_enable) 1326 sprctl |= SPRITE_PIPE_CSC_ENABLE; 1327 1328 return sprctl; 1329 } 1330 1331 static bool ivb_need_sprite_gamma(const struct intel_plane_state *plane_state) 1332 { 1333 struct drm_i915_private *dev_priv = 1334 to_i915(plane_state->uapi.plane->dev); 1335 const struct drm_framebuffer *fb = plane_state->hw.fb; 1336 1337 return fb->format->cpp[0] == 8 && 1338 (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)); 1339 } 1340 1341 static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state, 1342 const struct intel_plane_state *plane_state) 1343 { 1344 struct drm_i915_private *dev_priv = 1345 to_i915(plane_state->uapi.plane->dev); 1346 const struct drm_framebuffer *fb = plane_state->hw.fb; 1347 unsigned int rotation = plane_state->hw.rotation; 1348 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1349 u32 sprctl; 1350 1351 sprctl = SPRITE_ENABLE; 1352 1353 if (IS_IVYBRIDGE(dev_priv)) 1354 sprctl |= SPRITE_TRICKLE_FEED_DISABLE; 1355 1356 switch (fb->format->format) { 1357 case DRM_FORMAT_XBGR8888: 1358 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX; 1359 break; 1360 case DRM_FORMAT_XRGB8888: 1361 sprctl |= SPRITE_FORMAT_RGBX888; 1362 break; 1363 case DRM_FORMAT_XBGR2101010: 1364 sprctl |= SPRITE_FORMAT_RGBX101010 | SPRITE_RGB_ORDER_RGBX; 1365 break; 1366 case DRM_FORMAT_XRGB2101010: 1367 sprctl |= SPRITE_FORMAT_RGBX101010; 1368 break; 1369 case DRM_FORMAT_XBGR16161616F: 1370 sprctl |= SPRITE_FORMAT_RGBX161616 | SPRITE_RGB_ORDER_RGBX; 1371 break; 1372 case DRM_FORMAT_XRGB16161616F: 1373 sprctl |= SPRITE_FORMAT_RGBX161616; 1374 break; 1375 case DRM_FORMAT_YUYV: 1376 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV; 1377 break; 1378 case DRM_FORMAT_YVYU: 1379 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU; 1380 break; 1381 case DRM_FORMAT_UYVY: 1382 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY; 1383 break; 1384 case DRM_FORMAT_VYUY: 1385 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY; 1386 break; 1387 default: 1388 MISSING_CASE(fb->format->format); 1389 return 0; 1390 } 1391 1392 if (!ivb_need_sprite_gamma(plane_state)) 1393 sprctl |= SPRITE_INT_GAMMA_DISABLE; 1394 1395 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1396 sprctl |= SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709; 1397 1398 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1399 sprctl |= SPRITE_YUV_RANGE_CORRECTION_DISABLE; 1400 1401 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1402 sprctl |= SPRITE_TILED; 1403 1404 if (rotation & DRM_MODE_ROTATE_180) 1405 sprctl |= SPRITE_ROTATE_180; 1406 1407 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1408 sprctl |= SPRITE_DEST_KEY; 1409 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1410 sprctl |= SPRITE_SOURCE_KEY; 1411 1412 return sprctl; 1413 } 1414 1415 static void ivb_sprite_linear_gamma(const struct intel_plane_state *plane_state, 1416 u16 gamma[18]) 1417 { 1418 int scale, i; 1419 1420 /* 1421 * WaFP16GammaEnabling:ivb,hsw 1422 * "Workaround : When using the 64-bit format, the sprite output 1423 * on each color channel has one quarter amplitude. It can be 1424 * brought up to full amplitude by using sprite internal gamma 1425 * correction, pipe gamma correction, or pipe color space 1426 * conversion to multiply the sprite output by four." 1427 */ 1428 scale = 4; 1429 1430 for (i = 0; i < 16; i++) 1431 gamma[i] = min((scale * i << 10) / 16, (1 << 10) - 1); 1432 1433 gamma[i] = min((scale * i << 10) / 16, 1 << 10); 1434 i++; 1435 1436 gamma[i] = 3 << 10; 1437 i++; 1438 } 1439 1440 static void ivb_update_gamma(const struct intel_plane_state *plane_state) 1441 { 1442 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1443 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1444 enum pipe pipe = plane->pipe; 1445 u16 gamma[18]; 1446 int i; 1447 1448 if (!ivb_need_sprite_gamma(plane_state)) 1449 return; 1450 1451 ivb_sprite_linear_gamma(plane_state, gamma); 1452 1453 /* FIXME these register are single buffered :( */ 1454 for (i = 0; i < 16; i++) 1455 I915_WRITE_FW(SPRGAMC(pipe, i), 1456 gamma[i] << 20 | 1457 gamma[i] << 10 | 1458 gamma[i]); 1459 1460 I915_WRITE_FW(SPRGAMC16(pipe, 0), gamma[i]); 1461 I915_WRITE_FW(SPRGAMC16(pipe, 1), gamma[i]); 1462 I915_WRITE_FW(SPRGAMC16(pipe, 2), gamma[i]); 1463 i++; 1464 1465 I915_WRITE_FW(SPRGAMC17(pipe, 0), gamma[i]); 1466 I915_WRITE_FW(SPRGAMC17(pipe, 1), gamma[i]); 1467 I915_WRITE_FW(SPRGAMC17(pipe, 2), gamma[i]); 1468 i++; 1469 } 1470 1471 static void 1472 ivb_update_plane(struct intel_plane *plane, 1473 const struct intel_crtc_state *crtc_state, 1474 const struct intel_plane_state *plane_state) 1475 { 1476 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1477 enum pipe pipe = plane->pipe; 1478 u32 sprsurf_offset = plane_state->color_plane[0].offset; 1479 u32 linear_offset; 1480 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1481 int crtc_x = plane_state->uapi.dst.x1; 1482 int crtc_y = plane_state->uapi.dst.y1; 1483 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1484 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1485 u32 x = plane_state->color_plane[0].x; 1486 u32 y = plane_state->color_plane[0].y; 1487 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1488 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1489 u32 sprctl, sprscale = 0; 1490 unsigned long irqflags; 1491 1492 sprctl = plane_state->ctl | ivb_sprite_ctl_crtc(crtc_state); 1493 1494 /* Sizes are 0 based */ 1495 src_w--; 1496 src_h--; 1497 crtc_w--; 1498 crtc_h--; 1499 1500 if (crtc_w != src_w || crtc_h != src_h) 1501 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; 1502 1503 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1504 1505 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1506 1507 I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride); 1508 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x); 1509 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w); 1510 if (IS_IVYBRIDGE(dev_priv)) 1511 I915_WRITE_FW(SPRSCALE(pipe), sprscale); 1512 1513 if (key->flags) { 1514 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value); 1515 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask); 1516 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value); 1517 } 1518 1519 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 1520 * register */ 1521 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 1522 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x); 1523 } else { 1524 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset); 1525 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x); 1526 } 1527 1528 /* 1529 * The control register self-arms if the plane was previously 1530 * disabled. Try to make the plane enable atomic by writing 1531 * the control register just before the surface register. 1532 */ 1533 I915_WRITE_FW(SPRCTL(pipe), sprctl); 1534 I915_WRITE_FW(SPRSURF(pipe), 1535 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 1536 1537 ivb_update_gamma(plane_state); 1538 1539 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1540 } 1541 1542 static void 1543 ivb_disable_plane(struct intel_plane *plane, 1544 const struct intel_crtc_state *crtc_state) 1545 { 1546 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1547 enum pipe pipe = plane->pipe; 1548 unsigned long irqflags; 1549 1550 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1551 1552 I915_WRITE_FW(SPRCTL(pipe), 0); 1553 /* Disable the scaler */ 1554 if (IS_IVYBRIDGE(dev_priv)) 1555 I915_WRITE_FW(SPRSCALE(pipe), 0); 1556 I915_WRITE_FW(SPRSURF(pipe), 0); 1557 1558 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1559 } 1560 1561 static bool 1562 ivb_plane_get_hw_state(struct intel_plane *plane, 1563 enum pipe *pipe) 1564 { 1565 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1566 enum intel_display_power_domain power_domain; 1567 intel_wakeref_t wakeref; 1568 bool ret; 1569 1570 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1571 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1572 if (!wakeref) 1573 return false; 1574 1575 ret = I915_READ(SPRCTL(plane->pipe)) & SPRITE_ENABLE; 1576 1577 *pipe = plane->pipe; 1578 1579 intel_display_power_put(dev_priv, power_domain, wakeref); 1580 1581 return ret; 1582 } 1583 1584 static int g4x_sprite_min_cdclk(const struct intel_crtc_state *crtc_state, 1585 const struct intel_plane_state *plane_state) 1586 { 1587 const struct drm_framebuffer *fb = plane_state->hw.fb; 1588 unsigned int hscale, pixel_rate; 1589 unsigned int limit, decimate; 1590 1591 /* 1592 * Note that crtc_state->pixel_rate accounts for both 1593 * horizontal and vertical panel fitter downscaling factors. 1594 * Pre-HSW bspec tells us to only consider the horizontal 1595 * downscaling factor here. We ignore that and just consider 1596 * both for simplicity. 1597 */ 1598 pixel_rate = crtc_state->pixel_rate; 1599 1600 /* Horizontal downscaling limits the maximum pixel rate */ 1601 hscale = drm_rect_calc_hscale(&plane_state->uapi.src, 1602 &plane_state->uapi.dst, 1603 0, INT_MAX); 1604 if (hscale < 0x10000) 1605 return pixel_rate; 1606 1607 /* Decimation steps at 2x,4x,8x,16x */ 1608 decimate = ilog2(hscale >> 16); 1609 hscale >>= decimate; 1610 1611 /* Starting limit is 90% of cdclk */ 1612 limit = 9; 1613 1614 /* -10% per decimation step */ 1615 limit -= decimate; 1616 1617 /* -10% for RGB */ 1618 if (fb->format->cpp[0] >= 4) 1619 limit--; /* -10% for RGB */ 1620 1621 /* 1622 * We should also do -10% if sprite scaling is enabled 1623 * on the other pipe, but we can't really check for that, 1624 * so we ignore it. 1625 */ 1626 1627 return DIV_ROUND_UP_ULL(mul_u32_u32(pixel_rate, 10 * hscale), 1628 limit << 16); 1629 } 1630 1631 static unsigned int 1632 g4x_sprite_max_stride(struct intel_plane *plane, 1633 u32 pixel_format, u64 modifier, 1634 unsigned int rotation) 1635 { 1636 return 16384; 1637 } 1638 1639 static u32 g4x_sprite_ctl_crtc(const struct intel_crtc_state *crtc_state) 1640 { 1641 u32 dvscntr = 0; 1642 1643 if (crtc_state->gamma_enable) 1644 dvscntr |= DVS_GAMMA_ENABLE; 1645 1646 if (crtc_state->csc_enable) 1647 dvscntr |= DVS_PIPE_CSC_ENABLE; 1648 1649 return dvscntr; 1650 } 1651 1652 static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state, 1653 const struct intel_plane_state *plane_state) 1654 { 1655 struct drm_i915_private *dev_priv = 1656 to_i915(plane_state->uapi.plane->dev); 1657 const struct drm_framebuffer *fb = plane_state->hw.fb; 1658 unsigned int rotation = plane_state->hw.rotation; 1659 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1660 u32 dvscntr; 1661 1662 dvscntr = DVS_ENABLE; 1663 1664 if (IS_GEN(dev_priv, 6)) 1665 dvscntr |= DVS_TRICKLE_FEED_DISABLE; 1666 1667 switch (fb->format->format) { 1668 case DRM_FORMAT_XBGR8888: 1669 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR; 1670 break; 1671 case DRM_FORMAT_XRGB8888: 1672 dvscntr |= DVS_FORMAT_RGBX888; 1673 break; 1674 case DRM_FORMAT_XBGR2101010: 1675 dvscntr |= DVS_FORMAT_RGBX101010 | DVS_RGB_ORDER_XBGR; 1676 break; 1677 case DRM_FORMAT_XRGB2101010: 1678 dvscntr |= DVS_FORMAT_RGBX101010; 1679 break; 1680 case DRM_FORMAT_XBGR16161616F: 1681 dvscntr |= DVS_FORMAT_RGBX161616 | DVS_RGB_ORDER_XBGR; 1682 break; 1683 case DRM_FORMAT_XRGB16161616F: 1684 dvscntr |= DVS_FORMAT_RGBX161616; 1685 break; 1686 case DRM_FORMAT_YUYV: 1687 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV; 1688 break; 1689 case DRM_FORMAT_YVYU: 1690 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU; 1691 break; 1692 case DRM_FORMAT_UYVY: 1693 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY; 1694 break; 1695 case DRM_FORMAT_VYUY: 1696 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY; 1697 break; 1698 default: 1699 MISSING_CASE(fb->format->format); 1700 return 0; 1701 } 1702 1703 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709) 1704 dvscntr |= DVS_YUV_FORMAT_BT709; 1705 1706 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE) 1707 dvscntr |= DVS_YUV_RANGE_CORRECTION_DISABLE; 1708 1709 if (fb->modifier == I915_FORMAT_MOD_X_TILED) 1710 dvscntr |= DVS_TILED; 1711 1712 if (rotation & DRM_MODE_ROTATE_180) 1713 dvscntr |= DVS_ROTATE_180; 1714 1715 if (key->flags & I915_SET_COLORKEY_DESTINATION) 1716 dvscntr |= DVS_DEST_KEY; 1717 else if (key->flags & I915_SET_COLORKEY_SOURCE) 1718 dvscntr |= DVS_SOURCE_KEY; 1719 1720 return dvscntr; 1721 } 1722 1723 static void g4x_update_gamma(const struct intel_plane_state *plane_state) 1724 { 1725 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1726 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1727 const struct drm_framebuffer *fb = plane_state->hw.fb; 1728 enum pipe pipe = plane->pipe; 1729 u16 gamma[8]; 1730 int i; 1731 1732 /* Seems RGB data bypasses the gamma always */ 1733 if (!fb->format->is_yuv) 1734 return; 1735 1736 i9xx_plane_linear_gamma(gamma); 1737 1738 /* FIXME these register are single buffered :( */ 1739 /* The two end points are implicit (0.0 and 1.0) */ 1740 for (i = 1; i < 8 - 1; i++) 1741 I915_WRITE_FW(DVSGAMC_G4X(pipe, i - 1), 1742 gamma[i] << 16 | 1743 gamma[i] << 8 | 1744 gamma[i]); 1745 } 1746 1747 static void ilk_sprite_linear_gamma(u16 gamma[17]) 1748 { 1749 int i; 1750 1751 for (i = 0; i < 17; i++) 1752 gamma[i] = (i << 10) / 16; 1753 } 1754 1755 static void ilk_update_gamma(const struct intel_plane_state *plane_state) 1756 { 1757 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1758 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1759 const struct drm_framebuffer *fb = plane_state->hw.fb; 1760 enum pipe pipe = plane->pipe; 1761 u16 gamma[17]; 1762 int i; 1763 1764 /* Seems RGB data bypasses the gamma always */ 1765 if (!fb->format->is_yuv) 1766 return; 1767 1768 ilk_sprite_linear_gamma(gamma); 1769 1770 /* FIXME these register are single buffered :( */ 1771 for (i = 0; i < 16; i++) 1772 I915_WRITE_FW(DVSGAMC_ILK(pipe, i), 1773 gamma[i] << 20 | 1774 gamma[i] << 10 | 1775 gamma[i]); 1776 1777 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1778 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1779 I915_WRITE_FW(DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1780 i++; 1781 } 1782 1783 static void 1784 g4x_update_plane(struct intel_plane *plane, 1785 const struct intel_crtc_state *crtc_state, 1786 const struct intel_plane_state *plane_state) 1787 { 1788 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1789 enum pipe pipe = plane->pipe; 1790 u32 dvssurf_offset = plane_state->color_plane[0].offset; 1791 u32 linear_offset; 1792 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 1793 int crtc_x = plane_state->uapi.dst.x1; 1794 int crtc_y = plane_state->uapi.dst.y1; 1795 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 1796 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 1797 u32 x = plane_state->color_plane[0].x; 1798 u32 y = plane_state->color_plane[0].y; 1799 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 1800 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16; 1801 u32 dvscntr, dvsscale = 0; 1802 unsigned long irqflags; 1803 1804 dvscntr = plane_state->ctl | g4x_sprite_ctl_crtc(crtc_state); 1805 1806 /* Sizes are 0 based */ 1807 src_w--; 1808 src_h--; 1809 crtc_w--; 1810 crtc_h--; 1811 1812 if (crtc_w != src_w || crtc_h != src_h) 1813 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; 1814 1815 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1816 1817 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1818 1819 I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride); 1820 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x); 1821 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w); 1822 I915_WRITE_FW(DVSSCALE(pipe), dvsscale); 1823 1824 if (key->flags) { 1825 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value); 1826 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask); 1827 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value); 1828 } 1829 1830 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset); 1831 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x); 1832 1833 /* 1834 * The control register self-arms if the plane was previously 1835 * disabled. Try to make the plane enable atomic by writing 1836 * the control register just before the surface register. 1837 */ 1838 I915_WRITE_FW(DVSCNTR(pipe), dvscntr); 1839 I915_WRITE_FW(DVSSURF(pipe), 1840 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 1841 1842 if (IS_G4X(dev_priv)) 1843 g4x_update_gamma(plane_state); 1844 else 1845 ilk_update_gamma(plane_state); 1846 1847 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1848 } 1849 1850 static void 1851 g4x_disable_plane(struct intel_plane *plane, 1852 const struct intel_crtc_state *crtc_state) 1853 { 1854 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1855 enum pipe pipe = plane->pipe; 1856 unsigned long irqflags; 1857 1858 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 1859 1860 I915_WRITE_FW(DVSCNTR(pipe), 0); 1861 /* Disable the scaler */ 1862 I915_WRITE_FW(DVSSCALE(pipe), 0); 1863 I915_WRITE_FW(DVSSURF(pipe), 0); 1864 1865 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 1866 } 1867 1868 static bool 1869 g4x_plane_get_hw_state(struct intel_plane *plane, 1870 enum pipe *pipe) 1871 { 1872 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1873 enum intel_display_power_domain power_domain; 1874 intel_wakeref_t wakeref; 1875 bool ret; 1876 1877 power_domain = POWER_DOMAIN_PIPE(plane->pipe); 1878 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); 1879 if (!wakeref) 1880 return false; 1881 1882 ret = I915_READ(DVSCNTR(plane->pipe)) & DVS_ENABLE; 1883 1884 *pipe = plane->pipe; 1885 1886 intel_display_power_put(dev_priv, power_domain, wakeref); 1887 1888 return ret; 1889 } 1890 1891 static bool intel_fb_scalable(const struct drm_framebuffer *fb) 1892 { 1893 if (!fb) 1894 return false; 1895 1896 switch (fb->format->format) { 1897 case DRM_FORMAT_C8: 1898 return false; 1899 case DRM_FORMAT_XRGB16161616F: 1900 case DRM_FORMAT_ARGB16161616F: 1901 case DRM_FORMAT_XBGR16161616F: 1902 case DRM_FORMAT_ABGR16161616F: 1903 return INTEL_GEN(to_i915(fb->dev)) >= 11; 1904 default: 1905 return true; 1906 } 1907 } 1908 1909 static int 1910 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 1911 struct intel_plane_state *plane_state) 1912 { 1913 const struct drm_framebuffer *fb = plane_state->hw.fb; 1914 const struct drm_rect *src = &plane_state->uapi.src; 1915 const struct drm_rect *dst = &plane_state->uapi.dst; 1916 int src_x, src_w, src_h, crtc_w, crtc_h; 1917 const struct drm_display_mode *adjusted_mode = 1918 &crtc_state->hw.adjusted_mode; 1919 unsigned int stride = plane_state->color_plane[0].stride; 1920 unsigned int cpp = fb->format->cpp[0]; 1921 unsigned int width_bytes; 1922 int min_width, min_height; 1923 1924 crtc_w = drm_rect_width(dst); 1925 crtc_h = drm_rect_height(dst); 1926 1927 src_x = src->x1 >> 16; 1928 src_w = drm_rect_width(src) >> 16; 1929 src_h = drm_rect_height(src) >> 16; 1930 1931 if (src_w == crtc_w && src_h == crtc_h) 1932 return 0; 1933 1934 min_width = 3; 1935 1936 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1937 if (src_h & 1) { 1938 DRM_DEBUG_KMS("Source height must be even with interlaced modes\n"); 1939 return -EINVAL; 1940 } 1941 min_height = 6; 1942 } else { 1943 min_height = 3; 1944 } 1945 1946 width_bytes = ((src_x * cpp) & 63) + src_w * cpp; 1947 1948 if (src_w < min_width || src_h < min_height || 1949 src_w > 2048 || src_h > 2048) { 1950 DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1951 src_w, src_h, min_width, min_height, 2048, 2048); 1952 return -EINVAL; 1953 } 1954 1955 if (width_bytes > 4096) { 1956 DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1957 width_bytes, 4096); 1958 return -EINVAL; 1959 } 1960 1961 if (stride > 4096) { 1962 DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n", 1963 stride, 4096); 1964 return -EINVAL; 1965 } 1966 1967 return 0; 1968 } 1969 1970 static int 1971 g4x_sprite_check(struct intel_crtc_state *crtc_state, 1972 struct intel_plane_state *plane_state) 1973 { 1974 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1975 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1976 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 1977 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 1978 int ret; 1979 1980 if (intel_fb_scalable(plane_state->hw.fb)) { 1981 if (INTEL_GEN(dev_priv) < 7) { 1982 min_scale = 1; 1983 max_scale = 16 << 16; 1984 } else if (IS_IVYBRIDGE(dev_priv)) { 1985 min_scale = 1; 1986 max_scale = 2 << 16; 1987 } 1988 } 1989 1990 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 1991 &crtc_state->uapi, 1992 min_scale, max_scale, 1993 true, true); 1994 if (ret) 1995 return ret; 1996 1997 ret = i9xx_check_plane_surface(plane_state); 1998 if (ret) 1999 return ret; 2000 2001 if (!plane_state->uapi.visible) 2002 return 0; 2003 2004 ret = intel_plane_check_src_coordinates(plane_state); 2005 if (ret) 2006 return ret; 2007 2008 ret = g4x_sprite_check_scaling(crtc_state, plane_state); 2009 if (ret) 2010 return ret; 2011 2012 if (INTEL_GEN(dev_priv) >= 7) 2013 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 2014 else 2015 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); 2016 2017 return 0; 2018 } 2019 2020 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 2021 { 2022 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2023 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2024 unsigned int rotation = plane_state->hw.rotation; 2025 2026 /* CHV ignores the mirror bit when the rotate bit is set :( */ 2027 if (IS_CHERRYVIEW(dev_priv) && 2028 rotation & DRM_MODE_ROTATE_180 && 2029 rotation & DRM_MODE_REFLECT_X) { 2030 DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n"); 2031 return -EINVAL; 2032 } 2033 2034 return 0; 2035 } 2036 2037 static int 2038 vlv_sprite_check(struct intel_crtc_state *crtc_state, 2039 struct intel_plane_state *plane_state) 2040 { 2041 int ret; 2042 2043 ret = chv_plane_check_rotation(plane_state); 2044 if (ret) 2045 return ret; 2046 2047 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 2048 &crtc_state->uapi, 2049 DRM_PLANE_HELPER_NO_SCALING, 2050 DRM_PLANE_HELPER_NO_SCALING, 2051 true, true); 2052 if (ret) 2053 return ret; 2054 2055 ret = i9xx_check_plane_surface(plane_state); 2056 if (ret) 2057 return ret; 2058 2059 if (!plane_state->uapi.visible) 2060 return 0; 2061 2062 ret = intel_plane_check_src_coordinates(plane_state); 2063 if (ret) 2064 return ret; 2065 2066 plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state); 2067 2068 return 0; 2069 } 2070 2071 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state, 2072 const struct intel_plane_state *plane_state) 2073 { 2074 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2075 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2076 const struct drm_framebuffer *fb = plane_state->hw.fb; 2077 unsigned int rotation = plane_state->hw.rotation; 2078 struct drm_format_name_buf format_name; 2079 2080 if (!fb) 2081 return 0; 2082 2083 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) && 2084 is_ccs_modifier(fb->modifier)) { 2085 DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n", 2086 rotation); 2087 return -EINVAL; 2088 } 2089 2090 if (rotation & DRM_MODE_REFLECT_X && 2091 fb->modifier == DRM_FORMAT_MOD_LINEAR) { 2092 DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n"); 2093 return -EINVAL; 2094 } 2095 2096 if (drm_rotation_90_or_270(rotation)) { 2097 if (fb->modifier != I915_FORMAT_MOD_Y_TILED && 2098 fb->modifier != I915_FORMAT_MOD_Yf_TILED) { 2099 DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n"); 2100 return -EINVAL; 2101 } 2102 2103 /* 2104 * 90/270 is not allowed with RGB64 16:16:16:16 and 2105 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards. 2106 */ 2107 switch (fb->format->format) { 2108 case DRM_FORMAT_RGB565: 2109 if (INTEL_GEN(dev_priv) >= 11) 2110 break; 2111 /* fall through */ 2112 case DRM_FORMAT_C8: 2113 case DRM_FORMAT_XRGB16161616F: 2114 case DRM_FORMAT_XBGR16161616F: 2115 case DRM_FORMAT_ARGB16161616F: 2116 case DRM_FORMAT_ABGR16161616F: 2117 case DRM_FORMAT_Y210: 2118 case DRM_FORMAT_Y212: 2119 case DRM_FORMAT_Y216: 2120 case DRM_FORMAT_XVYU12_16161616: 2121 case DRM_FORMAT_XVYU16161616: 2122 DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n", 2123 drm_get_format_name(fb->format->format, 2124 &format_name)); 2125 return -EINVAL; 2126 default: 2127 break; 2128 } 2129 } 2130 2131 /* Y-tiling is not supported in IF-ID Interlace mode */ 2132 if (crtc_state->hw.enable && 2133 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE && 2134 (fb->modifier == I915_FORMAT_MOD_Y_TILED || 2135 fb->modifier == I915_FORMAT_MOD_Yf_TILED || 2136 fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || 2137 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS || 2138 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS || 2139 fb->modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS)) { 2140 DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n"); 2141 return -EINVAL; 2142 } 2143 2144 return 0; 2145 } 2146 2147 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state, 2148 const struct intel_plane_state *plane_state) 2149 { 2150 struct drm_i915_private *dev_priv = 2151 to_i915(plane_state->uapi.plane->dev); 2152 int crtc_x = plane_state->uapi.dst.x1; 2153 int crtc_w = drm_rect_width(&plane_state->uapi.dst); 2154 int pipe_src_w = crtc_state->pipe_src_w; 2155 2156 /* 2157 * Display WA #1175: cnl,glk 2158 * Planes other than the cursor may cause FIFO underflow and display 2159 * corruption if starting less than 4 pixels from the right edge of 2160 * the screen. 2161 * Besides the above WA fix the similar problem, where planes other 2162 * than the cursor ending less than 4 pixels from the left edge of the 2163 * screen may cause FIFO underflow and display corruption. 2164 */ 2165 if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) && 2166 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) { 2167 DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n", 2168 crtc_x + crtc_w < 4 ? "end" : "start", 2169 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x, 2170 4, pipe_src_w - 4); 2171 return -ERANGE; 2172 } 2173 2174 return 0; 2175 } 2176 2177 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state) 2178 { 2179 const struct drm_framebuffer *fb = plane_state->hw.fb; 2180 unsigned int rotation = plane_state->hw.rotation; 2181 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16; 2182 2183 /* Display WA #1106 */ 2184 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2185 src_w & 3 && 2186 (rotation == DRM_MODE_ROTATE_270 || 2187 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) { 2188 DRM_DEBUG_KMS("src width must be multiple of 4 for rotated planar YUV\n"); 2189 return -EINVAL; 2190 } 2191 2192 return 0; 2193 } 2194 2195 static int skl_plane_max_scale(struct drm_i915_private *dev_priv, 2196 const struct drm_framebuffer *fb) 2197 { 2198 /* 2199 * We don't yet know the final source width nor 2200 * whether we can use the HQ scaler mode. Assume 2201 * the best case. 2202 * FIXME need to properly check this later. 2203 */ 2204 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv) || 2205 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) 2206 return 0x30000 - 1; 2207 else 2208 return 0x20000 - 1; 2209 } 2210 2211 static int skl_plane_check(struct intel_crtc_state *crtc_state, 2212 struct intel_plane_state *plane_state) 2213 { 2214 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2215 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2216 const struct drm_framebuffer *fb = plane_state->hw.fb; 2217 int min_scale = DRM_PLANE_HELPER_NO_SCALING; 2218 int max_scale = DRM_PLANE_HELPER_NO_SCALING; 2219 int ret; 2220 2221 ret = skl_plane_check_fb(crtc_state, plane_state); 2222 if (ret) 2223 return ret; 2224 2225 /* use scaler when colorkey is not required */ 2226 if (!plane_state->ckey.flags && intel_fb_scalable(fb)) { 2227 min_scale = 1; 2228 max_scale = skl_plane_max_scale(dev_priv, fb); 2229 } 2230 2231 ret = drm_atomic_helper_check_plane_state(&plane_state->uapi, 2232 &crtc_state->uapi, 2233 min_scale, max_scale, 2234 true, true); 2235 if (ret) 2236 return ret; 2237 2238 ret = skl_check_plane_surface(plane_state); 2239 if (ret) 2240 return ret; 2241 2242 if (!plane_state->uapi.visible) 2243 return 0; 2244 2245 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state); 2246 if (ret) 2247 return ret; 2248 2249 ret = intel_plane_check_src_coordinates(plane_state); 2250 if (ret) 2251 return ret; 2252 2253 ret = skl_plane_check_nv12_rotation(plane_state); 2254 if (ret) 2255 return ret; 2256 2257 /* HW only has 8 bits pixel precision, disable plane if invisible */ 2258 if (!(plane_state->hw.alpha >> 8)) 2259 plane_state->uapi.visible = false; 2260 2261 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state); 2262 2263 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 2264 plane_state->color_ctl = glk_plane_color_ctl(crtc_state, 2265 plane_state); 2266 2267 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) && 2268 icl_is_hdr_plane(dev_priv, plane->id)) 2269 /* Enable and use MPEG-2 chroma siting */ 2270 plane_state->cus_ctl = PLANE_CUS_ENABLE | 2271 PLANE_CUS_HPHASE_0 | 2272 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25; 2273 else 2274 plane_state->cus_ctl = 0; 2275 2276 return 0; 2277 } 2278 2279 static bool has_dst_key_in_primary_plane(struct drm_i915_private *dev_priv) 2280 { 2281 return INTEL_GEN(dev_priv) >= 9; 2282 } 2283 2284 static void intel_plane_set_ckey(struct intel_plane_state *plane_state, 2285 const struct drm_intel_sprite_colorkey *set) 2286 { 2287 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 2288 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 2289 struct drm_intel_sprite_colorkey *key = &plane_state->ckey; 2290 2291 *key = *set; 2292 2293 /* 2294 * We want src key enabled on the 2295 * sprite and not on the primary. 2296 */ 2297 if (plane->id == PLANE_PRIMARY && 2298 set->flags & I915_SET_COLORKEY_SOURCE) 2299 key->flags = 0; 2300 2301 /* 2302 * On SKL+ we want dst key enabled on 2303 * the primary and not on the sprite. 2304 */ 2305 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_PRIMARY && 2306 set->flags & I915_SET_COLORKEY_DESTINATION) 2307 key->flags = 0; 2308 } 2309 2310 int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, 2311 struct drm_file *file_priv) 2312 { 2313 struct drm_i915_private *dev_priv = to_i915(dev); 2314 struct drm_intel_sprite_colorkey *set = data; 2315 struct drm_plane *plane; 2316 struct drm_plane_state *plane_state; 2317 struct drm_atomic_state *state; 2318 struct drm_modeset_acquire_ctx ctx; 2319 int ret = 0; 2320 2321 /* ignore the pointless "none" flag */ 2322 set->flags &= ~I915_SET_COLORKEY_NONE; 2323 2324 if (set->flags & ~(I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2325 return -EINVAL; 2326 2327 /* Make sure we don't try to enable both src & dest simultaneously */ 2328 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) 2329 return -EINVAL; 2330 2331 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 2332 set->flags & I915_SET_COLORKEY_DESTINATION) 2333 return -EINVAL; 2334 2335 plane = drm_plane_find(dev, file_priv, set->plane_id); 2336 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY) 2337 return -ENOENT; 2338 2339 /* 2340 * SKL+ only plane 2 can do destination keying against plane 1. 2341 * Also multiple planes can't do destination keying on the same 2342 * pipe simultaneously. 2343 */ 2344 if (INTEL_GEN(dev_priv) >= 9 && 2345 to_intel_plane(plane)->id >= PLANE_SPRITE1 && 2346 set->flags & I915_SET_COLORKEY_DESTINATION) 2347 return -EINVAL; 2348 2349 drm_modeset_acquire_init(&ctx, 0); 2350 2351 state = drm_atomic_state_alloc(plane->dev); 2352 if (!state) { 2353 ret = -ENOMEM; 2354 goto out; 2355 } 2356 state->acquire_ctx = &ctx; 2357 2358 while (1) { 2359 plane_state = drm_atomic_get_plane_state(state, plane); 2360 ret = PTR_ERR_OR_ZERO(plane_state); 2361 if (!ret) 2362 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2363 2364 /* 2365 * On some platforms we have to configure 2366 * the dst colorkey on the primary plane. 2367 */ 2368 if (!ret && has_dst_key_in_primary_plane(dev_priv)) { 2369 struct intel_crtc *crtc = 2370 intel_get_crtc_for_pipe(dev_priv, 2371 to_intel_plane(plane)->pipe); 2372 2373 plane_state = drm_atomic_get_plane_state(state, 2374 crtc->base.primary); 2375 ret = PTR_ERR_OR_ZERO(plane_state); 2376 if (!ret) 2377 intel_plane_set_ckey(to_intel_plane_state(plane_state), set); 2378 } 2379 2380 if (!ret) 2381 ret = drm_atomic_commit(state); 2382 2383 if (ret != -EDEADLK) 2384 break; 2385 2386 drm_atomic_state_clear(state); 2387 drm_modeset_backoff(&ctx); 2388 } 2389 2390 drm_atomic_state_put(state); 2391 out: 2392 drm_modeset_drop_locks(&ctx); 2393 drm_modeset_acquire_fini(&ctx); 2394 return ret; 2395 } 2396 2397 static const u32 g4x_plane_formats[] = { 2398 DRM_FORMAT_XRGB8888, 2399 DRM_FORMAT_YUYV, 2400 DRM_FORMAT_YVYU, 2401 DRM_FORMAT_UYVY, 2402 DRM_FORMAT_VYUY, 2403 }; 2404 2405 static const u64 i9xx_plane_format_modifiers[] = { 2406 I915_FORMAT_MOD_X_TILED, 2407 DRM_FORMAT_MOD_LINEAR, 2408 DRM_FORMAT_MOD_INVALID 2409 }; 2410 2411 static const u32 snb_plane_formats[] = { 2412 DRM_FORMAT_XRGB8888, 2413 DRM_FORMAT_XBGR8888, 2414 DRM_FORMAT_XRGB2101010, 2415 DRM_FORMAT_XBGR2101010, 2416 DRM_FORMAT_XRGB16161616F, 2417 DRM_FORMAT_XBGR16161616F, 2418 DRM_FORMAT_YUYV, 2419 DRM_FORMAT_YVYU, 2420 DRM_FORMAT_UYVY, 2421 DRM_FORMAT_VYUY, 2422 }; 2423 2424 static const u32 vlv_plane_formats[] = { 2425 DRM_FORMAT_C8, 2426 DRM_FORMAT_RGB565, 2427 DRM_FORMAT_XRGB8888, 2428 DRM_FORMAT_XBGR8888, 2429 DRM_FORMAT_ARGB8888, 2430 DRM_FORMAT_ABGR8888, 2431 DRM_FORMAT_XBGR2101010, 2432 DRM_FORMAT_ABGR2101010, 2433 DRM_FORMAT_YUYV, 2434 DRM_FORMAT_YVYU, 2435 DRM_FORMAT_UYVY, 2436 DRM_FORMAT_VYUY, 2437 }; 2438 2439 static const u32 chv_pipe_b_sprite_formats[] = { 2440 DRM_FORMAT_C8, 2441 DRM_FORMAT_RGB565, 2442 DRM_FORMAT_XRGB8888, 2443 DRM_FORMAT_XBGR8888, 2444 DRM_FORMAT_ARGB8888, 2445 DRM_FORMAT_ABGR8888, 2446 DRM_FORMAT_XRGB2101010, 2447 DRM_FORMAT_XBGR2101010, 2448 DRM_FORMAT_ARGB2101010, 2449 DRM_FORMAT_ABGR2101010, 2450 DRM_FORMAT_YUYV, 2451 DRM_FORMAT_YVYU, 2452 DRM_FORMAT_UYVY, 2453 DRM_FORMAT_VYUY, 2454 }; 2455 2456 static const u32 skl_plane_formats[] = { 2457 DRM_FORMAT_C8, 2458 DRM_FORMAT_RGB565, 2459 DRM_FORMAT_XRGB8888, 2460 DRM_FORMAT_XBGR8888, 2461 DRM_FORMAT_ARGB8888, 2462 DRM_FORMAT_ABGR8888, 2463 DRM_FORMAT_XRGB2101010, 2464 DRM_FORMAT_XBGR2101010, 2465 DRM_FORMAT_XRGB16161616F, 2466 DRM_FORMAT_XBGR16161616F, 2467 DRM_FORMAT_YUYV, 2468 DRM_FORMAT_YVYU, 2469 DRM_FORMAT_UYVY, 2470 DRM_FORMAT_VYUY, 2471 }; 2472 2473 static const u32 skl_planar_formats[] = { 2474 DRM_FORMAT_C8, 2475 DRM_FORMAT_RGB565, 2476 DRM_FORMAT_XRGB8888, 2477 DRM_FORMAT_XBGR8888, 2478 DRM_FORMAT_ARGB8888, 2479 DRM_FORMAT_ABGR8888, 2480 DRM_FORMAT_XRGB2101010, 2481 DRM_FORMAT_XBGR2101010, 2482 DRM_FORMAT_XRGB16161616F, 2483 DRM_FORMAT_XBGR16161616F, 2484 DRM_FORMAT_YUYV, 2485 DRM_FORMAT_YVYU, 2486 DRM_FORMAT_UYVY, 2487 DRM_FORMAT_VYUY, 2488 DRM_FORMAT_NV12, 2489 }; 2490 2491 static const u32 glk_planar_formats[] = { 2492 DRM_FORMAT_C8, 2493 DRM_FORMAT_RGB565, 2494 DRM_FORMAT_XRGB8888, 2495 DRM_FORMAT_XBGR8888, 2496 DRM_FORMAT_ARGB8888, 2497 DRM_FORMAT_ABGR8888, 2498 DRM_FORMAT_XRGB2101010, 2499 DRM_FORMAT_XBGR2101010, 2500 DRM_FORMAT_XRGB16161616F, 2501 DRM_FORMAT_XBGR16161616F, 2502 DRM_FORMAT_YUYV, 2503 DRM_FORMAT_YVYU, 2504 DRM_FORMAT_UYVY, 2505 DRM_FORMAT_VYUY, 2506 DRM_FORMAT_NV12, 2507 DRM_FORMAT_P010, 2508 DRM_FORMAT_P012, 2509 DRM_FORMAT_P016, 2510 }; 2511 2512 static const u32 icl_sdr_y_plane_formats[] = { 2513 DRM_FORMAT_C8, 2514 DRM_FORMAT_RGB565, 2515 DRM_FORMAT_XRGB8888, 2516 DRM_FORMAT_XBGR8888, 2517 DRM_FORMAT_ARGB8888, 2518 DRM_FORMAT_ABGR8888, 2519 DRM_FORMAT_XRGB2101010, 2520 DRM_FORMAT_XBGR2101010, 2521 DRM_FORMAT_ARGB2101010, 2522 DRM_FORMAT_ABGR2101010, 2523 DRM_FORMAT_YUYV, 2524 DRM_FORMAT_YVYU, 2525 DRM_FORMAT_UYVY, 2526 DRM_FORMAT_VYUY, 2527 DRM_FORMAT_Y210, 2528 DRM_FORMAT_Y212, 2529 DRM_FORMAT_Y216, 2530 DRM_FORMAT_XVYU2101010, 2531 DRM_FORMAT_XVYU12_16161616, 2532 DRM_FORMAT_XVYU16161616, 2533 }; 2534 2535 static const u32 icl_sdr_uv_plane_formats[] = { 2536 DRM_FORMAT_C8, 2537 DRM_FORMAT_RGB565, 2538 DRM_FORMAT_XRGB8888, 2539 DRM_FORMAT_XBGR8888, 2540 DRM_FORMAT_ARGB8888, 2541 DRM_FORMAT_ABGR8888, 2542 DRM_FORMAT_XRGB2101010, 2543 DRM_FORMAT_XBGR2101010, 2544 DRM_FORMAT_ARGB2101010, 2545 DRM_FORMAT_ABGR2101010, 2546 DRM_FORMAT_YUYV, 2547 DRM_FORMAT_YVYU, 2548 DRM_FORMAT_UYVY, 2549 DRM_FORMAT_VYUY, 2550 DRM_FORMAT_NV12, 2551 DRM_FORMAT_P010, 2552 DRM_FORMAT_P012, 2553 DRM_FORMAT_P016, 2554 DRM_FORMAT_Y210, 2555 DRM_FORMAT_Y212, 2556 DRM_FORMAT_Y216, 2557 DRM_FORMAT_XVYU2101010, 2558 DRM_FORMAT_XVYU12_16161616, 2559 DRM_FORMAT_XVYU16161616, 2560 }; 2561 2562 static const u32 icl_hdr_plane_formats[] = { 2563 DRM_FORMAT_C8, 2564 DRM_FORMAT_RGB565, 2565 DRM_FORMAT_XRGB8888, 2566 DRM_FORMAT_XBGR8888, 2567 DRM_FORMAT_ARGB8888, 2568 DRM_FORMAT_ABGR8888, 2569 DRM_FORMAT_XRGB2101010, 2570 DRM_FORMAT_XBGR2101010, 2571 DRM_FORMAT_ARGB2101010, 2572 DRM_FORMAT_ABGR2101010, 2573 DRM_FORMAT_XRGB16161616F, 2574 DRM_FORMAT_XBGR16161616F, 2575 DRM_FORMAT_ARGB16161616F, 2576 DRM_FORMAT_ABGR16161616F, 2577 DRM_FORMAT_YUYV, 2578 DRM_FORMAT_YVYU, 2579 DRM_FORMAT_UYVY, 2580 DRM_FORMAT_VYUY, 2581 DRM_FORMAT_NV12, 2582 DRM_FORMAT_P010, 2583 DRM_FORMAT_P012, 2584 DRM_FORMAT_P016, 2585 DRM_FORMAT_Y210, 2586 DRM_FORMAT_Y212, 2587 DRM_FORMAT_Y216, 2588 DRM_FORMAT_XVYU2101010, 2589 DRM_FORMAT_XVYU12_16161616, 2590 DRM_FORMAT_XVYU16161616, 2591 }; 2592 2593 static const u64 skl_plane_format_modifiers_noccs[] = { 2594 I915_FORMAT_MOD_Yf_TILED, 2595 I915_FORMAT_MOD_Y_TILED, 2596 I915_FORMAT_MOD_X_TILED, 2597 DRM_FORMAT_MOD_LINEAR, 2598 DRM_FORMAT_MOD_INVALID 2599 }; 2600 2601 static const u64 skl_plane_format_modifiers_ccs[] = { 2602 I915_FORMAT_MOD_Yf_TILED_CCS, 2603 I915_FORMAT_MOD_Y_TILED_CCS, 2604 I915_FORMAT_MOD_Yf_TILED, 2605 I915_FORMAT_MOD_Y_TILED, 2606 I915_FORMAT_MOD_X_TILED, 2607 DRM_FORMAT_MOD_LINEAR, 2608 DRM_FORMAT_MOD_INVALID 2609 }; 2610 2611 static const u64 gen12_plane_format_modifiers_mc_ccs[] = { 2612 I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS, 2613 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2614 I915_FORMAT_MOD_Y_TILED, 2615 I915_FORMAT_MOD_X_TILED, 2616 DRM_FORMAT_MOD_LINEAR, 2617 DRM_FORMAT_MOD_INVALID 2618 }; 2619 2620 static const u64 gen12_plane_format_modifiers_rc_ccs[] = { 2621 I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS, 2622 I915_FORMAT_MOD_Y_TILED, 2623 I915_FORMAT_MOD_X_TILED, 2624 DRM_FORMAT_MOD_LINEAR, 2625 DRM_FORMAT_MOD_INVALID 2626 }; 2627 2628 static bool g4x_sprite_format_mod_supported(struct drm_plane *_plane, 2629 u32 format, u64 modifier) 2630 { 2631 switch (modifier) { 2632 case DRM_FORMAT_MOD_LINEAR: 2633 case I915_FORMAT_MOD_X_TILED: 2634 break; 2635 default: 2636 return false; 2637 } 2638 2639 switch (format) { 2640 case DRM_FORMAT_XRGB8888: 2641 case DRM_FORMAT_YUYV: 2642 case DRM_FORMAT_YVYU: 2643 case DRM_FORMAT_UYVY: 2644 case DRM_FORMAT_VYUY: 2645 if (modifier == DRM_FORMAT_MOD_LINEAR || 2646 modifier == I915_FORMAT_MOD_X_TILED) 2647 return true; 2648 /* fall through */ 2649 default: 2650 return false; 2651 } 2652 } 2653 2654 static bool snb_sprite_format_mod_supported(struct drm_plane *_plane, 2655 u32 format, u64 modifier) 2656 { 2657 switch (modifier) { 2658 case DRM_FORMAT_MOD_LINEAR: 2659 case I915_FORMAT_MOD_X_TILED: 2660 break; 2661 default: 2662 return false; 2663 } 2664 2665 switch (format) { 2666 case DRM_FORMAT_XRGB8888: 2667 case DRM_FORMAT_XBGR8888: 2668 case DRM_FORMAT_XRGB2101010: 2669 case DRM_FORMAT_XBGR2101010: 2670 case DRM_FORMAT_XRGB16161616F: 2671 case DRM_FORMAT_XBGR16161616F: 2672 case DRM_FORMAT_YUYV: 2673 case DRM_FORMAT_YVYU: 2674 case DRM_FORMAT_UYVY: 2675 case DRM_FORMAT_VYUY: 2676 if (modifier == DRM_FORMAT_MOD_LINEAR || 2677 modifier == I915_FORMAT_MOD_X_TILED) 2678 return true; 2679 /* fall through */ 2680 default: 2681 return false; 2682 } 2683 } 2684 2685 static bool vlv_sprite_format_mod_supported(struct drm_plane *_plane, 2686 u32 format, u64 modifier) 2687 { 2688 switch (modifier) { 2689 case DRM_FORMAT_MOD_LINEAR: 2690 case I915_FORMAT_MOD_X_TILED: 2691 break; 2692 default: 2693 return false; 2694 } 2695 2696 switch (format) { 2697 case DRM_FORMAT_C8: 2698 case DRM_FORMAT_RGB565: 2699 case DRM_FORMAT_ABGR8888: 2700 case DRM_FORMAT_ARGB8888: 2701 case DRM_FORMAT_XBGR8888: 2702 case DRM_FORMAT_XRGB8888: 2703 case DRM_FORMAT_XBGR2101010: 2704 case DRM_FORMAT_ABGR2101010: 2705 case DRM_FORMAT_XRGB2101010: 2706 case DRM_FORMAT_ARGB2101010: 2707 case DRM_FORMAT_YUYV: 2708 case DRM_FORMAT_YVYU: 2709 case DRM_FORMAT_UYVY: 2710 case DRM_FORMAT_VYUY: 2711 if (modifier == DRM_FORMAT_MOD_LINEAR || 2712 modifier == I915_FORMAT_MOD_X_TILED) 2713 return true; 2714 /* fall through */ 2715 default: 2716 return false; 2717 } 2718 } 2719 2720 static bool skl_plane_format_mod_supported(struct drm_plane *_plane, 2721 u32 format, u64 modifier) 2722 { 2723 struct intel_plane *plane = to_intel_plane(_plane); 2724 2725 switch (modifier) { 2726 case DRM_FORMAT_MOD_LINEAR: 2727 case I915_FORMAT_MOD_X_TILED: 2728 case I915_FORMAT_MOD_Y_TILED: 2729 case I915_FORMAT_MOD_Yf_TILED: 2730 break; 2731 case I915_FORMAT_MOD_Y_TILED_CCS: 2732 case I915_FORMAT_MOD_Yf_TILED_CCS: 2733 if (!plane->has_ccs) 2734 return false; 2735 break; 2736 default: 2737 return false; 2738 } 2739 2740 switch (format) { 2741 case DRM_FORMAT_XRGB8888: 2742 case DRM_FORMAT_XBGR8888: 2743 case DRM_FORMAT_ARGB8888: 2744 case DRM_FORMAT_ABGR8888: 2745 if (is_ccs_modifier(modifier)) 2746 return true; 2747 /* fall through */ 2748 case DRM_FORMAT_RGB565: 2749 case DRM_FORMAT_XRGB2101010: 2750 case DRM_FORMAT_XBGR2101010: 2751 case DRM_FORMAT_ARGB2101010: 2752 case DRM_FORMAT_ABGR2101010: 2753 case DRM_FORMAT_YUYV: 2754 case DRM_FORMAT_YVYU: 2755 case DRM_FORMAT_UYVY: 2756 case DRM_FORMAT_VYUY: 2757 case DRM_FORMAT_NV12: 2758 case DRM_FORMAT_P010: 2759 case DRM_FORMAT_P012: 2760 case DRM_FORMAT_P016: 2761 case DRM_FORMAT_XVYU2101010: 2762 if (modifier == I915_FORMAT_MOD_Yf_TILED) 2763 return true; 2764 /* fall through */ 2765 case DRM_FORMAT_C8: 2766 case DRM_FORMAT_XBGR16161616F: 2767 case DRM_FORMAT_ABGR16161616F: 2768 case DRM_FORMAT_XRGB16161616F: 2769 case DRM_FORMAT_ARGB16161616F: 2770 case DRM_FORMAT_Y210: 2771 case DRM_FORMAT_Y212: 2772 case DRM_FORMAT_Y216: 2773 case DRM_FORMAT_XVYU12_16161616: 2774 case DRM_FORMAT_XVYU16161616: 2775 if (modifier == DRM_FORMAT_MOD_LINEAR || 2776 modifier == I915_FORMAT_MOD_X_TILED || 2777 modifier == I915_FORMAT_MOD_Y_TILED) 2778 return true; 2779 /* fall through */ 2780 default: 2781 return false; 2782 } 2783 } 2784 2785 static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id) 2786 { 2787 return plane_id < PLANE_SPRITE4; 2788 } 2789 2790 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, 2791 u32 format, u64 modifier) 2792 { 2793 struct intel_plane *plane = to_intel_plane(_plane); 2794 2795 switch (modifier) { 2796 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: 2797 if (!gen12_plane_supports_mc_ccs(plane->id)) 2798 return false; 2799 /* fall through */ 2800 case DRM_FORMAT_MOD_LINEAR: 2801 case I915_FORMAT_MOD_X_TILED: 2802 case I915_FORMAT_MOD_Y_TILED: 2803 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: 2804 break; 2805 default: 2806 return false; 2807 } 2808 2809 switch (format) { 2810 case DRM_FORMAT_XRGB8888: 2811 case DRM_FORMAT_XBGR8888: 2812 case DRM_FORMAT_ARGB8888: 2813 case DRM_FORMAT_ABGR8888: 2814 if (is_ccs_modifier(modifier)) 2815 return true; 2816 /* fall through */ 2817 case DRM_FORMAT_YUYV: 2818 case DRM_FORMAT_YVYU: 2819 case DRM_FORMAT_UYVY: 2820 case DRM_FORMAT_VYUY: 2821 case DRM_FORMAT_NV12: 2822 case DRM_FORMAT_P010: 2823 case DRM_FORMAT_P012: 2824 case DRM_FORMAT_P016: 2825 if (modifier == I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS) 2826 return true; 2827 /* fall through */ 2828 case DRM_FORMAT_RGB565: 2829 case DRM_FORMAT_XRGB2101010: 2830 case DRM_FORMAT_XBGR2101010: 2831 case DRM_FORMAT_ARGB2101010: 2832 case DRM_FORMAT_ABGR2101010: 2833 case DRM_FORMAT_XVYU2101010: 2834 case DRM_FORMAT_C8: 2835 case DRM_FORMAT_XBGR16161616F: 2836 case DRM_FORMAT_ABGR16161616F: 2837 case DRM_FORMAT_XRGB16161616F: 2838 case DRM_FORMAT_ARGB16161616F: 2839 case DRM_FORMAT_Y210: 2840 case DRM_FORMAT_Y212: 2841 case DRM_FORMAT_Y216: 2842 case DRM_FORMAT_XVYU12_16161616: 2843 case DRM_FORMAT_XVYU16161616: 2844 if (modifier == DRM_FORMAT_MOD_LINEAR || 2845 modifier == I915_FORMAT_MOD_X_TILED || 2846 modifier == I915_FORMAT_MOD_Y_TILED) 2847 return true; 2848 /* fall through */ 2849 default: 2850 return false; 2851 } 2852 } 2853 2854 static const struct drm_plane_funcs g4x_sprite_funcs = { 2855 .update_plane = drm_atomic_helper_update_plane, 2856 .disable_plane = drm_atomic_helper_disable_plane, 2857 .destroy = intel_plane_destroy, 2858 .atomic_duplicate_state = intel_plane_duplicate_state, 2859 .atomic_destroy_state = intel_plane_destroy_state, 2860 .format_mod_supported = g4x_sprite_format_mod_supported, 2861 }; 2862 2863 static const struct drm_plane_funcs snb_sprite_funcs = { 2864 .update_plane = drm_atomic_helper_update_plane, 2865 .disable_plane = drm_atomic_helper_disable_plane, 2866 .destroy = intel_plane_destroy, 2867 .atomic_duplicate_state = intel_plane_duplicate_state, 2868 .atomic_destroy_state = intel_plane_destroy_state, 2869 .format_mod_supported = snb_sprite_format_mod_supported, 2870 }; 2871 2872 static const struct drm_plane_funcs vlv_sprite_funcs = { 2873 .update_plane = drm_atomic_helper_update_plane, 2874 .disable_plane = drm_atomic_helper_disable_plane, 2875 .destroy = intel_plane_destroy, 2876 .atomic_duplicate_state = intel_plane_duplicate_state, 2877 .atomic_destroy_state = intel_plane_destroy_state, 2878 .format_mod_supported = vlv_sprite_format_mod_supported, 2879 }; 2880 2881 static const struct drm_plane_funcs skl_plane_funcs = { 2882 .update_plane = drm_atomic_helper_update_plane, 2883 .disable_plane = drm_atomic_helper_disable_plane, 2884 .destroy = intel_plane_destroy, 2885 .atomic_duplicate_state = intel_plane_duplicate_state, 2886 .atomic_destroy_state = intel_plane_destroy_state, 2887 .format_mod_supported = skl_plane_format_mod_supported, 2888 }; 2889 2890 static const struct drm_plane_funcs gen12_plane_funcs = { 2891 .update_plane = drm_atomic_helper_update_plane, 2892 .disable_plane = drm_atomic_helper_disable_plane, 2893 .destroy = intel_plane_destroy, 2894 .atomic_duplicate_state = intel_plane_duplicate_state, 2895 .atomic_destroy_state = intel_plane_destroy_state, 2896 .format_mod_supported = gen12_plane_format_mod_supported, 2897 }; 2898 2899 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv, 2900 enum pipe pipe, enum plane_id plane_id) 2901 { 2902 if (!HAS_FBC(dev_priv)) 2903 return false; 2904 2905 return pipe == PIPE_A && plane_id == PLANE_PRIMARY; 2906 } 2907 2908 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, 2909 enum pipe pipe, enum plane_id plane_id) 2910 { 2911 /* Display WA #0870: skl, bxt */ 2912 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) 2913 return false; 2914 2915 if (IS_GEN(dev_priv, 9) && !IS_GEMINILAKE(dev_priv) && pipe == PIPE_C) 2916 return false; 2917 2918 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) 2919 return false; 2920 2921 return true; 2922 } 2923 2924 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv, 2925 enum pipe pipe, enum plane_id plane_id, 2926 int *num_formats) 2927 { 2928 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2929 *num_formats = ARRAY_SIZE(skl_planar_formats); 2930 return skl_planar_formats; 2931 } else { 2932 *num_formats = ARRAY_SIZE(skl_plane_formats); 2933 return skl_plane_formats; 2934 } 2935 } 2936 2937 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv, 2938 enum pipe pipe, enum plane_id plane_id, 2939 int *num_formats) 2940 { 2941 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) { 2942 *num_formats = ARRAY_SIZE(glk_planar_formats); 2943 return glk_planar_formats; 2944 } else { 2945 *num_formats = ARRAY_SIZE(skl_plane_formats); 2946 return skl_plane_formats; 2947 } 2948 } 2949 2950 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, 2951 enum pipe pipe, enum plane_id plane_id, 2952 int *num_formats) 2953 { 2954 if (icl_is_hdr_plane(dev_priv, plane_id)) { 2955 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); 2956 return icl_hdr_plane_formats; 2957 } else if (icl_is_nv12_y_plane(plane_id)) { 2958 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats); 2959 return icl_sdr_y_plane_formats; 2960 } else { 2961 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats); 2962 return icl_sdr_uv_plane_formats; 2963 } 2964 } 2965 2966 static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id) 2967 { 2968 if (gen12_plane_supports_mc_ccs(plane_id)) 2969 return gen12_plane_format_modifiers_mc_ccs; 2970 else 2971 return gen12_plane_format_modifiers_rc_ccs; 2972 } 2973 2974 static bool skl_plane_has_ccs(struct drm_i915_private *dev_priv, 2975 enum pipe pipe, enum plane_id plane_id) 2976 { 2977 if (plane_id == PLANE_CURSOR) 2978 return false; 2979 2980 if (INTEL_GEN(dev_priv) >= 10) 2981 return true; 2982 2983 if (IS_GEMINILAKE(dev_priv)) 2984 return pipe != PIPE_C; 2985 2986 return pipe != PIPE_C && 2987 (plane_id == PLANE_PRIMARY || 2988 plane_id == PLANE_SPRITE0); 2989 } 2990 2991 struct intel_plane * 2992 skl_universal_plane_create(struct drm_i915_private *dev_priv, 2993 enum pipe pipe, enum plane_id plane_id) 2994 { 2995 const struct drm_plane_funcs *plane_funcs; 2996 struct intel_plane *plane; 2997 enum drm_plane_type plane_type; 2998 unsigned int supported_rotations; 2999 unsigned int possible_crtcs; 3000 const u64 *modifiers; 3001 const u32 *formats; 3002 int num_formats; 3003 int ret; 3004 3005 plane = intel_plane_alloc(); 3006 if (IS_ERR(plane)) 3007 return plane; 3008 3009 plane->pipe = pipe; 3010 plane->id = plane_id; 3011 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id); 3012 3013 plane->has_fbc = skl_plane_has_fbc(dev_priv, pipe, plane_id); 3014 if (plane->has_fbc) { 3015 struct intel_fbc *fbc = &dev_priv->fbc; 3016 3017 fbc->possible_framebuffer_bits |= plane->frontbuffer_bit; 3018 } 3019 3020 plane->max_stride = skl_plane_max_stride; 3021 plane->update_plane = skl_update_plane; 3022 plane->disable_plane = skl_disable_plane; 3023 plane->get_hw_state = skl_plane_get_hw_state; 3024 plane->check_plane = skl_plane_check; 3025 plane->min_cdclk = skl_plane_min_cdclk; 3026 3027 if (INTEL_GEN(dev_priv) >= 11) 3028 formats = icl_get_plane_formats(dev_priv, pipe, 3029 plane_id, &num_formats); 3030 else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 3031 formats = glk_get_plane_formats(dev_priv, pipe, 3032 plane_id, &num_formats); 3033 else 3034 formats = skl_get_plane_formats(dev_priv, pipe, 3035 plane_id, &num_formats); 3036 3037 plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); 3038 if (INTEL_GEN(dev_priv) >= 12) { 3039 modifiers = gen12_get_plane_modifiers(plane_id); 3040 plane_funcs = &gen12_plane_funcs; 3041 } else { 3042 if (plane->has_ccs) 3043 modifiers = skl_plane_format_modifiers_ccs; 3044 else 3045 modifiers = skl_plane_format_modifiers_noccs; 3046 plane_funcs = &skl_plane_funcs; 3047 } 3048 3049 if (plane_id == PLANE_PRIMARY) 3050 plane_type = DRM_PLANE_TYPE_PRIMARY; 3051 else 3052 plane_type = DRM_PLANE_TYPE_OVERLAY; 3053 3054 possible_crtcs = BIT(pipe); 3055 3056 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3057 possible_crtcs, plane_funcs, 3058 formats, num_formats, modifiers, 3059 plane_type, 3060 "plane %d%c", plane_id + 1, 3061 pipe_name(pipe)); 3062 if (ret) 3063 goto fail; 3064 3065 supported_rotations = 3066 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | 3067 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; 3068 3069 if (INTEL_GEN(dev_priv) >= 10) 3070 supported_rotations |= DRM_MODE_REFLECT_X; 3071 3072 drm_plane_create_rotation_property(&plane->base, 3073 DRM_MODE_ROTATE_0, 3074 supported_rotations); 3075 3076 drm_plane_create_color_properties(&plane->base, 3077 BIT(DRM_COLOR_YCBCR_BT601) | 3078 BIT(DRM_COLOR_YCBCR_BT709), 3079 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3080 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3081 DRM_COLOR_YCBCR_BT709, 3082 DRM_COLOR_YCBCR_LIMITED_RANGE); 3083 3084 drm_plane_create_alpha_property(&plane->base); 3085 drm_plane_create_blend_mode_property(&plane->base, 3086 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 3087 BIT(DRM_MODE_BLEND_PREMULTI) | 3088 BIT(DRM_MODE_BLEND_COVERAGE)); 3089 3090 drm_plane_create_zpos_immutable_property(&plane->base, plane_id); 3091 3092 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3093 3094 return plane; 3095 3096 fail: 3097 intel_plane_free(plane); 3098 3099 return ERR_PTR(ret); 3100 } 3101 3102 struct intel_plane * 3103 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 3104 enum pipe pipe, int sprite) 3105 { 3106 struct intel_plane *plane; 3107 const struct drm_plane_funcs *plane_funcs; 3108 unsigned long possible_crtcs; 3109 unsigned int supported_rotations; 3110 const u64 *modifiers; 3111 const u32 *formats; 3112 int num_formats; 3113 int ret, zpos; 3114 3115 if (INTEL_GEN(dev_priv) >= 9) 3116 return skl_universal_plane_create(dev_priv, pipe, 3117 PLANE_SPRITE0 + sprite); 3118 3119 plane = intel_plane_alloc(); 3120 if (IS_ERR(plane)) 3121 return plane; 3122 3123 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3124 plane->max_stride = i9xx_plane_max_stride; 3125 plane->update_plane = vlv_update_plane; 3126 plane->disable_plane = vlv_disable_plane; 3127 plane->get_hw_state = vlv_plane_get_hw_state; 3128 plane->check_plane = vlv_sprite_check; 3129 plane->min_cdclk = vlv_plane_min_cdclk; 3130 3131 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3132 formats = chv_pipe_b_sprite_formats; 3133 num_formats = ARRAY_SIZE(chv_pipe_b_sprite_formats); 3134 } else { 3135 formats = vlv_plane_formats; 3136 num_formats = ARRAY_SIZE(vlv_plane_formats); 3137 } 3138 modifiers = i9xx_plane_format_modifiers; 3139 3140 plane_funcs = &vlv_sprite_funcs; 3141 } else if (INTEL_GEN(dev_priv) >= 7) { 3142 plane->max_stride = g4x_sprite_max_stride; 3143 plane->update_plane = ivb_update_plane; 3144 plane->disable_plane = ivb_disable_plane; 3145 plane->get_hw_state = ivb_plane_get_hw_state; 3146 plane->check_plane = g4x_sprite_check; 3147 3148 if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 3149 plane->min_cdclk = hsw_plane_min_cdclk; 3150 else 3151 plane->min_cdclk = ivb_sprite_min_cdclk; 3152 3153 formats = snb_plane_formats; 3154 num_formats = ARRAY_SIZE(snb_plane_formats); 3155 modifiers = i9xx_plane_format_modifiers; 3156 3157 plane_funcs = &snb_sprite_funcs; 3158 } else { 3159 plane->max_stride = g4x_sprite_max_stride; 3160 plane->update_plane = g4x_update_plane; 3161 plane->disable_plane = g4x_disable_plane; 3162 plane->get_hw_state = g4x_plane_get_hw_state; 3163 plane->check_plane = g4x_sprite_check; 3164 plane->min_cdclk = g4x_sprite_min_cdclk; 3165 3166 modifiers = i9xx_plane_format_modifiers; 3167 if (IS_GEN(dev_priv, 6)) { 3168 formats = snb_plane_formats; 3169 num_formats = ARRAY_SIZE(snb_plane_formats); 3170 3171 plane_funcs = &snb_sprite_funcs; 3172 } else { 3173 formats = g4x_plane_formats; 3174 num_formats = ARRAY_SIZE(g4x_plane_formats); 3175 3176 plane_funcs = &g4x_sprite_funcs; 3177 } 3178 } 3179 3180 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { 3181 supported_rotations = 3182 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | 3183 DRM_MODE_REFLECT_X; 3184 } else { 3185 supported_rotations = 3186 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; 3187 } 3188 3189 plane->pipe = pipe; 3190 plane->id = PLANE_SPRITE0 + sprite; 3191 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane->id); 3192 3193 possible_crtcs = BIT(pipe); 3194 3195 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 3196 possible_crtcs, plane_funcs, 3197 formats, num_formats, modifiers, 3198 DRM_PLANE_TYPE_OVERLAY, 3199 "sprite %c", sprite_name(pipe, sprite)); 3200 if (ret) 3201 goto fail; 3202 3203 drm_plane_create_rotation_property(&plane->base, 3204 DRM_MODE_ROTATE_0, 3205 supported_rotations); 3206 3207 drm_plane_create_color_properties(&plane->base, 3208 BIT(DRM_COLOR_YCBCR_BT601) | 3209 BIT(DRM_COLOR_YCBCR_BT709), 3210 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 3211 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 3212 DRM_COLOR_YCBCR_BT709, 3213 DRM_COLOR_YCBCR_LIMITED_RANGE); 3214 3215 zpos = sprite + 1; 3216 drm_plane_create_zpos_immutable_property(&plane->base, zpos); 3217 3218 drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs); 3219 3220 return plane; 3221 3222 fail: 3223 intel_plane_free(plane); 3224 3225 return ERR_PTR(ret); 3226 } 3227
Indexes created Thu Oct 02 07:10:07 GMT 2025