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intel_vga.c revision 1.1.1.1 
      1 /*	$NetBSD: intel_vga.c,v 1.1.1.1 2021/12/18 20:15:31 riastradh Exp $	*/
      2 
      3 // SPDX-License-Identifier: MIT
      4 /*
      5  * Copyright  2019 Intel Corporation
      6  */
      7 
      8 #include <sys/cdefs.h>
      9 __KERNEL_RCSID(0, "$NetBSD: intel_vga.c,v 1.1.1.1 2021/12/18 20:15:31 riastradh Exp $");
     10 
     11 #include <linux/pci.h>
     12 #include <linux/vgaarb.h>
     13 
     14 #include <drm/i915_drm.h>
     15 
     16 #include "i915_drv.h"
     17 #include "intel_vga.h"
     18 
     19 static i915_reg_t intel_vga_cntrl_reg(struct drm_i915_private *i915)
     20 {
     21 	if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
     22 		return VLV_VGACNTRL;
     23 	else if (INTEL_GEN(i915) >= 5)
     24 		return CPU_VGACNTRL;
     25 	else
     26 		return VGACNTRL;
     27 }
     28 
     29 /* Disable the VGA plane that we never use */
     30 void intel_vga_disable(struct drm_i915_private *dev_priv)
     31 {
     32 	struct pci_dev *pdev = dev_priv->drm.pdev;
     33 	i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
     34 	u8 sr1;
     35 
     36 	/* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
     37 	vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
     38 	outb(SR01, VGA_SR_INDEX);
     39 	sr1 = inb(VGA_SR_DATA);
     40 	outb(sr1 | 1 << 5, VGA_SR_DATA);
     41 	vga_put(pdev, VGA_RSRC_LEGACY_IO);
     42 	udelay(300);
     43 
     44 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
     45 	POSTING_READ(vga_reg);
     46 }
     47 
     48 void intel_vga_redisable_power_on(struct drm_i915_private *dev_priv)
     49 {
     50 	i915_reg_t vga_reg = intel_vga_cntrl_reg(dev_priv);
     51 
     52 	if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
     53 		DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
     54 		intel_vga_disable(dev_priv);
     55 	}
     56 }
     57 
     58 void intel_vga_redisable(struct drm_i915_private *i915)
     59 {
     60 	intel_wakeref_t wakeref;
     61 
     62 	/*
     63 	 * This function can be called both from intel_modeset_setup_hw_state or
     64 	 * at a very early point in our resume sequence, where the power well
     65 	 * structures are not yet restored. Since this function is at a very
     66 	 * paranoid "someone might have enabled VGA while we were not looking"
     67 	 * level, just check if the power well is enabled instead of trying to
     68 	 * follow the "don't touch the power well if we don't need it" policy
     69 	 * the rest of the driver uses.
     70 	 */
     71 	wakeref = intel_display_power_get_if_enabled(i915, POWER_DOMAIN_VGA);
     72 	if (!wakeref)
     73 		return;
     74 
     75 	intel_vga_redisable_power_on(i915);
     76 
     77 	intel_display_power_put(i915, POWER_DOMAIN_VGA, wakeref);
     78 }
     79 
     80 void intel_vga_reset_io_mem(struct drm_i915_private *i915)
     81 {
     82 	struct pci_dev *pdev = i915->drm.pdev;
     83 
     84 	/*
     85 	 * After we re-enable the power well, if we touch VGA register 0x3d5
     86 	 * we'll get unclaimed register interrupts. This stops after we write
     87 	 * anything to the VGA MSR register. The vgacon module uses this
     88 	 * register all the time, so if we unbind our driver and, as a
     89 	 * consequence, bind vgacon, we'll get stuck in an infinite loop at
     90 	 * console_unlock(). So make here we touch the VGA MSR register, making
     91 	 * sure vgacon can keep working normally without triggering interrupts
     92 	 * and error messages.
     93 	 */
     94 	vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
     95 	outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
     96 	vga_put(pdev, VGA_RSRC_LEGACY_IO);
     97 }
     98 
     99 static int
    100 intel_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
    101 {
    102 	unsigned int reg = INTEL_GEN(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
    103 	u16 gmch_ctrl;
    104 
    105 	if (pci_read_config_word(i915->bridge_dev, reg, &gmch_ctrl)) {
    106 		DRM_ERROR("failed to read control word\n");
    107 		return -EIO;
    108 	}
    109 
    110 	if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
    111 		return 0;
    112 
    113 	if (enable_decode)
    114 		gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
    115 	else
    116 		gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
    117 
    118 	if (pci_write_config_word(i915->bridge_dev, reg, gmch_ctrl)) {
    119 		DRM_ERROR("failed to write control word\n");
    120 		return -EIO;
    121 	}
    122 
    123 	return 0;
    124 }
    125 
    126 static unsigned int
    127 intel_vga_set_decode(void *cookie, bool enable_decode)
    128 {
    129 	struct drm_i915_private *i915 = cookie;
    130 
    131 	intel_vga_set_state(i915, enable_decode);
    132 
    133 	if (enable_decode)
    134 		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
    135 		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
    136 	else
    137 		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
    138 }
    139 
    140 int intel_vga_register(struct drm_i915_private *i915)
    141 {
    142 	struct pci_dev *pdev = i915->drm.pdev;
    143 	int ret;
    144 
    145 	/*
    146 	 * If we have > 1 VGA cards, then we need to arbitrate access to the
    147 	 * common VGA resources.
    148 	 *
    149 	 * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
    150 	 * then we do not take part in VGA arbitration and the
    151 	 * vga_client_register() fails with -ENODEV.
    152 	 */
    153 	ret = vga_client_register(pdev, i915, NULL, intel_vga_set_decode);
    154 	if (ret && ret != -ENODEV)
    155 		return ret;
    156 
    157 	return 0;
    158 }
    159 
    160 void intel_vga_unregister(struct drm_i915_private *i915)
    161 {
    162 	struct pci_dev *pdev = i915->drm.pdev;
    163 
    164 	vga_client_register(pdev, NULL, NULL, NULL);
    165 }
    166